Method, apparatus and system for anomaly detection for non-volatile memory device programming

Abstract

Methods, apparatus, and systems for anomaly detection for nonvolatile memory device programming are disclosed. An iterative program operation having at least first to nth program phases may be performed to program a nonvolatile memory device having memory cells connected through word lines. The nth program stage may apply an nth program voltage to a word line and generate an nth verify result indicating a number of a plurality of memory cells having at least a threshold voltage satisfying a specific verify voltage in the nth program stage. An nth model phase of the iterative model may be performed to determine an nth probability using an nth verification result and nth historical data associated with at least an (n-1) th programming phase. Programming anomalies may be determined based on an nth probability that satisfies at least an nth threshold probability. In response to a program exception, the iterative programming operation may be stopped before a final programming phase of the iterative programming operation is completed.

Description

Technical Field

[0001] The present invention relates to semiconductor memory devices, and more specifically, to non-volatile memory devices, programming methods thereof, and anomaly detection in such programming methods. Background Technology

[0002] Semiconductor memory devices can be categorized into volatile memory devices and non-volatile memory devices.

[0003] Non-volatile memory devices retain stored data even when power is cut off. Therefore, they are used to store essential information regardless of power supply. Examples of non-volatile memory devices include read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), flash memory, phase-change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), and so on.

[0004] Flash memory (a type of non-volatile memory) has the ability to erase data in cells collectively and is widely used in computer systems and memory cards.

[0005] Flash memory can be either NOR or NAND, depending on the connection between the memory cell transistors and the bit line. NOR flash memory uses two or more memory cell transistors connected in parallel to a bit line, storing data using a hot-electron channel method and erasing data using Fowler-Nordheim tunneling. NAND flash memory, on the other hand, uses two or more cell transistors connected in series to a bit line, and uses Fowler-Nordheim tunneling for both data storage and erasure. NOR flash memory is unsuitable for high integration density due to its high current consumption; however, its advantage lies in its ability to easily adapt to faster operating speeds. Conversely, NAND flash memory can achieve higher integration density due to its lower cell current consumption compared to NOR flash memory. Summary of the Invention

[0006] Some example embodiments of the inventive concepts described herein relate to methods, apparatus, and systems configured to implement programming anomalies in iterative (e.g., multi-stage) programming operations for programming non-volatile storage devices, wherein the anomaly can be determined based on a given nth programming stage (e.g., an nth programming loop) of an iterative programming operation having at least a sequence of first to nth programming stages, which can occur before the final programming stage of the programming operation.

[0007] In some example embodiments, a method (e.g., anomaly detection operation) can utilize an iterative model including, for example, a recurrent neural network (RNN) to determine a probability value associated with a likelihood of occurrence of at least one programming anomaly in an iterative programming operation, the iterative model processing data from a given nth programming stage (e.g., program loop, iterative program loop, etc.) in addition to data associated with one or more previous programming stages (e.g., (n-1)th programming stage) at a given nth model stage (e.g., model loop, iterative model loop, etc.). The occurrence of the programming anomaly in the 1st through nth programming stages of the iterative programming operation can be determined based on processing the probability value (e.g., comparing the probability value to a threshold value), and determining the occurrence of the at least one programming anomaly in response to determining that the probability value at least satisfies the threshold value.

[0008] The iterative model can operate each nth model stage based on the corresponding nth programming stage of the iterative programming operation. Each nth model stage can be executed at least partially concurrently with one or more stages (e.g., (n+1)th programming stage) of performing the programming operation, thereby enabling the performance of the programming anomaly detection in the iterative programming operation with minimal or no additional latency, thereby improving the anomaly detection capability without compromising the performance of the programming operation of the device implementing the iterative programming operation.

[0009] As a result, a programming anomaly in the iterative programming operation can be detected during the iterative programming operation (e.g., prior to completion of a final programming stage of the programming operation in example embodiments in which the iterative programming operation includes a predetermined“N” number of programming stages or program loops), which enables the implementation of “early” detection of the programming anomaly, and thus, initiation of early recovery actions to recover from the programming anomaly without having to wait until the final programming stage is completed. Such early recovery actions can include early termination of the iterative programming operation prior to completion of the final stage of the iterative programming operation. As a result, recovery from the programming anomaly can occur more quickly than if the anomaly detection were performed after completion of the final programming stage, thereby improving the speed of successfully completing the iterative programming operation on the non-volatile memory device, thereby improving the functionality of the device implementing the iterative programming operation.

[0010] The anomaly detection operation can detect the programming anomaly based on whether the validation result data for a given programming stage is determined to be associated with at least a threshold likelihood of occurrence / non-occurrence of an anomaly, and further based on historical data associated with one or more previous stages. Thus, the anomaly detection can be based on determining whether the validation result data for one or more stages is sufficiently unusual or unlikely to indicate that the validation result data for the one or more stages is indicative of the occurrence of an anomaly (e.g., the probability value at least satisfies a threshold probability value associated with the occurrence of a programming anomaly).

[0011] Because anomaly detection can be based on determining whether verification result data for one or more stages is sufficiently “unusual” or “unlikely,” rather than determining whether a lesser number of cells have a threshold voltage that reaches a verify voltage (e.g., an under-program anomaly), the anomaly detection process can enable detection of various additional types of programming anomalies. For example, the anomaly detection process can enable detection of an “over-program” anomaly in which one or more memory cells are programmed to a threshold voltage that exceeds an expected threshold voltage range for a target verify voltage. Thus, performing the anomaly detection operation can enable more general anomaly detection, thereby improving the reliability of a device that implements the iterative program operation and the anomaly detection operation.

[0012] According to some example embodiments, a method can include performing an iterative program operation to program a non-volatile memory device having at least a plurality of memory cells. The plurality of memory cells can be connected by a word line, the iterative program operation having a sequence of at least a first program stage to an nth program stage, n being a positive integer greater than one. The nth program stage can include applying an nth program voltage to the word line connected to the plurality of memory cells, and performing a verify operation associated with a particular verify voltage on the plurality of memory cells to generate an nth verify result value. The nth verify result value can indicate a number of memory cells in the plurality of memory cells that have a threshold voltage equal to or greater than the particular verify voltage at the nth program stage. The method can include performing at least an nth stage of an iterative model that utilizes the nth verify result value and an nth historical data associated with at least an (n-1)th program stage of the iterative program operation to determine an nth probability value that indicates a probability associated with an occurrence of at least one programming anomaly in the first stage to the nth stage of the iterative program operation.

[0013] According to some example embodiments, a computer-implemented method can be performed to train a neural network to determine the probability associated with the occurrence of at least one programming anomaly in an iterative programming operation that programs a non-volatile memory device having a plurality of memory cells connected by word lines. The method of training the neural network may include receiving measurement data based on performing one or more sample iterative programming operations having a sequence of multiple stages to program one or more sample non-volatile memory devices. For each sample iterative programming operation performed on each sample non-volatile memory device, the measurement data may include a sequence of sample verification result values, each sample verification result value indicating the number of memory cells in the sample non-volatile device having a threshold voltage equal to or greater than a specific verification voltage in a specific programming stage of the sample iterative programming operation. Each of the one or more sample iterative programming operations may not include any programming anomalies. Methods for training a neural network may include: training the neural network as an iterative model using measurement data as training input, such that the neural network is trained based on the measurement data to determine the probability of occurrence of at least one programming anomaly in the sequence of stages 1 to n of the iterative programming operation based on a threshold voltage indicating the number of memory cells having a specific verification voltage equal to or greater than the nth programming stage, and nth historical data associated with at least the (n-1)th programming stage of the iterative programming operation.

[0014] According to some example embodiments, a storage device may include a memory storing instruction programs and a processor. The processor may be configured to execute the instruction programs to perform an iterative programming operation to program a non-volatile storage device having at least a plurality of memory cells connected via word lines. The iterative programming operation may have a sequence of at least a first programming stage to an nth programming stage, where n is a positive integer greater than 1. The nth programming stage may include: applying an nth programming voltage to the word lines connected to the plurality of memory cells, and performing a verification operation associated with a specific verification voltage on the plurality of memory cells to generate an nth verification result value, the nth verification result value indicating the number of memory cells having a threshold voltage equal to or greater than the specific verification voltage of the nth programming stage. The processor may be configured to execute the instruction programs to perform at least an nth stage of an iterative model, the nth stage utilizing the nth verification result value and nth historical data associated with at least the (n-1)th programming stage of the iterative programming operation to determine an nth probability value, the nth probability value indicating the probability associated with the occurrence of at least one programming anomaly in the first to nth stages of the iterative programming operation.

[0015] According to some example embodiments, a storage device can include a memory storing a program of instructions, and a processor. The processor can be configured to execute the program of instructions to perform a method of training a neural network to determine a probability associated with an occurrence of at least one programming exception in an iterative programming operation that programs a non-volatile memory device having a plurality of memory cells connected by word lines. The method of training the neural network can include receiving measurement data based on performing one or more sample iterative programming operations having a sequence of a plurality of stages to program one or more sample non-volatile memory devices. The measurement data can include, for each sample iterative programming operation performed on each sample non-volatile memory device, a sequence of sample verify result values each indicating a number of memory cells in the sample non-volatile memory device having a threshold voltage equal to or greater than a particular verify voltage in a particular program stage of the sample iterative programming operation. Each of the one or more sample iterative programming operations can not include any programming exception. The method of training the neural network can include training the neural network as an iterative model using the measurement data as training input to the neural network such that the neural network is trained based on the measurement data to determine the probability associated with the occurrence of at least one programming exception in the sequence of the first stage to the nth stage of the iterative programming operation based on an nth verify result value indicating a number of memory cells in the plurality of memory cells having a threshold voltage equal to or greater than a particular verify voltage of an nth program stage, and an nth history data associated with at least an (n-1)th program stage of the iterative programming operation.

[0016] According to some example embodiments, a non-transitory computer readable storage medium can have recorded thereon a computer program. The computer program, when executed by at least one processor, can be configured to cause the at least one processor to perform a method including: performing an iterative programming operation to program a non-volatile memory device having at least a plurality of memory cells connected by word lines, the iterative programming operation having a sequence of at least a first program stage to an nth program stage, n being a positive integer greater than one. The nth program stage can include applying an nth program voltage to the word lines connected to the plurality of memory cells, and performing a verify operation associated with a particular verify voltage on the plurality of memory cells to generate an nth verify result value indicating a number of memory cells in the plurality of memory cells having a threshold voltage equal to or greater than the particular verify voltage of the nth program stage. The method can include performing at least an nth stage of an iterative model that utilizes the nth verify result value and an nth history data associated with at least an (n-1)th program stage of the iterative programming operation to determine an nth probability value indicating a probability associated with an occurrence of at least one programming exception in the first stage to the nth stage of the iterative programming operation.

[0017] According to some example embodiments, a non-transitory computer-readable storage medium can have recorded thereon a computer program. The computer program, when executed by at least one processor, can be configured to cause the at least one processor to perform a method of training a neural network to determine a probability associated with an occurrence of at least one programming exception in an iterative programming operation that programs a non-volatile memory device having a plurality of memory cells connected by a word line. The method of training the neural network can include receiving measurement data based on performing one or more sample iterative programming operations having a sequence of a plurality of programming stages to program one or more sample non-volatile memory devices. The measurement data can include, for each sample iterative programming operation performed on each sample non-volatile memory device, a sequence of sample verify result values each indicating a number of memory cells in the sample non-volatile memory device having a threshold voltage equal to or greater than a particular verify voltage in a particular programming stage of the sample iterative programming operation. Each of the one or more sample iterative programming operations can not include any programming exception. The method of training the neural network can include training the neural network as an iterative model using the measurement data as training input to the neural network such that the neural network is trained based on the measurement data to determine the probability associated with an occurrence of at least one programming exception in a sequence of a first stage to an nth stage of the iterative programming operation based on an nth verify result value indicating a number of memory cells in the plurality of memory cells having a threshold voltage equal to or greater than a particular verify voltage of the nth programming stage and nth historical data associated with at least an (n-1)th programming stage of the iterative programming operation. BRIEF DESCRIPTION OF DRAWINGS

[0018] The above and other objects and features of the present inventive concepts will become more apparent from the following detailed description, taken in conjunction with the accompanying drawings, when understood in conjunction with the following detailed description.

[0019] Figure 1 is a block diagram of a system including at least one memory device according to some example embodiments.

[0020] Figure 2 is a block diagram of a memory device according to some example embodiments.

[0021] Figure 3 is a block diagram of a memory device according to some example embodiments.

[0022] Figure 4 is a block diagram of a memory device according to some example embodiments.

[0023] Figure 5A is a diagram illustrating a first memory block of a plurality of memory blocks included in a memory cell array in Figure 4 according to some example embodiments.

[0024] Figure 5B is a graph illustrating a memory device according to some example embodiments.

[0025] Figure 6 is a distribution graph for describing an iterative program operation to program a non-volatile memory device according to some example embodiments.

[0026] Figure 7 is a timing graph for describing an iterative program operation to program a non-volatile memory device according to some example embodiments.

[0027] Figure 8 illustrates measured program rates for a plurality of iterative program operations performed on a non-volatile memory device according to some example embodiments.

[0028] Figure 9 illustrates a recurrent neural network (RNN) network structure of an iteration model of an iterative exception detection procedure according to some example embodiments.

[0029] Figure 10A is a flowchart illustrating a method of performing an iterative program operation to program a non-volatile memory device having at least a plurality of memory cells according to some example embodiments.

[0030] Figure 10B is a flowchart illustrating a method of performing an iterative exception detection procedure corresponding to an iterative program operation of Figure 10A according to some example embodiments.

[0031] Figure 11 is a flowchart illustrating a method including an iterative program operation and an iterative exception detection procedure according to some example embodiments.

[0032] Figure 12 is a distribution graph illustrating a failed iterative program operation to program a non-volatile memory device according to some example embodiments.

[0033] Figure 13 is a graph illustrating a conditional probability distribution of a verification result value for an n-th program phase of an iterative program operation according to some example embodiments.

[0034] Figure 14 is a distribution graph of a failed iterative program operation to program a non-volatile memory device according to some example embodiments.

[0035] Figure 15 is a line graph illustrating a plurality of probability value sequences determined for separate, respective iterative program operations including standard and failed iterative program operations according to some example embodiments.

[0036] Figure 16 is an expanded view of region X in Figure 15

[0037] Figure 17 is a flowchart illustrating a computer-implemented method of training a neural network according to some example embodiments.

[0038] Figure 18 is a schematic block diagram of an electronic device according to some example embodiments. DETAILED DESCRIPTION

[0039] Some example embodiments of the present inventive concept will hereinafter be described in detail with reference to the accompanying drawings, which are provided in the drawings for the purpose of illustration only. In the following description, specific details are provided that are merely exemplary in nature and are not intended to limit the scope of the inventive concept. Therefore, the inventive concept should not be construed as being limited to the following example embodiments. In the following description, the terms "module" and "unit" are used to refer to a component that is implemented by software, hardware, or a combination thereof. For example, the software can be machine code, firmware, embedded code, and application software. For example, the hardware can include a circuit, an electronic circuit, a processor, a computer, an integrated circuit core, a pressure sensor, an inertial sensor, a micro electro mechanical system (MEMS), a passive element, or a combination thereof.

[0040] In the detailed description, components described with reference to the terms "driver", "block", "unit", and the like will be implemented by software, hardware, or a combination thereof. For example, the software can be machine code, firmware, embedded code, and application software. For example, the hardware can include a circuit, an electronic circuit, a processor, a computer, an integrated circuit core, a pressure sensor, an inertial sensor, a micro electro mechanical system (MEMS), a passive element, or a combination thereof.

[0041] NAND memory devices strive to achieve high read throughput and low latency, while having low power consumption and low complexity. To achieve these goals, a minimum number of reads from the NAND need to be performed such that a single bit from a single bit in a NAND channel is measured per written bit, resulting in a hard decision (HD) binary channel.

[0042] An effective error correcting code (ECC) for an HD channel with good performance and low complexity is an algebraic code (e.g., Bose-Chaudhuri-Hocquenghem (BCH), Reed-Solomon (RS), and BCH generalized concatenated code (GCC)).

[0043] ​If the HD decoding fails, additional data can be read from the NAND and additional soft information is received via a soft defined (SD) channel. This mode of operation is rare and, thus, can be done with higher latency and complexity and requires high decoding capability.

[0044] For example, a polar code can be an efficient ECC for an SD channel with high decoding capability. However, a polar code requires very high complexity and latency. To overcome the high complexity and latency, a polar-GCC code can be used.

[0045] Some example embodiments of the present application include a construction of an ECC in the form of a GCC in which a set of P polar-BCH sub-codes (e.g., a combination of a polar code and a BCH code) is concatenated with an RS code. According to some example embodiments, this family of codes leverages the advantages of BCH-GCC with a low complexity decoder and excellent performance for an HD channel and also leverages the advantages of polar-GCC with higher latency but good coverage for an SD channel.

[0046] Figure 1 is a block diagram of a system 1000 including at least one storage device according to some example embodiments. Figure 1 The system 1000 of can be basically a mobile system, such as a portable communication terminal (e.g., a mobile phone), a smartphone, a tablet personal computer (PC), a wearable device, a healthcare device, or an Internet of Things (IOT) device. However, Figure 1 The system 1000 of can not necessarily be limited to a mobile system and can be a PC, a laptop computer, a server, a media player, or a car device (e.g., a navigation device). In some example embodiments, Figure 1 The system 1000 of can be referred to as an electronic device.

[0047] Referring to Figure 1 The system 1000 can include a main processor 1100, a memory (e.g., 1200a and 1200b), and a storage device (e.g., 1300a and 1300b). In addition, the system 1000 can include at least one of an image capturing device 1410, a user input device 1420, a sensor 1430, a communication device 1440, a display 1450, a speaker 1460, a power supply device 1470, and a connection interface 1480. Although the system 1000 is illustrated as including a plurality of memories 1200a and 1200b, example embodiments are not limited thereto, and in some example embodiments, the system 1000 can include a single memory (e.g., the memory 1200a). Although the system 1000 is illustrated as including a plurality of storage devices 1300a and 1300b, example embodiments are not limited thereto, and in some example embodiments, the system 1000 can include a single storage device (e.g., the storage device 1300a).

[0048] The main processor 1100 can control all operations of the system 1000, and more particularly, can control operations of other components included in the system 1000. The main processor 1100 can be implemented as a general-purpose processor, a special-purpose processor, or an application processor, etc.

[0049] The main processor 1100 can include at least one CPU core 1110, and further include a controller 1120 configured to control the memories 1200a and 1200b and / or the storage devices 1300a and 1300b. In some embodiments, the main processor 1100 can further include an accelerator 1130, which is a special-purpose circuit for high-speed data operations such as artificial intelligence (AI) data operations. The accelerator 1130 can include a graphics processing unit (GPU), a neural processing unit (NPU), and / or a data processing unit (DPU), and is implemented as a chip physically separated from other components of the main processor 1100.

[0050] The memories 1200a and 1200b can serve as main storage devices of the system 1000. Although each of the memories 1200a and 1200b can include a volatile memory (e.g., static random access memory (SRAM) and / or dynamic random access memory (DRAM)), each of the memories 1200a and 1200b can include a non-volatile memory (e.g., flash memory, phase-change RAM (PRAM), and / or resistive RAM (RRAM), etc.). The memories 1200a and 1200b can be implemented in the same package as the main processor 1100

[0051] The storage devices 1300a and 1300b can serve as non-volatile storage devices configured to store data regardless of whether power is supplied, and have a larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b can include storage controllers (STRG CTRL) 1310a and 1310b and NVMs (non-volatile memories) 1320a and 1320b, respectively, the NVMs 1320a and 1320b being configured to store data via control of the storage controllers 1310a and 1310b. Although the NVMs 1320a and 1320b can include flash memories having a two-dimensional (2D) structure or a three-dimensional (3D) V-NAND structure, the NVMs 1320a and 1320b can include other types of NVMs, such as PRAM and / or RRAM, etc.

[0052] Storage devices 1300a and 1300b may be physically separate from the main processor 1100 and included in the system 1000, or implemented in the same package as the main processor 1100. Additionally, storage devices 1300a and 1300b may be of the type of solid-state devices (SSDs) or memory cards, and may be removably coupled to other components of the system 1000 via an interface such as connection interface 1480, which will be described later. Storage devices 1300a and 1300b may be devices that apply (e.g., include) standard protocols such as Universal Flash Memory (UFS), Embedded Multimedia Card (eMMC), or NVMe, but are not limited thereto.

[0053] Image capture device 1410 can capture still images or moving images. Image capture device 1410 may include a camera, a portable video camera, and / or a webcam, etc.

[0054] User input device 1420 can receive various types of data input by the user of system 1000, and includes touchpad, keypad, keyboard, mouse and microphone, etc.

[0055] Sensor 1430 can detect various types of physical quantities that can be obtained from outside the system 1000 and convert the detected physical quantities into electrical signals. Sensor 1430 may include temperature sensors, pressure sensors, illuminance sensors, position sensors, acceleration sensors, biosensors, and / or gyroscope sensors, etc.

[0056] The communication device 1440 can send and receive signals between other devices outside the system 1000 according to various communication protocols. The communication device 1440 may include an antenna, transceiver, or modem, etc.

[0057] The display 1450 and the speaker 1460 can be used as output devices and are configured to output visual and auditory information to the user of the system 1000, respectively.

[0058] The power supply device 1470 can suitably convert power supplied from a battery (not shown) embedded in the system 1000 and / or an external power source, and supply the converted power to each component of the system 1000.

[0059] The connection interface 1480 can provide a connection between the system 1000 and an external device that is connected to the system 1000 and capable of transmitting and receiving data to and from the system 1000. The connection interface 1480 can be implemented by using various interface schemes, such as an advanced technology attachment (ATA), a serial ATA (SATA), an external SATA (e-SATA), a small computer small interface (SCSI), a serial attached SCSI (SAS), a peripheral component interconnect (PCI), a PCI express (PCIe), an NVMe, an IEEE 1394, a universal serial bus (USB) interface, a secure digital (SD) card interface, a multi media card (MMC) interface, an eMMC interface, a UFS interface, an embedded UFS (eUFS) interface, and a compact flash (CF) card interface, etc.

[0060] It will be appreciated that the system 1000 can be configured to perform any method, function, etc. according to any example embodiment including an iterative programming operation to program a non-volatile memory device (e.g., at least one of NVM 1320a and / or NVM 1320b) and an iterative anomaly detection procedure to execute an iterative model to determine at least a probability value each indicative of a probability associated with occurrence of at least one programming anomaly in one or more programming phases of the iterative programming operation, and in some example embodiments, to determine whether at least one programming anomaly has occurred in one or more programming phases of the iterative programming operation, e.g., based on determining that at least one probability value at least satisfies a corresponding threshold probability value. For example, the system 1000 can include a memory (e.g., memory 1200a and / or 1200b) storing a program of instructions and a processor (e.g., main processor 1100) configured to execute the program of instructions to implement any method, function, etc. of one or more apparatuses according to any example embodiment including an iterative anomaly detection procedure 900 according to any example embodiment including at least one iterative model 910 according to any example embodiment.

[0061] Figure 2 is a block diagram of a storage device 200 according to some example embodiments.

[0062] The storage device 200 can include a storage controller 210 and a non-volatile memory device NVM 220. For example, the storage device 200 can include at least one of a storage controller 1310a and / or 1310b as shown in Figure 1 so that the storage controller 210 can be at least one of a storage controller 1310a and / or 1310b as shown in Figure 1 and the NVM 220 can be at least one of a NVM 1320a and / or 1320b as shown in Figure 1 ​

[0063] The storage device 200 can include a storage medium configured to store data in response to a request from a host. As an example, the storage device 200 can include at least one of an SSD, an embedded memory, and a removable external memory. When the storage device 200 is an SSD, the storage device 200 can be a device conforming to an NVMe standard. When the storage device 200 is an embedded memory or an external memory, the storage device 200 can be a device conforming to a UFS standard or an eMMC standard. The storage device 200 can generate and transmit a packet according to a standard protocol adopted.

[0064] When the NVM 220 of the storage device 200 includes a flash memory, the flash memory can include a 2D NAND storage array or a 3D (or vertical) NAND (VNAND) storage array. As another example, the storage device 200 can include various other kinds of NVMs. For example, the storage device 200 can include a magnetic RAM (MRAM), a spin-transfer torque MRAM, a conductive-bridge RAM (CBRAM), a ferroelectric RAM (FRAM), a PRAM, a RRAM, and various other kinds of memories.

[0065] The storage controller 210 can include a host interface 211, a memory interface 212, and a CPU 213. In addition, the storage controller 210 can further include a flash translation layer (FTL), a packet manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an advanced encryption standard (AES) engine 218. The storage controller 210 can further include a working memory (not shown) in which the FTL 214 is loaded. The CPU 213 can execute the FTL 214 to control data write and read operations on the NVM 220.

[0066] The host interface 211 can transmit packets to a host (not shown) (e.g., a main processor 1100 shown in FIG. 1) and receive packets from the host (e.g., the main processor 1100 shown in FIG. 1). The packets transmitted from the host to the host interface 211 can include a command or data to be written to the NVM 220, etc. The packets transmitted from the host interface 211 to the host can include a response to the command or data read from the NVM 220. The memory interface 212 can transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory interface 212 can be configured to conform to a standard protocol such as Toggle or Open NAND Flash Interface (ONFI). Figure 1 The host interface 211 can transmit packets to a host (not shown) (e.g., a main processor 1100 shown in FIG. 1) and receive packets from the host (e.g., the main processor 1100 shown in FIG. 1). The packets transmitted from the host to the host interface 211 can include a command or data to be written to the NVM 220, etc. The packets transmitted from the host interface 211 to the host can include a response to the command or data read from the NVM 220. The memory interface 212 can transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory interface 212 can be configured to conform to a standard protocol such as Toggle or Open NAND Flash Interface (ONFI). Figure 1 The host interface 211 can transmit packets to a host (not shown) (e.g., a main processor 1100 shown in FIG. 1) and receive packets from the host (e.g., the main processor 1100 shown in FIG. 1). The packets transmitted from the host to the host interface 211 can include a command or data to be written to the NVM 220, etc. The packets transmitted from the host interface 211 to the host can include a response to the command or data read from the NVM 220. The memory interface 212 can transmit data to be written to the NVM 220 to the NVM 220 or receive data read from the NVM 220. The memory interface 212 can be configured to conform to a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

[0067] The FTL 214 can perform various functions, such as an address mapping operation, a wear leveling operation, and a garbage collection operation. The address mapping operation can be an operation of converting a logical address received from the host into a physical address used to actually store data in the NVM 220. The wear leveling operation can be a technique for preventing over-degradation of a specific block by allowing blocks of the NVM 220 to be used uniformly. As an example, the wear leveling operation can be implemented using a firmware technique that balances erase counts of physical blocks. The garbage collection operation can be a technique for securing available capacity in the NVM 220 by erasing an existing block after copying valid data of the existing block to a new block.

[0068] The packet manager 215 can generate a packet according to a protocol of an interface of the consenting host, or parse various types of information from a packet received from the host. In addition, the buffer memory 216 can temporarily store data to be written to the NVM 220 or data to be read from the NVM 220. Although the buffer memory 216 can be a component included in the storage controller 210, the buffer memory 216 can be external to the storage controller 210.

[0069] The ECC engine 217 can perform an error detection and correction operation on read data read from the NVM 220. More specifically, the ECC engine 217 can generate parity bits for write data to be written to the NVM 220, and the generated parity bits can be stored in the NVM 220 together with the write data. During reading of data from the NVM 220, the ECC engine 217 can correct errors in the read data by using the read data and the parity bits read from the NVM 220, and output the read data corrected for errors.

[0070] The AES engine 218 can perform at least one of an encryption operation or a decryption operation on data input to the storage controller 210 by using a symmetric key algorithm.

[0071] In some example embodiments, the ECC engine 217 can include an ECC encoding circuit and an ECC decoding circuit. In response to the ECC control signal ECC CON that can include a signal indicating that at least one programming exception occurrence is detected in the iterative programming operation performed on at least one selected word line of the memory cell array of the NVM 220, the ECC encoding circuit can generate parity bits ECCP[0:7] for write data WData[0:63] to be written to memory cells of the memory cell array of the NVM 220. The parity bits ECCP[0:7] can be stored in an ECC cell array of the ECC engine. According to some example embodiments, in response to the ECC control signal ECC CON, the ECC encoding circuit 510 can generate parity bits ECCP[0:7] for write data WData[0:63] to be written to memory cells of the memory cell array of the NVM 220 that include defective cells, where the defective cells can be determined to be one or more memory cells connected to the selected word line on which the iterative programming operation is determined to have at least one programming exception.

[0072] In response to the ECC control signal ECC CON, the ECC decoding circuit can correct error bit data by using read data RData[0:63] read from memory cells of the memory cell array and the parity bits ECCP[0:7] read from the ECC cell array, and output error corrected data [0:63]. According to some example embodiments, in response to the ECC control signal ECC CON, the ECC decoding circuit can correct error bit data by using read data RData[0:63] read from memory cells of the memory cell array that include defective cells and the parity bits ECCP[0:7] read from the ECC cell array, and output error corrected data [0:63].

[0073] It will be appreciated that the storage device 200 can be configured to perform any of the methods, functions, etc. in accordance with any of the example embodiments including the iterative programming operation and the iterative anomaly checking procedure, where the iterative programming operation is performed to program a non-volatile memory device (e.g., NVM 220), the iterative anomaly detection procedure is performed to execute an iterative model to determine at least a probability value each indicative of a probability associated with occurrence of at least one programming anomaly in one or more programming phases of the iterative programming operation, and in some example embodiments, determine whether at least one programming anomaly has occurred in one or more programming phases of the iterative programming operation, e.g., based on determining that at least one probability value at least satisfies a corresponding threshold probability value. For example, the storage device 200 (e.g., the storage controller 210) can include a memory (e.g., a working memory (not shown) of the storage controller 210, which can include a SSD storage device) storing an instruction program and a processor (e.g., the CPU 213) configured to execute the instruction program to implement any of the methods, functions of one or more devices, etc. in accordance with any of the example embodiments including the iterative anomaly detection procedure 900 including at least one iterative model 910 in accordance with any of the example embodiments.

[0074] Figure 3 is a block diagram of a storage device 15 in accordance with some example embodiments.

[0075] Referring to Figure 3 , the storage device 15 can include a memory device 17 and a memory controller 16. For example, the storage device 15 can include at least one of a storage device 1300a and / or 1300b as shown in Figure 1 , such that the memory controller can be at least one of a storage controller 1310a and / or 1310b as shown in Figure 1 , and the memory device 17 can be at least one of a NVM 1320a and / or 1320b as shown in Figure 1 . The storage device 15 can support multiple channels CH1 to CHm, and the memory device 17 can be connected to the memory controller 16 through the multiple channels CH1 to CHm. For example, the storage device 15 can be implemented as a storage device such as a SSD.

[0076] The memory device 17 can include a plurality of NVM devices NVM11 to NVMmn, where n and m can each independently be a positive integer. Each of the NVM devices NVM11 to NVMmn can be connected to one of a plurality of channels CH1 to CHm through a way corresponding thereto. For example, the NVM devices NVM11 to NVM1n can be connected to the first channel CH1 through ways W11 to W1n, and the NVM devices NVM21 to NVM2n can be connected to the second channel CH2 through ways W21 to W2n. In some example embodiments, each of the NVM devices NVM11 to NVMmn can be implemented as an arbitrary storage unit that can be operated according to a separate command from the memory controller 16. For example, each of the NVM devices NVM11 to NVMmn can be implemented as a chip or a die, but example embodiments are not limited thereto.

[0077] The memory controller 16 can transmit and receive signals to and from the memory device 17 through the plurality of channels CH1 to CHm. For example, the memory controller 16 can transmit commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 17 through the channels CH1 to CHm, or receive data DATAa to DATAm from the memory device 17.

[0078] The memory controller 16 can select one from the NVM devices NVM11 to NVMmn connected to each of the channels CH1 to CHm through a corresponding one of the channels CH1 to CHm, and transmit and receive signals to and from the selected NVM device. For example, the memory controller 16 can select the NVM device NVM11 from the NVM devices NVM11 to NVM1n connected to the first channel CH1. The memory controller 16 can transmit a command CMDa, an address ADDRa, and data DATAa to the selected NVM device NVM11 through the first channel CH1, or receive data DATAa from the selected NVM device NVM11.

[0079] The memory controller 16 can transmit and receive signals to and from the memory device 17 through different channels in parallel. For example, the memory controller 16 can transmit a command CMDb to the memory device 17 through the second channel CH2 while transmitting a command CMDa to the memory device 17 through the first channel CH1. For example, the memory controller 16 can receive data DATAb from the memory device 17 through the second channel CH2 while receiving data DATAa from the memory device 17 through the first channel CH1.

[0080] The memory controller 16 can control all operations of the memory device 17. The memory controller 16 can transmit a signal to the channels CH1 to CHm and control each of the NVM devices NVM11 to NVMmn connected to the channels CH1 to CHm. For example, the memory controller 16 can transmit a command CMDa and an address ADDRa to the first channel CH1 and control one selected from the NVM devices NVM11 to NVM1n.

[0081] Each of the NVM devices NVM11 to NVMmn can be operated via control of the memory controller 16. For example, the NVM device NVM11 can program data DATAa based on the command CMDa, the address ADDRa, and the data DATAa provided to the first channel CH1. For example, the NVM device NVM21 can read data DATAb based on the command CMDb and the address ADDDb provided to the second channel CH2 and transmit the read data DATAb to the memory controller 16.

[0082] Although Figure 3 An example is shown in which the memory device 17 communicates with the memory controller 16 through m channels and includes n NVM devices corresponding to each channel, but various changes can be made to the number of channels and the number of NVM devices connected to one channel.

[0083] It will be appreciated that the storage apparatus 15 can be configured to perform any of the methods, functions, etc. according to any of the example embodiments including an iterative programming operation to program a non-volatile memory device (the memory device 17) and an iterative anomaly detection procedure to perform an iterative model to determine at least a probability value each indicative of a probability associated with occurrence of at least one programming anomaly in one or more programming phases of the iterative programming operation, and in some example embodiments, determine whether at least one programming anomaly has occurred in one or more programming phases of the iterative programming operation, e.g., based on determining that at least one probability value at least satisfies a corresponding threshold probability value. For example, the storage apparatus 15 (e.g., the memory controller 16) can include a memory (e.g., a working memory (not shown) of the memory controller 16, which can include a SSD storage apparatus) storing an instruction program and a processor (e.g., a CPU (not shown) of the memory controller 16) configured to execute the instruction program to implement any of the methods, functions of one or more apparatuses, etc. according to any of the example embodiments including the iterative anomaly detection procedure 900 including at least one iterative model 910 according to any of the example embodiments.

[0084] Figure 4 is a block diagram of a memory device 300 according to some example embodiments.

[0085] Referring to Figure 4 , the memory device 300 can include a control logic circuit 320, a memory cell array 330, a page buffer 340, a voltage generator 350, and a row decoder 360. The memory device 300 can further include a memory interface circuit 310. In addition, the memory device 300 can further include column logic, a pre-decoder, a temperature sensor, a command decoder, and / or an address decoder. For example, the memory device 300 can include a memory device (e.g., a non-volatile memory device or NVM), and can include or be included in at least one of a memory device 17 as shown in Figure 3 , an NVM 220 as shown in Figure 2 , and / or at least one of NVMs 1320a and / or 1320b as shown in Figure 1 . The memory device 300 can include a non-volatile memory device (e.g., a NAND flash memory device), but example embodiments are not limited thereto.

[0086] The control logic circuit 320 can control all various operations of the memory device 300. The control logic circuit 320 can output various control signals in response to a command CMD and / or an address ADDR from the memory interface circuit 310. For example, the control logic circuit 320 can output a control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

[0087] The control logic circuit 320 can receive a command CMD and an address ADDR from the outside (e.g., from a memory controller via the memory interface circuit 310), and control erase, program, and read operations of the non-volatile memory device 300 based on the command CMD and the address ADDR. The erase operation can include performing a series of erase cycles, and the program operation can include performing a series of program cycles (also referred to herein interchangeably as an iterative program operation including a plurality of program phases). Each program phase can include a program operation (e.g., a programming operation) and a verify operation. Each erase cycle can include an erase operation and an erase verify operation. The read operation can include a normal read operation and a data recovery read operation.

[0088] The memory cell array 330 can include a plurality of memory blocks BLK1 through BLKz (where z is a positive integer), and each of the plurality of memory blocks BLK1 through BLKz can include a plurality of memory cells. Each of the memory blocks BLK1 through BLKz can represent a plurality of memory cells connected to a same word line WL. The memory cell array 330 can be connected to the page buffer 340 through bit lines BL and to the row decoder 360 through word lines WL, string selection lines SSL, and ground selection lines GSL.

[0089] In some example embodiments, the memory cell array 330 can include a 3D memory cell array including a plurality of NAND strings. Each NAND string can include a plurality of memory cells connected to word lines vertically stacked on a substrate, respectively. The disclosures of U.S. Patent Nos. 7,679,133, 8,553,466, 8,654,587, No. 8,559,235, and No. 9,536,970 are hereby incorporated by reference. In some example embodiments, the memory cell array 330 can include a 2D memory cell array including a plurality of NAND strings arranged in a row direction and a column direction.

[0090] The control logic circuit 320 can control the voltage generator 350 to generate various operating voltages (e.g., one or more of a plurality of program voltages, a plurality of verify voltages, a plurality of read voltages, and a plurality of erase voltages) required / used for the operation of the memory device 300. The control logic circuit 320 can receive a command CMD from an external device (e.g., a memory controller and / or a host). The control logic circuit 320 can control various components of the memory device 300 based on the received command CMD.

[0091] The page buffer 340 can include a plurality of page buffers PB1 through PBn (where n is an integer greater than or equal to 3) that can be connected to memory cells through a plurality of bit lines BL, respectively. The page buffer 340 can select at least one of the plurality of bit lines BL in response to a column address Y-ADDR. The page buffer 340 can operate as a write driver or a sense amplifier depending on an operation mode. For example, during a program operation, the page buffer 340 can apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer 340 can sense a current or a voltage of the selected bit line BL and sense data stored in a memory cell.

[0092] The voltage generator 350 can generate various voltages for program, read, and erase operations based on a voltage control signal CTRL vol. For example, the voltage generator 350 can generate a program voltage, a read voltage, a program verify voltage, and an erase voltage as a word line voltage VWL.

[0093] The voltage generator 350 can generate a plurality of word line voltages (e.g., a program voltage Vpgm (also denoted as PGM herein), a verify voltage Vvfy, a normal read voltage Vread) required for program, erase, and verify / normal read operations of the memory cell transistors. In addition, the voltage generator 350 can generate a bulk voltage Vbulk to be supplied to a bulk (substrate) in which the memory cell transistors are formed. The control logic circuit 320 can be configured to control the voltage generator 350 to generate a series of program voltages (Vpgm) by using an incremental step pulse programming (ISPP) in a program operation.

[0094] The row decoder 360 can select one of a plurality of word lines WL and select one of a plurality of string select lines SSL in response to a row address X-ADDR. For example, the row decoder 360 can apply a program voltage and a program verify voltage to the selected word line WL during a program operation, and apply a read voltage to the selected word line WL during a read operation.

[0095] In some example embodiments, the memory device 300 according to example embodiments can store data in the memory cell array 330 through a plurality of or a series of program loops (also referred to as program phases herein interchangeably). Each of the plurality of program loops (e.g., a given nth program phase) can include a program operation (e.g., an nth program phase, also referred to as a program step) in which a program voltage is applied to a selected word line, and a verify operation (also referred to as a verify step, a check step, etc. herein) in which a verify voltage is applied to the selected word line. In one verify operation, at least one program state can be verified. In some example embodiments, the memory device 300 can perform an operation for selecting a target program state (e.g., a target dump operation) during a bit line precharge operation. In this case, the total program time of the memory device 300 can be shortened. The operation of the memory device 300 according to some example embodiments will be described with reference to the accompanying drawings.

[0096] The control logic circuit 320 controls the overall operation related to the programming, erasing, and verify / normal read operations of the memory device 300. During the time interval in which a program is being performed, the control logic circuit 320 is configured to cause, for example, based on the control voltage generator 350, a program voltage Vpgm to be supplied (e.g., applied) to the selected word line, a bit line voltage Vb1 to be supplied (e.g., applied) to the selected bit line, and a bulk voltage Vbulk to be supplied (e.g., applied) to the bulk (substrate) in which the memory cell transistors are formed. The program voltage Vpgm can be generated by using an incremental step pulse programming (ISPP) method (e.g., at the voltage generator 350 based on being controlled via a command signal CTRL VOL from the control logic circuit 320). Each time a program phase is repeated, the level (e.g., amplitude) of the program voltage Vpgm is incremented by a predetermined voltage increment (AV) in steps. The number of supplies, voltage level, and voltage supply time period of the program voltage Vpgm used in the respective program phase can vary according to the control of an external device (e.g., a memory controller) or an internal device (e.g., the control logic circuit 320). Likewise, during the interval in which the control logic circuit 320 is conducting a verify read operation (e.g., a verify operation) or a normal read operation, a bias voltage for verify (e.g., a verify voltage) or a bias voltage for normal read is supplied to the selected word line and the selected bit line.

[0097] It will be appreciated that the memory device 300 can be configured to perform any of the methods, functions, etc. according to any of the example embodiments including the iterative programming operation and the iterative anomaly checking procedure, where the iterative programming operation is performed to program the non-volatile memory device (memory device 17), the iterative anomaly detection procedure is performed to execute the iterative model to determine at least the probability values each indicative of a probability associated with occurrence of at least one programming anomaly in one or more programming phases of the iterative programming operation, and in some example embodiments, determine whether at least one programming anomaly has occurred in one or more programming phases of the iterative programming operation, e.g., based on determining that at least one probability value at least satisfies a corresponding threshold probability value. For example, the memory device 300 (e.g., the control logic circuit 320) can include a memory (e.g., a working memory (not shown) of the control logic circuit 320, which can include an SSD storage) storing an instruction program and a processor (e.g., a CPU (not shown) of the control logic circuit 320) configured to execute the instruction program to implement any of the methods, functions of one or more apparatuses, etc. according to any of the example embodiments. As shown, for example, according to some example embodiments, the control logic circuit 320 can store an instruction program for implementing the iterative anomaly detection procedure 900 including at least one iterative model 910 (e.g., an RNN) in a working memory (e.g., an SSD storage) included in the control logic circuit 320, and the control logic circuit 320 can execute the stored instruction program to implement the iterative anomaly detection procedure 900 including at least one iterative model 910.

[0098] Figure 5A is a diagram illustrating a first memory block of a plurality of memory blocks included in a memory cell array 330 in Figure 4

[0099] Reference will be made to Figure 4 The first memory block BLK1 will be described. However, it will be appreciated that the remaining memory blocks included in the memory cell array 330 have a similar or identical structure to the first memory block BLK1, and / or can have a different structure, and the example embodiments are not limited thereto.

[0100] Reference will be made to Figure 4 and Figure 5A The first memory block BLK1 can include a plurality of cell strings CS11, CS12, CS21, and CS22. The plurality of cell strings CS11, CS12, CS21, and CS22 can be arranged along a row direction and a column direction.

[0101] ​The cell strings CS11, CS12, CS21, and CS22 can be connected to the same bit line. For example, the cell strings CS11 and CS21 can be connected to a first bit line BL1, and the cell strings CS12 and CS22 can be connected to a second bit line BL2. Each of the cell strings CS11, CS12, CS21, and CS22 can include a plurality of cell transistors. Each of the plurality of cell transistors can include a charge-trapping flash (CTF) memory cell, although example embodiments are not limited thereto. The plurality of cell transistors can be stacked in a height direction that is a direction perpendicular to a plane defined by a row direction and a column direction (e.g., a semiconductor substrate (not shown)).

[0102] The plurality of cell transistors of each cell string can be connected in series (e.g., from a source of one transistor to a drain of another transistor) between a corresponding bit line (e.g., BL1 or BL2) and a common source line CSL. For example, the plurality of cell transistors can include string select transistors SSTa and SSTb, dummy memory cells DMC1 and DMC2 that do not have electrical activity but can provide structural support, memory cells MC1 to MC4, and ground select transistors GSTa and GSTb. The series-connected string select transistors SSTa and SSTb can be disposed or connected between the series-connected memory cells MC1 to MC4 and the corresponding bit line (e.g., BL1 and BL2). The series-connected ground select transistors GSTa and GSTb can be disposed or connected between the series-connected memory cells MC1 to MC4 and the common source line CSL. In some example embodiments, the second dummy memory cell DMC2 can be disposed between the series-connected string select transistors SSTa and SSTb and the series-connected memory cells MC1 to MC4, and the first dummy memory cell DMC1 can be disposed between the series-connected memory cells MC1 to MC4 and the series-connected ground select transistors GSTa and GSTb.

[0103] Memory cells MC1 to MC4 of the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same height can share the same word line. For example, the first memory cells MC1 of the plurality of cell strings CS11, CS12, CS21, and CS22 can be disposed at the same height from the semiconductor substrate (not shown) and can share the first word line WL1. The second memory cells MC2 of the plurality of cell strings CS11, CS12, CS21, and CS22 can be disposed at the same height from the semiconductor substrate (not shown) and can share the second word line WL2. Similarly, the third memory cells MC3 of the plurality of cell strings CS11, CS12, CS21, and CS22 can be disposed at the same height from the semiconductor substrate (not shown) and can share the third word line WL3, and the fourth memory cells MC4 of the plurality of cell strings CS11, CS12, CS21, and CS22 can be disposed at the same height from the semiconductor substrate (not shown) and can share the fourth word line WL4.

[0104] Dummy memory cells DMC1 and DMC2 of the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same height can share the same dummy word line. For example, the first dummy memory cells DMC1 of the plurality of cell strings CS11, CS12, CS21, and CS22 can share the first dummy word line DWL1, and the second dummy memory cells DMC2 of the plurality of cell strings CS11, CS12, CS21, and CS22 can share the second dummy word line DWL2.

[0105] String selection transistors SSTa, SSTb of the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same height and the same row can share the same string selection line. For example, the string selection transistors SSTb of the cell strings CS11 and CS12 can share the string selection line SSL1b, and the string selection transistors SSTa of the cell strings CS11 and CS12 can share the string selection line SSL1a. The string selection transistors SSTb of the cell strings CS21 and CS22 can be connected to the string selection line SSL2b, and the string selection transistors SSTa of the cell strings CS21 and CS22 can be connected to the string selection line SSL2a.

[0106] Although Figure 5AAs shown in FIG. 1, the plurality of cell strings CS11, CS12, CS21, and CS22 can share the same ground select line GSL. Alternatively or additionally, at least some of the ground select transistors GSTb and GSTa among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same height can share the same ground select line. Alternatively or additionally, the ground select transistors among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same row can share the same ground select line.

[0107] As shown in FIG. 1, the plurality of cell strings CS11, CS12, CS21, and CS22 can share the same ground select line GSL. Alternatively or additionally, at least some of the ground select transistors GSTb and GSTa among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same height can share the same ground select line. Alternatively or additionally, the ground select transistors among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same row can share the same ground select line.

[0108] As shown in FIG. 1, the plurality of cell strings CS11, CS12, CS21, and CS22 can share the same ground select line GSL. Alternatively or additionally, at least some of the ground select transistors GSTb and GSTa among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same height can share the same ground select line. Alternatively or additionally, the ground select transistors among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same row can share the same ground select line. Figure 5A As shown in FIG. 1, the plurality of cell strings CS11, CS12, CS21, and CS22 can share the same ground select line GSL. Alternatively or additionally, at least some of the ground select transistors GSTb and GSTa among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same height can share the same ground select line. Alternatively or additionally, the ground select transistors among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same row can share the same ground select line.

[0109] Figure 5A As shown in FIG. 1, the plurality of cell strings CS11, CS12, CS21, and CS22 can share the same ground select line GSL. Alternatively or additionally, at least some of the ground select transistors GSTb and GSTa among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same height can share the same ground select line. Alternatively or additionally, the ground select transistors among the plurality of cell strings CS11, CS12, CS21, and CS22 that are disposed at the same row can share the same ground select line.

[0110] ​In some example embodiments, Figure 5A The first memory block BLK1 shown in FIG. 1A is merely an example. The number of cell strings can be increased or decreased, and the number of rows of cell strings and the number of columns of cell strings can be increased or decreased according to the number of cell strings. Additionally or alternatively, in the first memory block BLK1, the number of cell transistors (e.g., GST, MC, DMC, and SST) can be increased or decreased, and the height of the first memory block BLK1 can be increased or decreased according to the number of cell transistors. Additionally or alternatively, the number of lines (e.g., GSL, WL, DWL, and SSL) connected to the cell transistors can be increased or decreased according to the number of cell transistors. In some example embodiments, as the number of cell transistors of the first memory block BLK1 increases, the first memory block BLK1 can have a multi-stack structure.

[0111] Figure 5B is a diagram illustrating a memory device 600 according to some example embodiments. The memory device 600 can include at least a portion of the memory device 300 of Figure 4 the memory device 17 of Figure 3 the NVM 220, the NVMS 1320a and / or 1320b of Figure 2 or any combination thereof.

[0112] Referring to Figure 5B The memory device 600 can have a chip-to-chip (C2C) structure. The C2C structure can refer to a structure formed by manufacturing an upper chip including a cell region CELL on a first wafer, manufacturing a lower chip including a peripheral circuit region PERI on a second wafer separate from the first wafer, and then bonding the upper chip and the lower chip to each other. Here, the bonding process can include a method of electrically connecting a bonding metal formed on an uppermost metal layer of the upper chip and a bonding metal formed on an uppermost metal layer of the lower chip. For example, when the bonding metal can include copper (Cu), Cu-Cu bonding is used. However, example embodiments can not be limited thereto. For example, the bonding metal can also be formed of aluminum (Al) or tungsten (W).

[0113] Each of the peripheral circuit region PERI and the cell region CELL of the memory device 600 can include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

[0114] The peripheral circuit region (PERI) may include a first substrate 710, an interlayer insulating layer 715, a plurality of circuit elements 720a, 720b, and 720c formed on the first substrate 710, first metal layers 730a, 730b, and 730c respectively connected to the plurality of circuit elements 720a, 720b, and 720c, and second metal layers 740a, 740b, and 740c formed on the first metal layers 730a, 730b, and 730c. In some example embodiments, the first metal layers 730a, 730b, and 730c may be formed of tungsten with relatively high resistance, and the second metal layers 740a, 740b, and 740c may be formed of copper with relatively low resistance.

[0115] exist Figure 5B In some of the example embodiments shown, although first metal layers 730a, 730b, and 730c and second metal layers 740a, 740b, and 740c are shown and described, the example embodiments are not limited thereto, and one or more metal layers may be further formed on the second metal layers 740a, 740b, and 740c. At least a portion of one or more additional metal layers formed on the second metal layers 740a, 740b, and 740c may be formed of aluminum or the like, which have a lower resistivity than copper, which forms the second metal layers 740a, 740b, and 740c.

[0116] An interlayer insulating layer 715 may be disposed on a first substrate 710 and cover a plurality of circuit elements 720a, 720b and 720c, first metal layers 730a, 730b and 730c and second metal layers 740a, 740b and 740c. The interlayer insulating layer 715 may include an insulating material such as silicon oxide or silicon nitride.

[0117] Lower bonding metals 771b and 772b can be formed on the second metal layer 740b in the word line bonding area (WLBA). In the WLBA, the lower bonding metals 771b and 772b in the peripheral circuit area (PERI) can be electrically bonded to the upper bonding metals 871b and 872b in the cell area (CELL). The lower bonding metals 771b and 772b, as well as the upper bonding metals 871b and 872b, can be formed of aluminum, copper, tungsten, or the like. Furthermore, the upper bonding metals 871b and 872b in the cell area (CELL) can be referred to as first metal pads, and the lower bonding metals 771b and 772b in the peripheral circuit area (PERI) can be referred to as second metal pads.

[0118] The cell region CELL can include at least one memory block. The cell region CELL can include a second substrate 810 and a common source line 820. On the second substrate 810, a plurality of word lines 831 to 838 (i.e., 830) can be stacked in a direction (Z-axis direction) perpendicular to an upper surface of the second substrate 810. At least one string selection line and at least one ground selection line can be disposed above and below the plurality of word lines 830, respectively, and the plurality of word lines 830 can be disposed between the at least one string selection line and the at least one ground selection line.

[0119] In the bit line junction region BLBA, the channel structure CH can extend in a direction perpendicular to the upper surface of the second substrate 810 and pass through the plurality of word lines 830, the at least one string selection line, and the at least one ground selection line. The channel structure CH can include a data storage layer, a channel layer, a buried insulating layer, etc., and the channel layer can be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c can be a bit line contact, and the second metal layer 860c can be a bit line. In some example embodiments, the bit line 860c can extend in a first direction (Y-axis direction) parallel to the upper surface of the second substrate 810.

[0120] In Figure 5B In some example embodiments shown, a region in which the channel structure CH, the bit line 860c, etc., are disposed can be defined as a bit line junction region BLBA. In the bit line junction region BLBA, the bit line 860c can be electrically connected to the circuit element 720c that provides the page buffer 893 in the peripheral circuit region PERI. The bit line 860c can be connected to the upper junction metals 871c and 872c in the cell region CELL, and the upper junction metals 871c and 872c can be connected to the lower junction metals 771c and 772c connected to the circuit element 720c of the page buffer 893. In some example embodiments, since the write data of the page unit is stored in the page buffer 893, a program operation can be performed based on the page unit, and since the read data of the sub-page unit is stored in the page buffer 893, a read operation can be performed based on the sub-page unit. Also, in the program operation and the read operation, the units of data transmitted through the bit line can be different from each other.

[0121] In the word line bonding area WLBA, a plurality of word lines 830 can extend in a second direction (X-axis direction) parallel to the upper surface of the second substrate 810, and can be connected to a plurality of cell contact plugs 841 to 847 (i.e., 840). The plurality of word lines 830 and the plurality of cell contact plugs 840 can be connected to each other in pads provided by at least a portion of the plurality of word lines 830 extending in the second direction at different lengths. The first metal layer 850b and the second metal layer 860b can be sequentially connected to the upper portions of the plurality of cell contact plugs 840 connected with the plurality of word lines 830. The plurality of cell contact plugs 840 can be connected with the peripheral circuit area PERI through the upper bonding metals 871b and 872b of the cell area CELL and the lower bonding metals 771b and 772b of the peripheral circuit area PERI in the word line bonding area WLBA.

[0122] The plurality of cell contact plugs 840 can be electrically connected to the circuit elements 720b forming the row decoders 894 in the peripheral circuit area PERI. In some example embodiments, the operating voltage of the circuit elements 720b of the row decoders 894 can be different from the operating voltage of the circuit elements 720c forming the page buffer 893. For example, the operating voltage of the circuit elements 720c forming the page buffer 893 can be greater than the operating voltage of the circuit elements 720b forming the row decoders 894.

[0123] The common source line contact plug 880 can be disposed in the external pad bonding area PA. The common source line contact plug 880 can be formed of a conductive material such as a metal, a metal compound, polysilicon, etc., and can be electrically connected to the common source line 820. The first metal layer 850a and the second metal layer 860a can be sequentially stacked on the upper portion of the common source line contact plug 880. For example, a region in which the common source line contact plug 880, the first metal layer 850a, and the second metal layer 860a are disposed can be defined as the external pad bonding area PA.

[0124] The input-output pads 705 and 805 can be disposed in the external pad bonding area PA. Referring to FIG. 7, the input-output pads 705 and 805 can be disposed on the lower surface of the first substrate 710. The input-output pads 705 and 805 can be electrically connected to at least one of the plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit area PERI through the first input-output contact plug 703. The input-output pads 705 and 805 can be separated from the first substrate 710 by the lower insulating film 701. In addition, a side insulating film can be disposed between the first input-output contact plug 703 and the first substrate 710 to electrically isolate the first input-output contact plug 703 from the first substrate 710. Figure 5B A lower insulating film 701 covering the lower surface of the first substrate 710 can be formed under the first substrate 710, and a first input-output pad 705 can be formed on the lower insulating film 701. The first input-output pad 705 can be connected to at least one of a plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit area PERI through a first input-output contact plug 703, and can be separated from the first substrate 710 by the lower insulating film 701. In addition, a side insulating film can be disposed between the first input-output contact plug 703 and the first substrate 710 to electrically isolate the first input-output contact plug 703 from the first substrate 710.

[0125] Referring to Figure 5B An upper insulating film 801 covering an upper surface of the second substrate 810 can be formed on the second substrate 810, and a second input-output pad 805 can be provided on the upper insulating film 801. The second input-output pad 805 can be connected to at least one of the plurality of circuit elements 720a, 720b, and 720c provided in the peripheral circuit region PERI through a second input-output contact plug 803. In some example embodiments, the second input-output contact plug 803 is electrically connected to the circuit element 720a.

[0126] According to some example embodiments, the second substrate 810 and the common source line 820 can not be provided in a region in which the second input-output contact plug 803 is provided. In addition, the second input-output pad 805 can not overlap the word line 830 in the third direction (Z-axis direction). Referring to Figure 5B , the second input-output contact plug 803 can be separated from the second substrate 810 in a direction parallel to the upper surface of the second substrate 810 and can pass through the interlayer insulating layer 815 of the cell region CELL to be connected to the second input-output pad 805.

[0127] According to some example embodiments, the first input-output pad 705 and the second input-output pad 805 can be selectively formed. For example, the memory device 600 can include only the first input-output pad 705 provided on the first substrate 710 or the second input-output pad 805 provided on the second substrate 810. Alternatively, the memory device 600 can include both the first input-output pad 705 and the second input-output pad 805.

[0128] In each of the external pad bonding region PA and the bit line bonding region BLBA included in the cell region CELL and the peripheral circuit region PERI, respectively, a metal pattern provided on the uppermost metal layer can be provided as a dummy pattern or the uppermost metal layer can not exist.

[0129] In the peripheral circuit region PERI, the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI can not be connected to a contact. Similarly, in the external pad bonding region PA, an upper metal pattern 872a can be formed in the uppermost metal layer of the cell region CELL, the upper metal pattern 872a corresponding to the lower metal pattern 773a formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern 773a of the peripheral circuit region PERI.

[0130] The lower bonding metals 771b and 772b can be formed on the second metal layer 740b in the word line bonding region WLBA. In the word line bonding region WLBA, the lower bonding metals 771b and 772b of the peripheral circuit region PERI can be electrically connected to the upper bonding metals 871b and 872b of the cell region CELL by Cu-Cu bonding.

[0131] Further, in the bit line bonding region BLBA, an upper metal pattern 892 can be formed in the uppermost metal layer of the cell region CELL, the metal pattern 892 corresponding to the lower metal pattern 752 formed in the uppermost metal layer of the peripheral circuit region PERI and having the same shape as the lower metal pattern 752 of the peripheral circuit region PERI. No contact can be formed on the upper metal pattern 892 formed in the uppermost metal layer of the cell region CELL.

[0132] In some example embodiments, corresponding to a metal pattern formed in the uppermost metal layer in one of the cell region CELL and the peripheral circuit region PERI, an enhanced metal pattern having the same cross-sectional shape as the metal pattern can be formed in the uppermost metal layer in the other of the cell region CELL and the peripheral circuit region PERI. No contact can be formed on the enhanced metal pattern.

[0133] Figure 6 is a flow chart for describing an iterative programming operation for programming a non-volatile memory device according to some example embodiments. Figure 7 is a timing chart for describing an iterative programming operation for programming a non-volatile memory device according to some example embodiments. In Figure 6 and Figure 7 , the non-volatile memory device can be a memory device including Figure 1the NVM 1320a and / or 1320b therein, Figure 2 the NVM 220 therein, Figure 3 the memory device 17 therein, Figure 4 any one of non-volatile memory devices including the memory device 300 therein, any combination thereof, etc.

[0134] In some example embodiments, in Figure 6 the distribution graph of, the horizontal axis represents the threshold voltage of the memory cells of the memory device, and the vertical axis represents the number of memory cells having the corresponding threshold voltage. For example, within a block (e.g., Figure 4 any one of the memory blocks BLK1 to BLKz therein connected to a particular selected word line of the non-volatile memory device) within, and / or the number of memory cells within the semiconductor device. In some example embodiments, in Figure 7 the timing graph of, the horizontal axis represents time, and the vertical axis represents the word line voltage applied to the selected word line. For ease of description, it is assumed that each memory cell is a three-level cell storing 3 bits of data (e.g., three bits (e.g., "010") can be stored within the memory cell). However, the example embodiments are not limited thereto. For example, each memory cell can be a single-level cell (SLC) storing 1 bit, or a multi-level cell (MLC) storing, for example, 2 bits, or a quad-level cell (QLC) storing 2 or more bits. As described in more detail below, the number of latches LAT 1 to LAT 3 can be determined based on the number of bits that each memory cell can store; however, the example embodiments can be not limited thereto.

[0135] The mapping between the threshold voltage and the logical bit can be predefined and / or dynamically defined. Additionally or alternatively, memory cells having a threshold voltage less than zero volts (e.g., memory cells MC1 to MC4 (e.g., as Figure 5A shown)) can be in an erased state, and memory cells having a threshold voltage greater than zero volts (e.g., memory cells MC1 to MC4) can be in a programmed state; however, the example embodiments are not limited thereto. For example, the seventh programming state P7 can correspond to a bit value of "000" or "111"; the example embodiments are not limited thereto.

[0136] Referring to Figure 4 and Figure 6 the memory device 300 can store and / or program data in the memory cells by changing the threshold voltages of the multiple memory cells (e.g., Figure 5A MC1 to MC4 of

[0137] For example, the memory device 300 can perform a program operation (e.g., an iterative program operation as described herein) on the storage cells based on the data to be stored, e.g., a storage cell in the erase state “E” has the erase state “E” and one of the plurality of program states P1-P7. In some example embodiments, the iterative program operation can be performed in units of word lines and / or in units of pages.

[0138] In some example embodiments, after a program operation (e.g., an iterative program operation) has been performed in the non-volatile memory device, it can be determined whether the storage cell transistor is programmed correctly to have the required threshold voltage Vth that correctly indicates the stored data value. Such an operation is referred to as a verify operation (or, verify-read operation, check operation, etc.). Typically, the program operation and the verify operation form a cycle, which can also be interchangeably referred to herein as an iteration, a loop, a phase, etc., of the program operation, and such a cycle is repeated a certain number of times. Accordingly, the execution of a certain number of program cycles can be interchangeably referred to as a certain number of program phases (e.g., program phases iteratively executed) of performing an iterative program operation. For example, after a storage cell transistor is programmed, it is determined whether the threshold voltage Vth of the programmed storage cell transistor is higher than a certain verify voltage (also referred to as a verify-read voltage, which is also referred to herein as a verify voltage V l ) based on a verify voltage (e.g., a verify-read voltage) applied to the selected word line. If the threshold voltage Vth of the programmed storage cell transistor is determined to be higher than the verify-read voltage (e.g., V l ), a re-program operation of the storage cell transistor is not performed, and the next cycle is cancelled. Such a storage cell transistor can then be considered as a correctly programmed cell. On the other hand, if the threshold voltage Vth of the programmed storage cell transistor is determined to be lower than the verify-read voltage, a re-program operation of the storage cell transistor is performed in the next cycle. The number of programmed cells can gradually increase with the repetition of the program cycle. In other words, the number of storage cell transistors to be programmed (or the number of bits to be programmed) can gradually decrease with the repetition of the program cycle.

[0139] In some example embodiments, the memory device 300 can perform the iterative program operation based on an incremental step pulse programming (ISPP) scheme. For example, as described in more detail below, the memory device 300 can perform the iterative program operation based on a plurality of program pulses (e.g., program pulses P1-P7) applied to the storage cells in the memory device 300. Figure 7As shown, the memory device 300 can perform an iterative program operation through a sequence of a first program level PL1 to an nth program level PLn (also referred to herein interchangeably as program loops). Each of the first program level PL1 to the nth program level PLn can include a program step (also referred to herein interchangeably as a program operation) of applying a program voltage to a selected word line, and / or a subsequent verify step (also referred to herein interchangeably as a verify operation) of verifying a program state of a storage unit.

[0140] For example, the memory device 300 can perform a first program level PL1. The first program level PL1 can include a first program step and a first verify step VFY1. In the first program step, a first program voltage PGM1 can be applied to a selected word line to change a threshold voltage of a storage unit connected to the selected word line. In the first verify step VFY1, one or more of a plurality of verify voltages VF1 to VF7 can be sequentially applied to the selected word line to verify a program state of the storage unit connected to the selected word line.

[0141] After (e.g., after completing the first verify step VFY1), the memory device 300 can perform a second program level PL2. The second program level PL2 can include a second program step and / or a subsequent second verify step VFY2. In the second program step, a second program voltage PGM2 can be applied to the selected word line to change the threshold voltage of the storage unit connected to the selected word line. In the second verify step VFY2, one or more of the plurality of verify voltages VF1 to VF7 can be sequentially applied to the selected word line to verify the program state of the storage unit connected to the selected word line.

[0142] After (e.g., after completing the second verify step VFY2), the memory device 300 can perform an nth program level PLn. The nth program level PLn can include an nth program step and / or a subsequent nth verify step VFYn. In the nth program step, an nth program voltage PGMn can be applied to the selected word line to change the threshold voltage of the storage unit connected to the selected word line. In the nth verify step VFYn, one or more of the plurality of verify voltages VF1 to VF7 can be sequentially applied to the selected word line to verify the program state of the storage unit connected to the selected word line.

[0143] In some example embodiments, the amplitude of the program voltage applied to the selected word line can remain constant or can increase as the programming phase is repeatedly (e.g., iteratively) performed. For example, the amplitude of the second program voltage PGM2 can be greater than the first program voltage PGM1 by a given level. The amplitude of the nth program voltage PGMn can be greater than the program voltage of the (n-1)th programming phase by a given level. In each programming phase, the program voltage can be set to a given level (e.g., a given amplitude) or can vary depending on the state of the storage unit.

[0144] In some example embodiments, the storage units can be selectively verified in the verify step depending on the programming phase. For example, in the first verify step VFY1 of the first programming phase PL1, the storage units corresponding to the first program state P1 and the second program state P2 can be verified. In this case, the first verify step VFY1 can be performed by selectively pre-charging the bit lines connected to the storage units corresponding to the first program state P1 and the second program state P2, and sequentially applying the first verify voltage VF1 and the second verify voltage VF2 to the selected word line. In more detail, to verify the storage units corresponding to the first program state P1, the memory device 300 can selectively pre-charge the bit lines connected to the storage units corresponding to the first program state P1, and can apply the first verify voltage VF1 for verifying the first program state P1 to the selected word line. Thereafter, to verify the storage units corresponding to the second program state P2, the memory device 300 can selectively pre-charge the bit lines connected to the storage units corresponding to the second program state P2, and can apply the second verify voltage VF2 for verifying the second program state P2 to the selected word line.

[0145] Hereinafter, to more easily describe some example embodiments of the inventive concept, the terms "first to seventh verify operations" are used. The first verify operation can indicate an operation of verifying the storage units corresponding to the first program state P1 or to be programmed to the first program state P1 from among the storage units connected to the selected word line. Similarly, the second to seventh verify operations can indicate operations of verifying the storage units corresponding to the second to seventh program states P2 to P7, or to be programmed to the second to seventh program states P2 to P7, from among the storage units connected to the selected word line. For example, one verify step included in one programming phase can include one or more of the first to seventh verify operations.

[0146] Accordingly, it will be appreciated that a given nth programming phase can include performing a set of L verify operations on the plurality of memory cells connected to the selected word line, each verify operation associated with a particular verify voltage, where "L" can be any positive integer and can be the same as or different from the value of "n" (e.g., can be independent of the value of "n"). In some example embodiments, the same number "L" of verify operations are performed in each individual programming phase of the sequence of 1st programming phase through nth programming phase (herein, referred to interchangeably as first programming phase through nth programming phase).

[0147] In some example embodiments, various variations can be made to the order of performing the verify operations included in one of the first verify operation through seventh verify operation. For example, in one verify step, when the fifth verify operation through seventh verify operation are performed, the fifth verify operation through seventh verify operation can be performed in the order of fifth verify operation, sixth verify operation and seventh verify operation, in the order of seventh verify operation, sixth verify operation and fifth verify operation, or in any order. The above terms are for the convenience of describing some example embodiments, and it will be appreciated that the scope and spirit of the example embodiments are not limited by these terms.

[0148] In the second verify step VFY2 of the second programming phase PL2, the first verify operation through third verify operation can be performed. For example, in the second verify step VFY2, the first verify operation through third verify operation can be performed sequentially on the memory cells having the first programming state through third programming state P1, P2 and P3 among the memory cells connected to the selected word line. Similarly, in the nth verify step VFYn of the nth programming phase PLn, the fifth verify operation through seventh verify operation can be performed. For example, in the nth verify step VFYn, the fifth verify operation through seventh verify operation can be performed sequentially on the memory cells having the fifth programming state through seventh programming state P5, P6 and P7 among the memory cells connected to the selected word line.

[0149] As described above, in the verify steps VFY1 through VFYn of the plurality of programming phases PL1 through PLn, the verify operations can be performed on some of the memory cells connected to the selected word line according to the relevant programming state. In this case, the bit lines corresponding to some of the memory cells can be selectively pre-charged only to perform the verify operations on some of the memory cells.

[0150] For example, the memory device 300 can perform the fifth to seventh verify operations in the nth verify step VFYn. In this case, in the seventh verify operation, the memory device 300 can selectively pre-charge the bit lines connected to the memory cells corresponding to the seventh program state P7 through a dump operation of a latch included in the page buffer circuit 340, and after the seventh verify operation is completed, the memory device 300 can perform the sixth verify operation.

[0151] In some example embodiments, the memory device 300 according to some example embodiments can perform a dump operation for selectively pre-charging the bit lines connected to the memory cells corresponding to the sixth program state P6 during the bit line pre-charge operation in the seventh verify operation. In other words, during the bit line pre-charge period of the current verify operation, a dump operation for selecting the bit lines to be pre-charged in the next verify operation can be performed. In this case, the total program time can be shortened.

[0152] In some example embodiments, the above-described program scheme is merely an example, and example embodiments are not limited thereto. For example, the memory device 300 can perform the word line or page-based program operation in various schemes (e.g., a shadow program scheme, a fast program scheme, and a reprogram scheme).

[0153] Figure 8 A measured program rate of a plurality of iterative program operations performed on a non-volatile memory device according to some example embodiments is shown.

[0154] In some example embodiments, still referring to the memory device 300 in Figure 4 During the iterative program operation on at least one selected word line of the non-volatile memory device, one or more errors (also referred to as one or more program exceptions, one or more program errors, etc.) can occur. Such program exceptions can generally be detected based on detecting that the number of memory cells connected to the selected word line that have reached a desired verify level (e.g., the number of memory cells having a threshold voltage equal to or greater than a particular verify voltage) is less than a particular threshold (which can be stored in the memory of the device) after the final program phase of the iterative program operation is completed. In response to detecting such a program exception, it can be determined that the iterative program operation has failed, and in response to such a determination, a recovery action including a corrective action and / or various error correction operations can be performed, which can include marking the selected word line on which the iterative program operation was performed, and the memory cells (e.g., blocks) connected thereto, as a bad block (e.g., Figure 4 BLK1 in Figure 4BLK2 in the middle), and in the newly allocated address (e.g., Figure 4 Repeat the iterative programming operation at BLK2).

[0155] In some example embodiments, and at least as shown Figure 11 As shown, an iterative anomaly detection procedure 900 is executed to determine whether at least one programming anomaly has occurred in at least the first to the nth programming stages (e.g., first to nth programming stages) of an iterative programming operation 800 with N programming stages, where N is a positive integer and "n" is a positive integer between 1 and N. The iterative anomaly detection procedure 900 may be executed at least partially during the iterative programming operation 800 (e.g., before the completion of the final programming stage N of the iterative programming operation). For example, the iterative anomaly detection procedure 900 may include applying the result of a verification step (e.g., a verification operation) of a given (nth) programming stage of the iterative programming operation 800 to a corresponding (nth) model stage of the iterative model 910 using the result of the given (nth) programming stage, to generate an output that can be used to determine whether at least one programming anomaly (e.g., at least one programming anomaly in the first to nth programming stages) has occurred in the iterative programming operation prior to at least the given (nth) programming stage. In some example embodiments, the model phases of iterative model 910 (also referred to as model iteration, model loop, model repetition, model unit, etc.) are executed in response to the individual programming phases being executed in iterative programming operation 800, so that the individual model phases of iterative anomaly detection procedure 900 can be executed in response to each programming phase.

[0156] Accordingly, the iterative anomaly detection program 900 can detect programming anomalies in the iterative programming operation before the completion of a predetermined "N" programming stages of the iterative programming operation 800. Therefore, if anomaly detection is not performed until after the final programming stage is completed, recovery actions (e.g., terminating the programming operation, generating an alarm, performing a correction operation, etc.) can be initiated before the time step of the final "N"th programming stage of the programming operation. For example, if the iterative anomaly detection program 900 determines that at least one programming anomaly has occurred in the iterative programming operation, the iterative programming operation 800 in which the programming anomaly has been determined to have occurred (also referred to herein as a faulty programming operation) can be terminated "early," thereby also enabling "early" initiation and completion of recovery from the programming anomaly. As a result, the apparatus that executes the iterative anomaly detection program 900 and the iterative programming operation 800 together (e.g., executes at least...) Figure 11 The method 1400 shown can detect programming exceptions more quickly, thereby enabling a faster response to programming exceptions and thus a faster execution of corrective actions to recover from identified programming exceptions. Therefore, by configuring the storage device to recover from programming exceptions more quickly during iterative programming operations, the performance of the storage device can be improved.

[0157] In some example embodiments, the iterative anomaly detection procedure 900 determines whether at least one programming anomaly has occurred in the 1st programming phase through the nth programming phase of the iterative programming operation based on determining a probability (also referred to herein as a“probability value”) associated with the occurrence of at least one programming anomaly in the 1st programming phase through the nth programming phase of the iterative programming operation. The probability value can indicate that the programming rate of the iterative programming operation 800 indicates a likelihood that the 1st programming phase through the nth programming phase of the iterative programming operation 800 is free of anomalies. Alternatively or additionally, the probability value can indicate that the programming rate of the iterative programming operation indicates a likelihood that at least one programming anomaly has occurred during the 1st programming phase through the nth programming phase. The probability value can be determined based on implementing the iterative model 910 to process data generated based on performing the 1st programming phase through the nth programming phase to determine how“unusual” the programming rate of the iterative programming operation 800 is at least at the nth programming phase compared to a non-faulty or“standard” programming rate. For example, the probability value can indicate a statistical variance of the iterative programming operation 800 in a probability distribution (e.g., a conditional probability distribution), where the variance indicates whether the iterative programming operation 800 is“unusual” to indicate the occurrence or absence of a programming anomaly in the iterative programming operation 800. The probability value can be compared to a threshold probability value to determine the occurrence of at least one anomaly based on whether the probability value at least satisfies the threshold probability value.

[0158] For example, Figure 8 A plurality of typical (e.g., non-faulty, non-anomalous, anomaly-free, “standard,” etc.) programming rates 700 are shown as a plurality of ranks or sequences of the number of cells having a threshold voltage equal to or greater than a particular verify voltage Vvfy (e.g., a verify level) at each of the pulse indices 1 through 8 in each of a plurality of iterative programming operations. As shown, in a standard (non-anomalous) iterative programming operation, the number of cells having a threshold voltage Vth equal to or greater than a particular verify voltage Vvfy (such that the cells are“programmed” at a given programming phase“n”) is denoted herein as Figure 8 l Figure 8 The typical programming rates 700 in each of the plurality of iterative programming operations are each shown as a separate dashed sequence of verify result values measured by the non-volatile memory device at each of the programming phases 1 through 8 during the iterative programming operation (including at least 8 programming phases, and performed to program a particular non-volatile memory device having a particular number (e.g., more than 1010 5 ) of memory cells) is shown as a solid line sequence of verify result values measured by the non-volatile memory device at each of the programming phases 1 through 8 during the iterative programming operation (including at least 8 programming phases, and performed to program a particular non-volatile memory device having a particular number (e.g., more than 1010 ​​Memory device. The non-volatile memory device from which the typical program rate 700 is measured can be a triple-level cell (TLC) flash memory device having a particular number (e.g., more than 10 5 ) of memory cells.

[0159] As shown, the typical program rate 700 of a standard iterative program operation performed to program a particular non-volatile memory device exhibits a relatively similar shape and progression of programmed cells in program stages 1 through 8, where the typical program rate 700 of the standard iterative program operation is shown to rapidly increase at a similar rate in the 8 program stages of the iterative program operation presented in Figure 8 In some example embodiments, it will be appreciated that a “faulty” iterative program operation having at least one program anomaly can have a program rate that is significantly different from the program rate of a standard (e.g., non-faulty) iterative program operation. The iteration anomaly detection procedure 900 can execute an iteration model 910 to generate an output that enables detection of at least one program anomaly in the iteration program operation 800 based on determining a probability value that indicates a likelihood that the iteration program operation includes or does not include at least one program anomaly. Restated, the probability value can indicate how “unusual” the program rate of the iteration program operation immediately preceding a given nth program stage is relative to the program rate of a “standard” non-faulty iteration program operation preceding the given program stage, where “unusual” can refer to a deviation or variance from the standard program rate that is too large (e.g., exceeds a threshold value), the deviation or variance exceeding a threshold deviation indicated by a threshold probability value.

[0160] The iteration anomaly detection procedure 900 can determine the probability value based on applying the verification result values of one or more program stages to an iteration model 910 that utilizes the verification result values of a given program stage and historical data from at least one previous model stage (or a predetermined zeroth historical data value if no previous model stage exists) at a given model stage to determine the probability value. As described herein, the iteration model can include a neural network such as a recurrent neural network (RNN) that processes each of a sequence of verification result values generated in separate, respective program stages (e.g., RNN units) at separate, respective model stages of the iteration model using a forward pass scheme to enable determination of the probability value based on each program sequence. In response to determining that a given probability value determined based on a given program stage indicates occurrence of at least one program anomaly, a recovery action can be performed to enable the non-volatile memory device to recover from the at least one program error.

[0161] ​Determining whether a programming anomaly occurs based on a probability value indicating whether a programming rate at an nth programming phase is unusual to indicate that a programming anomaly occurs is not limited to detecting a programming anomaly (e.g., under-programming) caused by only a small number of memory cells reaching a desired verify level, but can also detect an “unusual” programming rate indicative of other types of programming anomalies including, for example, programming cells to a higher than desired verify level (e.g., over-programming). For example, an “unusual” programming rate can indicate that for at least one verify voltage (e.g., verify level) of a plurality of verify voltages, at least a threshold number of memory cells of a plurality of memory cells have a threshold voltage that is outside a reference range of threshold voltages of memory cells programmed to the at least one verify voltage. Accordingly, the iterative anomaly detection procedure 900 can enable detection (and thus recovery) of a greater range of programming anomalies than, for example, corresponding to the original cell count, based on determining whether a programming rate at an nth programming phase is too unusual. Because the iterative anomaly detection procedure 900 can be able to detect and thus recover more programming anomalies, the reliability of a memory device executing the iterative anomaly detection procedure 900 with the iterative programming operation 800 can be improved without loss of capacity or performance of the memory device, thereby improving functionality of the memory device.

[0162] Figure 9 A network structure of an iterative model 910 of a recurrent neural network (RNN) including an iterative anomaly detection procedure according to some example embodiments is shown.

[0163] In some example embodiments, the iterative model 910 executed by the iterative anomaly detection procedure 900 includes a neural network model (e.g., a recurrent neural network (RNN)) that is capable of implementing online machine learning detection of at least one programming anomaly during the iterative programming operation 800 (e.g., prior to a final programming phase of the iterative programming operation 800) to enable programming correction. Such an iterative model 910 (e.g., a neural network such as an RNN) can be trained to generate an output (e.g., a negative log likelihood, indicating a negative log likelihood of no programming anomaly for the 1st programming phase to the nth programming phase of the iterative programming operation) at an nth forward pass (e.g., an nth model phase MLn, an nth node, an nth cell, etc.) indicating an nth probability value.

[0164] With reference to Figure 9 , the RNN iterative model 910 can include a repeating structure of a particular node or cell ML shown on the left side. Figure 9 Figure 9 ​The structure shown on the right can represent the RNN iterative model 910 shown on the left having its recurrent connections unfolded (or unrolled). The term “unfolded” means that the RNN is written out or illustrated to include a full or entire sequence of all nodes (e.g., units, model stages, etc.) ML1 through MLn.

[0165] In the RNN iterative model 910, Figure 9 In the RNN iterative model 910, may be an input at a time step “n” (or pulse index “n”, or responsive to a programming stage “n”, etc.) and associated with a particular nth verification voltage “V l ” at the time step “n” (or pulse index “n”, or responsive to the programming stage “n”, etc.). In the RNN iterative model 910, Figure 9 In the RNN iterative model 910, may be a hidden state at a time step “n” (or pulse index “n”, or responsive to a programming stage “n”, etc.) and associated with a particular nth verification voltage “V l ” at the time step “n” (or pulse index “n”, or responsive to the programming stage “n”, etc.). The hidden state can be computed based on a previous hidden state at a previous step (model stage) and an input at the current step (model stage). For example, in some example embodiments, the nth hidden state at the nth model stage MLn can be determined as (e.g., at a previous (n-1)th model stage ML(n-1)) where U and W can be weights and / or biases determined based on training the RNN iterative model 910 described herein. For example, the function f can generally be a non-linear function (e.g., tanh or RELU). As an example of computing a hidden state at the first model stage ML1, may generally be initialized to have an initial value of all zeros.

[0166] In the RNN iterative model 910, Figure 9 In the RNN iterative model 910, may be an output at a time step “n” (or pulse index “n”, or responsive to a programming stage “n”, etc.) and associated with a particular nth verification voltage “V l ” at the time step “n” (or pulse index “n”, or responsive to the programming stage “n”, etc.). In some example embodiments, O can be a probability value indicative of a likelihood associated with at least one programming anomaly in the iterative programming operation. In some example embodiments, is one or more parameters of a probability distribution (e.g., a conditional probability distribution) that can be applied to, for example, the input value (As shown in the equation, the nth verification result value can be generated at the nth programming phase of the iterative programming operation 800 and associated with a particular 1th verification voltage "V l ) generates a further probability value (e.g., indicative of a conditional probability for a given nth time step or programming phase and associated with a particular 1th verification voltage "V l Figure 9 , as shown, may be a nth conditional probability value or can include information for calculating the nth conditional probability value, and as described herein, the calculated nth conditional probability value may be used to calculate the nth probability value In another example, may be a nth probability value or can include information for calculating the nth probability value.

[0167] In the RNN iterative model 910 in Figure 9 , the hidden state can be the "memory" of the RNN iterative model 910. In other words, the RNN iterative model 910 can have a "memory" that captures information about what has been calculated so far (e.g., in previous model phases). The hidden state H n may capture information about what has happened in all previous time steps (e.g., previous model phases ML1 to ML(n-1)). The output may be calculated based on the memory at the current time step n and associated with a particular 1th verification voltage "V l " at the current time step n. In addition, unlike conventional neural networks that use different parameters at each layer, the RNN can share the same parameters (e.g., weights and / or biases (e.g., U and W in Figure 9 ) at all time steps (e.g., at all model phases ML1 to MLn). This can mean that the same task can be performed in each step, just with different inputs. This can greatly reduce the total number of parameters that need to be trained or learned, thereby improving the efficiency of the neural network and, therefore, the efficiency and / or performance of the services and / or applications performed, run, or processed by the device implementing the neural network.

[0168] Accordingly, based on utilizing a neural network (e.g., an RNN as shown in Figure 9 as an iterative model, a probability distribution can be generated based on indicating a plurality of memory cells at a nth programming phase (e.g., at an input I n ​​the number of storage cells having a threshold voltage Vth equal to or greater than a particular nth verification voltage "V l " and nth historical data associated with at least an (n-1)th programming phase of the iterative programming operation and the particular nth verification voltage "V l " to determine a probability value associated with occurrence of at least one programming anomaly in a sequence of the 1st programming phase to the nth programming phase of the iterative programming operation, to improve efficiency and / or performance of the iterative anomaly detection procedure, and one or more apparatuses and / or systems implementing the iterative anomaly detection procedure. Although Figure 9 An RNN iterative model 910 is shown, in which the 1st model phase to the nth model phase (e.g., RNN units) compute an output l The output can be an nth conditional probability value associated with the particular nth verification voltage "V l " or can include information for computing the nth conditional probability value based on an input (e.g., ) and historical data associated with the particular nth verification voltage "V l " but example embodiments are not limited thereto.

[0169] Figure 9 is a flowchart illustrating a method of performing an iterative programming operation 800 to program a non-volatile memory device having at least a plurality of storage cells, according to some example embodiments. Figure 10A is a flowchart illustrating a method of performing an iterative anomaly detection procedure 900 corresponding to the iterative programming operation of Figure 10B , according to some example embodiments. Figure 10A is a flowchart illustrating a method 1400 including the iterative programming operation 800 and the iterative anomaly detection procedure 900, according to some example embodiments. Figure 11 The iterative programming operation 800 shown can be the iterative programming operation 800 shown. Figure 11 The iterative programming operation 800 shown. Figure 10A The iterative anomaly detection procedure 900 shown can be the iterative anomaly detection procedure 900 shown. Figure 11 ​The iterative exception detection procedure 900 is shown. In some example embodiments, the non-volatile memory device (e.g., at least one of the memory device 300, the memory device 17, the NVM 220, the NVM 1320a and / or 1320b) can be a NAND flash memory device. In some example embodiments, the non-volatile memory device (e.g., at least one of the memory device 300, the memory device 17, the NVM 220, the NVM 1320a and / or 1320b) can be included in an electronic device (e.g., the system 1000 in Figure 10B , Figure 1 the electronic device 2000 in ,

[0170] It will be understood that Figure 18 , Figure 10A and Figure 10B the methods shown in Figure 11 , Figure 1 the storage device 200 in Figure 2 , Figure 3 the memory device 300 in ,

[0171] may be implemented, for example, by any device, system (e.g., the system 1000 in Figure 4 , Figure 10A the storage device 200 in Figure 10A , Figure 10A the storage device 15 in Figure 10A , Figure 10A the memory device 300 in Figure 10B , Figure 10B may be implemented, for example, by any device, system (e.g., the system 1000 in Figure 10B , Figure 10B the storage device 200 in Figure 10B , Figure 11 the storage device 15 in Figure 11 , Figure 11 may be implemented, for example, by any device, system (e.g., the system 1000 in Figure 11 , may be implemented, for example, by any device, system (e.g., the system 1000 in

[0172] , Figure 11 , Figure 10A and Figure 10BIn some example embodiments, based on performing the iterative model 910 to determine that a probability value indicative of at least one programming anomaly in the iterative programming operation 800 is equal to or greater than a threshold probability value (or alternatively, a probability value that there is no programming anomaly in the iterative programming operation 800 is less than a threshold probability value), the iterative anomaly detection procedure 900 based on the iterative programming operation 800 can enable detection (including “early” detection) of one or more programming anomalies in the iterative programming operation.

[0173] As described herein, a programming anomaly can include one or more operational and structural faults in a non-volatile memory device (e.g., a NAND device) that are known to have impeded data storage during a programming phase.

[0174] In some example embodiments, the iterative anomaly detection procedure provides an iterative model (e.g., an algorithm) for detecting a faulty programming scenario that is indicative of there being at least one programming anomaly in an iterative programming operation to program a non-volatile memory device (e.g., a NAND device). Such a faulty programming scenario that can be detected by the iterative anomaly detection procedure can include, for example, (1) a faulty NAND block (physical damage), (2) an extreme bit error rate after programming, (3) programming of a partially erased block, (4) a programming process that recovers from errors after a pause, any combination thereof, etc., although example embodiments of a faulty programming scenario that can be detected based on performing an anomaly detection procedure with the iterative model are not limited thereto.

[0175] The iterative model 910 of the iterative anomaly detection procedure 900 can enable real-time (e.g., during the iterative programming operation) detection of a faulty programming scenario (e.g., detecting that the iterative programming operation is a faulty iterative programming operation that includes at least one programming anomaly) without any additional read operations and allow for early correction, recovery, and / or termination of such a faulty iterative programming operation. Detecting such a faulty programming scenario can reduce, minimize, or prevent data storage errors and, thus, improve the reliability of the non-volatile device being programmed and / or the device performing the iterative programming operation 800 and the iterative anomaly detection procedure 900. The iterative anomaly detection procedure 900 and / or the method 1400 including the iterative anomaly detection procedure 900 in conjunction with the iterative programming operation 800 can be referred to as a real-time anomaly detection scheme for non-volatile memory programming and recovery algorithms (e.g., NAND flash programming and recovery algorithms).

[0176] Reference is now generally made to the iterative programming operation 800 shown in Figure 11 and Figure 10A and further back to Figure 11 and Figure 6, storing data in a NAND flash memory device via the iterative programming operation 800 can be implemented based on applying a series (sequence) of N programming pulses (programming voltages of programming steps) and verify operations (e.g., N programming phases PL1 to PLN) on each WL, where N can be any positive integer. The inhibit vector for each pulse (except the first pulse) is determined by a set of one or more verify operations (verify steps) performed at a given verify voltage {V l : l ∈ [L]} where L is the number of levels above the erase level and can be any positive integer. The number of memory cells connected to a selected word line WL having a respective threshold voltage Vth above a particular verify voltage V l is denoted by , where N cells is the number of memory cells connected to a single selected word line WL. The programming anomaly is then detected based on determining that at least the 1st programming phase to the nth programming phase of the iterative programming operation generates a sequence of impossible verify results (also referred to herein as verify result values) for each l ∈ [L].

[0177] Now referring in further detail to Figure 7 and Figure 10A , and further referring to Figure 11 and Figure 6 , the iterative programming operation 800 can include repeatedly (e.g., iteratively) performing a programming phase PL (e.g., a programming loop) at least “n” times to program a plurality of memory cells (e.g., Figure 7 in BLK1) connected to a word line to a desired program voltage, where each nth programming phase PL includes applying an nth program voltage PGMn to the memory cells and then performing a set of “L” verify operations VFYn, where “n” and “L” are each independently positive integers. In some example embodiments, “n” is a positive integer equal to or greater than 1. In some example embodiments, the iterative programming operation has a particular (or alternatively, predetermined) number of programming loops or programming phases N (being a positive integer) such that the nth phase is one of the 1st programming phase to the Nth programming phase, and thus the value of “n” can be between 1 and N. The Nth programming phase can be referred to herein as the final programming phase of the iterative programming operation 800.

[0178] As shown in Figure 4 , the iterative programming operation 800 can include repeatedly (e.g., iteratively) performing a programming phase PL such that the iterative programming operation includes performing a sequence of at least the 1st programming phase to the nth programming phase (PL1 to PLn). With respect to Figure 11 ​The description is provided for a given nth stage (PLn) of an iterative programming operation 800 comprising at least one programming stage up to the nth programming stage. However, it will be understood that... Figure 10A The method shown for the nth programming stage can be applied to any programming stage of iterative programming operation 800. It will be understood that... Figure 10A and Figure 10A The iterative programming operation 800 shown can be executed according to the ISPP scheme.

[0179] At S802, the nth programming stage PLn is given. For example... Figure 11 As shown, each given programming stage PL can begin in response to a specific time step “n” (pulse index “n”, etc.).

[0180] At S804, it is determined whether a programming operation termination command (RC1) has been received. The programming operation termination command will be further described below. If received (S804 = Yes), at S826, at least one recovery action is initiated, which may include at least one of the following: terminating the iterative programming operation 800 before completing the final programming stage of the iterative programming operation 800 (S828); an error correction operation, which may include, for example, removing the memory cell array (e.g., including the word line selected when the iterative programming operation 800 is being performed and the memory cells connected to the selected word line) from the memory cell array. Figure 11 The block flag of BLK1 is a bad block, and a new address is allocated for iterative programming operations (e.g., Figure 4 BLK2 in the middle), and in the newly allocated address (e.g., Figure 4 Repeated iterative programming operation 800 (S830) at BLK2); and / or sending alarm signals (e.g., via a communication device (e.g., Figure 4 The communication device 1140 in the middle), via the display (e.g., Figure 1 The display 1450 (or similar device) is used to provide an indication of at least one programming exception occurring to external devices, users supported by the device performing the iterative programming operation 800, etc. (S832).

[0181] If no programming operation termination command is received (S804 = No), then at S806, the nth programming step executes the programming steps of the nth programming stage (e.g., the nth programming step). Figure 1 As shown, the programming steps of the nth programming stage (PLn) include: applying the nth programming voltage Vpgm (e.g., PGMn) to a specific plurality of memory cells (e.g., non-volatile memory devices) of the non-volatile memory device. Figure 7 and Figure 4The selected word lines connected to the BLK1 of the shown memory cells cause the nth programming voltage PGMn to be applied to a specific set of memory cells. Applying the nth programming voltage PGMn can change the threshold voltage Vth of the memory cell.

[0182] At S808, the iterative programming operation 800 performs a verification step, which includes: performing verification on multiple memory cells (e.g., BLK1) that receive the nth programming voltage PGMn at S806 with individual, corresponding specific verification voltage V. 1 V 2 , ..., V L An associated set of "L" verification operations from S808-1 to S808-L, for each specific verification voltage V. l (Where "l" is a positive integer between 1 and L) Generate the nth verification result value. The nth verification result value Indicates that in multiple memory cells, at PLN in the nth programming stage, there is a specific verification voltage V equal to or greater than V. l The number of memory cells (e.g., BLK1) with a threshold voltage Vth.

[0183] At S810, the first verification operation S808- includes: applying a specific first verification voltage V. l Apply WL to the selected word line connected to the memory cell (e.g., BLK1). (See reference) Figure 5A The control logic circuit 320 can control the voltage generator 350 to verify the voltage V. l An application is made to the selected word line WL. At S812, the first verification operation includes: determining the first threshold voltage Vth of the memory cell (e.g., the memory cell of BLK1) connected to the selected word line (e.g., via an operation as follows). Figure 4 The ground selection line transistors GSTA and / or GSTb are shown to read the voltage of the memory cell connected to the selected word line. In S814, the first verification operation S808- includes: comparing the first threshold voltage Vth of the read memory cell with a specific first verification voltage V. l Compare to verify voltage V for those that are equal to or greater than a specific voltage. l The number of memory cells at the threshold voltage Vth is counted. This number indicates the number of memory cells that have a threshold voltage Vth at the nth programming stage PLN that is equal to or greater than a specific verification voltage Vth. l The number of storage cells (e.g., BLK1) of the threshold voltage Vth, the verification result value.

[0184] At S816, a set of "L" verification result values ​​from verification operations S808-1 to S808-L can be collected to establish a sequence of one or more nth verification result values. Where “L” can be any positive integer.

[0185] As used herein, “L” can be any positive integer including 1, such that a set of “L” verification operations can include performing a single verification operation or performing multiple verification operations. In some example embodiments, where L = 1, performing a set of “L” verification operations at S808 includes performing verification on multiple memory cells with a specific verification voltage V. 1 The associated verification operation (e.g., S808-1) generates the nth verification result value. The nth verification result value Indicates that in multiple memory cells, at PLn in the nth programming stage, there is a specific verification voltage V equal to or greater than V. 1 The threshold voltage Vth is the number of memory cells. In some example embodiments, where L is greater than 1, performing a set of "L" verification operations at S808 includes performing multiple verification operations S808-1 to S808-L on multiple memory cells to generate multiple, for example, the nth verification result value. In this context, multiple verification operations (e.g., S808-l, where "l" is between 1 and L) are each associated with multiple verification voltages V. 1 V 2 ,...,V L The different individual and corresponding verification voltages V l Related, and multiple nth verification result values Each individual nth verification result value Indicates that in multiple memory cells, at PLn in the nth programming stage, there are multiple verification voltages V equal to or greater than a certain number. 1 V 2 , ..., V L Individual verification voltage V l The individual number of memory cells with a threshold voltage Vth.

[0186] refer to Figure 5A and Figure 10A At S818, the iterative programming operation 800 will verify the nth value 826 (e.g., When L>2, the output is provided (e.g., output) to the iterative anomaly detection procedure 900 (e.g., as input to one or more model stages ML of one or more iterative models 910). Figure 11 The output "A" is shown, as well as... Figure 10A (As shown). In Figure 10BAt S818, the nth verification result value provided to the iterative anomaly detection procedure (e.g., ) is collectively referred to as

[0187] At S820, a determination is made as to whether the current nth programming phase is a final programming phase of the iterative programming operation 800. For example, when the iterative programming operation 800 is configured to have a predetermined N number of programming phases PL1 through PLN (where N is a particular positive integer), the determination at S820 can include determining whether “n” is equal to or greater than “N”. If so (S820 = YES), the iterative programming operation 800 ends at S824. If not, at S822, the iterative programming operation 800 advances to a next programming phase at a next time step, pulse index, etc., such that the current phase increases from the “nth” programming phase to the (n+1)th programming phase. As shown in Figure 11 , a given programming phase PL can be completed prior to a time step of a next programming phase, although example embodiments are not limited thereto.

[0188] Referring now generally to Figure 11 and Figure 10B , the iterative anomaly detection procedure 900 of the method 1400 is configured to receive S818 one or more process verification result values 826 (e.g., ) at one or more programming phases of the iterative programming operation 800 and corresponding to one or more particular verification voltages, to determine a probability value associated with a likelihood of at least one programming anomaly in the iterative programming operation 800. For example, the iterative anomaly detection procedure 900 can determine whether a sequence of verification result values for a given verification voltage for a series of 1st programming phases through nth programming phases is sufficiently unusual (e.g., a sequence that deviates from “standard”, a non-faulty iterative programming operation) so as to indicate a presence of at least one programming anomaly in the iterative programming operation 800.

[0189] The iterative anomaly detection procedure 900 can utilize an iterative model 910 (e.g., an RNN iterative model as shown in Figure 11 ) that is configured to repeatedly execute a model phase ML based on repeatedly executing a programming phase PL of the iterative programming operation 800, such that at a given nth model phase MLn, the iterative model takes as input at least one verification result value of the nth programming phase along with historical data comprising information associated with at least an (n-1)th programming phase (PL(n-1)) of the iterative programming operation 800 (e.g., generated based on at least an (n-1)th programming phase (PL(n-1)) of the iterative programming operation 800) (For example, the hidden states, hidden layers, etc. of the RNN iterative model 910) are processed together to determine the nth probability value, which indicates the probability of the occurrence of at least one programming exception in the first to nth programming stages of the iterative programming operation 800.

[0190] In some example embodiments, the iterative model 910 may, for example, establish a probability distribution (e.g., a conditional probability distribution) at each model stage ML based on parameters that determine the probability distribution, which solves for probability values ​​at least as a function of the validation result value, and based on the nth validation result value. Further determine the nth probability value indicated by the probability distribution. The nth probability value can then be processed (e.g., compared with a threshold probability value corresponding to the nth programming stage and / or the nth model stage) to determine whether the nth probability value indicates the occurrence (e.g., existence) of at least one programming exception in the first programming stage PL1 to the nth programming stage PLn of the iterative programming operation 800.

[0191] For example, for a given voltage V, verify the voltage V. l The iterative model 910 can use an autoregressive model to analyze the subsequences of the first to nth validation results from the first to the nth programming stages. The density is modeled, and this autoregressive model can use an RNN (see [link]). Figure 9 The learning process is illustrated in the diagram. Each time step of the iterative model (e.g., the time step of an RNN) can correspond to a single programming pulsar and its accompanying verification operation (e.g., a single programming phase PL of iterative programming operation 800).

[0192] The description herein may describe the iterative model as a neural network including, for example, an RNN; however, it will be understood that the example embodiments are not limited thereto and may include any iterative model and / or algorithm configured to iteratively (repeatedly) execute model phases, each model phase utilizing the verification result value of the corresponding programming phase (PLn) and historical data associated with at least one previous programming phase (PL(n-1)) of the iterative programming operation 800 to determine an nth probability value, which indicates the probability associated with the occurrence of at least one programming anomaly in the first to nth programming phases of the iterative programming operation 800.

[0193] Now combine Figure 9 For further details, please refer to Figure 9 and Figure 10BThe iterative anomaly detection procedure 900 may include repeatedly (e.g., iteratively) executing model phases ML of an iterative model 910, such that the iterative anomaly detection procedure 900 includes executing a sequence of at least the first model phase to the nth model phase (ML1 to MLn). As shown, the iterative anomaly detection procedure 900 may execute at least the nth model phase MLn of the iterative model 910, which utilizes the nth verification result value generated at the nth programming phase PLn of the iterative programming operation 800 (e.g., ) and the nth historical data associated with at least the (n-1)th programming stage PL(n-1) of the iterative programming operation 800 (e.g., To determine the nth probability value, the nth probability value can be determined by... Figure 11 In This indicates the probability of the occurrence of at least one programming exception associated with the occurrence of the first programming stage PL1 to the nth programming stage PLn of the iterative programming operation 800.

[0194] about Figure 11 The description is provided for a given nth model stage (MLn) of the iterative model 910 of the iterative anomaly detection procedure 900, which includes at least the first model stage through the nth model stage, but it will be understood that... Figure 10B The method shown for the nth model stage MLn can be applied to any model stage of the iterative model 910 of the iterative anomaly detection procedure 900.

[0195] At S902, the nth model stage of the iterative model 910 executing the iterative anomaly detection procedure 900 may include: operations based on the nth programming stage PLn of the iterative programming operation 800 (such as...). Figure 10B As shown in the input "A", this input "A" is... Figure 10B The output "A" shown corresponds to this, and as... Figure 10A As shown, at point 826, the nth programming stage PLn of the iterative programming operation 800 is provided to the nth model stage MLn of the iterative anomaly detection procedure 900. ), receiving at least one specific verification voltage (V) l At least one corresponding nth verification result value For example, when the number of verification voltages "L" in the iterative programming operation is greater than 1, the reception at S902 may include: receiving a sequence of verification result values ​​for each of the verification voltages 1 to L. (exist Figure 11 The Chinese character is represented as However, the example embodiments are not limited thereto, and in some example embodiments, a single nth verification result value may be received at S904 (e.g., )(exist Figure 11is represented in ).

[0196] At S906, the nth model stage of the iterative model of the iterative model 910 can include receiving (e.g., from a previous model stage of the iterative model 910 and / or a storage device) at least one nth historical data value associated with at least the (n-1)th programming stage PL(n-1) of the iterative programming operation 800 and in Figure 11 is represented in At S906, the nth model stage of the iterative model of the iterative model 910 can include receiving (e.g., from a previous model stage of the iterative model 910 and / or a storage device) at least one nth historical data value associated with at least the (n-1)th programming stage PL(n-1) of the iterative programming operation 800 and in As described herein, the nth historical data value may be generated at a previous (n-1)th model stage of the iterative model 910 in order to provide a “memory” of the previous model stage (e.g., at least the (n-1)th model stage ML(n-1)) in the operation of the nth model stage. For example, where the number of verification voltages “L” in the iterative programming operation is greater than 1, the receiving at S906 can include receiving a sequence of historical data values (e.g., hidden states) for each verification voltage 1 through L is represented in Figure 11 is represented in ), but example embodiments are not so limited, and in some example embodiments, a single nth historical data result value (e.g., ) can be received at S906. S906 can be represented in Figure 11 as receiving the nth historical data of the iterative model 910 of the iterative anomaly detection procedure 900. It will be understood that, as described with reference to Figure 11 , each of the (e.g., ) in can be stored in a memory of a device implementing the first model stage ML1, and can generally be initialized to an initial value, which can have a value of all zeros.

[0197] At S910, the iterative model 910 of the iterative anomaly detection procedure 900 can conduct (e.g., execute) the nodes S912 (e.g., units) of the nth model stage MLn. Each node can utilize at least one nth verification result value as an input to the node, and can further use at least one nth historical data value received at S906 to generate at least one output value Generating the at least one output value can include determining at least one nth probability value Such a process can be performed for each of the first, verification voltages 1 through L, and thus using the corresponding nth verification result value and historical data In order to determine the nth probability value respectively

[0198] References include, for example Figure 9 The iterative model of the RNN iterative anomaly detection procedure 900 is shown, and as... Figure 9 As shown, the input of the iterative model 910 at time step n∈{1,...N} can be at least one verification result value at S904. The result of the verification operation received in the previous programming stage PL(n), although the example embodiments are not limited thereto. In some example embodiments, the iterative model includes an RNN, with the nth historical data... This could be a hidden stage from a previous iteration of the iterative model (e.g., a previous (n-1)th model stage). The output of the iterative model 910 at a given time step (e.g., the output of the nth model stage MLn) can be, or can be used to determine the nth conditional probability value, wherein, given the values ​​of some or all of the verification result values ​​from the first verification result value to the (n-1)th verification result value generated in some or all of the first programming stage PL1 to the (n-1)th programming stage PL(n-1) of the iterative programming operation 800, the nth conditional probability value indicates the nth verification result value. The probability of the value of . The conditional probability value of this type n can be expressed as formula (1):

[0199]

[0200] To reiterate, the nth model stage of the iterative model 910, executed in response to the nth stage verification operation of the nth programming stage, can use the output (e.g., as hidden states, hidden layers, etc.) from the previous (n-1)th model stage iterative model (e.g., RNN) to compute the nth verification result value for each of one or more verification voltages "L". The conditional probability (e.g., the probability of such a verification result value occurring in an iterative programming operation that does not include any programming exceptions, given the verification result value of a previous programming stage) is shown in Equation (1).

[0201] At S914, the iterative anomaly detection procedure 900 determines the nth probability value based on the output of the nth model stage of the iterative model 910. In some example embodiments, the output of the nthmodel stage of the iterative model 910 at S912 is the nthprobability value, and S914 is omitted as a separate operation. In some example embodiments, the output of the nthmodel stage at S912 is the nthconditional probability value as shown in equation (1), or is an output used to determine the nthconditional probability value as shown in equation (1), and at S914 the iterative anomaly detection procedure 900 can utilize the nthconditional probability value of the iterative model 910 to compute the nthprobability value as shown in equation (2) (e.g., a subsequence of a likelihood:

[0202]

[0203] The nthprobability value as shown in equation (2) may be determined based on a product of conditional probability values determined according to execution of the 1stmodel stage ML1 through the nthmodel stage MLn. It will be understood that a given conditional probability value computed at a given model stage (e.g., based on the output at S912) can be stored in memory (e.g., a non-transitory storage device) such that at S914 of the nthmodel stage MLn S910, the iterative anomaly detection procedure 900 can load the 1stconditional probability value through the (n-1)thconditional probability value from memory (e.g., memory of a device implementing the iterative anomaly detection procedure 900) in response to or based on determining the nthconditional probability value from memory (e.g., memory of a device implementing the iterative anomaly detection procedure 900) and determine the nthprobability value according to equation (2) It will be understood that in the first model stage (n = 1), the nthconditional probability value may be the same as the nthprobability value.

[0204] Reiterating, at S914, the nthmodel stage of the iterative model 910 executed in response to the nthstage verify operation of the nthprogram stage can utilize output (e.g., as a hidden state, hidden layer, etc.) from the previous (n-1)thmodel stage of the iterative model (e.g., RNN) to compute the nthprobability value indicative of a likelihood of a subsequence of (e.g., a likelihood of a sequence of such verify result values occurring in the iterative program operation 800 without including any program anomalies).

[0205] Still referring to S910, in some example embodiments where the number of verify voltages “L” in the iterative program operation is greater than 1, such that multiple verify operations S808-1 through S808-L are performed at the nthprogram stage as shown in Figure 11 to generate multiple nthverify result values The receiving at S902 may include: receiving a sequence of verification result values ​​for each of the verification voltages 1 to L. The execution of the nth model stage may include, at S912, the iterative anomaly detection procedure 900 including one or more iterative models 910, which are configured to generate multiple nth probability values ​​based on applying individual nth verification result values ​​corresponding to individual “L” verification voltages to one or more iterative models, such that S910 generates multiple “L” probability values, for example, based on performing the above operation at S912 and S914 for each individual 1 to L verification voltages. As In some example embodiments, the nth model stage of iterative model 910 may use a sequence of validation result values. As input to a single node at S910, it generates a value used at S912 to determine multiple "L" probability values. As The output of this model is used to execute a single iterative model 910, which generates multiple nth probability values ​​based on multiple nth verification result values ​​and historical data associated with multiple verification voltages during at least the (n-1)th programming phase of the iterative programming operation. In some example embodiments, the iterative model 910 is actually multiple iterative models 910, each generating a separate nth probability value from the multiple nth probability values, wherein each nth model phase of each separate iterative model utilizes multiple nth verification result values. The individual nth verification result value associated with a specific verification voltage among multiple verification voltages, and individual historical data associated with a specific verification voltage in at least the (n-1)th programming stage of the iterative programming operation. In such an example embodiment, execution at S912 may include: implementing the nth model stage node of multiple individual iterative models 910 in parallel to generate multiple "L" probability values ​​that are processed in parallel to generate at S914. As The separate output.

[0206] In some example embodiments, the output of a given model stage node at S912 is the nth probability value, thus omitting S914. In some example embodiments, the output of the given nth model stage node at S912 is used at S914 to determine the nth probability value.

[0207] In some example embodiments, the nth probability value is determined at S914 (e.g., includes determining an nth conditional probability distribution based on executing the at least nth model stage of the iteration model (e.g., S910), where the nth conditional probability distribution indicates a distribution of probability values corresponding to the verification result values, and determining, as the nth probability value, a probability value indicated by the nth conditional probability distribution corresponding to the nth verification result value.

[0208] For example, in some example embodiments, the nth conditional probability value is modeled as a Beta-Binomial distribution B(N cells , a, b), which can describe a probability of a variable having a value between 0 and N. The Beta-Binomial distribution can be defined by two parameters, and (which can also be referred to herein as a first parameter and a second parameter of the Beta-Binomial distribution) can be shown as follows in Equation (3):

[0209]

[0210] In Equation (3), “N” is a number of storage cells connected to the selected word line (e.g., a number of storage cells in BLK1), which can be a predetermined value stored in a memory device and accessed by a device implementing the iteration anomaly detection program 900, and “x” is a number of program failures for a particular verification voltage generated at the nth program stage. Accordingly, the Beta-Binomial distribution P α，β，N (x) shown in Equation (3) corresponds to the nth conditional probability value P (x) shown in Equation (1) given the previous verification result values of the previous program stages 1 to (n-1) of the iteration program operation 800. Such nth conditional probability values can also be used to determine the nth probability value indicating a probability that at least one program anomaly has occurred (or has not occurred) during the at least first program stage PL1 to the nth program stage PLn of the iteration program operation 800, as shown in Equation (2). Thus, based on the nth verification result value generated at the nth program stage of the iteration program operation 800, the nth verification result value can be inserted into P α，β，N (x) as “x” to determine P α，β，N (x) as a probability of P (x) given the previous verification result values of the previous program stages 1 to (n-1) of the iteration program operation 800, and the determined P α，β，N (x) can be determined as the nth conditional probability value the (n-1)th conditional probability value together to determine the nth probability value at equation (2) that indicates a likelihood (e.g., a log-likelihood) of the determined sequence of verification result values, e.g., a likelihood that such a sequence (e.g., sub-sequence) occurred in the iterative program operation 800 that did not include any program exceptions.

[0211] In some example embodiments, where the conditional probability values used to determine the probability values are modeled as a conditional probability distribution (e.g., a Beta-Binomial distribution as indicated by at least equation (3)), the iterative model (e.g., RNN) can be configured to generate, at S912, the a and b parameters of the conditional probability distribution (e.g., Beta-Binomial distribution as indicated by equation (3)) as output of a given nth model stage (MLn) The a and b parameters can then be applied to the Beta-Binomial distribution (which parameters can be accessed from memory, storage, etc., in addition to the value N that is known to be the number of memory cells connected to the selected word line), and then, the nth verification result value as“x” to the Beta-Binomial distribution to determine P α，β，N (x) as the nth conditional probability value corresponding to (e.g., equal to) the conditional probability The overall nth probability value indicating an overall probability that an exception occurred (or did not occur) in the 1st program stage to the nth program stage of the iterative program operation 800) can be further determined using the nth conditional probability value and the prior conditional probability values (e.g., the 1st conditional probability value to the (n-1)th conditional probability value) in accordance with equation (2), and such overall probability can be applied by the iterative exception detection program as the determined nth probability value at S914 for a given nth verification voltage V l and applied at S915 to determine whether a program exception has occurred in the iterative program operation 800, although example embodiments are not limited thereto.

[0212] In some example embodiments, the iterative model 910 includes a recurrent neural network (RNN) that is configured to perform, at S912, an nth forward pass operation (e.g., based on executing RNN nodes or RNN cells) to generate the nth output of the RNN The nth output corresponds to (e.g., is equal to or can be processed at S914 to determine) an nth probability value that is based on using at least one nth verification result sample as the nth input and using at least one historical data value associated with at least an (n-1)th program phase as an nth hidden layer generated based on the RNN performing an (n-1)th forward pass operation prior to performing an nth forward pass operation. For example, the iterative model 910 can include a neural network, e.g., an RNN that can have three sets of weights W hi , W hh , and W oh , and two sets of biases b hi , and b hh . At each time step “n” or nth model phase of the RNN, a hidden layer for a next (e.g., (n+1)th) model phase can be computed using the weights and biases as shown in equation (4):

[0213]

[0214] In equation (4), x n is an nth verification result value indicating a number of storage cells in the plurality of storage cells having a threshold voltage Vth equal to or greater than a particular nth verify voltage V l at the nth program phase, and is a hidden layer computed at a previous (n-1)th time step (e.g., (n-1)th model phase) of the RNN. At the first time step, the can be an initial value accessed from the memory device, and such initial value can be zero. The weights W hi , W hh , and W oh and biases b hi , and b hh can be determined during training of the RNN as described herein.

[0215] At a given nth model phase (e.g., at the nth RNN cell of the RNN at S912), the iterative model 910 can compute an output including parameters and determined based on performing a linear transformation of to determine a conditional probability density (e.g., P l (x) as shown in equation (3)) for an expected number of cells having a threshold voltage equal to or above a verify voltage V α，β，N after the nth program pulse.

[0216] In more detail, is a vector of size M, M being the hidden layer​ the size of the hidden layer (e.g., the hidden state) can need to capture the non-linearity of the iterative model 910. In contrast, the output of the neural network (e.g., RNN) iterative model 910 at each model stage can only have 2 parameters per validation level (e.g., per “l” validation voltage). Thus, to convert to and (e.g., each validation level “l”), the hidden layer can be multiplied by a matrix of size M x (2 x L) to obtain a product, and a vector of size 2*L can be added to such product to obtain and as shown in equation (5) below:

[0217]

[0218] the weights in the matrix O l and the bias c l in equation (5) can be determined during a process of training the RNN as described herein.

[0219] In some example embodiments, the neural network (e.g., RNN) can be trained to determine the probability values as negative log likelihoods, and the neural network can be trained to minimize the negative log likelihoods. For example, the iterative model 910 can be a neural network (e.g., RNN) that can be trained to minimize the negative log likelihoods of the sequence , or to maximize the log likelihoods of the sequence . For example, the neural network (e.g., RNN) can be trained to determine the probability values as log likelihoods, and the training of the neural network can be trained to maximize the log likelihoods of the sequence of the following equation (6):

[0220]

[0221] Accordingly, in some example embodiments, the nth probability value determined at S910 (e.g., at S914) can correspond to an nth iteration of a probability distribution (e.g., a conditional probability distribution) that indicates the probability values as a function of the validation result values (e.g., as in equation (3)), and has one or more distribution parameters (e.g., a and b), the nth iteration of the probability distribution (e.g., determined at S910) having nth values (e.g., and ) of the one or more distribution parameters of the probability distribution, such that the nth output the nth value of one or more distribution parameters (e.g., and ), and determining the nth probability value at S914 includes: (e.g., using Equation (3), and / or based on applying P α，β，N (x) as shown in Equation (3) using the 1st through (n-1)st conditional probability values loaded from memory) applying the nth value of one or more parameters to generate the nth iteration of the probability distribution, and determining the probability value indicated by the nth iteration of the probability distribution corresponding to the nth validation result value as the nth probability value (e.g., applying to Equation (3)). In some example embodiments, the probability distribution can be a conditional probability distribution (e.g., a Beta-Binomial distribution), such that the one or more distribution parameters include a first parameter and a second parameter (e.g., a and b) of the Beta-Binomial distribution, although example embodiments are not limited thereto. In some example embodiments, the probability distribution is determined based on applying P α，β，N (x) to Equation (2), and determining the probability value indicated by the nth iteration of the probability distribution corresponding to the nth validation result value as the nth probability value (e.g., applying to Equation (3)) to Equation (2).

[0222] Still referring to Figure 10A At S915, the nth model stage of the iterative anomaly detection procedure 900 determines whether any of the nth probability values determined at S910 (e.g., the plurality of probability values ) at S914 satisfy (e.g., are equal to or exceed) the corresponding nth threshold probability value. If not (S915 = No), then it is determined at S916 that the iterative programming operation 800 is free of programming anomalies at least up to the nth programming stage MLn, and the iterative model 910 advances to the next model stage (n+1) at S918. As Figure 10B indicated, the iterative programming operation 800 can optionally continue based on a determination that the iterative programming operation 800 is free of programming anomalies at least up to the nth programming stage MLn (e.g., based on no probability value satisfying the corresponding nth threshold probability value at S915). In S918, the iterative model 910 advances to the next model stage (n+1). If yes (S915 = Yes), then it is determined at S920 that at least one programming anomaly has occurred in the 1st through nth programming stages of the iterative programming operation 800. In response, a recovery action can then be initiated at S922, which can include sending a termination command RC1 (926) at S924 that causes the iterative programming operation 800 to terminate at Figure 11the next programming phase (e.g., the (n+2)th programming phase) in the sequence of iterative programming operations 800 at S804, and performing one or more recovery actions at S826, the one or more recovery actions including at least one of performing an error correction operation (S830), terminating the iterative programming operation 800 (which can include terminating prior to completion of the final programming phase of the iterative programming operation) (S828), or sending an alert signal to provide an indication that at least one programming exception occurred (S832). In some example embodiments, the iterative exception detection procedure 900 can perform the one or more recovery actions of S826 at S922 without sending a termination command (RC1) or separate from sending a termination command (RC1). For example, the operations at S922 can include sending a termination command (RC1) at S924, and the iterative programming operation 800 can respond at S804 and S826 by terminating the iterative programming operation at S828, and the operations at S922 can also perform one or more of S830 or S832. But example embodiments are not limited thereto. In some example embodiments, one or more of the recovery actions S828, S830, or S832 can be implemented by a device that implements one or both of the iterative programming operation 800 or the exception detection procedure 900 (e.g., implements the method 1400), where such one or more recovery actions are performed by a device that is independent of the iterative programming operation 800 and / or the iterative exception detection procedure 900.

[0223] It will be appreciated that, in general, the nth probability value is determined as a product of the 1st conditional probability value through the nth conditional probability value as shown in equation (2) may indicate that there is at least one programming exception in the sequence of iterative programming operations 800. However, it will be appreciated that example embodiments are not limited to a probability value that is calculated as a product of the 1st conditional probability value through the nth conditional probability value as shown in equation (2). For example, in some example embodiments, the nth probability value may be calculated via a different equation than equation (2). For example, in some example embodiments, the nth probability value may be calculated via a different equation than equation (2). For example, in some example embodiments, the nth probability value may be calculated via a different equation than equation (2). For example, in some example embodiments, the nth probability value may be calculated via a different equation than equation (2). For example, in some example embodiments, the nth probability value may be calculated via a different equation than equation (2). For example, in some example embodiments, the nth probability value

[0224] In some example embodiments, a corresponding threshold probability value can be stored (e.g., predetermined) in, for example, a memory for each of the 1st programming phase to the n* programming phase (pulse index) and for each verify voltage (e.g., verify level) in each programming phase, and the n* probability value for a given n* programming phase and n* verify voltage (e.g., verify level) can be compared to the corresponding threshold probability value for the given programming phase and verify level at S915 to determine whether the n* probability value indicates occurrence of at least one programming anomaly in the iterative programming operation. The threshold probability values can be determined empirically and can be stored in a lookup table (e.g., a lookup table stored at a memory of a device implementing the iterative anomaly detection procedure 900). The threshold probability values can be determined empirically to establish a decision boundary that provides a desired false positive rate. The iterative anomaly detection procedure 900 can access the lookup table and determine the n* threshold probability value that also corresponds to the same n* programming phase and n* verify level in response to determining the n* probability value corresponding to the n* programming phase and n* verify level at S915, and further determine whether a programming anomaly has occurred in the iterative programming operation 800 based on determining whether the probability value at least satisfies the corresponding threshold probability value.

[0225] In some example embodiments, the determination at S914 can be based on determining that the n* probability value is less than the n* threshold probability value. In some example embodiments, the determination at S915 can be based on determining that any (e.g., at least one) of the plurality of n* probability values satisfies the corresponding n* threshold probability value.

[0226] In some example embodiments, the determination at S915 can be based on determining that at least one of the plurality of n* probability values satisfies the corresponding n* threshold probability value. In some example embodiments, the determination at S915 can be based on determining that at least one of the plurality of n* probability values satisfies the corresponding n* threshold probability value.

[0227] Referring to Figure 10A , the model phase of the iterative model 910 of the iterative anomaly detection procedure 900 can be performed after the corresponding programming phase of the iterative programming operation 800 is performed. For example, as Figure 11 ​As shown, although the nth programming stage PLn can be executed at time step n, the corresponding nth model stage MLn of the iterative model 910 utilizing the nth verification result value generated in the nth programming stage PLn can be executed at a subsequent time step (n+1). For example, as shown, the nth model stage of the iterative model 910 utilizing at least one nth verification result value generated in the nth programming stage can be executed at least partially concurrently with the (n+1)th programming stage PL(n+1) executing the iterative programming operation at time step (n+1). As a result, the iterative anomaly detection program 900 can be executed without introducing additional delays in the iterative programming operation 800, thereby providing improved anomaly detection provided by the iterative anomaly detection program 900, and thus improving the reliability of the device implementing the iterative anomaly detection program without reducing the device's capacity or programming performance with respect to the iterative programming operation 800.

[0228] Still referencing Figure 11 In response to the determination of at least one programming exception in the iterative programming operation 800 during the nth model stage MLn, the iterative exception detection procedure 900 may cause a termination command (RC1) to be generated and sent to prematurely terminate the iterative programming operation 800 (e.g., before executing the next programming stage ML(n+2) after determination), thereby terminating the iterative programming operation and enabling iterative programming operation to be terminated. Figure 11 The recovery action is performed in advance at S826, thereby improving the response and recovery performance of the device implementing method 1400.

[0229] To demonstrate the effectiveness of the present invention, at least in Figure 10A An example is shown in the document demonstrating the ability of a test iterative model to detect at least one programming anomaly in an iterative programming operation.

[0230] Figures 12 to 14 This is a distribution diagram illustrating the fault-based iterative programming operations for programming non-volatile memory devices according to some example embodiments. Figure 12 It is a graph illustrating the probability distribution of the verification result values ​​for the nth programming stage of an iterative programming operation according to some example embodiments, and an indicator of the probability values ​​of the verification result values ​​for the nth programming stage of both the standard sample iterative programming operation and the fault iterative programming operation. Figure 13 This is a distribution diagram of fault-based iterative programming operations for programming non-volatile storage devices according to some example embodiments. Figure 14 It is a line graph showing a sequence of multiple probability values ​​determined for individual, corresponding iterative programming operations (including standard and fault iterative programming operations) according to some example embodiments. Figure 15 yes Figure 16An expanded view of region X in [reference], showing a threshold decision boundary according to some example embodiments that divides sequences of probability values determined for individual, respective standard iterative programming operations and sequences of probability values determined for individual, respective faulty iterative programming operations. Figure 15 and Figure 12 each include at least partial overlap of a distribution map of faulty iterative programming operations and a distribution map of non-faulty (“standard”) iterative programming operations.

[0231] Figure 14 as shown in the example of [reference], and particularly as Figures 12 to 14 and Figure 12 the distribution maps of [reference] illustrate an iterative anomaly detection program 900 configured to detect at least one programming anomaly in an iterative programming operation configured to emulate a programming anomaly (e.g., error) that occurs during a pause in a block erase process. Due to the programming anomaly, the erase process in iterative programming operation 800 is not completed, and most of the memory cells of the non-volatile memory device still have a threshold voltage Vth, such that most cells still have a threshold voltage higher than the erase level (e.g., represented by Figure 14 and Figure 12 the overlap between the faulty and non-faulty “standard” distribution maps). Such an error is emulated by applying a low voltage pulse to 7 / 8 of the memory cells connected to the selected word line WL before performing the iterative programming operation 800 to program the memory cells connected to the selected word line WL (e.g., ISPP scheme). As Figure 14 and Figure 12 shown, memory cells not pre-programmed with the low voltage pulse mimic cells at the erase level before the incomplete erase process (e.g., represented by Figure 14 and Figure 12 the leftmost part of the faulty distribution map of each of [reference]).

[0232] In Figure 14 the example shown, after applying a 15.5V low voltage pulse to 7 / 8 of the memory cells, an iterative programming operation 800 is performed on the memory cells. As a result, as Figure 12 shown, at the end of the iterative programming operation 800, the erase level is significantly higher than expected.

[0233] Turning to Figure 12 , the iterative anomaly detection program 900 is executed to utilize a given verification voltage V Figure 13 generated at the first programming stage (n = 1) of the iterative programming operation 800 for generating the distribution shown in l the first stage verification result value where the iterative model 910 of the iterative anomaly detection program 900 is based on the first stage verification result value and an initialized hidden state value to perform to determine a probability parameter or a distribution parameter (e.g., a Beta-binomial distribution parameter) and are 0.782 and 16163.67, respectively. Then use and the determined values, together with the known number of memory cells connected to the selected word line (as shown, N = 147456), to generate a first-stage probability distribution 1302, which is a function of the first-stage verification result value in formula (2) further applied to formula (3), where the result conditional probability at n = 1 can be the same as the probability value at stage n = 1. As shown, the probability distribution 1302 can indicate the probability that the iterative programming operation for which the probability value is determined does not have any programming anomalies. The value of

[0234] Figure 12 shows the probability distribution 1302 learned by the iterative model 910 (e.g., an RNN) for (the number of cells passing through the first verification level after the first ISPP pulse (e.g., the first programming stage PL1)). Figure 13 The example shown in compares the probability distribution 1302 with the verification result value Figure 13 for the simulated faulty iterative programming operation 800(1306). As shown in the chart in the verification result value output by the iterative model for the simulated faulty iterative programming operation 800(1306) has a very low probability, so the simulated faulty iterative programming operation 800(1306) can be easily identified and classified as including one or more programming anomalies by the iterative anomaly detection program 900.

[0235] As Figure 13 shown, when at least the first programming stage of the iterative programming operation 800 is performed without simulating programming anomalies, the resulting probability value 1304 determined based on applying the first-stage verification result value of such a "standard" iterative programming operation to the probability distribution 1302 is usually relatively low (e.g., less than 50), and usually corresponds to a probability value of at least 0.001 indicated by the probability distribution 1302, as Figure 13 shown.

[0236] As Figure 13 further shown, when using as in reference Figure 13When the programming anomaly of the 15.5V pulse simulation is used to perform at least the first programming phase of the iterative programming operation 800, the resulting probability value 1306 typically corresponds to a probability value less than about 0.001 indicated by the probability distribution 1302, such as... Figure 12 As shown. Further, such an outcome probability value 1306 may far exceed the decision boundary indicated by the threshold probability value, for example, exceeding one or more standard deviations from the mean of probability distribution 1302. As a result, for example, since the outcome probability value 1306 is determined to at least satisfy the threshold probability value (e.g., less than 0.001), the threshold variance (e.g., greater than two standard deviations from the mean of probability distribution 1302), etc., the outcome probability value 1306 generated from the verification result value of the first programming stage of the simulation of the iterative programming operation can be determined as indicating the presence of a programming anomaly in the iterative programming operation following at least a single programming stage (e.g., the first programming step and the first verification step).

[0237] like Figure 13 As shown, the iterative anomaly detection procedure 900, which includes an iterative model, can detect programming anomalies corresponding to inappropriate starting points of iterative programming operations, which result in unusual threshold voltage distributions after the first programming stage PL1 (e.g., the first programming pulse). Figure 13 The model is shown for The distribution learned is the number of units that pass the first verification level after the first ISPP pulse. The iterative anomaly detection program 900 can compare the distribution 1302 with the distribution for fault procedures. (For example, 1306) is compared. As shown, based on the first programming stage PL1, the iterative model 910 outputs a probability value (1306) indicating a very low likelihood of an iterative programming operation for a fault (for example, in Figure 13 (at S914 in the text), therefore, for example, based on determination (e.g., in Figure 10B The programming operation at S915 corresponds to a probability value that satisfies at least a threshold probability value (e.g., less than 0.001), a threshold variance (e.g., greater than two standard deviations of the mean), etc. Such iterative programming operations can be easily classified as faulty (e.g., including at least one programming anomaly).

[0238] Because the iterative anomaly detection program 900 can detect programming anomalies in the simulation after a single programming stage PL1, faulty programming operations can be terminated and / or corrected without waiting for the entire programming operation (e.g., eight programming stages) to complete. Additionally, programming anomalies other than those programmed to at least a specific verification level (verification voltage) can also be detected. As a result, the performance speed and reliability of devices implementing the iterative anomaly detection program 900 can be improved.

[0239] Next, asFigure 10B As shown, after applying a 14.5V low-voltage pulse to 7 / 8 of the memory cells to simulate a fault erase scenario, iterative programming operation 800 is performed on the multiple memory cells. Figure 14 As shown, the programmed threshold voltage distribution is almost indistinguishable from the threshold voltage distribution of a standard (e.g., non-abnormal) iterative programming operation (e.g., by...). Figure 14 The diagram shows the overlapping portion between the fault distribution map and the non-fault "standard" distribution map. However, as shown... Figure 14 and Figure 15 As shown, the iterative model can be used to clearly distinguish such fault programming operations from standard (non-abnormal) iterative programming operations.

[0240] Figure 16 and Figure 15 The iterative model 910 of the iterative anomaly detection procedure 900 is shown. Figure 16 The operations represented in the figure correspond to the additional programming stages PL (e.g., pulse indexing) of the iterative programming operation 800, and therefore the iterative model 910 has 40 corresponding model stages for each iterative programming operation 800. For each model stage, the iterative model generates a probability value indicating the logarithmic likelihood associated with the existence of a programming anomaly. And for each individual iteration, program the sequence of each probability value. On the line graph, it is represented by a single dashed line connecting data points that represent probability values ​​(as log probabilities) generated for a single iterative programming operation based on the corresponding programming stage (e.g., impulse index) of the iterative programming operation 800 (e.g., based on formula (2) at each model stage).

[0241] Figure 14 and Figure 15 The line graph shown illustrates the sequence of probability values ​​for a given fault iterative programming operation (1504) during multiple programming phases of the iterative programming operation (e.g., )(For example, Figure 16 The distribution shown in the figure can be compared with the probability value sequence of the standard (non-anomaly) iterative programming operation (1502) (e.g., The differences between fault iterative programming operations and standard iterative programming operations are significant. Figure 14 The distribution diagram for fault iteration programming operations is not immediately apparent.

[0242] Still referencing Figure 14A threshold probability value can be stored (e.g., predetermined) for each programming stage (pulse index), and the probability value for a given programming stage can be compared with the corresponding threshold probability value for that given programming stage to determine whether the probability value indicates the occurrence of at least one programming anomaly in the iterative programming operation. Figure 16 As shown, the threshold probability value can be represented as a sequence of threshold probability values ​​corresponding to the individual programming stages that provide the decision boundary 1602, such that, given the probability value of the nth stage... The threshold probability value for comparison (e.g., represented as log probability) changes with the sequence of programming phases.

[0243] The threshold probability value of decision boundary 1602 can be determined empirically and can be stored in a lookup table (e.g., a lookup table stored in the memory of the device implementing the iterative anomaly detection program 900). The threshold probability value of decision boundary 1602 can be defined empirically to establish a decision boundary 1602 that provides the desired false alarm rate. The anomaly detection program can access the lookup table and determine the nth threshold probability value corresponding to the same nth programming stage in response to determining the nth probability value, and further determine whether a programming anomaly has occurred in the iterative programming operation 800 based on whether the nth probability value at least satisfies the nth threshold probability value.

[0244] For example, refer to Figure 16 Each as a result of the above references Figure 16 The simulation describes a sequence of probability values ​​generated by the iterative anomaly detection program 900 corresponding to the iterative fault programming operation 800. The probability value sequences 1504-1 and 1504-2 can provide the probability values ​​at model stage 1 and model stage 2. The probability values ​​are each a negative logarithmic probability less than the corresponding threshold probability values ​​for model stage 1 and model stage 2 represented by decision boundary 1602 at stages (pulse exponents) 1 and 2. Therefore, the iterative anomaly detection procedure 900 can determine that each iterative programming operation represented by sequences 1504-1 and 1504-2 does not have a programming anomaly at model stage 1 and model stage 2, thus deriving a result consistent with... Figure 14 The similarity between the fault distribution map and the standard distribution map shown after the first programming stage corresponds to similar conclusions. However, starting from model stage 3 (corresponding to programming stage 3, impulse exponent 3, etc.), the corresponding third-stage probability values ​​for each iterative programming operation represented by sequences 1504-1 and 1504-2 are... The provided negative log likelihood is approximately 30, which is greater in magnitude than the corresponding 3rd stage threshold probability value including decision boundary 1602 at the 3rd model stage having a negative log likelihood of approximately 25, such that iterative anomaly detection procedure 900 can determine that the respective 3rd stage probability value for each iterative program operation represented by sequences 1504-1 and 1504-2 is greater than the corresponding 3rd stage threshold probability value represented by decision boundary 1602 at the third stage (third pulse index), such that iterative anomaly detection procedure 900 can determine that each iterative program operation represented by sequences 1504-1 and 1504-2 does have at least one program anomaly at model stage 3, in response to which determination, iterative anomaly detection procedure 900 can cause a recovery action to be initiated, including, for example: sending a termination command RC1 to cause iterative program operation 800 to terminate early, and / or performing an error correction operation (e.g., flagging a bad block, changing an address, repeating iterative program operation 800 at a new address, etc.).

[0245] Figure 14 FIG. 17 is a flowchart illustrating a computer-implemented method 1700 of training a neural network, in accordance with some example embodiments. According to some example embodiments, computer-implemented method 1700 can be a computer-implemented method for determining a probability associated with occurrence of at least one program anomaly in an iterative program operation to program a non-volatile memory device having a plurality of storage cells connected through a word line.

[0246] In some example embodiments, the training includes obtaining measurement data indicative of sample verification result values for a plurality of sample iterative program operations (also referred to herein as “standard” or “non-faulty” iterative program operations) that do not include any program anomaly, and then training a neural network (e.g., an RNN) to determine a probability value based on at least some of the sample verification result values, where the neural network is trained to minimize a negative likelihood (e.g., to minimize a negative log likelihood) or to maximize a likelihood indicated by the sample verification result values (e.g., to maximize a log likelihood). Because the sample verification result values correspond to sample iterative program operations that do not include any program anomaly, the probability values determined based on applying the sample verification result values to the neural network as input can be trained to indicate an absence of a program anomaly in a sample iterative program operation via determining the probability value as a likelihood (e.g., a log likelihood) or a negative likelihood (e.g., a negative log likelihood) that a corresponding iterative program operation from which the input verification result value is generated includes or does not include any program anomaly.

[0247] Reference is made to Figure 17At S1712, method 1700 includes performing a set of 1 to M (e.g., one or more) sample iterative programming operations, where M is any positive integer. Performing each sample iterative programming operation includes executing a sequence of one or more programming stages (PLs) to program one or more sample non-volatile storage devices. Such sample iterative programming operations can be as follows: Figure 17 The example shown is performed for iterative programming operation 800. For example, as shown, for each given nth programming stage in 1 to N programming stages of the sample iterative programming operation, each of the 1 to M sample iterative programming operations may include: performing a programming operation (e.g., a programming step) at S1714 to apply a programming voltage Vpgm to a memory cell connected to a selected word line of the sample non-volatile memory device (e.g., corresponding to...). Figure 10A In step S806, and then at S1716, 1 to L verification operations (e.g., verification steps) are performed for each of the 1 to L verification voltages to generate 1 to L sample verification result values ​​for a given nth programming stage. (For example, with) Figure 10A Corresponding to S808 in the above, based on applying a verification voltage to the memory cell connected to the selected word line, the number of memory cells having a threshold voltage equal to or greater than a specific verification voltage in the verification voltage is determined.

[0248] As a result, at S1718, in each of the 1 to M sample iterative programming operations, the sequence of determined (e.g., generating, obtaining, etc.) sample verification result values ​​for each of the L verification voltages and for each of the N programming stages is represented as follows: The sample verification result value determined at S1718 may be referred to herein as measurement data, sample measurement data, standard measurement data, etc., wherein, for each sample iterative programming operation performed on each sample non-volatile memory device, the measurement data includes a sequence of sample verification result values, each sample verification result value indicating the number of memory cells of the sample non-volatile memory device having a threshold voltage equal to or greater than a specific verification voltage at a specific programming stage of the sample iterative programming operation, wherein each sample iterative programming operation in one or more sample iterative programming operations does not include any programming anomalies.

[0249] like Figure 10AFurther shown, at S1720, method 1700 includes: training a neural network to determine the probability associated with the occurrence of at least one programming anomaly in an iterative programming operation programming a non-volatile memory device having multiple memory cells connected by word lines (e.g., generating an indicative probability value or an output that can be used to determine the probability value). The training at S1720 may be performed based on using (e.g., receiving) some or all of the measurement data (e.g., a sequence of sample validation result values). At S1722, the training may include selecting one of the sequences of sample validation result values ​​determined at S1718 (e.g., A sequence of data used as input to a neural network. A neural network can be, for example, a sequence of data that serves as input to the neural network. Figure 17 The RNN shown may include a sequence of 1 to N RNN units, each RNN unit being configured to use one of 1 to N sample validation result values ​​in the sequence (each sample validation result value indicates the number of storage units in a plurality of storage units of a sample nonvolatile storage device having a threshold voltage equal to or greater than a specific validation voltage among L validation voltages at a specific programming stage in N programming stages) as input, and further utilize historical data associated with a previous programming stage at least at the (n-1)th programming stage of the iterative programming operation (or, in the case of the first RNN unit in the sequence, a predetermined zeroth historical data value) to generate an output value for determining a probability value corresponding to the sample validation result value. At S1724, training may include: simulating a neural network to determine at least one probability value associated with the occurrence of at least one programming anomaly in the sequence of programming stages 1 to 10 of the iterative programming operation, based on both the nth sample verification result value and the nth historical data, wherein the nth sample verification result value indicates the number of memory cells among a plurality of memory cells having a threshold voltage equal to or greater than the specific verification voltage at the nth programming stage, and the nth historical data is associated with at least the (n-1)th programming stage of the iterative programming operation. In some example embodiments, the simulation at S1724 includes: based on the corresponding sample verification result value for a specific verification voltage among 1 to N sample verification result values ​​(e.g., To execute each of the 1 to N units (e.g., model stages) of a neural network (e.g., an RNN) to generate a sequence of probability values ​​corresponding to individual sample validation result values ​​(e.g., for the final Nth programming stage, as probabilities) The probability value at S1724 can be determined by... Figure 9 , Figure 9 and / or Figure 10B The execution of one or more model stages of the iterative model in the iterative anomaly detection procedure 900 shown is the same.

[0250] At S1726, the logarithmic function is determined based on the input used during the simulation at S1724 (e.g., sample validation result values) and the probability values ​​generated as simulation results at S1724. At S1728, it is determined whether the loss function determined in S1726 has been optimized (e.g., whether the loss function has been minimized). If yes, then at S1730, it is determined that the neural network has been trained and training has ended. If not, then at S1732, one or more weights and biases used by the neural network are updated based on the loss function (e.g., increasing one or more weights and biases used by the neural network by a predetermined amount), and a sequence of newly selected validation result values ​​(e.g., ...) are used. Repeat the training. Then repeat the process until it is determined that S1728 = .

[0251] As described above, the neural network trained at S1720 can be a recurrent neural network (RNN). The RNN can be trained to determine the probability value at S1724 as one of a negative probability (e.g., a negative log probability) or a probability (e.g., a log probability) corresponding to the probability or negative probability of at least one programming anomaly in the sample iterative programming operation represented by the input validation result value. As described above, training at S1720 can train the RNN to minimize the negative log probability or maximize the log probability.

[0252] In some example embodiments, training at S1720 is performed using backpropagation, for example, in an example embodiment where the neural network being trained is an RNN. In some example embodiments, the determination of the loss function at S1726 includes the negative logarithmic probability as shown in Equation (7) below, although the example embodiments are not limited thereto:

[0253]

[0254] At each stage (e.g., iteration) of training 1720, and for each set of validation results from batches (of measurement data), and for example in the neural network as described above (e.g., based on execution) (linear transformation) determine In an example embodiment of the value, training at S1720 may include: (1) for the nth programming stage, at S1724, validating the sequence of result values ​​using the selected samples. To find the corresponding... through RNN iteration. (2) At S1726, use the formula (7) above. and The loss function is computed, and (3) at S1728, S1730, and / or S1732, the weights and biases of the RNN are updated via backpropagation (e.g., via known backpropagation processes).

[0255] Once it is determined that the neural network is trained (e.g., at S1728 = Yes, the loss function is minimized), the neural network can be applied to a device according to any example embodiment for an iterative anomaly detection procedure. For example, the updated weights and biases of the trained neural network can be applied to the RNN of a device according to any example embodiment to configure the device to utilize the trained RNN as an iterative model of the iterative anomaly detection procedure 900 to determine probabilities associated with occurrences of at least one programming anomaly in an iterative programming operation.

[0256] Figure 11 is a schematic block diagram of an electronic device according to some example embodiments.

[0257] Referring to Figure 18 The electronic device 2000 according to some example embodiments can include a microprocessor 2010 that performs data communication using a bus 2040, a memory 2020, and a user interface 2030. The microprocessor 2010 can include a central processing unit (CPU) or an application processor (AP). The electronic device 2000 can further include a random access memory (RAM) 2050 that directly communicates with the microprocessor 2010. The microprocessor 2010 and / or the RAM 2050 can be implemented in a single module or package. The user interface 2030 can be used to input data to the electronic device 2000 or output data from the electronic device 2000. For example, the user interface 2030 can include a keyboard, a touchpad, a touchscreen, a mouse, a scanner, a voice detector, a liquid crystal display (LCD), a micro light emitting device (LED), an organic light emitting diode (OLED) device, an active matrix light emitting diode (AMOLED) device, a printer, a lighting, or various other input / output devices (without limitation). The memory 2020 can store operation codes of the microprocessor 2010, data processed by the microprocessor 2010, or data received from an external device. The memory 2020 can include a memory controller, a hard disk, or a solid state drive (SSD).

[0258] As described herein, any apparatus, system, module, portion, unit, controller, circuit, and / or portion thereof according to any example embodiment (including but not limited to system 1000, host processor 1100, memory 1200a, memory 1200b, storage 1300a, memory controller 1310a, NVM 1320a, storage 1300b, memory controller 1310b, NVM 1320b, storage 200, storage controller 210, NVM 220, storage 15, memory controller 16, memory device 17, memory device 300, memory interface circuit 310, control logic circuit 320, memory cell array 330, page buffer 340, voltage generator 350, row decoder 360, memory device 600, electronic device 2000, microprocessor 2010, memory 2020, RAM 2050, user interface 2030, any portion thereof, etc.) can include one or more instances of processing circuitry such as hardware including logic circuitry; hardware / software combination such as a processor executing software; or a combination thereof, can be included in, implemented in, and / or realized by one or more instances of processing circuitry such as hardware including logic circuitry; hardware / software combination such as a processor executing software; or a combination thereof, and / or by one or more instances of processing circuitry such as hardware including logic circuitry; hardware / software combination such as a processor executing software; or a combination thereof. For example, more specifically, the processing circuitry can include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a graphics processing unit (GPU), an application processor (AP), a digital signal processor (DSP), a microcomputer, a field programmable gate array (FPGA), a programmable logic unit, a microprocessor, an application specific integrated circuit (ASIC), a neural network processing unit (NPU), an electronic control unit (ECU), an image signal processor (ISP), etc. In some example embodiments, the processing circuitry can include a non-transitory computer readable storage medium (e.g., a memory such as memory 2020 in electronic device 2000 in Figure 18 Figure 18 ​a processor configured to execute a program of instructions to implement functions and / or methods performed by some or all of any apparatus, system, module, portion, unit, controller, circuit, and / or portion thereof according to any example embodiment (including performing any method according to any example embodiment), including, for example, iterative programming operations to program a non-volatile memory device having at least a plurality of storage units (where the plurality of storage units according to any example embodiment are connected by a word line), iterative exception detection procedures according to any example embodiment, neural network training operations according to any example embodiment, any combination thereof, and the like.

[0259] It will be appreciated that, in some example embodiments, a non-transitory computer-readable storage medium (e.g., an SSD storage device) can be provided, where the non-transitory computer-readable storage medium stores a program of instructions that, when executed by at least one processor, is configured to cause the at least one processor to perform any method according to an example embodiment, including, for example, iterative programming operations to program a non-volatile memory device having at least a plurality of storage units (where the plurality of storage units according to any example embodiment are connected by a word line), iterative exception detection procedures according to any example embodiment, neural network training operations according to any example embodiment, any combination thereof, and the like. Such a non-transitory computer-readable storage medium can be provided independently, or can be included in another apparatus (e.g., an electronic device (e.g., Figure 18 Figure 18 a memory 2020 in the electronic device 2000 in

[0260] While the present inventive concept has been described with reference to certain example embodiments thereof, it is to be understood that various other changes or modifications can be made to the present inventive concept without departing from the spirit and scope of the present inventive concept as set forth in the appended claims.

Claims

1. A method for anomaly detection in programming non-volatile storage devices, comprising: An iterative programming operation is performed to program a non-volatile storage device having at least a plurality of memory cells connected by word lines. The iterative programming operation has a sequence of at least a first programming stage to an nth programming stage, where n is a positive integer greater than 1. The nth programming stage includes: Apply the nth programming voltage to the word lines connected to the plurality of memory cells, and A verification operation associated with a specific verification voltage is performed on the plurality of memory cells to generate an nth verification result value, the nth verification result value indicating the number of memory cells in the plurality of memory cells that have a threshold voltage equal to or greater than the specific verification voltage in the nth programming stage, and At least an nth model stage of the iterative model is executed, the nth model stage using the nth verification result value and nth historical data associated with at least the (n-1)th programming stage of the iterative programming operation to determine an nth probability value, the nth probability value indicating the probability associated with the occurrence of at least one programming exception in the first to the nth programming stages of the iterative programming operation.

2. The method according to claim 1, further comprising: Multiple verification operations are performed on the plurality of storage units to generate multiple nth verification result values, wherein, The plurality of verification operations include the verification operations. The multiple verification operations are associated with corresponding individual verification voltages among multiple different verification voltages. The plurality of nth verification result values ​​include the nth verification result value, and Each individual nth verification result value indicates the individual number of memory cells in the plurality of memory cells that have a threshold voltage equal to or greater than the individual verification voltage among the plurality of verification voltages during the nth programming stage; and An nth model stage of executing one or more iterative models, the nth model stage determining a plurality of nth probability values ​​using the plurality of nth verification result values ​​and historical data associated with at least the (n-1)th programming stage of the iterative programming operation, wherein, The plurality of nth probability values ​​includes the nth probability value. Each individual nth probability value is determined by applying one of the plurality of nth verification result values ​​to the one or more iterative models, and Each of the plurality of nth probability values ​​indicates a separate probability associated with the occurrence of at least one programming exception in the first to the nth programming stages of the iterative programming operation.

3. The method according to claim 2, further comprising: Based on determining that at least one of the plurality of nth probability values ​​satisfies at least the corresponding nth threshold probability value, it is determined that at least one programming exception has occurred in the first to the nth programming stages of the iterative programming operation.

4. The method according to claim 2, wherein, The nth model phase of executing the one or more iterative models includes: Execute the nth model stage of each individual iterative model in a plurality of iterative models, wherein the nth model stage of each individual iterative model generates a single nth probability value from the plurality of nth probability values ​​by utilizing a single nth verification result value associated with a specific verification voltage among the plurality of verification voltages and single historical data associated with the specific verification voltage in at least the (n-1)th programming stage of the iterative programming operation. A single iterative model is executed to generate the plurality of nth probability values ​​based on historical data associated with the plurality of verification result values ​​and the plurality of verification voltages in at least the (n-1)th programming phase of the iterative programming operation.

5. The method according to claim 1, further comprising: Based on determining that the nth probability value at least satisfies the nth threshold probability value, it is determined that at least one programming exception has occurred in the first to the nth programming stages of the iterative programming operation.

6. The method according to claim 5, further comprising: The recovery action is performed in response to determining that at least one programming exception has occurred in the first to the nth programming stages of the iterative programming operation, the recovery action including at least one of the following: Error correction operation, The iterative programming operation is terminated before the final programming phase is completed, or Send an alarm signal to provide an indication that at least one of the programming exceptions has occurred.

7. The method according to claim 1, wherein, The nth model phase of the iterative model is executed at least partially concurrently with the (n+1)th programming phase that performs the iterative programming operation at the (n+1)th time step.

8. The method according to claim 1, wherein, Determining the nth probability value includes: The nth conditional probability distribution is determined based on at least the nth model stage of executing the iterative model, the nth conditional probability distribution indicating the distribution of probability values ​​corresponding to the validation result values, and The probability value indicated by the nth conditional probability distribution corresponding to the nth verification result value is determined as the nth probability value.

9. The method according to claim 1, wherein, The iterative programming operation includes a total of N stages, where n is less than N, and The method further includes: determining, before the completion of the Nth programming stage of the iterative programming operation, that at least one programming exception has occurred during the first to the nth programming stages of the iterative programming operation.

10. The method of claim 9, further comprising: A recovery action is performed in response to determining that at least one programming exception has occurred during the first to the nth programming stages of the iterative programming operation, and the recovery action is performed before the completion of the Nth programming stage of the iterative programming operation, the recovery action including at least one of the following: Error correction operation, Terminate the iterative programming operation, or Send an alarm signal to indicate that at least one programming exception has occurred.

11. A storage device, comprising: A non-volatile storage device having at least a plurality of memory cells, wherein the plurality of memory cells are connected by word lines; and The processor is configured as follows: An iterative programming operation is performed to program the non-volatile storage device, the iterative programming operation having a sequence of at least a first programming stage to an nth programming stage. n is a positive integer greater than 1, and the nth programming stage includes: Apply the nth programming voltage to the word lines connected to the plurality of memory cells, and A verification operation associated with a specific verification voltage is performed on the plurality of memory cells to generate an nth verification result value, the nth verification result value indicating the number of memory cells in the plurality of memory cells that have a threshold voltage equal to or greater than the specific verification voltage in the nth programming stage, and At least an nth model stage of the iterative model is executed, the nth model stage using the nth verification result value and nth historical data associated with at least the (n-1)th programming stage of the iterative programming operation to determine an nth probability value, the nth probability value indicating the probability associated with the occurrence of at least one programming exception in the first to the nth programming stages of the iterative programming operation.

12. The storage device of claim 11, wherein the processor is further configured to: Multiple verification operations are performed on the plurality of storage units to generate multiple nth verification result values, wherein, The plurality of verification operations include the verification operations. The multiple verification operations are associated with corresponding individual verification voltages among multiple different verification voltages. The plurality of nth verification result values ​​include the nth verification result value, and Each individual nth verification result value indicates the individual number of memory cells in the plurality of memory cells that have a threshold voltage equal to or greater than the individual verification voltage among the plurality of verification voltages during the nth programming stage, and An nth model stage of executing one or more iterative models, the nth model stage determining a plurality of nth probability values ​​using the plurality of nth verification result values ​​and historical data associated with at least the (n-1)th programming stage of the iterative programming operation, wherein, The plurality of nth probability values ​​includes the nth probability value. Each individual nth probability value is determined by applying one of the plurality of nth verification result values ​​to the one or more iterative models, and Each of the plurality of nth probability values ​​indicates a separate probability associated with the occurrence of at least one programming exception in the first to the nth programming stages of the iterative programming operation.

13. The storage device of claim 12, wherein the processor is further configured to: Based on determining that at least one of the plurality of nth probability values ​​satisfies at least the corresponding nth threshold probability value, it is determined that at least one programming exception has occurred in the first to the nth programming stages of the iterative programming operation.

14. The storage device according to claim 12, wherein, The nth model phase of executing the one or more iterative models includes: Execute the nth model stage of each individual iterative model in a plurality of iterative models, wherein the nth model stage of each individual iterative model uses a single nth verification result value associated with a specific verification voltage among the plurality of verification voltages from the plurality of nth verification result values ​​and single historical data associated with the specific verification voltage in at least the (n-1)th programming stage of the iterative programming operation to generate a single nth probability value among the plurality of nth probability values, or A single iterative model is executed to generate the plurality of nth probability values ​​based on historical data associated with the plurality of verification result values ​​and the plurality of verification voltages in at least the (n-1)th programming phase of the iterative programming operation.

15. An electronic device comprising: The storage device according to claim 11; as well as A control circuit is configured to communicate with the storage device to write data to the storage device and / or read data from the storage device.

16. A non-transitory computer-readable storage medium having a computer program recorded thereon, the computer program being configured, when executed by at least one processor, to cause the at least one processor to perform a method, the method comprising: An iterative programming operation is performed to program a non-volatile storage device having at least a plurality of memory cells connected by word lines. The iterative programming operation has at least a sequence of programming stages from the first to the nth, where n is a positive integer greater than 1. The nth programming stage includes: Apply the nth programming voltage to the word lines connected to the plurality of memory cells, and A verification operation associated with a specific verification voltage is performed on the plurality of memory cells to generate an nth verification result value, the nth verification result value indicating the number of memory cells in the plurality of memory cells that have a threshold voltage equal to or greater than the specific verification voltage in the nth programming stage, and At least an nth model stage of the iterative model is executed, the nth model stage using the nth verification result value and nth historical data associated with at least the (n-1)th programming stage of the iterative programming operation to determine an nth probability value, the nth probability value indicating the probability associated with the occurrence of at least one programming exception in the first to the nth programming stages of the iterative programming operation.

17. The non-transitory computer-readable storage medium of claim 16, further comprising: Multiple verification operations are performed on the plurality of storage units to generate multiple nth verification result values, wherein, The plurality of verification operations include the verification operations. The multiple verification operations are associated with corresponding individual verification voltages among multiple different verification voltages. The plurality of nth verification result values ​​include the nth verification result value, and Each individual nth verification result value among the plurality of nth verification result values ​​indicates the individual number of memory cells in the plurality of memory cells that have a threshold voltage equal to or greater than the individual verification voltage among the plurality of verification voltages during the nth programming stage, and An nth model stage of executing one or more iterative models, the nth model stage determining a plurality of nth probability values ​​using the plurality of nth verification result values ​​and historical data associated with at least the (n-1)th programming stage of the iterative programming operation, wherein, The plurality of nth probability values ​​includes the nth probability value. Each individual nth probability value is determined by applying one of the plurality of nth verification result values ​​to the one or more iterative models, and Each of the plurality of nth probability values ​​indicates a separate probability associated with the occurrence of at least one programming exception in the first to the nth programming stages of the iterative programming operation.

18. The non-transitory computer-readable storage medium of claim 17, further comprising: Based on determining that at least one of the plurality of nth probability values ​​satisfies at least the corresponding nth threshold probability value, it is determined that at least one programming exception has occurred in the first to the nth programming stages of the iterative programming operation.

19. The non-transitory computer-readable storage medium according to claim 17, wherein, The nth model phase of executing the one or more iterative models includes: Execute the nth model stage of each individual iterative model in a plurality of iterative models, wherein the nth model stage of each individual iterative model generates a single nth probability value from the plurality of nth probability values ​​by utilizing a single nth verification result value associated with a specific verification voltage among the plurality of verification voltages and single historical data associated with the specific verification voltage in at least the (n-1)th programming stage of the iterative programming operation, or A single iterative model is executed to generate the plurality of nth probability values ​​based on historical data associated with the plurality of verification result values ​​and the plurality of verification voltages in at least the (n-1)th programming phase of the iterative programming operation.

20. An electronic device comprising: The non-transitory computer-readable storage medium according to claim 16; as well as The processor is configured to execute a computer program recorded on the non-transitory computer-readable storage medium to perform the method.

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