Loss leveling start gap algorithm using multiple gap positions

Abstract

The invention relates to a wear-leveling start gap algorithm using multiple gap positions. Systems, methods, and apparatus are provided for memory management operations in a memory device. In one method, wear leveling for the memory device is performed using a start gap algorithm. The wear leveling is performed using a plurality of gap locations in a single set region. In response to a memory management command, one or more gap locations and corresponding user data are moved. After moving the user data, one or more pointers to the gap location are updated. And updating an initial position pointer of the set region when the gap position completes movement circulation in the set region every time.

Description

[0001] Related Applications

[0002] This application claims priority to provisional U.S. Patent Application No. 63 / 641,667, filed May 2, 2024, the entire disclosure of which is hereby incorporated by reference herein. TECHNICAL FIELD

[0003] At least some embodiments disclosed herein relate generally to memory devices, and more particularly, but not by way of limitation, to memory devices performing memory management operations (e.g., wear leveling). BACKGROUND

[0004] Memory devices can include semiconductor circuitry that provides electronic data storage for a host system (e.g., a server or other computing device). Memory devices can be volatile or non-volatile. Volatile memory requires power to maintain data, and includes devices such as random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), among others. Non-volatile memory can retain stored data when not powered, and includes devices such as flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistive variable memory such as phase change random access memory (PCRAM), resistive random access memory (RRAM), or magnetoresistive random access memory (MRAM), among others.

[0005] A host system (e.g., a host device) can include a host processor, a first amount of host memory (e.g., main memory, typically volatile memory such as DRAM) to support the host processor, and one or more storage systems (e.g., non-volatile memory such as flash memory) to provide additional storage to retain data in addition to or separate from the main memory.

[0006] A storage system (e.g., a solid state drive (SSD)) can include a memory controller and one or more memory devices, including a number (e.g., a plurality) of dies or logical units (LUNs). In certain examples, each die can include a number of memory arrays and peripheral circuitry thereon, such as die logic or a die processor. The memory controller can include interface circuitry configured to communicate with a host device (e.g., a host processor or interface circuitry) over a communication interface (e.g., a bidirectional parallel or serial communication interface). The memory controller may, for example, receive commands or operations associated with memory operations or instructions from a host system, such as read or write operations to transfer data (e.g., user data and associated integrity data, such as error data or address data, etc.) between the memory device and the host device, erase operations to erase data from the memory device, perform drive management operations (e.g., data migration, garbage collection, block retirement), etc.

[0007] Many memory devices, particularly non-volatile memory devices (e.g., NAND flash memory devices, etc.), frequently relocate data or otherwise manage data in the memory device (e.g., garbage collection, wear leveling, drive management, etc.). NAND flash memory is a type of flash memory built using NAND logic gates. Alternatively, NOR flash memory is a type of flash memory built using NOR logic gates.

[0008] Volatility memory devices (e.g., DRAM) typically refresh stored data. For example, a refresh is to activate a row and then pre-charge the row. At the activation time, the data in the cell is sensed (implicit read), and at the pre-charge time, the data is written back to the cell (implicit write).

[0009] A storage device can have a controller that receives data access requests from a host computer and performs programmed computational tasks to implement the requests in a manner that can be specific to the media and structure configured in the storage device. In one example, a flash memory controller manages data stored in flash memory and communicates with a computing device. In some cases, a flash memory controller is used in a solid state drive used in a mobile device, or in an SD card or similar media used in a digital camera.

[0010] Firmware can be used to operate a flash memory controller of a particular storage device. In one example, when a computer system or device reads data from or writes data to a flash memory device, it communicates with the flash memory controller.

[0011] While current memory technologies provide various functionalities and benefits, situations often arise that can potentially cause degradation of memory devices, potential data loss, damage to memory cells of memory devices, and potentially harmful effects to memory devices. For example, certain memory cells of a memory array can be targets of disproportionate numbers of read operations, write operations, other operations, or combinations thereof, as compared to other memory cells of the memory array. In such instances, such memory cells can wear out faster than other, less frequently used memory cells.

[0012] Various techniques exist for extending the life of memory cells and balancing memory usage in memory devices. For example, wear leveling is a memory management technique that can extend the useful life of memory cells of a device by effectively spreading memory usage across various sections of a memory array such that the sections experience comparable memory usage. For example, wear leveling can involve transferring data from a source memory row located in a section of a memory array to a target row that can be located in another section of the memory array, and then mapping addresses of the source memory row to addresses corresponding to the target memory row. Memory management techniques can be enhanced to reduce the amount of memory resources used to perform memory management, reduce errors in data and error correction bits, and further extend the life of memory. SUMMARY

[0013] Embodiments of the present disclosure provide an apparatus comprising: at least one memory array; and at least one controller configured to perform wear leveling for a same cluster using a plurality of gap locations in a cluster of memory locations in the memory array.

[0014] Another embodiment of the present disclosure provides a method comprising: determining a context of a memory device configured to perform memory management using a plurality of gaps in a single cluster; and modulating a duration based on the determined context, wherein at least one of the gaps is moved for the duration.

[0015] Yet another embodiment of the present disclosure provides a system comprising: bias circuitry; a plurality of access lines; and at least one processing device configured to: apply at least one voltage to at least one of the access lines using the bias circuitry to provide access to a first physical memory location and a second physical memory location; copy data from the first physical memory location to the second physical memory location, wherein the second physical memory location is one of a plurality of unused memory locations; and based on copying the data, update a moved pointer corresponding to a first unused memory location. BRIEF DESCRIPTION OF DRAWINGS

[0016] The embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings in which like references indicate similar elements.

[0017] Figure 1 A memory device is shown that biases access lines (e.g., word lines, digit lines, bit lines) to move data when performing wear leveling for memory cells in a memory array, in accordance with some embodiments.

[0018] Figure 2 A memory device is shown that performs wear leveling using multiple gap locations in a cluster, in accordance with some embodiments.

[0019] Figure 3 A sense amplifier latch is shown to hold data associated with memory cells of a memory array, in accordance with some embodiments.

[0020] Figure 4 A data path is shown for read and write operations of a host device for each of multiple banks in a memory device, in accordance with some embodiments.

[0021] Figures 5A to 5E An example of a starting gap algorithm for a cluster using a single gap location is shown.

[0022] Figure 6 Wear leveling is shown using a cluster of multiple gap locations, in accordance with some embodiments, where there is a fixed spacing between the gap locations.

[0023] Figure 7 Wear leveling is shown using a cluster of multiple gap locations, in accordance with some embodiments, where there is a variable spacing between the gap locations.

[0024] Figure 8 Wear leveling is shown using a cluster of multiple gap locations, in accordance with some embodiments, where a separate pointer points to each gap location.

[0025] Figure 9 A method is shown for wear leveling using multiple gap locations in a cluster, in accordance with some embodiments. DETAILED DESCRIPTION

[0026] The following disclosure describes various embodiments for performing memory management operations (e.g., wear leveling) using multiple gap locations in the same cluster. At least some embodiments herein relate to non-volatile memory devices that include a wear leveling manager (e.g., logic circuitry and / or firmware) for performing wear leveling using multiple gap locations in a single cluster of memory cells in one or more memory arrays. In some embodiments, volatile memory devices perform wear leveling using multiple gap locations in the same cluster. These memory devices can, for example, store data used by a host device (e.g., a computing device of an autonomous vehicle, or another computing device that accesses data stored in the memory device). In one example, the memory device is a solid state drive installed in an electric vehicle.

[0027] Storage elements in a memory device can degrade and fail over time with use. In some cases, a memory device can implement an algebraic wear leveling scheme to mitigate wear and an on-die ECC scheme. This wear leveling scheme will adjust the mapping of logical to physical addresses for a wear leveling cluster as part of performing wear leveling. Each wear leveling cluster requires specific circuitry to facilitate wear leveling moves and logical to physical address translations. In one example, a wear leveling cluster is an individual memory bank.

[0028] In some cases, an on-die wear leveling algorithm for a memory device (e.g., DRAM, non-volatile RAM, or NOR flash memory) is based on a starting gap algorithm. The algorithm is used as a cluster of memory locations (e.g., that store user data) in a memory array(s). The cluster contains an extra location (referred to as a gap location, or sometimes simply a gap) that moves (e.g., rolls or cycles) through the cluster. Moving the gap location allows the memory device to remove the correlation between the logical addresses of user data and the physical addresses in memory where the user data is stored. This will evenly distribute access to physical memory along the entire cluster.

[0029] In one example, the use of a starting gap algorithm manages the problem where a user repeatedly accesses the same memory address (e.g., physically accesses the same memory cell). Reading the same physical cell multiple times increases the stress on the cell. Also, programming the same cell multiple times increases the stress on the cell. In one example, a hacker can attempt to access a memory device by stressing cells in this way. The hacker attempts to kill some memory cells (e.g., to break a security system of the memory device). In one example, the hacker can attempt to kill certain cells that store privileged data. This is part of an attempt to gain improper access to a security system.

[0030] DRAMs are generally more resistant to the above issues, but NOR, NAND, and non-volatile RAMs are generally more susceptible to the above issues. For example, in NOR / NAND devices, excessive access degrades the physical cell (and thus its ability to store data), whereas for DRAMs, data is lost but the physical cell is not worn out as much. The wear leveling algorithm overcomes this issue by distributing wear across a larger set of cells by moving user data to different physical cells. Thus, there is a periodic remapping of logical addresses to physical addresses of the cells used by hackers.

[0031] The wear leveling algorithm is applied to a pool of memory cells in a memory device. The larger the pool, the longer the life of the memory device. The size of the pool is limited by the endurance of the memory technology used in the memory device (e.g., measured in terms of the number of reads and / or writes to a given cell). The wear leveling algorithm requires moving locations in the pool before they wear out from frequent access.

[0032] The gap location moves through the pool. The gap location must move to the farthest location in the pool from its starting location before any given memory cell wears out (e.g., due to repeated access by a hacker to a given logical address).

[0033] In one example, the gap location is moved each time a memory management (MM) command is received by the controller or other logic circuitry of the memory device. If Ψ is defined as the ratio between access commands and memory management commands, the size of a suitable pool can be determined as follows: PoolSize < Endurance / Ψ.

[0034] A larger pool distributes memory access over a larger number of physical cells. This reduces the stress on each individual cell. If the pool size is too small, this can cause a technical problem of a shortened life of the memory device.

[0035] However, there can be a technical problem of a memory cell dying before the gap location moves through the entire size of the pool using a larger pool. Thus, the endurance of the physical memory cells in the pool can limit the size of the pool. As an example, consider a memory cell at logical address 0 being repeatedly attacked by a hacker. This situation continues as the gap location moves through the pool. The gap location needs to move to address 0 (so that the stored user data is moved) before the memory cell dies from the attacks. The larger the pool, the longer the stored user data must wait before being moved.

[0036] In one example, the gap location is moved each time a memory management command is received. Normal activity of the memory is suspended in order to move the gap. Moving the gap location requires copying user data to be moved to a new physical address location, and changing the start location and gap location pointers used in implementing the start gap algorithm. When the foregoing operations are complete, the stored user data in the memory is blocked and inaccessible to the host.

[0037] In one example, the issuance of the memory management command can be based on time or activity. For example, the memory management can be performed every 100 write commands. In one example, the memory die receives this command from the memory controller.

[0038] In one example, each physical memory cell has a durability of up to one million accesses. The bin size is 1,000 memory cells, and Ψ is 1,000. It is desirable for Ψ to remain high to avoid significantly degrading quality of service or bandwidth.

[0039] In one example, an algebra-based wear leveling scheme, such as the start gap algorithm discussed above, for example, uses extra rows in the memory array to allow wear leveling moves. A wear leveling move consists of moving source data (e.g., pointed to by a source pointer) to a target row (e.g., pointed to by a target pointer). The physical address is determined by adding the current or next offset to the logical address. Given a logical address, and assuming the target and source pointers are properly maintained, the algorithm allows the physical address to be determined. The source data at the source address is moved to the target address. The target and source pointers are updated after each wear leveling move. The offset pointer is updated periodically according to the moves.

[0040] In one example, wear leveling moves can be triggered by an activity-based, such as a refresh management (RFM) command for DRAM, or periodic memory management (MM) command, such as based on a repeating time interval. For example, each memory management command causes a wear leveling move to occur. The amount of movement in a bin caused by a MM command is related to the number of gap locations available. In one embodiment, a multiple memory management (MMM) command can be used, which suspends and governs multiple banks and applies memory management operations in each of the multiple banks in parallel. In contrast, a single MM command is applied to only one bin and suspends other memory activity on the bank that the bin is located.

[0041] In one example, the memory device is a flash memory in an SSD, or a device using another memory technology with cells that sustain enough wear to require wear leveling to ensure sufficient lifetime. A wear leveling set includes cycling through wear leveling moves such that any given logical address (e.g., for stored user data) can be associated with any physical address in the set over time. An activity-based refresh management command (RFM) for DRAM is used to trigger the wear leveling moves. In one example, the wear leveling moves are split into two parts using a holding register. The data is ECC cleaned as it is transferred from the source address to the holding register. Then, the data is moved from the holding register to the target address one codeword at a time.

[0042] In one example, the source data is ECC cleaned before the source data is written to the target row during wear leveling. Cleaning correctable errors during wear leveling prevents the accumulation of correctable errors that can aggregate into uncorrectable errors. Thus, cleaning correctable errors during wear leveling reduces the likelihood of experiencing uncorrectable errors.

[0043] In one example, each memory bank in the memory device has its own wear leveling engine, and multiple memory banks can be maintained in parallel. In one case, if a multi-memory management command is used, wear leveling occurs in parallel for several memory banks. While the cleaning process for wear leveling is occurring, the controller cannot access any data in any memory bank (e.g., within a memory bank group).

[0044] Various embodiments of the present disclosure provide technical solutions to one or more of the above technical problems. In one embodiment, a wear leveling initiation gap algorithm in a memory device uses multiple gap locations for a single set. For example, using several gap locations per set (rather than using only a single gap location per set, as described above) allows for optimization of wear leveling algorithms for memory devices using newer memory technologies (e.g., phase change memory using chalcogenide memory cells) that have lower inherent endurance than existing technologies (e.g., non-volatile RAM, SRAM). Using several gap locations in the same set allows for the use of larger sets, which provides lifetime benefits while ensuring that the memory cells in the set do not die before being moved (e.g., as described above) as the gap locations cycle through the set.

[0045] In one embodiment, a memory device has a memory array configured to store user data of a host device. A controller performs wear leveling for a set of memory locations in the memory array using a start-gap algorithm implemented using a plurality of gap locations in the same set. The memory device includes a register storing a respective pointer for each of the gap locations. For example, the gap locations can be stored in a register, RAM, FIFO buffer, and / or other memory accessible to the controller.

[0046] The memory device also includes a register or other memory to store a start location for the set. The start location is incremented after a last of the gap locations cycles through all memory locations in the set. The gap locations can be moved by the same memory management command, or each gap location can be moved by a different memory management command.

[0047] In one embodiment, the memory device includes bias circuitry to apply a voltage to an access line for accessing a memory cell. For example, a processing device of the controller uses the bias circuitry to apply a voltage to an access line to provide access to a first physical memory location and a second physical memory location (e.g., memory cells accessed using an activated word line).

[0048] In response to the memory management command, the controller manages the wear leveling set by copying data from the first physical memory location to a second physical memory location. The second physical memory location is one of a plurality of unused memory locations (e.g., a plurality of gap locations) in the same set.

[0049] After copying the data, the controller updates a pointer corresponding to movement of one or more of the unused memory locations (e.g., updates the pointer for moving the first and second gap locations in the set). In one embodiment, the gap pointer is updated based on a number of memory locations moved during a memory management operation initiated by the memory management command.

[0050] The unused memory locations cycle through a set of physical memory locations in the wear leveling set. For example, the start location is updated when a last of the unused memory locations completes a cycle through a fixed number or range (e.g., a defined range or subset of the set) of physical memory locations.

[0051] In one embodiment, each bank group in a memory device contains its own ECC engine(s) (e.g., located at the edge of the bank group). The ECC engine(s) are used during standard read and write commands using data path operations. The ECC engine(s) are also used to facilitate ECC clean-up during wear leveling moves. The ECC engine(s) serve read and write as well as other memory management operations (e.g., clean-up during wear leveling).

[0052] In one embodiment, a memory device has a controller that moves data from a source page to a target page during wear leveling. The data is updated as needed based on error correction of the data. The memory device includes error correction circuitry (e.g., a wear leveling ECC engine) to perform error correction. After error correction, the controller moves the data to the target page.

[0053] In one embodiment, a codeword ECC engine is used to detect and correct errors on a given codeword. The codeword is composed of data to be processed by the codeword ECC engine and parity bits. Clean-up by the codeword ECC engine is triggered by memory management operations.

[0054] Figure 1 A memory device is shown that biases an access line 140 (e.g., precharges a word line or bit line) to move data when performing wear leveling (e.g., using a start-gap algorithm that employs multiple gap locations in a cluster) for memory cells 110 in a memory array 102 in accordance with some embodiments. In one example, the memory device precharges a word line and / or bit line in a precharge phase to prepare for sensing memory cells 110 in the memory array 102. In one example, the memory cells 110 are chalcogenide memory cells. In one example, a controller 120 controls the timing of turning on and off the precharge.

[0055] A memory device is configured as a memory package 101 that encapsulates memory dies 132, 142. Each memory die 132 has a local wear leveling manager 119. A memory controller 120 of the memory die 142 communicates with one or more memory dies 132. The memory controller 120 includes a wear leveling manager 117. Wear leveling using multiple gaps in a cluster as described herein can be implemented by the wear leveling manager 117 and / or the wear leveling manager 119. The wear leveling managers 117, 119 can be implemented using logic circuitry, state machines, and / or firmware.

[0056] Sensing circuitry 122 senses the state of memory cells 110. Sensing circuitry 122 includes detector 130. In one example, detector 130 is a transistor, an inverter, or a differential amplifier. Memory cells 110 are selected using access lines 140. In one example, access lines 140 include word lines and bit lines in a cross-point memory array.

[0057] Biasing circuitry 124 biases selected ones of access lines 140 for selecting a portion of memory cells 110 to be sensed. Biasing circuitry 124 also supplies power to sensing circuitry 122, including to detector 130.

[0058] Memory controller 120 controls various operations of the memory device, including read and write operations to memory cells 110. Memory controller 120 includes processing device 116 and memory 118. Controller 120 controls some operations in response to various commands received from host device 126 on communication interface 150.

[0059] In one embodiment, communication interface 150 receives a read or write command from host device 126. In response to receiving the command, controller 120 initiates a read or write operation. For example, as part of a read operation, memory cells 110 are selected to have their logical state determined by sensing circuitry 122.

[0060] Biasing circuitry 124 drives voltages on access lines 140 to select memory cells, including driving voltages on word lines or bit lines used to select memory cells. To sense the state of a memory cell, detector 130 monitors the voltage on a bit line.

[0061] In one embodiment, in a pre-charge phase using pre-charge circuitry, the voltage on a bit line is first driven to an initial voltage. After the bit line reaches the initial voltage, pre-charge is turned off. Then, detector 130 is used to detect whether the bit line voltage is pulled low due to a memory cell 110 having reached a switching threshold. In other embodiments, instead of or in addition to bit lines, word lines or other access lines can be pre-charged and sensed.

[0062] Detector 130 detects voltage changes on a bit line caused by memory cell switching. The output of detector 130 is used by sensing circuitry 122 to determine the logical state (e.g., 1 or 0) of a memory cell that has been read.

[0063] In one embodiment, memory cell 110 stores user data of host device 126. Memory cell 110 stores data in either a first logic state or a second logic state. In one example, bias circuitry system 124 includes word line and bit line drivers (not shown) to bias the word lines and bit lines of memory array 102.

[0064] The sensing circuitry 122 may include a sensing amplifier for sensing characteristics associated with memory cells of the memory array 102. These characteristics may be, for example, voltage and / or current associated with a selected memory cell. In one embodiment, this characteristic is used by a controller to determine the duration of a loss equalization operation, as described below.

[0065] In one embodiment, controller 120 causes bias circuitry 124 to apply voltage to selected memory cell 110. In one instance, the voltage is an increment of voltage values ​​separated by steps (e.g., 0.5V steps) (e.g., +2, +2.5, +3, +3.5, +4, +4.5, +5V).

[0066] In one embodiment, the memory controller 120 includes one or more processing devices 116 and a memory 118. In one example, the memory 118 stores firmware executed by the processing device 116 to select and apply read voltages. The memory controller 120 may use a bias circuit system 124 to generate voltages for applying read and other voltages (e.g., initial read and read retries). The bias circuit system 124 may also generate voltages for applying write voltages to the memory cells 110 as part of a programming operation (e.g., as used in wear leveling).

[0067] In one embodiment, if the sensing circuitry 122 determines that the current of a memory cell is greater than a fixed threshold (e.g., a predetermined current level), then the memory controller 120 determines that the memory cell has been switched (e.g., a sudden change).

[0068] In one embodiment, the memory controller 120 receives a write command from the host device 126. The write command is accompanied by data to be written to the memory array 102 (e.g., user data of the user of the host device 126). In response to receiving the write command, the controller 120 initiates a programming operation.

[0069] In one instance, the polarity of a read or write pulse can be either a first polarity or a second polarity. For example, a write pulse can apply a voltage to a memory cell of the first polarity (e.g., a bit line at 6V and a word line at 0V).

[0070] In one example, circuitry coupled to access lines that can be coupled to the memory cell is used to provide read pulses (e.g., access line drivers included in decoder circuitry). This circuitry may be controlled by internal control signals provided by control logic (e.g., controller 120). The read voltage or pulse may be a voltage applied to the memory cell over a period of time (e.g., 10 to 50 ns, 1 to 100 ns, 1 ns to 1 microsecond). In some embodiments, the read pulse may be a square wave pulse. In some embodiments, the read pulse may be a ramp, i.e., a linearly increasing voltage may be applied across the memory cell.

[0071] In one instance, after being accessed (e.g., selected), the memory cell can be read or sensed by a sensing component (e.g., sensing circuitry 122) to determine the stored state of the memory cell. For example, a voltage can be applied to the memory cell (using word lines and bit lines), and the presence of the resulting current can depend on the applied voltage and the threshold voltage of the memory cell. In some cases, more than one voltage can be applied. Additionally, if the applied voltage does not result in current flow, other voltages can be applied until the sensing component detects current.

[0072] The stored logic state of a memory cell can be determined by evaluating the voltage that causes current flow. In some cases, the voltage may ramp up until current flow is detected (e.g., the memory cell is turned on, switched on, conducts current, or is activated). Current can be applied to the memory cell, and the magnitude of the voltage that produces the current may depend on the resistance of the memory cell or a threshold voltage.

[0073] In some cases, memory cells (e.g., PCM cells) contain materials that can change their crystalline configuration (e.g., between a crystalline phase and an amorphous phase), which in turn determines the threshold voltage of the memory cell for storing information. In other cases, memory cells contain materials that maintain a crystalline configuration (e.g., an amorphous phase), which can exhibit a variable threshold voltage for storing information.

[0074] The sensing component may include various transistors or amplifiers to detect and amplify signal differences. The detected logic state of the output memory cell can then be used as an output via a column decoder. In some cases, the sensing component may be part of a column decoder or a row decoder.

[0075] At least some embodiments herein relate to memory devices that use bipolar operation for memory arrays (e.g., for multilevel memory cells). In one example, a bipolar selection voltage is used to select memory cells in the memory array. In one example, the memory cells are arranged in a crosspoint architecture. In one example, each memory cell is formed using a single selection device. In one example, the selection device comprises a chalcogenide material that switches (e.g., abruptly changes) when a sufficient voltage is applied across the memory cell.

[0076] In some cases, the memory device may include an array of memory cells arranged in a three-dimensional (3D) architecture (e.g., a cross-point architecture) to store a set of data. The memory cells in the cross-point architecture may, for example, represent a first logic state (e.g., logic 1, set state) associated with a first set of threshold voltages, or a second logic state (e.g., logic 0, reset state) associated with a second set of threshold voltages.

[0077] In other embodiments, the memory cells may be arranged in a three-dimensional (3D) vertical architecture. The 3D vertical architecture may include memory cells located at the intersections of vertical access lines (e.g., bit line struts) and each of a plurality of second access lines (e.g., word lines), the memory cells being formed in horizontal planes or stacks parallel to each other.

[0078] More generally, integrated circuit memory cells (e.g., cross-point memory or memory cells in a 3D vertical array) can be programmed to store data by their state under a voltage applied across the memory cell. For example, if a memory cell is configured or programmed such that a considerable current is allowed to pass through the state of the memory cell at a voltage within a predefined voltage range, then the memory cell is considered to be configured or programmed to store a first bit value (e.g., 1 or 0); otherwise, the memory cell stores a second bit value (e.g., 0 or 1).

[0079] Optionally, a memory cell can be configured or programmed to store more than one data bit by being configured or programmed, for example, to have a threshold voltage in one of more than two separate voltage regions.

[0080] In one example, the threshold voltage of a memory cell causes it to switch rapidly or abruptly (e.g., for chalcogenide memory cells) or jump from a non-conductive state to a conductive state when the voltage applied across the memory cell increases above the threshold voltage. The non-conductive state allows a small leakage current to flow through the memory cell; conversely, the conductive state allows more current than the threshold amount to flow. Therefore, the memory device can use a detector (e.g., a sense amplifier) ​​to detect the change or determine one or more conductive / non-conductive states of the memory device under applied voltage to evaluate or classify the level of the threshold voltage of the memory cell and thus its stored data.

[0081] For example, memory cells in memory array 102 can be configured or programmed to store one data item in single-level cell (SLC) mode, two data items in multi-level cell (MLC) mode, three data items in three-level cell (TLC) mode, or four data items in four-level cell (QLC) mode.

[0082] Figure 2 A memory device 202 is shown that performs wear leveling using multiple gap locations in cluster 230 according to some embodiments. In one example, cluster 230 is part of memory array 206 (e.g., having 25% of the size of the memory bank). In one example, memory array 206 has a total of eight memory banks. User data is stored in one or more of the memory array 206. Bias circuitry 224 applies voltage to the access lines of memory array 206. In one example, bias circuitry 224 activates word lines in memory array 206.

[0083] Controller 204 uses register 240 to implement loss leveling management. Loss leveling for a set of memory locations in cluster 230 of memory array 206 can be managed using a start-gap algorithm applying multiple gap locations in cluster 230. In one embodiment, cluster 230 includes memory to store data (e.g., start location, gap location spacing or offset, size) about the cluster of memory cells of memory array 206 to which loss leveling is applied. Register 240 stores a pointer to the start location of cluster 230 and one or more pointers to multiple gap locations. In one embodiment, controller 204 uses the data stored in register 240 to determine the physical address location in the cluster based on a logical address received from host device 201. For example, when using the start-gap algorithm described herein, only the start location and gap location information are needed to determine the physical address from the logical address. This provides a very lightweight translation table.

[0084] In one instance, controller 204 implements loss leveling manager 117. Controller 204 is an instance of memory controller 120. Memory array 206 is an instance of memory array 102.

[0085] In one embodiment, error correction circuitry 210 serves memory management operations performed on data stored in memory array(s) 206. A portion of the data from memory array(s) 206 is copied to a temporary storage device (e.g., a buffer) during servicing (e.g., wear leveling). In one instance, the temporary storage device includes holding registers. In one instance, error correction circuitry 210 includes a wear leveling ECC engine.

[0086] Error correction circuitry system 210 serves read and write operations. For example, a read or write operation is performed in response to a command or other signal received from host device 201.

[0087] Controller 204 accesses portions of memory array 206 in response to commands received from host device 201 via communication interface 216. Sensing amplifier 208 senses data stored in memory cells of memory array 206. Controller 204 accesses stored data by activating one or more rows of memory array 206. In one instance, the activated row corresponds to a page of stored data. In one instance, controller 204 receives memory management commands from host device 201 via communication interface 216.

[0088] When a row of memory array 206 is activated, data can be read from that row as part of a read or other operation (e.g., wear leveling). Error correction circuitry 210 is used to detect and correct any errors identified in the accessed data on the row (e.g., for reads requested by host device 201). Corrected read data is provided for output at communication interface 216 by I / O circuitry 214.

[0089] In one embodiment, the communication interface (I / F) 216 is a bidirectional parallel or serial communication interface. The host device 201 may include a host processor (for example, a host central processing unit (CPU) or other processor or processing circuitry, such as a memory management unit (MMU), interface circuitry, etc.).

[0090] In one embodiment, memory array 206 may be configured in several non-volatile memory devices (e.g., dies or LUNs), such as one or more stacked flash memory devices, each comprising a non-volatile memory (NVM) having one or more groups of non-volatile memory cells and a local device controller or other peripheral circuitry (e.g., device logic, etc.), and controlled by controller 204 via an internal memory system communication interface (e.g., an Open NAND Flash Interface (ONFI) bus, etc., separate from communication interface 216.

[0091] In one embodiment, each memory cell in the NOR, NAND, 3D crossover, MRAM, or one or more other architecture semiconductor memory arrays 206 can be individually or collectively programmed into one or more programmed states. A single-level cell (SLC) can represent one data bit per cell in one of two programmed states (e.g., 1 or 0). A multi-level cell (MLC) can represent several programmed states (e.g., 2... n In a memory cell (where n is the number of data bits), each cell contains two or more data bits. In some instances, MLC can refer to a memory cell that can store two data bits in one of four programmable states. A three-level cell (TLC) can represent three data bits per cell in one of eight programmable states. A four-level cell (QLC) can represent four data bits per cell in one of 16 programmable states. In other instances, MLC can refer to any memory cell that can store more than one data bit per cell, including TLC and QLC.

[0092] Controller 204 may receive instructions from host device 201 and may transfer (e.g., write or erase) data to or from one or more memory cells of memory array 206. Controller 204 may include, in particular, circuitry or firmware, such as components or integrated circuits. For example, controller 204 may include one or more memory control units, circuitry, or components configured to control access across the memory array and provide a translation layer between host device 201 and the memory system, such as a memory manager, one or more memory management tables, etc.

[0093] In one embodiment, controller 204 may include circuitry or firmware, such as several components or integrated circuits associated with various memory management functions, including wear leveling, error detection or correction, memory bank or block deactivation, or one or more other memory management functions, as well as other functions.

[0094] In one embodiment, controller 204 may include a set of management tables configured to maintain various information associated with one or more components of memory device 202 (e.g., various information associated with cluster 230, memory array 206, and / or one or more memory cells coupled to controller 204). For example, the management tables may contain information about the age of a memory bank or block coupled to controller 204, block erase counts, error history, or one or more error counts (e.g., write operation error counts, read bit error counts, read operation error counts, erase error counts, etc.). In some instances, a bit error may be referred to as an uncorrectable bit error if the number of detected errors in one or more of the error counts exceeds a threshold. The management tables may maintain counts of correctable or uncorrectable bit errors, etc.

[0095] In one embodiment, memory device 202 may include one or more three-dimensional (e.g., 3D NAND) architecture semiconductor memory arrays 206. Memory array 206 may include a plurality of memory cells arranged as, for example, a memory bank, several devices, planes, blocks, physical pages, superblocks, or superpages. As an example, a TLC memory device may include 18,592 data bytes (B) per page, 1,536 pages per block, 548 blocks per plane, and 4 planes per device.

[0096] In one embodiment, data may be written to or read from memory device 202 page by page. However, one or more memory operations (e.g., read, write, erase, etc.) may be performed on larger or smaller groups of memory cells as needed. For example, partial updates to tagged data from offloading units may be collected during data migration or obsolete item collection to ensure efficient rewriting.

[0097] In one instance, a data page contains several bytes of user data (e.g., data payload) and its corresponding metadata. As an example, a data page may contain 4kB of user data and several bytes (e.g., 32B, 54B, 224B, etc.) of auxiliary data or metadata corresponding to the user data, such as integrity data (e.g., error detection or error correction code data), address data (e.g., logical address data, etc.), or other metadata associated with the user data. Different types of memory cells or memory arrays may provide different page sizes or may require different amounts of metadata associated with them.

[0098] Figure 3Sensing amplifier latches 320, 321, and 322, according to some embodiments, are shown for storing data associated with memory cells 310, 311, 312, and 313 of a memory array. In one example, the memory cells are located in memory arrays 102 and 206. The memory cells can be of various memory types, including volatile and / or non-volatile memory cells.

[0099] Memory cells are accessed using word lines (e.g., WL0) and digital lines (e.g., DL0) or bit lines. Individual memory cells are accessed by activating a word line selected by row decoder 330 and selecting a digital line or bit line selected by column decoder 340. When a word line is activated, data from each memory cell on the row flows from the cell to the corresponding sense amplifier latch for each digital line or bit line.

[0100] Data residing in the sense amplifier latch can be used as input to logic circuit systems 350, 351 for various calculations. These calculations may include using parity bits or other metadata stored in memory cells to detect and / or correct errors in data retrieved from memory cells. In one embodiment, logic circuit system 350 includes error correction circuit system 210. In one instance, logic circuit system 350 is arbitrary logic that operates on data at the page level.

[0101] Logic circuit system 351 is coupled to column decoder 340. In one embodiment, logic circuit system 351 includes error correction circuit system 210. In one instance, logic circuit system 351 is arbitrary logic (e.g., using an ECC engine) that operates on data at the column (e.g., codeword) level.

[0102] In one embodiment, the memory device including a memory array has a plurality of memory cells 310, 311, 312, 313, etc., and one or more circuits or components to provide communication with the memory array or to perform one or more memory operations on the memory array. A single memory array or additional memory arrays, dies, or LUNs can be used. The memory device may include a row decoder 330, a column decoder 340, a sense amplifier, a page buffer, a selector, an input / output (I / O) circuit system, and a controller.

[0103] In some non-volatile memory devices (e.g., NAND flash memory), the memory cells of the memory array can be arranged in blocks. Each block can contain sub-blocks. Each sub-block can contain several physical pages, and each page contains several memory cells. In some instances, the memory cells can be arranged in several rows, columns, pages, sub-blocks, blocks, etc., and accessed using, for example, access lines, data lines, or one or more select gate, source lines, etc.

[0104] In volatile memory devices (e.g., DRAM) and some emerging non-volatile memory technologies, the memory cells of a memory array can be arranged as banks or other forms of partitions. In one example, when an activation for a row address is issued, the row address is addressed by using the bank address (to specify which bank within the memory device) and the row address (to specify which row within the specified bank) to address the bits on the activation command. The word line associated with the row address is pulled high.

[0105] A controller (e.g., controller 204) can control memory operations of the memory device based on one or more signals or instructions received on a control line (e.g., from host device 201), said signals or instructions including one or more clock signals or control signals, or address signals (A0 to AX) received on one or more address lines, indicating the desired operation (e.g., write, read, erase, etc.). One or more devices external to the memory device can control the values ​​of the control signals on the control line or the address signals on the address lines. Examples of devices external to the memory device may include, but are not limited to, a host, a memory controller, a processor, or one or more circuits or components.

[0106] Memory devices can use access lines and data lines to transfer (e.g., write or erase) data to or from one or more memory cells (e.g., read) data (e.g., when moving user data in wear leveling). Row decoders and column decoders can receive and decode address signals (A0 to AX) from address lines, determine which memory cells will be accessed, and provide signals to one or more access lines (e.g., one or more word lines (e.g., WL0 to WLm)) or one or more data lines (e.g., one or more bit lines (BL0 to BLn)).

[0107] The memory device may include sensing circuitry configured to determine, for example, a data value read from or to be written to a memory cell using data lines, such as a sense amplifier 208. In one example, the sense amplifier is used to sense voltage (e.g., in the case of charge sharing in DRAM). In one example, in a selected memory cell, one or more of the sense amplifiers may read a logic level in the selected memory cell in response to a read current flowing through the selected cells to the data lines in the memory array.

[0108] One or more devices external to the memory device may communicate with the memory device using I / O lines (e.g., DQ0 to DQN), address lines (e.g., A0 to AX), or control lines. An I / O circuitry (e.g., 214) may use the I / O lines to pass data values ​​into or out of the memory device, such as into or out of a page buffer or memory array, according to, for example, control and address lines. A page buffer may store data received from one or more devices external to the memory device before data is programmed into the relevant portion of the memory array, or data read from the memory array before data is transferred to one or more devices external to the memory device.

[0109] The column decoder 340 can receive address signals (e.g., A0 to AX) and decode them into one or more column select signals (e.g., CSEL1 to CSELn). A selector (e.g., selector circuitry) can receive the column select signals (CSEL1 to CSELn) and select data in the page buffer representing a data value to be read from or programmed into a memory cell. The selected data can be transferred between the page buffer and the I / O circuitry system.

[0110] Figure 4 Data paths 404, 406 are illustrated according to some embodiments for read and write operations by a host device (e.g., 201) for each of a plurality of storage banks in a memory device. The storage banks may be arranged in a group of storage banks (e.g., as denoted by "storage bank group"). <n>"any number of banks" n indicated).

[0111] Data paths 404, 406 are examples of data paths that include I / O circuitry 214 and communication interface 216. In one embodiment, each bank group has an associated ECC engine 420, 421. ECC engines 420, 421 service read and write operations on data paths 404, 406. ECC engines 420, 421 are examples of error correction circuitry 210.

[0112] In some embodiments, to reduce total scrub time, there can be multiple ECC engines on the memory device to allow scrubbing of multiple banks in parallel. For example, a memory device can contain four bank groups and four ECC engines. In this case, each bank group is associated with its own ECC engine. A memory management group can contain a subset of banks that can exist across one or more bank groups.

[0113] In one example, each page of a bank is composed of a codeword or column. The page is a specific set of memory cells that are activated when an activate command is issued. The activate command has a bank address as well as a row address.

[0114] In one embodiment, each bank group is coupled to a particular data path of that bank group. In one example, the data path is 100 bits wide.

[0115] In one example, a particular memory die can have multiple memory management groups. Memory management commands are issued to a particular memory management group. This causes memory management operations to occur for all banks in the group. The group is coupled to the ECC engine(s). The controller iterates through each bank in the group. In one example, the standard data bus for a memory device is a bidirectional bus.

[0116] Figures 5A to 5E An example of a starting gap algorithm using a cluster of single gap locations is shown. The cluster includes memory cells located at physical addresses 502 (e.g., 0 to 16). Physical addresses 502 correspond to memory locations in the cluster that can store user data (e.g., A to P). One of the memory locations is not used to store user data. Instead, the unused memory location is a gap location 506 that is moved through the cluster when wear leveling is performed in response to a memory management command.

[0117] The first user data enters the zone at a start location 504. A gap location 506 starts at, for example, physical address 16. The gap location 506 is decremented with each execution of a data move, as illustrated. When the gap location 506 completes a full cycle through the zone, the start location 504 is incremented to the next address, as illustrated in Figure 5E

[0118] As Figure 5A illustrated in the example, user data A through P can be considered to be stored at logical addresses 0 through 15. For example, user data A is stored at logical address 0, and user data P is stored at logical address 15.

[0119] In performing a first wear leveling operation, user data P is copied or moved from physical address 15 to physical address 16, as illustrated in Figure 5B After the data is moved, the pointer to the gap location is decremented to physical address 15. For example, user data P has a logical address of 15 (from the user / host perspective), but is stored at physical address 16 after being moved.

[0120] As Figure 5C illustrated in the example, user data H stored at physical address 7 is moved to the gap location at physical address 8 after several wear leveling operations have been performed. The pointer to the gap location is decremented to physical address 7.

[0121] In general, the physical address at which user data is stored can be determined based on a comparison of the logical address of the user data to the gap location. If the logical address of the user data is after the gap location, the logical address is incremented by 1 to determine the physical address. If the logical address of the user data is before the gap location, the logical address is incremented by 0 to determine the physical address. The logical address is also adjusted by the value of the start location to determine the physical address.

[0122] Eventually, as Figure 5D illustrated in the example, the gap location 506 reaches the start location 504. User data P is moved from physical address 16 to physical address 0. The gap location 506 is moved from physical address 0 to physical address 16. Because the application has completed a full cycle through the zone, the pointer to the start location 504 is incremented by 1 so that the start location 504 is at physical address 1, as illustrated in Figure 5E

[0123] As Figure 5E illustrated in the example, the next cycle of the gap location 506 begins by moving the gap location 506 from physical address 16 to physical address 15. User data O is moved to physical address 16.

[0124] ​​In one example, the physical address of stored user data is determined based on the logical address of the data, the start location 504, and a comparison of the logical address to the gap location 506 (e.g., the logical address 14 of user data O is added to the start location 1 and incremented by 1 due to being located after the gap location 506 to provide a physical address of 14 + 1 + 1 = 16) (note that this is not shown in Figure 5E

[0125] As described above, the start gap algorithm moves stored data to a different physical address in the cluster to distribute wear. The gap location address is not available to the user. The start location and this gap allow the data to be moved. For example, both the start address and the gap address are hidden from the user (e.g., a hacker) to avoid allowing the user / hacker to track the location of the physical unit under attack.

[0126] In one example, the cluster has physical addresses 0 to 16. The host / user has programmed data A to P into logical addresses 0 to 15. For wear leveling, data P is first moved by copying into physical address 16. Then, the controller changes the address mapping of data P. The logical address 15 of user data P now points to physical address 16 in the cluster. Thus, when the host / user reads logical address 15, data is accessed from physical address 16.

[0127] In one example, two counters are used: one counter is a start counter, the other counter is a gap counter. The start counter indicates the horizontal level of the gap cycle through the cluster. Once the gap moves to physical address 0, the start counter moves / increases because the gap has moved through a full cycle.

[0128] In one example, the start counter indicates the initial or first physical location of user data. The controller uses the start and gap counters along with logic circuitry (e.g., an adder) to determine the association between logical addresses and physical addresses. In one example, the memory device has multiple managed clusters.

[0129] Figure 6 Wear leveling is shown that uses multiple gap locations per cluster according to some embodiments, with a fixed delta spacing between the gap locations. For example, the four gap locations shown (e.g., GL0, GL1, GL2, GL3) are separated by a fixed offset or delta (e.g., the gap locations are determined as the first gap location + delta, the first gap location + 2 delta, the first gap location + 3 delta, as shown).

[0130] The illustrated cluster stores user data A to X. The illustrated cluster includes four gap locations. The illustrated cluster is an example of cluster 230. In one example, the location of the pointer to the gap location gap 0 is stored in register 240. ​

[0131] In one embodiment, a single pointer is stored for the first gap location (GapO). When a memory management command is received, the other three gap locations can be determined based on multiples of the offset from the first application, as explained. In one embodiment, the controller uses a single gap register to manage all gap locations (GL) of a pool. In one embodiment, all gap locations of a pool are moved by the same memory management command.

[0132] As explained, when multiple gap locations are used, the start location is incremented similarly as discussed above. Note that each gap location cycles through the entire or whole pool. The start location is incremented, for example, when Gap3 (GL3) completes a cycle of all user data A through X movement through.

[0133] In one embodiment, the calculation of the logical to physical address mapping uses similar principles as the start gap algorithm for a pool using a single gap location described above. However, when performing the logical to physical address mapping, the logical address is compared to multiple (e.g., four) gap location values, rather than a single gap location value.

[0134] The pool size when using multiple gap locations per pool can increase compared to the pool size when using a single gap location as described above. The pool size is now given by:

[0135] PoolSize < Endurance * NbGLperPool / Ψ, where NbGLperPool is the number of gap locations per pool.

[0136] In one embodiment, the gap locations are evenly distributed in the pool. In one embodiment, the gap locations can be unevenly distributed. However, this can not be optimal as the maximum gap (Amaz) will be a limiting factor on the pool size. The maximum increment is given by: Amaz < endurance / Ψ.

[0137] For a pool with distributed gap locations, the limitation on size is the distance between a gap location and the farthest address that the gap location must move to complete a cycle. Staying within the maximum increment (Amaz) ensures that each respective gap location reaches the farthest address before the corresponding physical cell attributed to the access of the cell is repeatedly stressed to death.

[0138] In one embodiment, a single register is used to manage all gap locations. Moving all gap locations needs to be handled with a single memory management command. In one embodiment, data movement corresponding to all gap locations is handled using a faster write command (e.g., operating in memory mode using a burst or stream command). In one example, user data F, L, R, X are moved in response to a single memory management command. Then, the pointer to gap 0 is incremented.

[0139] In some cases, using a single wear leveling command instead of four separate commands can reduce command bus utilization. Because a fixed gap and a single register are used, gap locations are moved simultaneously. When a single memory management command is used, the time to move gap locations is typically less. In one embodiment, when wear leveling operations are performed using an internal wear leveling machine instead of firmware, wear leveling operations can be performed faster. This can result in higher availability of the memory device and / or controller.

[0140] An advantage of using multiple gap locations per collection is the ability to increase the size of the collection. For example, when four gaps are used, the collection size can be increased by a factor of four, as Figure 6 illustrated in FIG. 1.

[0141] The start counter contains the address of the first user data added to the collection. The single gap counter contains the address of the gap location (gap 0). In alternative embodiments, four different gap counters can be used for four gap locations. In the illustrated case, the gap locations are always maintained a same distance increment from each other. In other embodiments, the increment can be a fixed constant, or the increment can be changed by the controller.

[0142] In one example, the mapping of logical to physical addresses is determined based on whether the logical address is before or after each gap location. For four gaps as illustrated, the wear leveling manager makes four comparisons of the logical address to each of the four gap locations. The physical address is determined by incrementing the logical address based on the number of comparisons where the logical address is after the respective gap location.

[0143] Figure 7 Wear leveling of a collection using multiple gap locations with variable spacing between the gap locations (e.g., different increment spacing values of Dl, D2, D3 between the gap locations) is shown according to some embodiments. The increment spacing values of Dl, D2, D3 are different, and each value is saved in a register or other memory by the controller.

[0144] A single counter is used to store the first gap location (gap 0). The other gap locations are determined based on an offset from the first application as determined by the saved increment spacing values. Figure 7 wear leveling of a collection of FIG. 1. Figure 6 The wear leveling of the cluster is similarly managed.

[0145] Figure 8 A wear leveling of a cluster using multiple gap locations is shown, in which a separate pointer points to each gap location (e.g., gapO, gapl, gap2, gap3), according to some embodiments. This approach provides greater flexibility, as it allows the controller to manage four gap locations in multiple different memory management commands (e.g., four different commands). Figure 8 The wear leveling of the cluster is similarly managed. Figure 6 The wear leveling of the cluster is similarly managed.

[0146] In one instance, the controller uses four separate counters. Each gap location has a location stored by a different counter.

[0147] In one embodiment, the gap is moved in response to different commands. For example, the controller moves gapO according to a first memory management command, then moves gapl according to a second memory management command, etc. Then, the controller returns and moves gapO again according to another memory management command.

[0148] This approach allows the controller to modulate the duration for performing operations in response to commands by dealing with the number of gap locations that changes with each command. The controller can modulate the duration based on the context of the memory device. For example, a single gap location can be moved during busy times, while 2 to 4 gap locations can be moved during idle times. In one embodiment, the duration is adjusted to allow movement of a selected number of gap locations.

[0149] In one embodiment, the controller can determine the context based on characteristics of one or more memory cells in the array (e.g., cells storing data to be moved, or cells in the same cluster as cells storing data to be moved). In one instance, the characteristics include read or write performance or timing, and / or error rate during reads.

[0150] The memory management command can indicate the number of gap locations to be moved based on current operating conditions. In one instance, the host or controller determines the scope of traffic by examining the command queue. In one instance, the host or controller determines the length of the queue. In one instance, the host or controller determines the number and / or type of commands waiting for action. Based on the foregoing factors, the host or controller determines the number of gap locations to be moved in response to the memory management command.

[0151] Figure 9 A method for wear leveling using multiple gap locations in a cluster is shown, according to some embodiments. For example, Figure 9 The method of may be performed in a memory device Figure 2 implemented in the memory device 202.

[0152] Figure 9 The method of claim 1 can be performed by processing logic that can include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuitry, etc.), software (e.g., instructions run or executed on a processing device), or a combination thereof. In some embodiments, the processing logic includes the controller 120 of claim 1. Figure 9 The method of claim 1 is performed, at least in part, by one or more processing devices (e.g., the controller 120 of claim 1) and / or logic circuitry. Figure 1 The method of claim 1 is performed, at least in part, by one or more processing devices (e.g., the controller 120 of claim 1) and / or logic circuitry.

[0153] Although shown in a particular order or sequence, unless otherwise specified, the order or sequence can be modified. Thus, the illustrated embodiments should be understood only as examples, the illustrated processes can be performed in different orders, and some processes can be performed in parallel. Additionally, one or more processes can be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0154] At block 901, a memory management command is received. In one example, the command is received by the wear leveling manager 119 from the memory controller 120. In one example, the command is received by the memory controller 120 from the host device 126.

[0155] At block 903, access is provided to physical memory locations in the bin. In one example, the bias circuitry 124 applies a voltage to the access line 140 to provide access to memory cells storing user data.

[0156] At block 905, data is moved from one or more first physical memory locations to one or more second physical memory locations. In one example, the user data F, L, R, X of Figure 8 is moved in response to the memory management command. Figure 6 、 7 or 8.

[0157] At block 907, one or more pointers to gap locations are updated. In one example, the pointer to gap 2 of Figure 8 is updated after the user data R is moved. Figure 8

[0158] At block 909, a pointer to a starting location is updated if one or more gap applications have completed a cycle. In one example, the pointer to the starting location of the bin 230 is updated.

[0159] ​In some aspects, the techniques described herein relate to an apparatus comprising: at least one memory array (e.g., 102, 206); and at least one controller (e.g., 120, 204) configured to perform wear leveling for a same cluster of memory locations using a plurality of gap locations in the cluster (e.g., 230) of memory locations in the memory array.

[0160] In some aspects, the techniques described herein relate to an apparatus wherein the controller is further configured to move at least one of the gap locations in response to receiving a memory management command.

[0161] In some aspects, the techniques described herein relate to an apparatus wherein an indication indicative of a number of gap locations to be moved is provided to the memory management command.

[0162] In some aspects, the techniques described herein relate to an apparatus wherein the gap locations are separated by a fixed offset (e.g., gap locations determined as first gap location + delta, first gap location + 2 delta, first gap location + 3 delta).

[0163] In some aspects, the techniques described herein relate to an apparatus wherein the controller is further configured to move all gap locations in a same cluster in response to a single memory management command.

[0164] In some aspects, the techniques described herein relate to an apparatus further comprising a register (e.g., 240) configured to store a respective pointer for each of the gap locations (e.g., gap locations stored in a register, RAM, FIFO buffer, or other memory).

[0165] In some aspects, the techniques described herein relate to an apparatus further comprising a register (e.g., 240) configured to store a start location, wherein the wear leveling is further performed using the start location.

[0166] In some aspects, the techniques described herein relate to an apparatus further comprising a register (e.g., 240) configured to store a first gap location, wherein at least one second gap location is determined using the first gap location (e.g., second and third gap locations determined based on an offset from the first gap location).

[0167] In some aspects, the techniques described herein relate to a method comprising: determining a context (e.g., length of a command queue, resource utilization of a memory device) of a memory device configured to perform memory management using a plurality of gaps in a single cluster; and modulating a duration based on the determined context, wherein at least one of the gaps is moved for the duration.

[0168] In some aspects, the techniques described herein relate to a method, wherein a number of gaps to be moved is based on the determined context.

[0169] In some aspects, the techniques described herein relate to a method, wherein a pointer for each moved gap is decremented.

[0170] Generally, the gap position and the start position are moved in opposite directions. The start and gap positions are updated after user data is moved. Generally, the update can be either incremented or decremented, as long as the start and gap positions are incremented / decremented oppositely in a manner corresponding to such movement in opposite directions.

[0171] In some aspects, the techniques described herein relate to a method, wherein the determined context is based on a number of pending commands in a queue.

[0172] In some aspects, the techniques described herein relate to a method, wherein the memory device includes a memory array, and the determined context is based on a characteristic of at least one memory cell in the memory array.

[0173] In some aspects, the techniques described herein relate to a system, comprising: bias circuitry (e.g., 124, 224); a plurality of access lines (e.g., 140); and at least one processing device (e.g., 116) configured to: apply, using the bias circuitry, at least one voltage to at least one of the access lines to provide access to a first physical memory location and a second physical memory location (e.g., memory cells accessed using an activated word line); copy data (e.g., user data P at logical address 15) from the first physical memory location (e.g., physical address 15) to the second physical memory location (e.g., physical address 16), wherein the second physical memory location is one of a plurality of unused memory locations (e.g., a plurality of gap positions); and based on copying the data, update a pointer corresponding to movement of a first unused memory location.

[0174] In some aspects, the techniques described herein relate to a system, wherein copying the data includes writing the data using a burst or stream mode.

[0175] In some aspects, the techniques described herein relate to a system, wherein the unused memory locations cycle through a set of physical memory locations (e.g., the set of memory locations is a wear leveling set region), and a start position is updated when the first unused memory location completes a cycle through the entire set region (e.g., locations of user data A through X).

[0176] In some aspects, the techniques described herein relate to a system, further including a register configured to store each of the unused memory locations (e.g., each of the plurality of gap locations).

[0177] In some aspects, the techniques described herein relate to a system, wherein the processing device is further configured to receive a memory management command, copy the data in response to receiving the memory management command, and update the pointer to the start location in response to a last unused memory location completing a cycle. In some cases, all gap locations complete a cycle at the same time.

[0178] In some aspects, the techniques described herein relate to a system, wherein the first unused memory location is a first gap location, and the processing device is further configured to: determine a physical address of the second physical memory location based on a logical address of the data, a start location, and a comparison of the logical address to at least one gap location (e.g., logical address 14 of user data O is added to start location 1 and incremented by 1 due to being located after the first gap location to provide a physical address of 14 + 1 + 1 = 16); and update the start location in response to the first gap location completing a cycle.

[0179] In some aspects, the techniques described herein relate to a system, wherein the processing device is further configured to determine a logical to physical address mapping by comparing a logical address of the data to a plurality of gap locations.

[0180] The disclosure includes various apparatuses that perform the above-described methods and implement the above-described systems, including data processing systems that perform these methods, and computer- readable media having instructions that, when executed on a data processing system, cause the system to perform these methods.

[0181] The description and drawings are illustrative and are not to be construed as limiting. Numerous specific details are described to provide a thorough understanding. However, in certain instances, well known or conventional details are not described in order to avoid obscuring the description. References to one or an embodiment in the present disclosure are not necessarily references to the same embodiment; and, such references mean at least one.

[0182] As used herein, "coupled to" or "coupled with" generally refers to a connection between components, which can be an indirect communicative connection or a direct communicative connection (e.g., without intervening components), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0183] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the present disclosure. The appearances of the phrase "in one embodiment" in various places throughout the specification are not necessarily all referring to the same embodiment, nor are they necessarily all

[0184] In this description, various functions and / or operations can be described as being performed by software code. However, those skilled in the art will recognize that the expressions are intended to mean that the functions and / or operations result from execution of the code by one or more processing devices (such as a microprocessor, an application specific integrated circuit (ASIC), a graphics processing unit, and / or a field programmable gate array (FPGA)). Alternatively or in combination, the functions and operations can be implemented using special purpose circuitry (e.g., logic circuitry) with or without software instructions. Embodiments can be implemented without software instructions, or in combination with software instructions using hardwired circuitry. Accordingly, the described technology is neither limited to hardware circuitry nor software of any particular source, nor to any particular source of instructions for execution by computing devices.

[0185] While some embodiments can be implemented in a fully functioning computer system and computer system, various embodiments can be distributed over a networked environment and can be applied in accordance with a distributed computing scenario.

[0186] At least some aspects disclosed can be embodied, at least in part, in software. That is, the technology can be carried out in a computing device or other system in response to its processor, such as a microprocessor, executing sequences of instructions contained in a memory, such as ROM, volatile RAM, non-volatile memory, cache or a remote storage device.

[0187] Routines executed to implement embodiments can be implemented as part of an operating system, middleware, service delivery platform, SDK (Software Development Kit) component, web service, or other specific application, component, program, object, module or sequence of instructions (sometimes referred to as a computer program). The

[0188] Computer-readable media can be used to store software and data which, when executed by a computing device, cause the device to perform various methods. The executable software and data can be stored in various places including, for example, ROM, volatile RAM, non-volatile memory and / or a cache. Portions of this software and / or data can be stored in any one of these storage locations. Moreover, the data and instructions can be obtained from centralized servers or peer to peer networks. Different portions of the data and instructions can be obtained from different centralized servers and / or peer to peer networks at different times and in different communication sessions or in a same communication session. The data and instructions can be obtained in entirety prior to the execution of the applications. Alternatively, portions of the data and instructions can be obtained dynamically, just in time, when needed, and / or in the middle of an execution of the applications. Thus, it should be appreciated that the data and instructions described herein need not be retrieved from a single location or by a single entity. Further, the data and instructions des cribed herein can be stored locally and / or remotely from a computer running applications. The data and instructions des cribed herein can be stored by any memory medium des cribed herein.

[0189] Examples of computer-readable media include but are not limited to media of recordable and non-recordable type, such as volatile and non-volatile memory devices, read-only memory (ROM), random access memory (RAM), flash memory devices, solid-state disk storage media, removable disks, disk storage media, optical storage media (e.g., compact disks, digital versatile disks, etc.), among others. The computer-readable media can store instructions. Other examples of computer-readable media include, but are not limited to, non-volatile embedded devices using NOR flash or NAND flash architecture. The media used in these architectures can include unmanaged NAND devices and / or managed NAND devices, including, for example, eMMC, SD, CF, UFS, and SSD.

[0190] Generally, a non-transitory computer-readable medium includes any mechanism that provides (e.g., stores) information in a form accessible by a computing device (e.g., a computer, a mobile device, a network device, a personal digital assistant, a manufacturing tool that has a controller, any device that has a set of one or more processors, etc.). As used herein, "computer- readable medium" can include single- or multiple-media (e.g., storing one or more sets of instructions).

[0191] In various embodiments, hardwired circuitry can be used in combination with software and firmware instructions to implement the techniques. Thus, the techniques are neither limited to hardware circuitry nor software, and can therefore be not limited to any particular combination of hardware and software.

[0192] The various embodiments set forth herein can be implemented using various types of computing devices. As used herein, examples of a "computing device" include, but are not limited to, a server, a centralized computing platform, a system of multiple computing processors and / or components, a mobile device, a user terminal, a vehicle, a personal communication device, a wearable digital device, an electronic kiosk, a general purpose computer, an electronic book reader, a tablet computer, a laptop computer, a smartphone, a digital camera, a home appliance, a television, or a digital music player. Additional examples of computing devices include devices that are part of what is referred to as the "Internet of Things" (IOT). Such "things" can occasionally interact with their owners or administrators, who can monitor the things or modify settings related to these things. In some cases, such owners or administrators play the role of users with respect to the "thing" devices. In some examples, a user's primary mobile device (e.g., an Apple iPhone) can be an administrator server with respect to a paired "thing" device (e.g., an Apple Watch) that is worn by the user.

[0193] In some embodiments, a computing device can be a computer or host system implemented, for example, as a desktop computer, a laptop computer, a network server, a mobile device, or other computing device that includes a memory and a processing device. The host system can include or be coupled to a memory sub-system such that the host system can read data from or write data to the memory sub-system. The host system can be coupled to the memory sub-system via a physical host interface. In general, a host system can access multiple memory sub-systems via the same communication connection, multiple separate communication connections, and / or a combination of communication connections.

[0194] In some embodiments, a computing device is a system that includes one or more processing devices. Examples of processing devices can include a microcontroller, a central processing unit (CPU), a special purpose logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), a system on a chip (SoC), or other suitable processor.

[0195] In one example, a computing device is a controller of a memory system. The controller includes a processing device and a memory containing instructions that are executed by the processing device to control various operations of the memory system.

[0196] Although some of the diagrams include sequential ordering, some operations can be re-ordered and / or omitted and / or combined and other operations can be added while still others can be subdivided into multiple operations. Particular re-ordering or other grouping of operations will be apparent to one of ordinary skill in the art and, thus, no exhaustive list of alternatives is presented. Also, it is to be recognized that the stages can be implemented in hardware, firmware, software, or any combination thereof.

[0197] Unless specifically stated otherwise, e.g., with consistent use of the term "implementations," the disjunctive language such as "at least one of X, Y or Z," unless specifically stated otherwise, is otherwise understood within the context as used. Therefore, such disjunctive language

[0198] In the foregoing specification, the disclosure has been described with reference to specific exemplary embodiments thereof. It will be evident that various modifications can be made to the disclosure without departing from the broader spirit and scope of the disclosure as set forth in the appended claims. The Specification and drawings are, accordingly, to be regarded in an illustrative sense rather than a restrictive sense.< / n>

Claims

1. An apparatus comprising: At least one memory array; and At least one controller is configured to perform loss equalization for the same set of memory locations using multiple gap locations in a set of memory locations in the memory array.

2. The device according to claim 1, wherein: The controller is further configured to move at least one of the gap positions in response to receiving a memory management command; and Together with the memory management commands, an indication is provided of the number of the gap positions to be moved.

3. The device according to claim 1, wherein: The gap positions are separated by a fixed offset; and The controller is further configured to move all of the gap positions of a single set area in response to a single memory management command.

4. The device according to claim 1, further comprising: A register configured to store a corresponding pointer to each of the said gap positions; A register configured to store the starting position, wherein the loss equalization is further performed using the starting position; and A register configured to store a first gap position, wherein at least one second gap position is determined using the first gap position.

5. A method comprising: Determine the context of a memory device configured to perform memory management using multiple gaps in a single set region; and Based on the determined context modulation duration, wherein at least one of the gaps is moved within the duration.

6. The method according to claim 5, wherein: The number of gaps to be moved is based on the determined context; The pointer decreases with each movement interval; The memory device includes a memory array; and The determined context is based on the characteristics of at least one memory cell in the memory array and the number of pending commands in the queue.

7. A system comprising: Bias circuit system; Multiple access lines; and At least one processing device configured to: The bias circuit system is used to apply at least one voltage to at least one of the access lines to provide access to the first physical memory location and the second physical memory location. Data is copied from the first physical memory location to the second physical memory location, wherein the second physical memory location is one of a plurality of unused memory locations; and Based on the copied data, the pointer corresponding to the movement at the first unused memory location is updated.

8. The system of claim 7, further comprising a register configured to store each of the unused memory locations, wherein: Copying the data includes writing the data using burst or streaming modes; The unused memory locations cycle through a set of physical memory locations; and The starting position is updated when the first unused memory location completes a loop through a fixed portion of the physical memory location.

9. The system according to claim 7, wherein: The processing device is further configured to receive memory management commands and determine a logical-to-physical address mapping by comparing the logical address of the data with a plurality of gap locations; and The data is copied in response to receiving the memory management command, and the pointer to the starting position is updated in response to the completion of the loop in the first unused memory location.

10. The system of claim 7, wherein the first unused memory location is a first gap location, and the processing device is further configured to: The physical address of the second physical memory location is determined based on the logical address of the data, the starting position, and a comparison of the logical address with at least one gap position; and The starting position is updated in response to the completion of the loop at the first gap position.

Images