Wafer intelligent encapsulation method and system in semiconductor chip

Abstract

The application discloses a kind of semiconductor chip in wafer intelligent encapsulation method and system, it is related to semiconductor manufacturing technology field, including, initialization magnetoelectric field synergy parameter, and magnetoelectric field synergy parameter is optimized to multiple target genetic algorithm, and drive core-shell nanoparticles to high-precision via wafer is metallized filling, and the wafer of metallized via structure is generated;Based on metallized via structure wafer, through laser doppler frequency vibration spectrum analysis method generates bonding parameter, and realizes flip chip interconnection using thermal ultrasonic virtual process, and generates low-defect bonding wafer;Using finite element inversion algorithm, the stress distribution atlas of bonding interface is established, and the thermal stress packaging layer is constructed by intelligent stress matching algorithm, and low-defect bonding wafer is packaged;Through multiple target genetic algorithm optimization magnetoelectric field synergy parameter and drive core-shell nanoparticles directional deposition, the precision control of metallization filling process is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and particularly relates to a wafer intelligent packaging and testing method and system in a semiconductor chip. BACKGROUND

[0002] In the field of semiconductor chip packaging and testing, a traditional method usually adopts a step-by-step process control strategy. A conventional technical solution mainly includes: obtaining wafer surface topography parameters through optical measurement equipment, combining finite element analysis to perform stress simulation, and performing process optimization based on an empirical formula. In a specific implementation, a white light interferometer is used to measure surface characteristics, material parameters are obtained through thermal mechanical analysis, and finally, a bonding process is implemented according to an industry standard. This method has formed a complete technical system, and its reliability has been verified by long-term practice.

[0003] However, the prior art has two main deficiencies in dealing with advanced packaging requirements: first, the traditional topography-stress analysis adopts a static processing method of step-by-step Z-score standardization and Pearson correlation, which is difficult to realize dynamic thickness compensation of a three-dimensional through-hole grid model; second, the conventional thermal ultrasonic bonding process parameters are generated based on an empirical formula, and lack of collaborative optimization of surface acoustic wave resonance spectrum data and thermal mechanical coupling fields. SUMMARY

[0004] In view of the above existing problems, the present application is proposed.

[0005] Therefore, the present application provides a wafer intelligent packaging and testing method in a semiconductor chip to solve the problems of insufficient dynamic thickness compensation of a three-dimensional through-hole and inaccurate collaborative optimization of thermal ultrasonic bonding parameters.

[0006] To solve the above technical problems, the present application provides the following technical solutions:

[0007] In a first aspect, the present application provides a wafer intelligent encapsulation method in a semiconductor chip, which comprises collecting wafer surface three-dimensional topography data, temperature distribution and bonding stress data, constructing a three-dimensional through-hole grid model using a data fusion algorithm, and optimizing the three-dimensional through-hole grid model through a PPO algorithm to generate a high-precision through-hole wafer; initializing magnetoelectric field synergy parameters, optimizing the magnetoelectric field synergy parameters through a multi-objective genetic algorithm, and driving core-shell nanoparticles to metalize and fill the high-precision through-hole wafer to generate a wafer with a metallized through-hole structure; based on the wafer with the metallized through-hole structure, generating bonding parameters through a laser Doppler frequency vibration spectrum analysis method, and realizing flip-chip interconnection using a thermal ultrasonic virtual process to generate a low-defect bonded wafer; using a finite element inversion algorithm, establishing a stress distribution map of the bonding interface, and constructing a thermal stress resistant packaging layer through an intelligent stress matching algorithm, and packaging the low-defect bonded wafer; based on the structure parameters of the packaged low-defect bonded wafer and the initial material parameters of the bonding interface, predicting the thermal stress resistant packaging effect score through multi-physics field coupling simulation, and generating a test report.

[0008] As a preferred scheme of the wafer intelligent encapsulation method in the semiconductor chip, the three-dimensional through-hole network model is constructed using a data fusion algorithm, and the steps are as follows,

[0009] The wafer surface three-dimensional topography data is dimensionless processed using Z-score standardization to generate a normalized topography feature matrix;

[0010] Based on the normalized topography feature matrix and the bonding stress data, a topography-stress correlation coefficient table is generated through a Pearson correlation coefficient;

[0011] The normalized topography feature matrix is converted into a triangular mesh using a Marching Cubes algorithm, and a three-dimensional through-hole grid model with stress compensation is generated by implanting thickness compensation according to the topography-stress correlation coefficient table.

[0012] As a preferred scheme of the wafer intelligent encapsulation method in the semiconductor chip, the high-precision through-hole wafer is generated by optimizing the three-dimensional through-hole grid model through a PPO algorithm, and generating a through-hole parameter instruction set, and converting the through-hole parameter instruction set into a device control signal through a G code parser to drive the device to generate the high-precision through-hole wafer.

[0013] As a preferred scheme of the wafer intelligent encapsulation method in the semiconductor chip, the magnetoelectric field synergy parameters include magnetic field strength, electric field strength and core-shell nanoparticle concentration.

[0014] The magnetic-electric field coordination parameters are optimized by a multi-objective genetic algorithm, and the core-shell nanoparticles are driven to metalize and fill the high-precision through-hole wafer to generate a wafer with a metalized through-hole structure, and the steps are as follows,

[0015] Based on the geometric parameters of the three-dimensional through-hole grid model, the magnetic-electric field coordination parameters are initialized;

[0016] The non-dominated sorting and elitist strategy are performed on the magnetic-electric field coordination parameters to generate a Pareto optimal solution set;

[0017] The core-shell nanoparticles are driven to deposit on the three-dimensional through-hole grid model by using the Pareto optimal solution set to generate a wafer with a metalized through-hole structure.

[0018] As a preferred scheme of the wafer intelligent packaging and testing method of the semiconductor chip, the bonding parameters are generated by the laser Doppler frequency spectrum analysis method, and the flip-chip interconnection is realized by the thermal ultrasonic virtual process to generate a low-defect bonded wafer, and the steps are as follows,

[0019] Based on the metalized through-hole structure wafer, the laser Doppler frequency spectrum analysis method is combined with the fast Fourier transform spectrum analysis to extract the surface acoustic wave resonance spectrum data;

[0020] Based on the surface acoustic wave resonance spectrum data, the thermal-mechanical coupling finite element analysis method is used to identify the temperature field and stress field distribution to generate a set of thermal ultrasonic bonding process parameters;

[0021] Based on the set of thermal ultrasonic bonding process parameters and the three-dimensional structure data of the metalized through-hole structure wafer, the surface wave activation algorithm is used to generate the bonding parameters, and the flip-chip interconnection alignment compensation algorithm is used to generate a set of bonding alignment parameters;

[0022] Based on the set of bonding alignment parameters and the wafer surface temperature distribution, the multi-temperature zone progressive annealing method is used for gradient temperature regulation to generate a low-defect bonded wafer.

[0023] As a preferred scheme of the wafer intelligent packaging and testing method of the semiconductor chip, the stress distribution map of the bonding interface is established by using the finite element inversion algorithm, the anti-thermal stress packaging layer is constructed by using the intelligent stress matching algorithm, and the low-defect bonded wafer is packaged, and the steps are as follows,

[0024] The stress wave signal of the low-defect bonded wafer surface is obtained by SAW, the lattice distortion is measured by X-ray diffraction method, and the stress distribution map of the bonding interface is established by the finite element inversion algorithm;

[0025] Based on the stress distribution map of the bonding interface, a three-dimensional stress field model containing flip-chip bumps, metalized through-holes and bonding interfaces is constructed by using the discrete element analysis method;

[0026] The three-dimensional stress field model of the bonding interface is analyzed by the principal stress trajectory line method, the initial material parameters of the bonding interface are obtained by nanoindentation testing and a thermal mechanical analyzer, and the initial material parameters of the bonding interface are optimized by a deep DDPG algorithm based on an Actor-Critic framework;

[0027] Based on the optimized initial material parameters of the bonding interface, a thermal stress-resistant packaging layer is constructed by a variable-density topology optimization algorithm, and the low-defect bonded wafer is packaged.

[0028] As a preferred scheme of the wafer intelligent packaging method in the semiconductor chip, the anti-thermal stress packaging effect is evaluated by the multi-physical field coupling simulation, and the steps are as follows,

[0029] The anti-thermal stress packaging effect score is predicted by the triple nonlinear coupling calculation of the Gaussian attenuation function, the error function and the hyperbolic tangent function through the multi-physical field nonlinear coupling scoring method;

[0030] Based on historical packaging test data, the packaging effect evaluation threshold is defined and compared with the anti-thermal stress packaging effect score to analyze the anti-thermal stress packaging effect and generate a test report.

[0031] The test report includes the anti-thermal stress packaging effect score, the structural parameters of the low-defect bonded wafer after packaging, the stress distribution map of the bonding interface and packaging improvement suggestions.

[0032] In a second aspect, the present application provides a wafer intelligent packaging system in a semiconductor chip, comprising a three-dimensional modeling module, a metal filling module, a flip-chip interconnection module, a packaging module and an evaluation module; the three-dimensional modeling module is used to collect wafer surface three-dimensional topography data, temperature distribution and bonding stress data, construct a three-dimensional via grid model by using a data fusion algorithm, and generate a high-precision via wafer by optimizing the PPO algorithm; the metal filling module is used to initialize the magnetoelectric field synergy parameters, optimize the magnetoelectric field synergy parameters by a multi-objective genetic algorithm, and drive the core-shell nanoparticles to metalize the high-precision via wafer to generate a metalized via structure wafer; the flip-chip interconnection module is used to generate bonding parameters based on the metalized via structure wafer by a laser Doppler frequency spectrum analysis method, and realize flip-chip interconnection by a thermal ultrasonic virtual process to generate a low-defect bonded wafer; the packaging module is used to establish a stress distribution map of the bonding interface by using a finite element inversion algorithm, construct a thermal stress-resistant packaging layer by an intelligent stress matching algorithm, and package the low-defect bonded wafer; the evaluation module is used to predict the anti-thermal stress packaging effect score based on the structural parameters of the low-defect bonded wafer after packaging and the initial material parameters of the bonding interface, and generate a test report.

[0033] In a third aspect, the present application provides a computer device comprising a memory and a processor, wherein the memory stores a computer program, and wherein the computer program, when executed by the processor, implements any step of the wafer intelligent encapsulation method in a semiconductor chip according to the first aspect of the present application.

[0034] In a fourth aspect, the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements any step of the wafer intelligent encapsulation method in a semiconductor chip according to the first aspect of the present application.

[0035] The present application has the following beneficial effects: the Z-score standardization is used to process the three-dimensional topography data of the wafer surface and generate a normalized topography feature matrix, so that the non-dimensional integration of multi-source heterogeneous data is realized, and a reliable foundation is provided for stress compensation. The multi-objective genetic algorithm is used to optimize the magnetic-electric field coordination parameters and drive the directional deposition of the core-shell nanoparticles, so that the precise control of the metallization filling process is realized, the filling uniformity and structure stability are ensured by combining with the Pareto optimal solution set, and the overall quality and reliability of the optimized wafer are improved. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0037] Fig. 1 The flowchart of the wafer intelligent encapsulation method in a semiconductor chip.

[0038] Fig. 2 The schematic diagram of the wafer intelligent encapsulation system in a semiconductor chip.

[0039] Fig. 3 The flowchart of the three-dimensional via grid model construction.

[0040] Fig. 4 The flowchart of the metallization filling optimization. DETAILED DESCRIPTION

[0041] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings of the specification.

[0042] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, the present application can be practiced without the specific details. In other instances, well-known methods have not been described in detail in order not to unnecessarily obscure aspects of the present application. The present application is not limited to the embodiments described herein which can be practiced with or without the same.

[0043] It should also be noted that, as used in the specification and in the claims, the article "a", "an", or "the" is intended to mean that there is at least one of the particular feature. For example, "an element" shall mean that there is at least one element.

[0044] Reference will now be made to the drawings, in which Figs. 1-4 For one embodiment of the present application, the embodiment provides a wafer intelligent encapsulation method in a semiconductor chip, comprising the following steps:

[0045] S1, collect wafer surface three-dimensional topography data, temperature distribution and bonding stress data, construct a three-dimensional through-hole grid model using a data fusion algorithm, and optimize it through a PPO algorithm to generate a high-precision through-hole wafer;

[0046] The wafer surface three-dimensional topography data includes surface roughness, step height, aperture size and position deviation.

[0047] The bonding stress data includes shear stress, normal contact stress and thermal mismatch stress.

[0048] It should be noted that the wafer surface three-dimensional topography data is obtained by scanning with a white light interferometer, the surface roughness is measured by a non-contact optical profiler, the step height is obtained by a high-precision laser displacement sensor, and the aperture size and position deviation are captured by an automatic optical inspection device based on machine vision. The shear stress is measured by a cross-beam stress sensor, the normal contact stress is captured by a thin film pressure sensor array, and the thermal mismatch stress is calculated by an X-ray diffraction stress analyzer combined with the thermal expansion coefficient difference.

[0049] The wafer surface three-dimensional topography data is processed by Z-score standardization to generate a normalized topography feature matrix;

[0050] Further, the wafer surface three-dimensional topography data is processed by Z-score standardization. The topography data of each dimension is subtracted from the current dimension mean and divided by the standard deviation to eliminate the dimensional difference and retain the distribution characteristics of the three-dimensional topography data. The mean of each dimension after processing is zero and the standard deviation is 1, forming a normalized topography feature matrix with uniform dimension.

[0051] Based on the normalized topography feature matrix and the bonding stress data, a topography-stress correlation coefficient table is generated by Pearson correlation coefficient.

[0052] Further, the normalized topography feature matrix is matched with the bonding stress data according to the sampling point positions, and the Pearson correlation coefficient of the topography feature matrix and the bonding stress data is identified by using the covariance method, the linear correlation between the wafer surface three-dimensional topography data and the bonding stress data is quantified, and finally a topography-stress correlation coefficient table is generated;

[0053] The normalized topography feature matrix is converted into a triangular mesh using the Marching Cubes algorithm, and a thickness compensation is implanted according to the topography-stress correlation coefficient table to generate a three-dimensional via mesh model with stress compensation.

[0054] Further, the normalized topography feature matrix is converted into a triangular mesh by the Marching Cubes algorithm, the Marching Cubes algorithm establishes a regular cubic mesh in three-dimensional space and calculates the isosurface based on the topography feature value interpolation. The topography-stress correlation coefficient table is used to determine the compensation coefficient of each mesh vertex, and the Pearson correlation coefficient is distributed by weight and then converted into a thickness compensation amount after accumulation. The thickness compensation amount is implanted into the triangular mesh through vertex displacement, so that the triangular mesh automatically adjusts the geometric morphology in the stress sensitive area, and finally a three-dimensional via mesh model with stress compensation is generated.

[0055] The PPO algorithm is used to optimize the geometric parameters of the three-dimensional via mesh model, and a via parameter instruction set is generated.

[0056] Further, the three-dimensional via mesh model with stress compensation is used as the input of the PPO algorithm, and the via inclination angle, aperture compensation amount, side wall thickness and filling density are used as the optimized geometric parameters. The PPO algorithm establishes a strategy network and a value network based on the three-dimensional via mesh model with stress compensation, the strategy network outputs the geometric parameter adjustment action, and the value network evaluates the state value. In the iterative optimization process, the strategy network generates a geometric parameter adjustment scheme, calculates the immediate reward based on the stress distribution and structural strength, and the value network evaluates the state value. Finally, a via parameter instruction set that minimizes the thermal mismatch stress and maximizes the structural strength is obtained.

[0057] The via parameter instruction set is converted into a device control signal through a G code parser to drive the device to generate a high-precision via wafer.

[0058] Further, the through-hole parameter instruction set is input into the G code parser, and the parser decomposes the through-hole parameter instruction set into coordinate movement instructions and machining parameters executable by the machine tool according to the ISO 6983 standard. The through-hole inclination is converted into a rotary shaft angle instruction, the hole diameter compensation amount is mapped into a tool radial compensation value, the side wall thickness generates an axial feed rate parameter, and the filling density is converted into a laser power or deposition rate control signal. The parsed device control signals are transmitted to the servo drive of the machining equipment through the field bus, driving the spindle motor, linear motor and auxiliary actuator to cooperate and accurately execute the through-hole machining process on the wafer surface, and finally generating a high-precision through-hole wafer.

[0059] S2, initialize the magnetoelectric field synergy parameter, optimize the magnetoelectric field synergy parameter through the multi-objective genetic algorithm, and drive the core-shell nanoparticles to metalize the high-precision through-hole wafer to generate a wafer with a metalized through-hole structure;

[0060] Based on the geometric parameters of the three-dimensional through-hole grid model, the magnetoelectric field synergy parameter is initialized; the magnetoelectric field synergy parameter includes the magnetic field strength, the electric field strength and the core-shell nanoparticle concentration;

[0061] The non-dominated sorting and elitist reservation strategy are performed on the magnetoelectric field synergy parameter to generate a Pareto optimal solution set;

[0062] Further, the non-dominated sorting is the core operation of the multi-objective genetic algorithm, and the individuals in the population are divided into the first front level by comparing the objective function values of the individuals, and then the subsequent front levels are determined recursively. The elitist reservation strategy selects the individuals with higher front levels into the next generation during each generation evolution process, and at the same time, some excellent parent individuals are reserved to prevent the loss of good genes. In the optimization process of the magnetoelectric field synergy parameter, the multi-objective genetic algorithm first initializes a population containing combinations of the magnetic field strength, the electric field strength and the core-shell nanoparticle concentration. In each iteration, the multi-objective genetic algorithm performs non-dominated sorting on the current population, and divides the population individuals into several non-dominated front levels according to the two optimization objectives of minimizing the thermal mismatch stress and maximizing the structural strength. Then, the elitist reservation strategy is used to select the candidate solutions into the next generation from the individuals with the highest front level in proportion, and at the same time, some parent individuals with special advantages are reserved. After generating new individuals through crossover and mutation operations, the multi-objective genetic algorithm re-evaluates and updates the non-dominated front level division. After several iterations, the population gradually converges to the Pareto front, and finally outputs the Pareto optimal solution set of the magnetoelectric field synergy parameter that optimally balances the thermal mismatch stress and the structural strength.

[0063] The Pareto optimal solution set is used to drive the core-shell nanoparticles to deposit on the three-dimensional through-hole grid model to generate a wafer with a metalized through-hole structure.

[0064] Further, the parameters of the magnetic field intensity, the electric field intensity and the core-shell nanoparticle concentration contained in the Pareto optimal solution set are directly applied to the deposition process control. The magnetic field intensity parameter adjusts the current output of the electromagnetic field generating device to establish a magnetic field distribution of a specific intensity in the deposition cavity; the electric field intensity parameter controls the voltage difference between the electrodes to form a directional electric field; and the core-shell nanoparticle concentration parameter adjusts the supply rate of the nanoparticle suspension. Under the synergistic action of the magnetic field and the electric field, the core-shell nanoparticles move along the trajectory set by the stress compensation geometry of the three-dimensional via grid model, and precise deposition is realized according to the spatial structure of the three-dimensional via grid model. Finally, a required metallized structure is formed in the via, and the preparation of the metallized via structure wafer is completed.

[0065] S3, based on the metallized via structure wafer, generating bonding parameters by laser Doppler frequency spectrum analysis method, and realizing flip-chip interconnection by thermal ultrasonic virtual process to generate low-defect bonded wafers;

[0066] Based on the metallized via structure wafer, the laser Doppler frequency spectrum analysis method is combined with the fast Fourier transform spectrum analysis to extract the surface acoustic wave resonance spectrum data;

[0067] Further, based on the metallized via structure wafer, first, the laser Doppler frequency spectrum analysis method is used to apply a standard sweep excitation of 10-50 MHz to the surface of the metallized via structure wafer and collect the vibration displacement signal, then the fast Fourier transform spectrum analysis is used to convert the vibration displacement signal in the frequency domain to generate the frequency spectrum characteristics. According to the frequency spectrum characteristics, the scanning frequency of the laser Doppler frequency spectrum analysis method is adjusted in real time, and finally the three-point calibration method is used to calibrate the output surface acoustic wave resonance spectrum data. During the extraction process, the laser Doppler frequency spectrum analysis method provides the vibration displacement signal, and the fast Fourier transform spectrum analysis is responsible for frequency spectrum analysis, and the two are realized through real-time interaction to achieve synergistic optimization.

[0068] Based on the surface acoustic wave resonance spectrum data, the thermal-mechanical coupling finite element analysis method is used to identify the temperature field and stress field distribution to generate the thermal ultrasonic bonding process parameter set;

[0069] Further, taking the surface acoustic wave resonance spectrum data as input, the boundary value of the coupled heat conduction equation and elastic mechanics equation is solved to identify the temperature field and stress field distribution of the metallized via structure wafer at the bonding interface, and finally the thermal ultrasonic bonding process parameter set is integrated and generated.

[0070] It should be noted that the heat conduction equation and the elastic mechanics equation are coupled and solved as follows: the surface acoustic wave resonance spectrum data is used as a boundary condition, the heat conduction equation is used to establish a temperature field control equation based on the Fourier law, and the thermal conductivity parameters of the metallized via structure wafer are considered; the elastic mechanics equation describes the stress-strain relationship caused by thermal expansion through the generalized Hooke's law, and the stress distribution is solved in combination with the temperature field calculation result. The two equations are iteratively solved in a bidirectional coupling manner through a temperature-stress coupling term, and the temperature field is updated and the stress field is calculated each time until convergence. Finally, the numerical solution of the temperature field and stress field distribution of the bonding interface is output.

[0071] Based on the thermal ultrasonic bonding process parameter set and the three-dimensional structure data of the metallized via structure wafer, the surface wave activation algorithm is used to generate bonding parameters, and the flip-chip alignment compensation algorithm is used to generate a bonding alignment parameter set.

[0072] Further, the surface wave activation algorithm is used to calculate the propagation characteristics and energy distribution of the surface acoustic wave at the bonding interface, and the optimal bonding pressure distribution area and ultrasonic vibration mode parameters are determined. The flip-chip alignment compensation algorithm reads the via position coordinates in the three-dimensional structure data of the metallized via structure wafer, calculates the position offset compensation amount in combination with the bonding pressure distribution area, and outputs a bonding alignment parameter set containing a lateral displacement correction value and an angle adjustment amount. The flip-chip alignment compensation algorithm is a numerical calculation method for precise alignment, which analyzes the via position coordinates in the three-dimensional structure data of the metallized via structure wafer, combines the thermal ultrasonic bonding process parameter set, identifies the lateral displacement amount and rotation angle that need to be compensated. At the same time, the geometric transformation principle is used to establish the mapping relationship between the actual position and the theoretical position of the via, and the bonding alignment parameter set is output.

[0073] It should be noted that the three-dimensional structure data of the metallized via structure wafer includes via three-dimensional geometric dimensions, metal plating thickness, material properties and position coordinates. The acquisition method is to measure the via topography by an optical interferometer, and to perform tomographic scanning by EDX composition analysis and X-ray diffraction.

[0074] Based on the bonding alignment parameter set and the wafer surface temperature distribution, a multi-temperature zone progressive annealing method is used for gradient temperature regulation to generate a low-defect bonded wafer.

[0075] Further, the displacement correction value and the angle adjustment provided by the bonding alignment parameter set are converted into a coordinate mapping of the heating area, combined with the wafer surface temperature distribution data, to establish a spatial temperature gradient in the multi-temperature zone heating device. The temperature gradient controls the thermal field distribution of each stage of the annealing process, which is divided into three stages: the heating stage adjusts the heating rate of each temperature zone according to the bonding alignment parameter set, so that the high stress region is preferentially heated; the temperature gradient distribution is maintained in the holding stage, so that the bonding interface forms a uniform intermetallic compound; and the cooling curve of each temperature zone is controlled in the cooling stage to match the difference in thermal expansion coefficient of different regions. The entire process dynamically adjusts the temperature zone power through real-time feedback of the wafer surface temperature distribution data, ultimately achieving stress release and interface optimization of low-defect bonded wafers.

[0076] S4, using a finite element inversion algorithm, a stress distribution map of the bonding interface is established, and an anti-thermal stress packaging layer is constructed by an intelligent stress matching algorithm to package the low-defect bonded wafer;

[0077] The SAW is used to obtain the stress wave signal on the surface of the low-defect bonded wafer, the X-ray diffraction method is used to measure the lattice distortion, and the finite element inversion algorithm is used to establish the stress distribution map of the bonding interface;

[0078] The specific process of establishing the stress distribution map of the bonding interface by the finite element inversion algorithm is as follows: first, a three-dimensional grid discrete system is constructed according to the actual geometric size of the low-defect bonded wafer, and the stress wave signal and the lattice distortion are obtained. The Navier-Cauchy wave equation and the stress-strain relationship of the generalized Hooke's law are solved by the finite element inversion algorithm, and the conjugate gradient method is used to iteratively optimize the stress tensor distribution of the grid nodes. After each iteration, the root mean square error of the calculated stress wave field and the measured stress wave field is compared, and the calculation is terminated when the error is lower than the stress convergence threshold (defined according to the measurement accuracy of the SAW sensor and the X-ray diffraction error analysis, with a value range of 0.05-0.15MPa). The final output of the bonding interface stress distribution map contains complete three-dimensional stress tensor information, which is displayed in the form of a color cloud map to visually show the first principal stress, shear stress concentration area and stress gradient variation characteristics. The spatial resolution of the map matches the detection accuracy of the SAW sensor, and can accurately identify micron-scale stress abnormal regions.

[0079] Based on the stress distribution map of the bonding interface, a three-dimensional stress field model including flip bumps, metallized vias and the bonding interface is constructed by using a discrete element analysis method.

[0080] Further, the flip chip bump is first decomposed into a cluster of spherical elements, the metallized via is converted into a chain of cylindrical elements, and the bonding interface generates a layer of contact surface elements by the discrete element analysis method. The normal force between elements is calculated by Hertz contact theory, the critical slip friction force between contact surfaces is calculated by Coulomb friction model, and the initial stress field is applied in combination with the stress distribution map. Under the condition of thermal-mechanical coupling, the displacement and deformation of the discrete element are iteratively calculated according to Newton's law of motion, and the contact network and stress transmission path are dynamically updated. The final output of the three-dimensional stress field model presents the contact stress of the flip chip bump, the stress concentration area inside the via structure, and the shear stress distribution of the bonding interface.

[0081] It should be noted that the bonding interface refers to the intermetallic compound connection layer formed by the thermal ultrasonic bonding process of the wafer and the substrate;

[0082] Based on the three-dimensional stress field model, the high stress aggregation area coordinates of the bonding interface are identified by the principal stress trajectory analysis method;

[0083] Further, the stress trajectory analysis method first calculates the principal stress size and direction at each grid node, then generates a cluster of principal stress trajectory lines through numerical streamline tracking technology, identifies the high stress aggregation area on the bonding interface, extracts the center point coordinates of the high stress aggregation area as the key position marker, and outputs it in the form of a three-dimensional coordinate list, accurately marking the spatial position of the dangerous area on the bonding interface where the stress value exceeds 85% of the material yield strength.

[0084] Based on the high stress aggregation area coordinates of the bonding interface, the initial material parameters of the bonding interface are measured by nanoindentation test and thermal mechanical analyzer;

[0085] Further, the high stress aggregation area coordinates guide the probe positioning of the nanoindentation tester, and the local elastic modulus and hardness are obtained by nanoindentation test at the marked position; the thermal mechanical analyzer performs point thermal expansion coefficient test according to the high stress aggregation area coordinates. The two measurement results are combined to generate the complete initial material parameters of the bonding interface in the key area of the bonding interface.

[0086] The initial material parameters of the bonding interface include elastic modulus, thermal expansion coefficient, Poisson's ratio and fracture toughness.

[0087] With the goal of minimizing thermal mismatch stress and maximizing structural strength, the deep DDPG algorithm based on Actor-Critic framework is used to optimize the initial material parameters of the bonding interface;

[0088] Further, the deep DDPG algorithm based on the Actor-Critic framework takes the initial material parameters of the bonding interface as the state input, the Actor network outputs the material parameter adjustment action, and the Critic network evaluates the comprehensive benefits of the thermal mismatch stress and the structural strength. The deep DDPG algorithm stores the state-action-reward samples in the experience replay buffer, and uses a double network structure to suppress the overestimation bias. In each iteration, the Actor network generates the optimization suggestions of the elastic modulus, Poisson's ratio and other parameters, and the Critic network calculates the Q value to guide the policy update. The optimization process continues until the thermal mismatch stress reduction rate and the structural strength improvement rate reach a balance, and the final optimized initial material parameters of the bonding interface are obtained. For example, the optimized initial material parameters of the bonding interface can reduce the stress concentration coefficient of the bonding interface by more than 35% under 300°C thermal cycling.

[0089] Based on the optimized initial material parameters of the bonding interface, a thermal stress-resistant packaging layer is constructed by a variable density topology optimization algorithm, and a low-defect bonded wafer is packaged.

[0090] Further, the optimized initial material parameters of the bonding interface are taken as input, and the variable density topology optimization algorithm establishes a density field in the packaging layer design domain, taking the thermal conductivity and the elastic modulus as constraint conditions, and updating the unit density through SIMP iteration, so as to minimize the maximum von Mises stress of the packaging layer under thermal load. Sensitivity analysis is used to guide the evolution of the density field during the optimization process, and finally a thermal stress-resistant packaging layer with gradient porosity structure is generated, and a low-defect bonded wafer is packaged. The packaging layer is integrated with the low-defect bonded wafer through a physical vapor deposition process, for example, the optimized packaging structure can reduce the thermal mismatch stress peak by 40% while maintaining more than 98% structural integrity.

[0091] It should be noted that the physical vapor deposition process is a technology that deposits materials in the form of atoms or molecules on the surface of a substrate to form a thin film through vacuum evaporation, sputtering or arc discharge.

[0092] S5, based on the structural parameters of the packaged low-defect bonded wafer and the initial material parameters of the bonding interface, and through multi-physical field coupling simulation, the anti-thermal stress packaging effect is evaluated, and a test report is generated.

[0093] The structural parameters of the packaged low-defect bonded wafer include cell size, wall thickness and geometric profile tolerance.

[0094] Based on the structural parameters of the packaged low-defect bonded wafer and the material performance parameters of the packaging layer, a multi-physical field nonlinear coupling scoring method is used to calculate the anti-thermal stress packaging effect score through triple nonlinear coupling calculation of Gaussian attenuation function, error function and hyperbolic tangent function, and the expression is:

[0095] ;

[0096] wherein, is the anti-thermal stress packaging effectiveness score, is the unit size of the low-defect packaged bonded wafer, is the wall thickness of the low-defect packaged bonded wafer, is the geometric profile tolerance of the low-defect packaged bonded wafer, is the stress concentration factor of the low-defect packaged bonded wafer, is the stress sensitivity factor of the low-defect packaged bonded wafer, is the thermal mismatch tolerance threshold, is the thermal expansion coefficient of the optimized bonding interface, is the thermal expansion coefficient of the low-defect packaged bonded wafer, is the critical fracture stress of the optimized bonding interface, is the measured stress of the bonding interface at the high stress concentration coordinate point, is the lateral coordinate of the high stress concentration region of the bonding interface, is the longitudinal coordinate of the high stress concentration region of the bonding interface, is the depth coordinate of the high stress concentration region of the bonding interface.

[0097] Further, based on the structural parameters of the low-defect packaged bonded wafer and the material performance parameters (thermal expansion coefficient ) of the packaging layer, the stress concentration factor of the low-defect packaged bonded wafer is first calculated. The stress concentration effect is evaluated by the Gaussian decay function part through the formula , wherein is the stress sensitivity factor of the low-defect packaged bonded wafer, which is used to quantify the sensitivity of stress concentration to reliability. The influence of the difference in thermal expansion coefficient is calculated by the error function part , wherein is the thermal expansion coefficient of the optimized bonding interface, is the thermal expansion coefficient of the low-defect packaged bonded wafer, is the thermal mismatch tolerance threshold, reflecting the upper limit of the allowed thermal expansion difference. The stress safety margin of the high stress concentration region (lateral coordinate , longitudinal coordinate , depth coordinate ) of the bonding interface is evaluated by the hyperbolic tangent function part , wherein is the critical fracture stress of the optimized bonding interface, is the measured stress of the corresponding coordinate point. Finally, the output values of the Gaussian decay function, the error function and the hyperbolic tangent function are multiplied in turn to complete the triple nonlinear coupling calculation, generating an anti-thermal stress packaging effectiveness score in the range of 0 to 1 The score The higher, the better the comprehensive performance of the package structure in stress concentration suppression, thermal matching optimization and fracture risk avoidance under thermal-mechanical coupling conditions.

[0098] It should be noted that the stress concentration coefficient of the low-defect bonded wafer after packaging The value range is 1.0 to 3.0, and the larger the value, the higher the stress concentration.

[0099] The stress sensitivity coefficient of the low-defect bonded wafer after packaging The value range is 0.5 to 2.0 MPa, and the smaller the value, the more sensitive the material to stress concentration.

[0100] The thermal expansion coefficient of the optimized bonding interface The value range is 4.0x10 -6 / K to 8.0x10 -6 / K, depending on the composition of the bonding material.

[0101] The thermal expansion coefficient of the low-defect bonded wafer after packaging The value range is 2.0x10 -6 / K to 6.0x10 -6 / K.

[0102] Thermal mismatch tolerance threshold It is defined based on the statistical distribution of the thermal cycle failure critical value in historical packaging reliability test data, and the value range is 0.5x10 -6 / K to 2.0x10 -6 / K.

[0103] Based on historical packaging test data, define the packaging effect evaluation threshold S1;

[0104] It should be noted that the historical packaging test data includes performance parameters such as thermal cycle life, bonding interface peel strength, and crack propagation rate. The value range of the packaging effect evaluation threshold S1 is 0.65 to 0.82.

[0105] When ≥S1, it is considered that the anti-thermal stress packaging effect has thermal mechanical stability and structural reliability;

[0106] For example, the anti-thermal stress packaging effect score reaches 0.78, and the complete bonding interface remains after 1000 times of -55℃~150℃ thermal cycle.

[0107] When <S1, it is considered that the anti-thermal stress packaging effect has a risk of thermal stress concentration or bonding interface failure, and process iteration is required to optimize the wall thickness distribution or correct the geometric tolerance.

[0108] For example, the packaging sample with a thermal stress resistance packaging effect score of 0.62 has a bonding interface crack after 500 thermal cycles, and the wall thickness needs to be adjusted from 50 μm to 65 μm and the geometric tolerance needs to be re-optimized.

[0109] According to the packaging effect evaluation result, a test report is generated.

[0110] The test report includes the thermal stress resistance packaging effect score, the structure parameters of the low-defect bonded wafer after packaging, the stress distribution map of the bonding interface, and the packaging improvement suggestions.

[0111] The embodiment also provides a wafer intelligent packaging and testing system in a semiconductor chip, which comprises a three-dimensional modeling module, a metal filling module, a flip interconnection module, a packaging module and an evaluation module.

[0112] The three-dimensional modeling module is configured to collect wafer surface three-dimensional topography data, temperature distribution and bonding stress data, construct a three-dimensional through-hole grid model by using a data fusion algorithm, and generate a high-precision through-hole wafer by optimizing the three-dimensional through-hole grid model through a PPO algorithm.

[0113] The metal filling module is configured to initialize magnetic-electric field synergy parameters, optimize the magnetic-electric field synergy parameters by using a multi-objective genetic algorithm, and drive core-shell nanoparticles to perform metal filling on the high-precision through-hole wafer to generate a through-hole structure wafer.

[0114] The flip interconnection module is configured to generate bonding parameters by using a laser Doppler frequency vibration spectrum analysis method based on the through-hole structure wafer, and realize flip interconnection by using a thermal ultrasonic virtual process to generate a low-defect bonded wafer.

[0115] The packaging module is configured to establish a stress distribution map of a bonding interface by using a finite element inversion algorithm, construct a thermal stress resistance packaging layer by using an intelligent stress matching algorithm, and package the low-defect bonded wafer.

[0116] The evaluation module is configured to predict a thermal stress resistance packaging effect score by using a multi-physical field coupling simulation based on the structure parameters of the low-defect bonded wafer after packaging and the initial material parameters of the bonding interface, and generate a test report.

[0117] The embodiment also provides a computer device suitable for the wafer intelligent packaging and testing method in a semiconductor chip, which comprises a memory and a processor.

[0118] The computer device can be a terminal, and the computer device includes a processor, a memory, a communication interface, a display screen and an input device connected by a system bus. The processor of the computer device is configured to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for running the operating system and the computer program in the non-volatile storage medium. The communication interface of the computer device is configured to perform wired or wireless communication with an external terminal. The wireless communication can be achieved by WIFI, an operator network, NFC (Near Field Communication) or other technologies. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen. The input device of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0119] The embodiment also provides a storage medium having a computer program stored thereon, the program being executed by a processor to implement the method for wafer intelligent packaging and testing in a semiconductor chip as described above. The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, a magnetic disk or an optical disk.

[0120] To sum up, the application realizes the non-dimensional integration of multi-source heterogeneous data by Z-score standardization processing wafer surface three-dimensional topography data and generating a normalized topography feature matrix, and provides a reliable foundation for stress compensation. The precise control of the metallization filling process is realized by optimizing the magnetic-electric field coordination parameters and driving the core-shell nanoparticles to deposit directionally through the multi-objective genetic algorithm, and the filling uniformity and structure stability are ensured by combining the Pareto optimal solution set, thereby improving the overall quality and reliability of the optimized wafer.

[0121] It should be noted that the above examples are only used to illustrate the technical solutions of the present application but not limit the present application. Although the present application is described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the present application can be modified or equivalently replaced, without departing from the spirit and scope of the technical solutions of the present application, which should be covered in the scope of the claims of the present application.

Claims

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2. The method of claim 1, wherein the wafer prooessing is performed by a wafer prooessing machine. The method comprises the following steps of:

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metalized via structure wafer, the bonding parameters are generated by using the surface wave activation algorithm, and the bonding alignment parameter set is generated by using the flip-chip interconnection alignment compensation algorithm; Based on the bonding alignment parameter set and the wafer surface temperature distribution, the low-defect bonded wafer is generated by using the multi-temperature zone progressive annealing method for gradient temperature regulation.

5. The wafer intelligent packaging and testing method for semiconductor chips as described in claim 1, characterized in that: The stress distribution map of the bonding interface is established by using the finite element inversion algorithm, the thermal stress resistant packaging layer is constructed by using the intelligent stress matching algorithm, and the low-defect bonded wafer is packaged, and the steps are as follows, The stress wave signal of the low-defect bonded wafer surface is obtained by using SAW, the lattice distortion is measured by using X-ray diffraction method, and the stress distribution map of the bonding interface is established by using the finite element inversion algorithm; Based on the stress distribution map of the bonding interface, a three-dimensional stress field model containing flip-chip bumps, metalized vias and bonding interfaces is constructed by using the discrete element analysis method; The initial material parameters of the bonding interface are obtained by using the principal stress trajectory analysis method, nanoindentation test and thermal mechanical analyzer, and are optimized by using the deep DDPG algorithm based on the Actor-Critic framework; Based on the optimized initial material parameters of the bonding interface, the thermal stress resistant packaging layer is constructed by using the variable density topology optimization algorithm, and the low-defect bonded wafer is packaged.

6. The method of claim 1, wherein the wafer prooessing is performed by a wafer prooessing tool. 5 The anti-thermal stress packaging effect is evaluated by multi-physics field coupling simulation, and the steps are as follows, The anti-thermal stress packaging effect score is predicted by using the multi-physics nonlinear coupling scoring method through the triple nonlinear coupling calculation of Gaussian attenuation function, error function and hyperbolic tangent function; Based on the historical packaging test data, the packaging effect evaluation threshold is defined and compared with the anti-thermal stress packaging effect score to analyze the anti-thermal stress packaging effect and generate a test report; The test report includes the anti-thermal stress packaging effect score, the structure parameters of the low-defect bonded wafer after packaging, the stress distribution map of the bonding interface and the packaging improvement suggestions.

7. A wafer intelligent encapsulation system in a semiconductor chip, based on the wafer intelligent encapsulation method in a semiconductor chip according to any one of claims 1-6, characterized in that: It includes a three-dimensional modeling module, a metal filling module, a flip-chip interconnection module, a packaging module and an evaluation module; The three-dimensional modeling module is used to collect wafer surface three-dimensional topography data, temperature distribution and bonding stress data, construct a three-dimensional via grid model by using a data fusion algorithm, and optimize it by using a PPO algorithm to generate a high-precision via wafer; The metal filling module is used to initialize the magnetoelectric field synergy parameters, optimize the magnetoelectric field synergy parameters by using a multi-objective genetic algorithm, and drive the core-shell nanoparticles to metalize and fill the high-precision via wafer to generate a metalized via structure wafer; The flip-chip interconnection module is used to generate bonding parameters based on the metalized via structure wafer by using laser Doppler frequency spectrum analysis method, and to realize flip-chip interconnection by using thermal ultrasonic virtual process to generate low-defect bonded wafer; The packaging module is used to establish the stress distribution map of the bonding interface by using the finite element inversion algorithm, and to construct the thermal stress resistant packaging layer by using the intelligent stress matching algorithm, and to package the low-defect bonded wafer. An evaluation module is configured to predict a heat stress resistance packaging effect score through multi-physical field coupling simulation based on the structural parameters of the packaged low-defect bonded wafer and the initial material parameters of the bonding interface, and generate a test report.

8. A computer device comprising a memory and a processor, the memory storing a computer program, characterized in that: The computer program is executed by the processor to implement the steps of the wafer intelligent encapsulation method in the semiconductor chip according to any one of claims 1-6.

9. A computer readable storage medium having stored thereon a computer program, characterized in that: The computer program is executed by the processor to implement the steps of the wafer intelligent encapsulation method in the semiconductor chip according to any one of claims 1-6.

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