Novel transformer internal fault protection anti-misoperation locking method and system under power system

Abstract

The invention discloses a novel transformer internal fault protection anti-misoperation locking method and system under an electric power system, and the method comprises the steps: sampling a power grid voltage, taking a detected voltage drop or voltage three-phase imbalance starting time point as a fault moment, obtaining a three-phase imbalance voltage amplitude and a phase jump angle through FFT after one-cycle sampling, and carrying out the fault locking of the three-phase imbalance. And substituting the measured value into the positive sequence voltage phase jump angle expression to solve the positive sequence voltage phase jump angle delta theta. And obtaining a PCC phase during stable operation of the system by using the memory voltage, and obtaining a difference between the PCC phase and an actual PLL output phase to obtain a PLL dynamic tracking angle delta theta-pll. Subtracting the positive sequence voltage phase jump angle delta theta from the PLL dynamic tracking angle delta theta-pll to obtain a phase locking error delta theta e in real time, and performing phase compensation at a PLL outlet by using the phase locking error delta theta e. According to the method, the second harmonic content in the differential current is inhibited, so that the error locking of the internal fault of the transformer of the double-high power system can be effectively prevented, and the protection reliability of the transformer is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of transformer protection, and more particularly relates to a novel transformer internal fault protection anti-mislock method and system under a new power system. BACKGROUND

[0002] To alleviate the shortage of traditional fossil energy, renewable energy has gradually become the backbone of power generation. In recent years, with the large-scale integration of new energy power sources, the new power system characterized by high proportion of renewable energy and high proportion of power electronic devices has developed rapidly.

[0003] The "double high" power system needs corresponding control strategies and means to regulate voltage due to the use of a large number of power electronic devices. Usually, PLL (Phase-Locked Loop) is used to track the frequency and phase of the grid voltage signals to ensure the synchronization of the new energy side and the grid side. The lock-in loop is a circuit that can automatically synchronize the output signal with the reference signal in frequency and phase, and its dynamic performance will affect the entire control system.

[0004] However, under the influence of high penetration rate distributed new energy, the power grid shows the characteristics of a weak grid with low short-circuit ratio. When a transformer has a serious internal fault, the phase of the PCC (Point of Common Coupling) voltage will jump, and the dynamic response process of the phase-locked loop will affect the output characteristics of the new energy, thereby causing the intermediate harmonic content of the differential current to be high. At this time, due to the influence of spectral leakage and fence effect, a large decomposition error will be caused, and when the current signal contains multiple frequency components, each frequency component will produce leakage superimposed interference, affecting the accuracy of harmonic parameter detection.

[0005] Therefore, even if there is no secondary harmonic component in the system, the amplitude of the secondary harmonic component detected by the FFT (Fast Fourier Transform) may still exceed the braking threshold value of the secondary harmonic criterion, causing the differential protection to be mislocked and affecting the reliability of the protection. SUMMARY

[0006] The purpose of the present application is to improve the problem that the traditional transformer protection scheme cannot be completely applied to the "double high" power system, and to propose a novel transformer internal fault protection anti-mislock method and system under a new power system.

[0007] Firstly, the three-phase unbalanced voltage amplitude and phase jump angle are obtained by sampling and FFT calculation; secondly, the measured value is substituted into the expression to solve the positive sequence voltage phase jump angle; at the same time, the PLL dynamic tracking angle is obtained by subtracting the PCC phase waveform during the steady-state operation of the system from the PLL output phase waveform after the fault; finally, the phase lock error is obtained by subtracting the positive sequence voltage phase jump angle from the PLL dynamic tracking angle, and real-time phase compensation is performed, so that the secondary harmonic content in the differential current is suppressed, and the differential protection is effectively prevented from mislocking under the internal fault of the transformer of the "double high" power system.

[0008] The application adopts the following technical scheme. The first aspect of the application provides a novel transformer internal fault protection anti-mislocking method in a power system, comprising the following steps:

[0009] The grid voltage is monitored, and the time point when the voltage drop or three-phase voltage imbalance is detected is the fault time;

[0010] Sampling is started from the fault time, and the three-phase unbalanced voltage amplitude and phase jump angle are calculated and obtained;

[0011] Based on the three-phase unbalanced voltage amplitude and phase jump angle, the positive sequence voltage phase jump angle is calculated and obtained;

[0012] Based on the PCC phase during the steady-state operation before the fault, the PLL dynamic tracking angle is obtained by subtracting the actual PLL output phase;

[0013] The phase lock error is obtained in real time by subtracting the positive sequence voltage phase jump angle from the PLL dynamic tracking angle, the phase lock error takes the positive sequence voltage phase jump angle as the initial value, and gradually decreases over time, and decreases to zero when the PLL completes dynamic tracking; a phase compensation link is added at the PLL outlet to compensate for the phase lock error.

[0014] Preferably, when the per-unit value of the voltage amplitude of any phase of the grid drops to 0.9 or below, it is determined that the system has voltage drop or three-phase voltage imbalance.

[0015] Preferably, the calculation of the positive sequence voltage phase jump angle based on the three-phase unbalanced voltage amplitude and phase jump angle comprises:

[0016] The sine value of the phase jump angle of each phase after the fault is multiplied by the voltage amplitude of the phase, and then the products are summed as the numerator;

[0017] The cosine value of the phase jump angle of each phase after the fault is multiplied by the voltage amplitude of the phase, and then the products are summed as the denominator;

[0018] The results of the numerator and the denominator operation are operated by the inverse tangent operation to obtain the positive sequence voltage phase jump angle.

[0019] Preferably, the calculation of the positive sequence voltage phase jump angle based on the three-phase unbalanced voltage amplitude and phase jump angle comprises:

[0020] The unbalanced three-phase voltage is taken as an input signal of the DSOGI-PLL, and the Clark transformation is performed to obtain the unbalanced voltage alpha and beta axis components in the two-phase stationary coordinate system;

[0021] The SOGI orthogonal phase of the unbalanced voltage alpha and beta axis components is calculated, and the PNSC is used to obtain the positive sequence voltage component, and then the Park transformation is performed to obtain the direct axis component and the quadrature axis component of the positive sequence voltage component;

[0022] The quadrature axis component is set to zero to obtain the positive sequence voltage phase jump angle under three-phase unbalance.

[0023] Preferably, the PLL dynamic tracking angle is obtained by subtracting the actual PLL output phase from the PCC phase under steady-state operation before the fault.

[0024] The waveform of the PLL dynamic tracking angle is obtained by subtracting the actual PLL output phase waveform from the PCC phase waveform under steady-state operation based on the memory voltage.

[0025] Preferably, the actual waveform of the PLL dynamic phase tracking angle is preprocessed, and the linear interpolation method is used to remove the outliers of the phase angle difference waveform.

[0026] Preferably, the phase compensation link for the phase-locked error at the outlet of the PLL is added, the phase-locked error takes the positive sequence voltage phase jump angle as the initial value, and gradually decreases over time, and decreases to zero when the PLL dynamic tracking angle tracks the positive sequence voltage phase jump angle.

[0027] The phase-locked error is obtained by subtracting the PLL dynamic tracking angle from the positive sequence voltage phase jump angle, and the phase-locked error is used for phase compensation at the outlet of the PLL. e

[0028] The second aspect of the present application provides a new transformer internal fault protection anti-mislock system in a power system, which comprises:

[0029] A monitoring module is used to monitor the grid voltage and start the phase angle compensation at the fault moment;

[0030] A DSOGI-PLL module comprises a compensation link for phase compensation of the phase-locked error at the outlet of the PLL, the phase-locked error takes the positive sequence voltage phase jump angle as the initial value, and gradually decreases over time, and decreases to zero when the PLL dynamic tracking angle tracks the positive sequence voltage phase jump angle.

[0031] ​Preferably, the compensation link is provided with a positive sequence voltage phase jump angle calculation model, and the positive sequence voltage phase jump angle is calculated based on the voltage amplitude and phase jump angle of each phase after the fault.

[0032] Preferably, the compensation link is provided with a positive sequence voltage phase jump angle calculation model, and the positive sequence voltage phase jump angle is calculated based on the voltage amplitude and phase jump angle of each phase after the fault. e Phase compensation is performed.

[0033] Compared with the prior art, the present application has at least the following beneficial effects:

[0034] 1. Aiming at the adaptability problem of the traditional transformer protection scheme to the double-high power system, a transformer internal fault differential protection anti-mislock method based on phase compensation is proposed, and the protection reliability is improved.

[0035] 2. The present application can sample the grid voltage and calculate the phase lock error in real time after the fault, and can accurately compensate the phase, so as to effectively suppress the second harmonic content in the differential current and reduce the probability of transformer differential protection mislock. BRIEF DESCRIPTION OF DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0037] Figure 1 The photovoltaic grid-connected system topology diagram;

[0038] Figure 2 The DSOGI-PLL structure block diagram;

[0039] Figure 3 The system steady-state operation and post-fault voltage phase angle waveform comparison diagram;

[0040] Figure 4 The PLL dynamic tracking angle preprocessing waveform and actual waveform comparison diagram;

[0041] Figure 5 The PCC voltage phase relationship diagram before and after the fault;

[0042] Figure 6 The DSOGI-PLL control diagram with the added phase compensation link;

[0043] Figure 7 The flow chart of the transformer internal fault anti-mislock method based on phase compensation of the present application;

[0044] Figure 8 Fig. 1 is a diagram of the PLL input voltage and its phase, differential current and its second harmonic content before fault;

[0045] Figure 9 Fig. 2 is a diagram of the PLL input voltage and its phase, differential current and its second harmonic content after phase compensation. DETAILED DESCRIPTION

[0046] In order to make the objects, technical solutions and advantages of the present application clearer, the technical solutions will be described clearly and completely below with reference to the drawings in the embodiments of the present application. The described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art without creative efforts based on the spirit of the present application shall fall within the protection scope of the present application.

[0047] Embodiment 1 of the present application provides a new transformer internal fault protection anti-mislock method in a new power system, and it can be understood that the transformer internal fault differential protection anti-mislock method provided by the present application is applicable to any new power system characterized by high proportion of renewable energy and high proportion of power electronic equipment. In Embodiment 1, a photovoltaic grid-connected system is exemplified but not limited as a "double high" power system for illustration.

[0048] Figure 1 Fig. 1 is a topology diagram of a photovoltaic grid-connected system, in which a photovoltaic array is connected to a transformer T1 through an inverter, the output end of the transformer T1 is connected to a PCC, the PCC is connected to a main transformer T2, and the output end of the main transformer T2 is connected to a system power source through a sending line, i.e., connected to a power grid. The object of the present application is the main transformer T2. When a serious internal fault occurs in the main transformer T2, it will cause the PCC voltage to drop and be accompanied by phase jump, and there is a short-time dynamic process in the tracking of the PCC voltage phase by a PLL, resulting in phase-locked error.

[0049] The present application performs PLL dynamic tracking and phase-locked error analysis based on a DSOGI-PLL (Double Second-Order Generalized Integrator Phase-Locked Loop, DSOGI-PLL), and the structure block diagram of the DSOGI-PLL is shown in Fig. 2. It can be understood that the DSOGI-PLL can realize positive and negative sequence separation and suppress harmonic components to a certain extent, and in the case of grid voltage imbalance and low harmonic content in the system, it can accurately and instantly track the positive sequence voltage phase signal of the PCC, realizing the synchronization of the phase at the inverter outlet side and the grid side. Figure 2

[0050] ​But the phase-locked error affects the Park transformation and the inverse transformation process, which affects the inverter output characteristics, resulting in a large harmonic component in the inverter output current. In the weak grid scenario, the proportion of the inverter output current in the differential current cannot be ignored, and the secondary harmonic content may cause the secondary harmonic criterion to malfunction, resulting in the transformer differential protection misoperation. Therefore, the present application is dedicated to providing a transformer internal fault differential protection anti-mislock method based on phase compensation, which effectively suppresses the secondary harmonic content in the differential current and reduces the probability of transformer differential protection mislock.

[0051] The transformer internal fault protection anti-mislock method under the new power system specifically includes the following steps:

[0052] Step 1: Monitor the grid voltage for fault identification. If voltage sag or three-phase voltage imbalance occurs, proceed to step 2.

[0053] Preferably but not limitedly, step 1 specifically includes:

[0054] The voltage amplitude of a certain phase of the grid is sampled, and when drops to the threshold value U th , it is determined that voltage sag or three-phase voltage imbalance occurs;

[0055] Further preferably but not limitedly, the sum of the positive and negative deviation absolute values of the 35kV and above power supply voltage is not more than 10% of the nominal voltage, so the threshold value U th is 0.9. That is, when the per-unit value of the voltage amplitude of any phase of the grid drops to 0.9 or below, it is determined that voltage sag or three-phase voltage imbalance occurs.

[0056] Step 2: Take the time point of detected voltage sag or three-phase voltage imbalance as the fault time, and after one cycle of sampling, obtain the three-phase imbalance voltage amplitude and phase jump angle by FFT, and substitute the measured values into the expression of the positive sequence voltage phase jump angle to solve the positive sequence voltage phase jump angle δ θ .

[0057] Preferably but not limitedly, step 2 specifically includes:

[0058] Assuming that the initial phase angle of phase A voltage θ0=0, the three-phase imbalance voltage after the fault is expressed by the following formula:

[0059]

[0060] In the formula:

[0061] v a , v b , and v c are the voltages of phases A, B, and C, respectively;

[0062] ω0 is the voltage fundamental angular frequency;

[0063] V sa , V sb , V sc and Δθ a , Δθ b , Δθ c are the voltage amplitude and phase jump angle of phase A, phase B and phase C after fault respectively.

[0064] The unbalanced three-phase voltage is taken as the input signal of the DSOGI-PLL, and the unbalanced voltage component in the two-phase stationary coordinate system, i.e. the α, β axis components of the grid voltage, is obtained through the Clark transformation, which is expressed by the following formula:

[0065]

[0066] In the formula:

[0067] V α , V β are the amplitude of the α, β axis components of the grid voltage after fault respectively;

[0068] θ α , θ β are the phase of the α, β axis components of the grid voltage after fault respectively.

[0069] The amplitude V α , V β and the phase θ α , θ β of the α, β axis components of the grid voltage after fault are functions of the voltage amplitude and phase jump angle V sa , V sb , V sc and Δθ a , Δθ b , Δθ c of phase A, phase B and phase C after fault, which is expressed by the following formula:

[0070]

[0071] In the formula:

[0072] V1, V2, V3 and V4 are the first, second, third and fourth intermediate variables respectively.

[0073] The α, β axis components of the grid voltage are divided, and the voltage positive sequence component is calculated through SOGI (Second-Order Generalized Integrator) orthogonal phase separation and PNSC (Positive-Negative-Sequence Calculator). The voltage positive sequence component is subjected to Park transformation to obtain the direct-axis component and quadrature-axis component of the voltage positive sequence component and quadrature-axis component which are expressed by the following formula:

[0074]

[0075] In the formula:

[0076] δ θ is the positive sequence voltage phase jump angle;

[0077] θ is the angle between the d-axis and the a-axis, θ = ω0t + δ θ .

[0078] According to the steady-state relationship of phase locking, the quadrature-axis component is The positive sequence voltage phase jump angle δ under three-phase unbalance is obtained θ which is expressed by the following formula:

[0079]

[0080] In the formula:

[0081] δ θ is the positive sequence voltage phase jump angle;

[0082] V sa , V sb , V sc and Δθ a , Δθ b , Δθ c are the voltage amplitude and phase jump angle of phase A, phase B and phase C after the fault respectively.

[0083] The starting time point of the detected voltage drop or three-phase unbalanced voltage is the fault time, and the three-phase unbalanced voltage amplitude and phase jump angle V sa , V sb , V sc and Δθ a , Δθ b , Δθ c are obtained by FFT after one cycle of sampling, and the measured values are substituted into the above formula to obtain the positive sequence voltage phase jump angle δ θ .

[0084] It is worth noting that the positive sequence voltage phase jump angle expression is also applicable to the case of "voltage sag and three-phase balance". In engineering practice, when the three-phase is balanced, the positive sequence voltage phase jump angle expression is equal to the phase jump angle of any phase.

[0085] Step 3: The phase of PCC at the time of stable system operation is obtained by using the memory voltage, and the difference between the actual PLL output phase is obtained to obtain the PLL dynamic tracking angle δ θ-pll .

[0086] Preferably but not limitedly, step 3 specifically includes:

[0087] The PLL dynamic tracking angle δ θ-pll is the phase angle that has been tracked in the PLL dynamic tracking process after the phase jump of the PCC voltage. As shown in Figure 3 , the PCC phase waveform at the time of stable system operation, i.e. the PCC phase waveform at the time of stable system operation obtained by using the memory voltage, is subtracted from the actual post-fault PLL output phase waveform, and the obtained waveform is the waveform of the inverse number of the PLL dynamic tracking angle, as shown by the solid line in Figure 4 .

[0088] Due to the waveform characteristics of the phase sawtooth wave and the existence of phase-locked deviation, the PLL dynamic phase tracking angle waveform will discontinuously appear outliers, which may cause data errors and affect the calculation of the PLL dynamic tracking angle. Therefore, the actual waveform of the PLL dynamic phase tracking angle is preprocessed, and the outliers of the phase angle difference waveform are removed by using the linear interpolation method to exclude possible phase angle data errors, as shown by the dotted line in Figure 4 .

[0089] Step 4: The positive sequence voltage phase jump angle δ θ is subtracted from the PLL dynamic tracking angle δ θ-pll to obtain the phase-locked error Δθ e in real time, and the phase-locked error Δθ e is used for phase compensation at the PLL outlet.

[0090] Preferably but not limitedly, step 4 specifically includes:

[0091] The phase relationship between the PLL dynamic tracking angle δ θ-pll , the positive sequence voltage phase jump angle δ θ and the phase-locked error Δθ e is expressed by the following formula:

[0092] Δθ e = δ θ - δ θ-pll (6)

[0093] In the formula:

[0094] δ θ-pll is the phase jump angle of positive sequence voltage;

[0095] δ θ is the phase jump angle of positive sequence voltage;

[0096] Δθ e is the phase-locked error.

[0097] The phase angle that has not been tracked in the process of PLL dynamic tracking is the phase-locked error Δθ e . The phase-locked error Δθ e changes over time, at the moment of fault occurrence, the PLL dynamic tracking angle is zero δ θ-pll = 0 and the phase-locked error is equal to the phase jump angle of positive sequence voltage Δθ e = δ θ ; and with the passage of time, the phase-locked error Δθ e gradually decreases until the PLL tracks the phase jump angle of positive sequence voltage δ θ ; at this time, the PLL dynamic tracking angle is equal to the phase jump angle of positive sequence voltage δ θ-pll = δ θ and the phase-locked error is zero Δθ e = 0.

[0098] The phase relationship diagram among the three is shown in Figure 5 . In the figure, e + and θ0 are the positive sequence voltage and its phase of PCC when the grid-connected system is normally running; e1 + and θ1 are the positive sequence voltage and its phase of PCC after the grid-connected system occurs asymmetric fault; the phase jump angle of positive sequence voltage δ θ is the d-axis phase difference before and after the fault, that is, δ θ = θ1- θ0.

[0099] The phase-locked error Δθ θ can be obtained in real time by subtracting the phase jump angle of positive sequence voltage δ θ-pll from the PLL dynamic tracking angle δ e , and the phase-locked error Δθ e is used for phase compensation at the outlet of the PLL. The control diagram of the DSOGI-PLL with an additional phase compensation link is shown in Figure 6 . The newly added phase compensation link does not affect the original characteristics of the DSOGI-PLL, and the improved PLL has no stability problem, which can effectively solve the adaptability problem of the traditional transformer protection scheme for the "double high" power system, and can effectively prevent the transformer from being mislocked under internal fault. The complete phase compensation-based transformer internal fault differential protection anti-mislock method flow chart is shown in Figure 7 .

[0100] Embodiment 2 of the present invention provides a novel transformer internal fault protection anti-misoperation interlocking system in a power system, comprising:

[0101] The monitoring module is used to monitor the grid voltage and activate phase angle compensation at the time of a fault.

[0102] The DSOGI-PLL module includes a compensation stage that performs phase compensation at the PLL output. The positive sequence voltage phase jump angle is used as the initial value and gradually decreases over time, decreasing to zero when the PLL dynamic tracking angle tracks the positive sequence voltage phase jump angle.

[0103] Preferably, but not restrictively, the compensation circuit incorporates a positive-sequence voltage phase jump angle calculation model, which calculates the positive-sequence voltage phase jump angle based on the voltage amplitude and phase jump angle of each phase after the fault.

[0104] Preferably, but not limitingly, the compensation circuit calculates the difference between the positive-sequence voltage phase jump angle and the PLL dynamic tracking angle to obtain the phase-locked error in real time, and uses the phase-locked error Δθ at the PLL output. e Perform phase compensation.

[0105] Embodiment 3 of the present invention provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor. When the computer program is loaded into the processor, it implements the novel transformer internal fault protection anti-misoperation interlocking method in a power system according to Embodiment 1.

[0106] Embodiment 4 of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the novel transformer internal fault protection anti-misoperation blocking method in a power system according to Embodiment 1.

[0107] To more clearly illustrate the outstanding substantive features of this invention and the significant progress it brings to the prior art, an application example of implementing this invention is described below.

[0108] Building a simulation platform based on Matlab / Simulink, such as Figure 1 The photovoltaic power grid-connected simulation model shown uses a DSOGI-PLL phase-locked loop. The simulation examines the performance of the PLL under different fault types to verify the effectiveness of the phase compensation improvement measures.

[0109] Figure 8 The following data is presented: a three-phase short-circuit fault occurs on the high-voltage side of the main transformer at t=0.5s. After the fault, the PLL input voltage and its phase, differential current and its second harmonic content are given. Figure 9 The phase-locked error Δθ is given when t = 0.52s. eThe compensation is to the PLL outlet, and the phase-compensated PLL input voltage and its phase, differential current and its second harmonic content are obtained. Through the simulation analysis, it is known that the phase-compensated phase-locked error is used to suppress the second harmonic content in the differential current, and the protection mis-trip under the transformer internal fault of the double-high power system can be effectively prevented.

[0110] The application provides a novel transformer internal fault protection mis-trip prevention method in a power system. Firstly, the grid voltage is sampled, and when the grid voltage standard value drops to a threshold value U th (U th 0.9) or less, it is determined that the system has voltage drop or three-phase voltage imbalance. Secondly, the detected voltage drop or three-phase voltage imbalance start time point is taken as the fault time, the three-phase imbalance voltage amplitude and phase jump angle are obtained by FFT after one cycle of sampling, and the measured value is substituted into the positive sequence voltage phase jump angle expression to solve the positive sequence voltage phase jump angle delta θ . Meanwhile, the memory voltage is used to obtain the PCC phase in the stable operation of the system, and the difference between the actual PLL output phase is obtained to obtain the PLL dynamic tracking angle delta θ-pll . Finally, the positive sequence voltage phase jump angle delta θ is subtracted from the PLL dynamic tracking angle delta θ-pll to obtain the phase-locked error delta theta e in real time, and the phase-locked error delta theta e is used for phase compensation at the PLL outlet. The phase-locked error of the PLL is compensated in real time, the second harmonic content in the differential current is suppressed, and the transformer internal fault mis-trip of the double-high power system can be effectively prevented, and the reliability of the transformer protection is improved.

[0111] Finally, it should be noted that the above examples are only used to illustrate the technical solutions of the application and not to limit it. Although the application has been described in detail with reference to the above examples, those skilled in the art should understand that the specific embodiments of the application can be modified or replaced by equivalents without departing from the spirit and scope of the application, and any modification or equivalent replacement without departing from the spirit and scope of the application should be covered in the protection scope of the claims of the application.

Claims

1. A novel method for preventing erroneous interlocking of transformer internal fault protection in a power system, characterized in that, Includes the following steps: Monitor the grid voltage and define the time when a voltage drop or three-phase voltage imbalance is detected as the fault moment; Sampling begins at the moment of the fault, and the amplitude and phase jump angle of the three-phase unbalanced voltage are calculated. The positive sequence voltage phase jump angle is calculated based on the three-phase unbalanced voltage amplitude and phase jump angle. The PLL dynamic tracking angle is obtained by subtracting the PCC phase from the actual PLL output phase during steady-state operation before the fault. The phase-locked error is obtained in real time by subtracting the positive-sequence voltage phase jump angle from the PLL dynamic tracking angle. The phase-locked error takes the positive-sequence voltage phase jump angle as the initial value and gradually decreases over time, decreasing to zero when the PLL completes dynamic tracking. A phase compensation stage is added at the PLL output to compensate for the phase-locked error.

2. The novel method for preventing erroneous interlocking of transformer internal fault protection in a power system according to claim 1, characterized in that: When the per-unit value of the voltage amplitude of any phase of the power grid drops below 0.9, it is determined that the system has experienced a voltage drop or a three-phase voltage imbalance.

3. The novel method for preventing erroneous interlocking of transformer internal fault protection in a power system according to claim 1, characterized in that: The calculation of the positive-sequence voltage phase jump angle based on the three-phase unbalanced voltage amplitude and phase jump angle includes: Multiply the sine value of the phase jump angle of each phase after the fault by the voltage amplitude of that phase, and then sum the products as the numerator; Multiply the cosine of the phase jump angle of each phase after the fault by the voltage amplitude of that phase, and then sum the products as the denominator; Perform an arctangent operation on the results of the operations on the numerator and denominator to obtain the positive sequence voltage phase jump angle.

4. A novel method for preventing erroneous interlocking of transformer internal fault protection in a power system according to claim 1, characterized in that: The calculation of the positive-sequence voltage phase jump angle based on the three-phase unbalanced voltage amplitude and phase jump angle includes: The unbalanced three-phase voltage is used as the input signal of the DSOGI-PLL, and the unbalanced voltage α and β axis components in the two-phase stationary coordinate system are obtained by Clark transformation. The positive sequence component of the unbalanced voltage is obtained by SOGI orthogonal phase splitting and PNSC calculation of the α and β axis components of the voltage, and then the direct axis component and quadrature axis component of the positive sequence component of the voltage are obtained by Park transformation. Setting the quadrature component to zero yields the positive sequence voltage phase jump angle under three-phase imbalance.

5. A novel method for preventing erroneous interlocking of transformer internal fault protection in a power system according to claim 1, characterized in that: The PLL dynamic tracking angle is obtained by subtracting the PCC phase from the actual PLL output phase during steady-state operation before the fault, including: The waveform of the PCC phase during steady-state operation, obtained based on the memory voltage, is subtracted from the actual PLL output phase waveform after the fault to obtain the waveform of the opposite value of the PLL dynamic tracking angle.

6. A novel method for preventing erroneous interlocking of transformer internal fault protection in a power system according to claim 5, characterized in that: Data preprocessing is performed on the actual waveform of the PLL dynamic phase tracking angle, and outliers in the phase angle difference waveform are removed using linear interpolation.

7. A novel method for preventing erroneous interlocking of transformer internal fault protection in a power system according to any one of claims 1 to 6, characterized in that: The step of adding phase compensation for phase-locked loop error at the PLL output, wherein the phase-locked loop error is initially set to the positive-sequence voltage phase jump angle and gradually decreases over time, decreasing to zero when the PLL dynamic tracking angle tracks the positive-sequence voltage phase jump angle, includes: The phase-locked error is obtained in real time by subtracting the positive-sequence voltage phase jump angle from the PLL dynamic tracking angle, and then used at the PLL output to calculate the phase-locked error Δθ. e Perform phase compensation.

8. A novel transformer internal fault protection anti-misoperation interlocking system in a power system, characterized in that, include: The monitoring module is used to monitor the grid voltage and activate phase angle compensation at the time of a fault. The DSOGI-PLL module includes a compensation stage that performs phase compensation for phase-locked loop error at the PLL output. The phase-locked loop error takes the positive sequence voltage phase jump angle as the initial value and gradually decreases over time, decreasing to zero when the PLL dynamic tracking angle tracks the positive sequence voltage phase jump angle.

9. A novel transformer internal fault protection anti-misoperation interlocking system for power systems according to claim 8, characterized in that: The compensation circuit incorporates a positive-sequence voltage phase jump angle calculation model, which calculates the positive-sequence voltage phase jump angle based on the voltage amplitude and phase jump angle of each phase after the fault.

10. A novel transformer internal fault protection anti-misoperation interlocking system for power systems according to claim 8 or 9, characterized in that: The compensation stage calculates the difference between the positive-sequence voltage phase jump angle and the PLL dynamic tracking angle to obtain the phase-locked error in real time, and then uses the phase-locked error Δθ at the PLL output. e Perform phase compensation.

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