A carrier synchronization method and carrier synchronization device without interconnection

Abstract

This invention discloses a carrier synchronization method and device without interconnecting lines, comprising: acquiring a voltage signal at a grid connection point; determining the current voltage phase angle at the grid connection point based on the voltage signal; determining a target voltage phase angle based on the equally divided interval of the current voltage phase angle; calculating the time difference between the current voltage phase angle and the target voltage phase angle; counting the time difference using a counting module with an operating frequency higher than the carrier frequency of the converter, and generating a counting completion signal when the counting meets a preset condition; determining the generation time of the counting completion signal as the carrier synchronization reference time in response to the counting completion signal; and performing carrier synchronization on the parallel converters based on the carrier synchronization reference time. This invention can solve the problem of low accuracy in existing carrier synchronization methods without interconnecting lines.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power systems, and in particular to a carrier wave synchronization method and device without interconnection lines. BACKGROUND

[0002] With the proposal of the goal of building a new power system, the proportion of new energy power generation will be further increased, and the application of group string type photovoltaic inverters and group string type energy storage converters is becoming more and more widespread. The application scenario of multiple photovoltaic inverters or energy storage converters connected in parallel at the AC end and then connected to a step-up transformer is becoming more and more common. However, when multiple inverters are connected in parallel at the AC end, current circulation at the switching frequency is easily caused, which not only reduces the power quality of the output current, but also threatens the safe operation of the inverters.

[0003] Currently, the core of the suppression measure for parallel circulation is to achieve carrier wave synchronization between inverters. The carrier wave synchronization method is mainly divided into carrier wave synchronization with interconnection lines and carrier wave synchronization without interconnection lines. The carrier wave synchronization method with interconnection lines usually needs to provide a reference time for the carrier waves of different inverters through a high-speed signal synchronization line or a communication line, and then the carrier waves are synchronized. When the number of inverters that need to be connected in parallel is too large or the distance is too far, the effectiveness of the carrier wave synchronization method with interconnection lines will decrease, and the cost will increase. The carrier wave synchronization method without interconnection lines usually uses public information of the power grid, such as grid voltage and grid current, to provide a time reference for carrier wave synchronization, which is suitable for large-scale inverter parallel connection scenarios.

[0004] However, the grid voltage and current are power frequency signals, and the carrier frequency of the converter is at the switching frequency level (much higher than the power frequency). How to provide a high-precision synchronization reference for high-frequency carriers based on power frequency signals is a key challenge and technical difficulty faced by such methods. SUMMARY

[0005] The present application provides a carrier wave synchronization method and device without interconnection lines to solve the problem of low precision of the carrier wave synchronization method without interconnection lines in the prior art.

[0006] In a first aspect, an embodiment of the present application provides a carrier wave synchronization method without interconnection lines, comprising: acquiring a voltage signal of a grid connection point; determining a current voltage phase angle of the grid connection point according to the voltage signal; determining a target voltage phase angle according to the interval in which the current voltage phase angle is located; calculating a time difference for the current voltage phase angle to reach the target voltage phase angle; counting the time difference by using a counting module with a working frequency higher than the carrier frequency of the converter, and generating a counting completion signal when the counting meets a preset condition; determining a carrier wave synchronization reference time as the time when the counting completion signal is generated in response to the counting completion signal; and performing carrier wave synchronization on the parallel-connected converters based on the carrier wave synchronization reference time.

[0007] Optionally, the step of determining the current voltage phase angle of the grid-connected point according to the voltage signal comprises: performing phase-locked loop control on the voltage signal to obtain the current voltage phase angle of the grid-connected point.

[0008] Optionally, the step of determining the target voltage phase angle according to the interval in which the current voltage phase angle falls comprises: dividing the range of 0-2π of the voltage phase angle of the grid-connected point in one power frequency cycle into N intervals, each interval corresponding to an angle of 2π / N, N being a positive integer; when the current voltage phase angle falls into an interval, the terminal phase angle of the interval is determined as the target voltage phase angle.

[0009] Optionally, the step of calculating the time difference for the current voltage phase angle to reach the target voltage phase angle comprises: determining the voltage frequency of the grid-connected point according to the voltage signal; determining the phase angle change rate based on the voltage frequency; determining the phase angle difference according to the difference between the current voltage phase angle and the target voltage phase angle; and calculating the time difference according to the phase angle change rate and the phase angle difference.

[0010] Optionally, the step of determining the voltage frequency of the grid-connected point according to the voltage signal comprises: performing phase-locked loop control or frequency-locked loop control on the voltage signal to obtain the voltage frequency of the grid-connected point.

[0011] Optionally, the step of determining the voltage frequency of the grid-connected point according to the voltage signal comprises: detecting the voltage frequency of the grid-connected point using a logic state capture unit.

[0012] Optionally, the time difference ; wherein, is the voltage frequency of the grid-connected point, is the phase angle change rate, N is the number of intervals into which the range of 0-2π of the voltage phase angle of the grid-connected point in one power frequency cycle is divided, is the current voltage phase angle, k is an integer satisfying 0≤k≤N-1, and N is a positive integer.

[0013] Optionally, the step of setting the initial value of the timer count of the converter master control chip based on the time difference and the main frequency of the converter master control chip and controlling the start of the timer comprises: performing a numerical multiplication operation on the time difference and the main frequency, and converting the operation result into an integer to obtain the initial value of the timer count; and setting the initial value to the timer and controlling the timer to start the count-down operation based on the clock period corresponding to the main frequency.

[0014] Optionally, the preset condition is that the timer decreases from the initial value to 0.

[0015] Optionally, the counting module is a timer of the converter main control chip, and the counting completion signal is an interrupt signal; the steps of using a counting module with an operating frequency higher than the carrier frequency of the converter to count the time difference and generating a counting completion signal when the count meets the preset conditions include: setting the initial counting value of the timer based on the time difference and the main frequency of the converter main control chip, and controlling the timer to start counting from the initial value; generating an interrupt signal when the timer count meets the preset conditions.

[0016] Optionally, the steps for setting the initial count value of the timer based on the time difference and the main frequency of the converter's main control chip include: performing a numerical multiplication operation based on the time difference and the main frequency, converting the operation result into an integer, and using it as the initial count value of the timer.

[0017] Optionally, the step of controlling the timer to start counting from the initial value includes: controlling the timer to start a countdown operation based on the clock cycle corresponding to the main frequency; wherein the preset condition is that the timer decreases from the initial value to 0 based on the clock cycle corresponding to the main frequency.

[0018] Secondly, embodiments of the present invention provide a carrier synchronization device without interconnection lines, comprising: a voltage detection module for acquiring a grid-connected point voltage signal; a phase angle processing module for determining the current voltage phase angle of the grid-connected point based on the voltage signal; a target voltage phase angle determination module for determining a target voltage phase angle based on the equally divided interval where the current voltage phase angle is located; a time calculation module for determining the time difference between the current voltage phase angle and the target voltage phase angle; a counting module, whose operating frequency is higher than the carrier frequency of the converter, for counting the time difference and generating a counting completion signal when the counting meets a preset condition; a reference time determination module for determining the generation time of the counting completion signal as the carrier synchronization reference time in response to the counting completion signal; and a synchronization execution module for performing carrier synchronization on parallel converters based on the carrier synchronization reference time.

[0019] The carrier synchronization method without interconnects provided in this invention determines the current voltage phase angle at the grid connection point based on the voltage signal, determines the target voltage phase angle based on the equally divided interval of the current voltage phase angle, calculates the phase angle change rate based on the phase angle difference between the current and target voltage phase angles and the grid connection point voltage frequency, and converts the phase difference into a precise time difference, ensuring a deviation-free conversion from phase information to time information, thus laying the foundation for the time accuracy of the synchronization reference. A counting module with a carrier frequency higher than the converter's operating frequency counts the time difference and generates a counting completion signal when the count meets preset conditions. In response to the counting completion signal, the generation time of the counting completion signal is determined as the carrier synchronization reference time. This process, leveraging the high-precision counting characteristics of the hardware counting module, ensures strict consistency of the synchronization reference time of different converters on the time axis, avoiding reference offsets caused by software calculation delays, crystal oscillator deviations, and other factors. The above carrier synchronization method transforms the originally difficult-to-use power frequency voltage signal into a high-precision synchronization reference that can be directly reused by a high-frequency carrier, thereby solving the core problem of inaccurate synchronization references in existing methods without interconnects.

[0020] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0021] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0022] Figure 1 This is a flowchart of a carrier synchronization method without interconnection lines provided in an embodiment of the present invention;

[0023] Figure 2 This is a circuit diagram of multiple inverters connected in parallel and grid-connected according to an embodiment of the present invention;

[0024] Figure 3 This is a waveform diagram of a three-phase voltage provided in an embodiment of the present invention;

[0025] Figure 4 This is a flowchart of another carrier synchronization method without interconnection lines provided in an embodiment of the present invention;

[0026] Figure 5 This is a flowchart of another carrier synchronization method without interconnection lines provided in an embodiment of the present invention;

[0027] Figure 6 This is a flowchart of another carrier synchronization method without interconnection lines provided in an embodiment of the present invention;

[0028] Figure 7 This is a flowchart of another carrier synchronization method without interconnection lines provided in an embodiment of the present invention;

[0029] Figure 8 This is a flowchart of another carrier synchronization method without interconnection lines provided in an embodiment of the present invention;

[0030] Figure 9 This is a schematic diagram of a carrier synchronization reference time selection method provided in an embodiment of the present invention;

[0031] Figure 10 This is a simulation waveform diagram of the inductor current of two converters and the filter capacitor current of one of them before the application of the interconnection-free carrier synchronization method.

[0032] Figure 11 This is a simulation waveform diagram of the inductor current of two converters and the filter capacitor current of one of them after the application of the interconnectless carrier synchronization algorithm.

[0033] Figure 12 This is a schematic diagram of a carrier synchronization device without interconnection lines provided in an embodiment of the present invention. Detailed Implementation

[0034] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0035] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0036] Figure 1This is a flowchart of a carrier synchronization method without interconnection lines provided by an embodiment of the present invention. This embodiment is applicable to the case of carrier synchronization. The method can be executed by a carrier synchronization device without interconnection lines. The carrier synchronization device without interconnection lines can be implemented in hardware and / or software. The carrier synchronization device without interconnection lines can be configured in an electronic device, which can be composed of two or more physical entities or a single physical entity.

[0037] like Figure 1 As shown, this embodiment of the invention provides a carrier synchronization method without interconnection lines, which specifically includes the following steps:

[0038] S101. Obtain the voltage signal at the grid connection point.

[0039] For example, Figure 2 This is a circuit diagram of multiple inverters connected in parallel and grid-connected. For example... Figure 2 As shown, the AC outputs of M inverters are connected in parallel to a step-up transformer and then to the power grid. The circulating current generated by this parallel connection at the switching frequency is caused by the asynchrony of the inverter switching transistor drive signals. Further analysis reveals that this is due to the deviation of the carrier frequency caused by the crystal oscillator deviation of each inverter. The voltage signal at the grid connection point can be obtained using the voltage sensors built into the inverters and the sampling and conditioning circuit on the control board. Figure 2 middle Indicates capacitance. Indicates inductance. This represents resistance, where M is an integer greater than or equal to 2.

[0040] S102. Determine the current voltage phase angle of the grid connection point based on the voltage signal.

[0041] The converters are connected in parallel at the grid connection point, and the same grid connection point voltage is collected. The three-phase voltage waveforms at the grid connection point are as follows: Figure 3 As shown. The converter uses a phase-locked loop to control the grid connection point voltage, obtaining the phase angle of the grid connection point voltage, and using phase a voltage as the reference. The peak value is at the moment of phase angle 0. It varies linearly within the range of 0 to 2π within one power frequency cycle. This represents the voltage of phase b. t represents the voltage of phase c, and t represents time.

[0042] Grid connection point voltage phase angle The phase angle of the AC voltage at the grid connection point at any given moment during the sinusoidal change process varies linearly within one power frequency cycle (corresponding to the period of the power grid frequency) along the range of 0 to 2π. It is an overall parameter reflecting the phase state of the power grid voltage.

[0043] Current voltage phase angle It is the phase angle of the grid connection point voltage. One specific manifestation refers to the phase angle value of the grid-connected point voltage collected and calculated at a specific moment, which is the phase angle of the grid-connected point voltage at a given time. The instantaneous value at the current moment. That is, the current voltage phase angle. It is the phase angle of the grid connection point voltage. The specific value of x at a certain moment is part of the phase angle of the grid connection point voltage. Here, x can take values ​​of 1, 2, and 3. The maximum value of x equals the number of inverters connected in parallel. An inverter is a specific application form of a converter in a particular scenario, and the converter in this embodiment of the invention can cover various types of inverters.

[0044] In some embodiments, the acquired voltage signal can be processed using phase-locked loop (PLL) software. The PLL tracks the phase changes of the voltage signal, calculates and outputs the current voltage phase angle at the grid connection point in real time. .

[0045] In practical applications, the starting point of the voltage phase angle can be flexibly set. For example, the peak time of phase a voltage can be taken as the phase angle 0 time to ensure that the voltage phase angle stably covers the range of 0~2π within one power frequency cycle.

[0046] S103. Determine the target voltage phase angle based on the equally divided intervals in which the current voltage phase angle is located.

[0047] The target voltage phase angle refers to the voltage phase angle within one power frequency cycle (corresponding to a phase angle range of 0~2π) at the grid connection point, based on the multiple relationship between the carrier frequency and the grid frequency (carrier frequency). For grid frequency The current voltage phase angle is the endpoint phase angle between the intervals after dividing the voltage phase angle of the grid connection point (where N is a positive integer) into N equal parts. In other words, the voltage phase angle of the grid connection point within one power frequency cycle is divided into N equal parts, resulting in N equal intervals. The angle corresponding to each interval is... / N, where N is a positive integer; when the current voltage phase angle falls into a certain equally divided interval, the endpoint phase angle between the equally divided intervals is determined as the target voltage phase angle.

[0048] In some embodiments, based on the grid connection point voltage frequency Set carrier frequency The phase angle of the grid connection point voltage within one power frequency cycle is 0~ The range is divided into N consecutive intervals, and each interval is represented as [k× / N, (k+1)× / N), where k is an integer and 0≤k≤N-1.

[0049] For example, assume the current voltage phase angle The equally divided intervals that fall into are [k× / N, (k+1)× / N), then the endpoint phase angle between the equal partitions is (k+1)× / N is determined as the target voltage phase angle.

[0050] S104. Calculate the time difference between the current voltage phase angle and the target voltage phase angle.

[0051] The time difference between the current voltage phase angle and the target voltage phase angle refers to the time difference from the current moment (corresponding to the current voltage phase angle). The time interval taken to reach the target voltage phase angle.

[0052] In some embodiments, based on voltage frequency The rate of change of phase angle is obtained as ; Calculate the current voltage phase angle Phase angle with target voltage (k+1)× The difference between / N yields the phase angle difference. = (k+1) × / N- The phase angle difference is converted into a time difference based on the rate of change of the phase angle. The calculation formula is: = / , This represents the rate of change of the phase angle.

[0053] S105. The time difference is counted using a counting module whose operating frequency is higher than the carrier frequency of the converter, and a counting completion signal is generated when the count meets the preset conditions.

[0054] The counting completion signal is an electrical or logical signal generated by the timing module after completing the timing for a preset time period, indicating the end of the timing. It is an event-triggered signal. Specifically, it can manifest as a hardware interrupt signal, such as a timer overflow interrupt or a capture-compare interrupt.

[0055] Level transition: A transition from low level to high level or from high level to low level.

[0056] In one embodiment, the counting module is implemented by a hardware timer inside the converter's main control chip. The operating clock of this hardware timer is provided by the main frequency of the control chip, and its frequency is much higher than the carrier frequency of the converter, thereby ensuring the high accuracy required for timing.

[0057] In another embodiment, the counting module may also be implemented by counter logic in a field-programmable gate array (FPGA) or an application-specific integrated circuit (ASIC).

[0058] The counting module operates using a high-frequency clock source. At the start of timing, a count value calculated based on the time difference and the high-frequency clock frequency is loaded into the counting module. The counting module decrements the count on each rising edge of the high-frequency clock. When the output value of the counting module is detected to be zero, it generates a high-level pulse signal as a counting completion signal.

[0059] S106. In response to the count completion signal, the generation time of the count completion signal is determined as the carrier synchronization reference time.

[0060] If the counting module is implemented by a hardware timer within the main control chip, when the timer's count value decrements to zero, its hardware circuit will automatically set its internal interrupt flag to 1 and send an interrupt request signal to the converter's main control chip. This interrupt request signal is the counting completion signal.

[0061] In response to the interrupt request, the converter's main control chip immediately enters the interrupt service routine. Within the interrupt service routine, the converter's main control chip records the moment the interrupt occurred (e.g., by reading a high-precision system clock register) and assigns this moment to a timestamp, which is then used as a system-wide variable. This timestamp is determined as the reference time for carrier synchronization of all parallel converters within the current cycle.

[0062] The count completion signal can also be the overflow status flag of the timer. The main program detects whether the count is complete by continuously polling this status flag. Once the flag is detected to be set, the converter's main control chip immediately records the current time and determines it as the carrier synchronization reference time, and then clears the status flag.

[0063] The counting module can also be implemented using an FPGA. Inside the FPGA, when the counter reaches its maximum count, it generates a high-level pulse signal with a clock cycle width. This pulse signal is directly connected to the enable pin of another logic module. In response to the rising edge of this pulse signal, the other logic module latches the current count value of the FPGA's high-speed clock and sends the latched value as a carrier synchronization reference time to the processor.

[0064] S107. Based on the carrier synchronization reference time, perform carrier synchronization on the parallel converters.

[0065] At the carrier synchronization reference time, the maximum value of the time base counter of the converter ePWM unit within the current analog-to-digital conversion interrupt cycle is recorded, and this value is determined as the original maximum value (i.e., the initial value TBPRD of the ePWM period register). This value is the reference parameter of the carrier period and directly affects the carrier frequency.

[0066] The trend of the ePWM unit's time base counter value after the carrier synchronization reference time is detected: if the time base counter value shows a downward trend (counting direction is decreasing), it indicates that the current carrier is in the stage of changing from peak value to valley value; if the time base counter value shows an upward trend (counting direction is increasing), it indicates that the current carrier is in the stage of changing from valley value to peak value.

[0067] Adjust the maximum value of the time base counter according to the above trend:

[0068] When the trend is downward, in the next analog-to-digital conversion interruption cycle, the maximum value of the time base counter is updated to the first target value (the difference between the original maximum value and the preset value Δ, i.e., TBPRD-Δ), and the carrier frequency is temporarily increased by shortening the carrier period to speed up phase alignment;

[0069] When the trend is upward, in the next analog-to-digital conversion interruption cycle, the maximum value of the time base counter is updated to the second target value (the sum of the original maximum value and the preset value Δ, i.e., TBPRD+Δ). The carrier frequency is temporarily reduced by extending the carrier period, and the phase change is slowed down to achieve alignment.

[0070] The duration for maintaining the target value is the first preset period, which is equal to the number of analog-to-digital conversion interruption periods corresponding to the quotient of the original maximum value and the preset value Δ (a multiple of the preset value), i.e., [TBPRD / (2Δ)] periods, where [] indicates rounding. After the preset period ends, the maximum value of the time base counter is restored to the original maximum value, so that the carrier frequency returns to normal, completing one synchronization adjustment. Through the above process, it can be ensured that the carrier of the parallel converter gradually aligns in phase at the carrier synchronization reference time and in subsequent periods, achieving high-precision carrier synchronization in scenarios without interconnection lines and effectively suppressing secondary circulating currents at the switching frequency.

[0071] The carrier synchronization method without interconnects provided in this invention determines the current voltage phase angle at the grid connection point based on the voltage signal, determines the target voltage phase angle based on the equally divided interval of the current voltage phase angle, calculates the phase angle change rate based on the phase angle difference between the current and target voltage phase angles and the grid connection point voltage frequency, and converts the phase difference into a precise time difference, ensuring a deviation-free conversion from phase information to time information, laying the foundation for the time accuracy of the synchronization reference. A counting module with an operating frequency higher than the converter's carrier frequency counts the time difference and generates a counting completion signal when the count meets preset conditions. In response to the counting completion signal, the generation time of the counting completion signal is determined as the carrier synchronization reference time. This process, leveraging the high-precision counting characteristics of the hardware counting module, ensures strict consistency of the synchronization reference time of different converters on the time axis, avoiding reference offsets caused by software calculation delays, crystal oscillator deviations, and other factors. The above carrier synchronization method transforms the originally difficult-to-use power frequency voltage signal into a high-precision synchronization reference that can be directly reused by a high-frequency carrier, thereby solving the core problem of inaccurate synchronization references in existing methods without interconnects.

[0072] Figure 4 This is a flowchart of another carrier synchronization method without interconnection lines provided by an embodiment of the present invention, as shown below. Figure 4 As shown, the carrier synchronization method includes:

[0073] S201. Obtain the voltage signal at the grid connection point.

[0074] S202. Perform phase-locked loop control on the voltage signal to calculate the current voltage phase angle at the grid connection point.

[0075] This refers to using a phase-locked loop (PLL) closed-loop control algorithm to track and analyze the collected grid connection point voltage signal in real time, and finally output the phase angle (i.e., the current voltage phase angle) of the grid connection point voltage at the current moment.

[0076] Optionally, the voltage signal is input into the phase-locked loop (PLL) algorithm module. The PLL calculates the phase angle through the following processes: filtering and synchronous sampling of the voltage signal to eliminate noise interference; the phase detector of the PLL compares the phase difference between the input voltage signal and the internal reference signal in real time, and adjusts the output of the voltage-controlled oscillator through the loop filter to ensure that the phase of the internal reference signal always tracks the phase change of the input voltage signal; based on the tracked phase relationship, the voltage phase angle corresponding to the current moment is calculated and output in real time to ensure that the phase angle can accurately reflect the instantaneous phase state of the grid connection point voltage in the range of 0~2π.

[0077] S203. Determine the target voltage phase angle based on the equally divided intervals in which the current voltage phase angle is located.

[0078] S204. Calculate the time difference between the current voltage phase angle and the target voltage phase angle.

[0079] S205. The time difference is counted using a counting module whose operating frequency is higher than the carrier frequency of the converter, and a counting completion signal is generated when the counting module counts to meet the preset conditions.

[0080] S206. In response to the count completion signal, the generation time of the count completion signal is determined as the carrier synchronization reference time.

[0081] S207. Based on the carrier synchronization reference time, perform carrier synchronization on the parallel converters.

[0082] Figure 5 This is a flowchart of another carrier synchronization method without interconnection lines provided by an embodiment of the present invention, as shown below. Figure 5 As shown, the carrier synchronization method includes:

[0083] S301. Obtain the voltage signal at the grid connection point.

[0084] S302. Determine the current voltage phase angle of the grid connection point based on the voltage signal.

[0085] S303. Determine the target voltage phase angle based on the equally divided intervals in which the current voltage phase angle is located.

[0086] S304. Determine the grid connection point voltage frequency based on the voltage signal.

[0087] In some embodiments, the voltage signal is subjected to phase-locked loop control or frequency-locked loop control to calculate the grid connection point voltage frequency.

[0088] In some embodiments, the logic state capture unit is used to detect the grid point voltage frequency.

[0089] Enhanced Capture (eCAP) is a hardware functional module integrated into the main control chip, such as embedded chips like digital signal processors (DSPs).

[0090] The voltage signal at the grid connection point is converted into a form suitable for eCAP detection. Typically, the sinusoidal voltage signal is converted into a square wave signal through a filter circuit. This allows eCAP to more easily detect edge changes in the signal, because the rising and falling edges of the square wave correspond to critical voltage change points, such as zero crossings.

[0091] Based on the detection requirements, configure eCAP to a suitable operating mode, such as continuous capture mode. Simultaneously, set the counter source and clock divider, defining the clock source and its division factor used by the internal timer to ensure accurate time recording.

[0092] The eCAP capture unit detects the falling or rising edge of the first target phase wave in real time. When an edge is detected, a corresponding event is triggered. By recording the trigger times of two consecutive rising or falling edges, the time difference between them is calculated; this time difference is the period of the voltage signal. Based on the relationship between frequency and period, f=1 / T, where f is the frequency and T is the period, the frequency of the grid-connected voltage can be obtained. For example, if the time difference between two rising edges is 0.02 seconds, then the voltage frequency is 50Hz.

[0093] S305. Determine the rate of change of phase angle based on voltage frequency.

[0094] The rate of change of phase angle refers to the angle of change of the voltage phase angle at the grid connection point per unit time. It is a parameter reflecting how quickly the phase of the grid voltage changes dynamically over time. Its magnitude is directly related to the voltage frequency at the grid connection point, and the unit is usually radians per second (rad / s). Within one power frequency cycle, the voltage phase angle changes linearly from 0 to 2π, and the rate of change of phase angle is a constant value.

[0095] Grid connection point voltage frequency The rate of change of phase angle is determined, and the relationship between the two is as follows: , This represents the rate of change of the phase angle. For example, when the grid frequency is 50 Hz, the rate of change of the phase angle is 100π rad / s.

[0096] S306. Determine the phase angle difference based on the difference between the current voltage phase angle and the target voltage phase angle.

[0097] Phase angle difference =Target voltage phase angle - Current voltage phase angle ;

[0098] S307. Calculate the time difference based on the rate of change of phase angle and the phase angle difference.

[0099] Time difference = / ;Right now ;

[0100] in, The voltage frequency at the grid connection point, Let N be the rate of change of the phase angle, N be the number of equal partitions within the range of 0 to 2π of the voltage phase angle at the grid connection point in one power frequency cycle, k be an integer 0 ≤ k ≤ N-1, and N be a positive integer.

[0101] S308. A counting module with an operating frequency higher than the carrier frequency of the converter is used to count the time difference, and a counting completion signal is generated when the counting module meets the preset conditions.

[0102] S309. In response to the count completion signal, the generation time of the count completion signal is determined as the carrier synchronization reference time.

[0103] S310. Based on the carrier synchronization reference time, perform carrier synchronization on the parallel converters.

[0104] Figure 6 This is a flowchart of another carrier synchronization method without interconnection lines provided by an embodiment of the present invention, as shown below. Figure 6 As shown, the carrier synchronization method includes:

[0105] S401, Obtain the voltage signal at the grid connection point.

[0106] S402. Determine the current voltage phase angle of the grid connection point based on the voltage signal.

[0107] S403. Determine the target voltage phase angle based on the equally divided intervals in which the current voltage phase angle is located.

[0108] S404. Calculate the time difference between the current voltage phase angle and the target voltage phase angle.

[0109] S405. The time difference is counted using a counting module whose operating frequency is higher than the carrier frequency of the converter, and a counting completion signal is generated when the counting module counts to meet the preset conditions.

[0110] S406. In response to the count completion signal, the generation time of the count completion signal is determined as the carrier synchronization reference time.

[0111] S407. Based on the carrier synchronization reference time, perform carrier synchronization on parallel converters.

[0112] Figure 7 This is a flowchart of another carrier synchronization method without interconnection lines provided in an embodiment of the present invention. The counting module is a timer of the converter main control chip, and the counting completion signal is an interrupt signal. Figure 7 As shown, the carrier synchronization method includes:

[0113] S501, Obtain the voltage signal at the grid connection point.

[0114] S502. Determine the current voltage phase angle of the grid connection point based on the voltage signal.

[0115] S503. Determine the target voltage phase angle based on the equally divided intervals in which the current voltage phase angle is located.

[0116] S504. Calculate the time difference between the current voltage phase angle and the target voltage phase angle.

[0117] S505 sets the initial count value of the timer based on the time difference and the main frequency of the converter's main control chip, and controls the timer to start counting from the initial value.

[0118] Specifically, the time difference is multiplied by the clock frequency, and the result is converted to an integer and used as the initial value for the timer count. The clock frequency refers to the operating clock frequency of the inverter's main control chip (usually measured in Hertz, i.e., the number of clock cycles per second), reflecting the base rate of the timer. The essence of multiplication is converting the time difference into the corresponding number of clock cycles. For example, if the time difference is 1 microsecond and the main control chip's clock frequency is 100 MHz, the product of the two is 100, indicating that the time difference corresponds to 100 clock cycles. Converting the result to an integer is necessary because the timer's counting unit is an integer number of clock cycles; rounding ensures that the parameters meet the timer's hardware requirements.

[0119] The initial value of the timer count refers to an integer parameter calculated based on the time difference between the current voltage phase angle and the target voltage phase angle, and the main frequency of the converter's main control chip. This parameter is used to set the start of the timer count. Its function is to convert the time difference into a counting unit that the timer can recognize, thereby achieving precise control of the synchronization timing. The main frequency of the converter's main control chip... That is, the operating clock frequency of the main control chip.

[0120] Initial value through formula = [ × ] Calculate the initial value of the timer count, where [] indicates that the product result is rounded down to ensure that the initial value is an integer; finally, write the calculated initial value into the timer's count register, and control the timer to start the count-down operation based on the clock cycle corresponding to the main control chip's main frequency.

[0121] S506. When the timer count meets the preset conditions, an interrupt signal is generated.

[0122] The preset condition is that the timer decreases from its initial value to 0 based on the clock cycle corresponding to the main frequency.

[0123] The main control chip's clock frequency This determines the timer's counting period, that is, the time consumed for each count is 1 / After the timer starts, it counts down by 1 sequentially from the preset initial value according to the clock cycle corresponding to the main frequency, until it counts to 0, triggering a timer interrupt and generating an interrupt signal. This countdown method based on the main frequency can accurately convert the time difference between the current voltage phase angle and the target phase angle into the timer's counting process, ensuring that the timers of different converters can trigger interrupts at the same time, thereby achieving a unified carrier synchronization reference time.

[0124] S507. In response to the interrupt signal, the generation time of the interrupt signal is determined as the carrier synchronization reference time.

[0125] S508. Based on the carrier synchronization reference time, perform carrier synchronization on parallel converters.

[0126] Figure 8 This is a flowchart of another carrier synchronization method without interconnection lines provided by an embodiment of the present invention, as shown below. Figure 8 As shown, the carrier synchronization method includes:

[0127] S601, Obtain the voltage signal at the grid connection point.

[0128] S602. Perform phase-locked loop control on the voltage signal to calculate the current voltage phase angle at the grid connection point.

[0129] S603. Determine the target voltage phase angle based on the equally divided intervals in which the current voltage phase angle is located.

[0130] S604. Determine the grid connection point voltage frequency based on the voltage signal.

[0131] S605. Determine the rate of change of phase angle based on voltage frequency.

[0132] S606. Determine the phase angle difference based on the difference between the current voltage phase angle and the target voltage phase angle.

[0133] S607. Calculate the time difference based on the rate of change of phase angle and the phase angle difference.

[0134] S608. Based on the time difference and the main frequency of the converter main control chip, set the initial value of the timer's count, and control the timer to start counting from the initial value.

[0135] S609. When the timer count meets the preset conditions, an interrupt signal is generated.

[0136] S610, in response to the interrupt signal, determines the generation time of the interrupt signal as the carrier synchronization reference time.

[0137] S611. Based on the carrier synchronization reference time, perform carrier synchronization on the parallel converters.

[0138] Based on the grid connection point voltage frequency With converter carrier frequency Taking the same method, where two converters are connected in parallel and grid-connected to implement carrier synchronization, as an example, the carrier of the first converter is carrier 1, and the carrier of the second converter is carrier 2. When the current voltage phase angle... Within the range [k*2π / N, (k+1)*2π / N), due to the phase deviation between carrier 1 and carrier 2, the current voltage phase angle calculated by the PLL of different converters will be different, respectively. , The time difference between the moment when the current voltage phase angle is calculated from the converter and the moment when the target voltage phase angle is (k+1)*2π / N. , They are respectively:

[0139] ;

[0140] ;

[0141] When the PLL of the converter calculates the current voltage phase angle, the timer of the converter's main control chip is loaded. The loaded values ​​for Timer 1 and Timer 2 are respectively [ * ]and[ * ],in, The clock frequency is the main control chip's clock speed, and [] indicates rounding. After the timer is loaded, it begins counting down according to the period corresponding to the main control chip's clock frequency. When the timer counts to 0, a timer interrupt is triggered, which serves as the reference time for carrier synchronization.

[0142] Figure 9 This is a schematic diagram of a carrier synchronization reference time selection method provided in an embodiment of the present invention. Figure 9 It can be seen that no matter how large the initial carrier deviation is between the converters, the same synchronization reference time can be obtained, and thus carrier synchronization between the converters can be achieved by various methods.

[0143] In the carrier synchronization method of this invention, k can be any positive integer between [0, N). Synchronization can be performed at any time within one power frequency cycle, and can be performed any number of times, even once in each carrier cycle. Compared with other wireless carrier synchronization methods, this carrier synchronization method is simple to operate and has high synchronization accuracy.

[0144] Taking the implementation of carrier synchronization using two converters connected in parallel to the grid as an example. Each converter has a rated power of 60kW, a rated voltage of 480V, and a rated frequency of 50Hz. Before and after applying the carrier synchronization method without interconnection lines, the waveforms of the inductor current (channel 1, channel 3) and the filter capacitor current (channel 4) of the two converters are as follows: Figure 10 and Figure 11Before the application of the interconnectless carrier synchronization method, the inductor currents of the two converters exhibited a phase deviation, resulting in a significant circulating current at the switching frequency between the two converters. This circulating current flowed through the filter capacitor, greatly increasing the switching frequency component of the filter capacitor current and causing noticeable fluctuations in the capacitor current envelope. After the application of the interconnectless carrier synchronization method, the phase deviation of the inductor currents of the two converters was significantly reduced, the circulating current at the switching frequency between the two converters was significantly reduced, the switching frequency component of the filter capacitor current returned to normal levels, and the capacitor current envelope became smoother. These findings verify the effectiveness of the high-precision interconnectless carrier synchronization method.

[0145] Based on the same inventive concept, embodiments of the present invention also provide a carrier synchronization device without interconnecting lines. Figure 12 This is a schematic diagram of the structure of a carrier synchronization device without interconnecting lines provided in an embodiment of the present invention. Figure 12 As shown, the carrier synchronization device 10 includes:

[0146] Voltage detection module 110 is used to acquire the voltage signal at the grid connection point.

[0147] The phase angle processing module 120 is used to determine the current voltage phase angle of the grid connection point based on the voltage signal.

[0148] The target voltage phase angle determination module 130 is used to determine the target voltage phase angle based on the equally divided interval where the current voltage phase angle is located.

[0149] The time calculation module 140 is used to determine the time difference between the current voltage phase angle and the target voltage phase angle.

[0150] The counting module 150 operates at a frequency higher than the carrier frequency of the converter. It is used to count the time difference and generate a counting completion signal when the count meets the preset conditions.

[0151] The reference time determination module 160 is used to determine the generation time of the count completion signal as the carrier synchronization reference time in response to the count completion signal.

[0152] The synchronization execution module 170 is used to perform carrier synchronization on parallel converters based on the carrier synchronization reference time.

[0153] The interconnectless carrier synchronization device provided in this embodiment of the invention can execute the interconnectless carrier synchronization method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method. The similarities with the carrier synchronization method can be referred to the explanation of the carrier synchronization method, which will not be repeated here.

[0154] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0155] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A carrier synchronization method without interconnect lines, characterized in that, include: Obtain the voltage signal at the grid connection point; Determine the current voltage phase angle of the grid connection point based on the voltage signal; Determine the target voltage phase angle based on the equally divided intervals in which the current voltage phase angle is located; Calculate the time difference between the current voltage phase angle and the target voltage phase angle; The time difference is counted using a counting module whose operating frequency is higher than the carrier frequency of the converter, and a counting completion signal is generated when the count meets a preset condition; In response to the count completion signal, the generation time of the count completion signal is determined as the carrier synchronization reference time; Based on the aforementioned carrier synchronization reference time, carrier synchronization is performed on the parallel converters; The step of determining the current voltage phase angle of the grid connection point based on the voltage signal includes: The voltage signal is subjected to phase-locked loop control to calculate the current voltage phase angle at the grid connection point; The step of determining the target voltage phase angle based on the equally divided intervals in which the current voltage phase angle is located includes: The voltage phase angle of the grid connection point is divided into N equal parts within a power frequency cycle from 0 to 2π, resulting in N equal intervals. The angle corresponding to each equal interval is 2π / N, where N is a positive integer. When the current voltage phase angle falls into one of the equal intervals, the endpoint phase angle between the equal intervals is determined as the target voltage phase angle; The target voltage phase angle refers to the final phase angle of the current voltage phase angle within one power frequency cycle of the grid connection point, after dividing the voltage phase angle into N equal parts according to the multiple relationship between the carrier frequency and the grid frequency.

2. The carrier synchronization method without interconnection lines according to claim 1, characterized in that, The step of calculating the time difference between the current voltage phase angle and the target voltage phase angle includes: The grid connection point voltage frequency is determined based on the voltage signal; The rate of phase angle change is determined based on the voltage frequency; The phase angle difference is determined based on the difference between the current voltage phase angle and the target voltage phase angle; The time difference is calculated based on the rate of change of the phase angle and the phase angle difference.

3. The carrier synchronization method without interconnecting lines according to claim 2, characterized in that, The step of determining the grid connection point voltage frequency based on the voltage signal includes: The voltage signal is subjected to phase-locked loop control or frequency-locked loop control to calculate the voltage frequency at the grid connection point; or, The step of determining the grid connection point voltage frequency based on the voltage signal includes: The voltage frequency at the grid connection point is detected using a logic state capture unit.

4. The carrier synchronization method without interconnection lines according to claim 2, characterized in that, The time difference ; in, The voltage frequency at the grid connection point, Let N be the rate of change of the phase angle, and N be the number of equal partitions within the range of 0 to 2π of the voltage phase angle at the grid connection point in one power frequency cycle. The current voltage phase angle is k, where k is an integer 0 ≤ k ≤ N-1, and N is a positive integer.

5. The carrier synchronization method without interconnecting lines according to claim 1, characterized in that, The counting module is a timer for the main control chip of the converter, and the counting completion signal is an interrupt signal; The step of using a counting module with an operating frequency higher than the carrier frequency of the converter to count the time difference and generating a counting completion signal when the count meets a preset condition includes: Based on the time difference and the main frequency of the converter main control chip, the initial count value of the timer is set, and the timer is controlled to start counting from the initial value; When the timer count meets a preset condition, the interrupt signal is generated.

6. The carrier synchronization method without interconnecting lines according to claim 5, characterized in that, The step of setting the initial count value of the timer based on the time difference and the main frequency of the converter main control chip includes: The time difference is multiplied by the main frequency, and the result is converted into an integer and used as the initial value for the timer count.

7. The carrier synchronization method without interconnecting lines according to claim 5, characterized in that, The step of controlling the timer to start counting from the initial value includes: The timer is controlled to start a countdown operation based on the clock cycle corresponding to the main frequency; wherein the preset condition is that the timer decreases from the initial value to 0.

8. A carrier synchronization device without interconnecting lines, characterized in that, A carrier synchronization method without interconnects as described in any one of claims 1-7, comprising: The voltage detection module is used to acquire the voltage signal at the grid connection point; The phase angle processing module is used to determine the current voltage phase angle of the grid connection point based on the voltage signal; The target voltage phase angle determination module is used to determine the target voltage phase angle based on the equally divided interval where the current voltage phase angle is located; The time calculation module is used to determine the time difference between the current voltage phase angle and the target voltage phase angle; The counting module, whose operating frequency is higher than the carrier frequency of the converter, is used to count the time difference and generate a counting completion signal when the count meets a preset condition. A reference time determination module is used to determine the generation time of the count completion signal as the carrier synchronization reference time in response to the count completion signal. The synchronization execution module is used to perform carrier synchronization on parallel converters based on the carrier synchronization reference time.

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