Method for improving resistance of switched capacitor

Abstract

The invention discloses a switched capacitor resistance improvement method, and belongs to the field of analog integrated circuits. When the conduction is reduced, the NMOS tube is used as a switch, and the gate end voltage of the switch is reduced from the power supply voltage VDD until the gate end voltage is close to the threshold voltage or even lower than the threshold voltage; when a PMOS (P-channel Metal Oxide Semiconductor) tube is used as a switch, the gate end voltage of the switch is increased from the ground GND until the gate end voltage is close to the threshold voltage or even higher than the threshold voltage. According to the invention, the low conduction voltage is adopted to carry out switch resistance switching, the generated channel charge is reduced, and the charge accumulated to the input / output end is correspondingly reduced. The threshold value of the switch MOS tube is correspondingly changed due to the conversion of the process corner and the temperature, and if the MOS tube is used as a switch, the MOS tube with the same size can be used for forming a diode connection method to form the switch voltage.

Description

Technical Field

[0001] This invention relates to the field of analog integrated circuit technology, and in particular to an improved method for switching capacitors and resistors. Background Technology

[0002] When designing large resistors, the current approach is to use methods such as... Figure 1 The switched capacitor and resistor diagram illustrates how switches control the transfer of charge within the capacitor, allowing the two switches to operate alternately.

[0003] When φ1 is high and φ2 is low, V1 charges capacitor C, and the charge on capacitor C is Q1 = CV1.

[0004] When φ1 is low and φ2 is high, V2 charges capacitor C, and the charge on capacitor C is Q2 = CV2.

[0005] When V2 charges capacitor C, if V1 > V2, then V2 will draw current from capacitor C, meaning capacitor C will charge V2. In the next cycle, V1 will charge C again, and current will flow from V1 to C. This means that if V1 > V2, the switched capacitor circuit will cause current to flow from V1 to V2, and vice versa. This is very similar to the voltage-current relationship of a resistor. Using this method, resistors in the Gohm or even Tohm range can be obtained.

[0006] However, this type of switching resistor has a problem: during the switching process, some channel charge is transferred to the input terminal, resulting in an excessive voltage deviation at the input terminal. Summary of the Invention

[0007] The purpose of this invention is to provide an improved method for switching capacitor resistors to solve the problems in the background art.

[0008] To solve the above-mentioned technical problems, the present invention provides an improved method for switching capacitor resistors, comprising:

[0009] When reducing conduction, for an NMOS transistor used as a switch, the gate voltage of the switch is reduced from the power supply voltage VDD until it approaches or even falls below the threshold voltage.

[0010] When using a PMOS transistor as a switch, the gate voltage of the switch is increased from ground (GND) until it approaches or even exceeds the threshold voltage.

[0011] Using a low on-state voltage for switching resistors reduces the channel charge generated, which in turn reduces the charge accumulated at the input / output terminals.

[0012] In an implementable embodiment, the switch voltage on the switch is formed by a diode connection of NMOS tubes, and the structure comprises NMOS tubes MN1, MN2, MN3 and a current source;

[0013] The input end of the current source is connected to a power supply voltage, the output end is connected to the drain end of the NMOS tube MN1, the source end of the NMOS tube MN1 is connected to the ground, and the gate end is connected to the output end of the current source;

[0014] The gate end of the NMOS tube MN2 is connected to the output end of the current source, the source end is connected to a V1 voltage, and the drain end is connected to the first end of a capacitor C;

[0015] The gate end of the NMOS tube MN3 is connected to the output end of the current source, the drain end is connected to a V2 voltage, and the source end is connected to the first end of the capacitor C; and the second end of the capacitor C is connected to the ground.

[0016] In an implementable embodiment, the gate voltages of the NMOS tubes MN2 and MN3 are changed by adjusting the number of parallel switches of the NMOS tube MN1 or changing the size of the current source.

[0017] In an implementable embodiment, the sizes of the NMOS tubes MN1, MN2 and MN3 are the same.

[0018] In an implementable embodiment, the switch voltage on the switch is formed by a diode connection of PMOS tubes, and the structure comprises PMOS tubes MP1, MP2, MP3 and a current source;

[0019] The input end of the current source is connected to a power supply voltage, the output end is connected to the drain end of the PMOS tube MP1, the source end of the PMOS tube MP1 is connected to the ground, and the gate end is connected to the output end of the current source;

[0020] The gate end of the PMOS tube MP2 is connected to the output end of the current source, the source end is connected to a V1 voltage, and the drain end is connected to the first end of a capacitor C;

[0021] The gate end of the PMOS tube MP3 is connected to the output end of the current source, the drain end is connected to a V2 voltage, and the source end is connected to the first end of the capacitor C; and the second end of the capacitor C is connected to the ground.

[0022] In an implementable embodiment, the gate voltages of the PMOS tubes MP2 and MP3 are changed by adjusting the number of parallel switches of the PMOS tube MP1 or changing the size of the current source.

[0023] In an implementable embodiment, the sizes of the PMOS tubes MP1, MP2 and MP3 are the same.

[0024] The application provides an improved method for switch capacitor resistance, in which, for NMOS as switch, the gate voltage of the switch is lowered from power supply voltage VDD until close to threshold voltage or even lower than threshold voltage; for PMOS as switch, the gate voltage of the switch is raised from ground GND until close to threshold voltage or even higher than threshold voltage. The application uses low on-voltage to switch resistance, reduces generated channel charge, and accordingly reduces the charge accumulated to input / output terminal. BRIEF DESCRIPTION OF DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or prior art description. Obviously, the drawings in the following description are some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative effort.

[0026] Figure 1 is a structural schematic diagram of prior switch capacitor resistance.

[0027] Figure 2 is a structural schematic diagram of prior switch capacitor resistance.

[0028] Figure 3 is a structural schematic diagram of prior switch capacitor resistance.

[0029] Figure 4 is a structural schematic diagram of prior switch capacitor resistance.

[0030] Figure 5 is a structural schematic diagram of prior switch capacitor resistance.

[0031] Figure 6 is a structural schematic diagram of prior switch capacitor resistance.

[0032] Figure 7 is a structural schematic diagram of prior switch capacitor resistance. DETAILED DESCRIPTION

[0033] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present application.

[0034] The application provides an improved method for switch capacitor resistance, in which, for NMOS as switch, the gate voltage of the switch is lowered from power supply voltage VDD until close to threshold voltage or even lower than threshold voltage; for PMOS as switch, the gate voltage of the switch is raised from ground GND until close to threshold voltage or even higher than threshold voltage. The application uses low on-voltage to switch resistance, reduces generated channel charge, and accordingly reduces the charge accumulated to input / output terminal. Figure 2As shown, for NMOS as switch, the voltage φ1 on the first switch is decreased from the power supply voltage VDD until close to the threshold voltage, even lower than the threshold voltage, so that the first switch is closed; the voltage φ2 on the second switch is set to 0V, so that the second switch is opened, and V1 charges the capacitor C; the voltage φ1 on the first switch is set to 0V, so that the first switch is opened; the voltage φ2 on the second switch is decreased from the power supply voltage VDD until close to the threshold voltage, even lower than the threshold voltage, so that the second switch is closed, and V2 charges the capacitor C.

[0035] For details, please continue to refer to Figure 2 For NMOS as switch, the voltage φ1 on the first switch is decreased from the power supply voltage VDD until close to the threshold voltage, even lower than the threshold voltage, so that the first switch is closed; the voltage φ2 on the second switch is set to 0V, so that the second switch is opened, and V1 charges the capacitor C; the voltage φ1 on the first switch is set to 0V, so that the first switch is opened; the voltage φ2 on the second switch is decreased from the power supply voltage VDD until close to the threshold voltage, even lower than the threshold voltage, so that the second switch is closed, and V2 charges the capacitor C.

[0036] For PMOS as switch, the voltage φ1 on the first switch is increased from the ground GND until close to the threshold voltage, even higher than the threshold voltage, so that the first switch is closed; the voltage φ2 on the second switch is set to 0V, so that the second switch is opened, and V1 charges the capacitor C; the voltage φ1 on the first switch is set to 0V, so that the first switch is opened; the voltage φ2 on the second switch is increased from the ground GND until close to the threshold voltage, even higher than the threshold voltage, so that the second switch is closed, and V2 charges the capacitor C.

[0037] Further, the number of switch resistors is not limited, and any number of switch resistors can be connected in series, such as Figure 3 As shown.

[0038] However, due to the change of corner (process angle) and temperature, the threshold of the switch MOS tube will change accordingly.

[0039] If all NMOS is used as switch, the same size NMOS can be used to form a diode connection method to form a switch voltage. As shown, Figure 4 The structure includes NMOS tubes MN1, MN2, MN3 and a current source, the input end of the current source is connected to the power supply voltage, the output end is connected to the drain end of the NMOS tube MN1, the source end of the NMOS tube MN1 is connected to the ground, and the gate end is connected to the output end of the current source; the gate end of the NMOS tube MN2 is connected to the output end of the current source, the source end is connected to the V1 voltage, and the drain end is connected to the first end of the capacitor C; the gate end of the NMOS tube MN3 is connected to the output end of the current source, the drain end is connected to the V2 voltage, and the source end is connected to the first end of the capacitor C; the second end of the capacitor C is connected to the ground.

[0040] The NMOS tubes MN1, MN2 and MN3 all use the same size switch, such as Figure 5As shown, the gate voltage of NMOS MN2 and MN3 can be changed by adjusting the number of parallel switch NMOS MN1 or changing the current of input NMOS, i.e. the size of current source, and NMOS MN2 and MN3 are used as on-off switches.

[0041] If PMOS is used as switch, the same size PMOS can be used to form a diode connection method to form a switching voltage. For example, Figure 6 As shown, the structure includes PMOS MP1, MP2, MP3 and a current source. The input end of the current source is connected to a power supply voltage, the output end is connected to the drain of PMOS MP1, the source of PMOS MP1 is connected to ground, and the gate is connected to the output end of the current source. The gate of PMOS MP2 is connected to the output end of the current source, the source is connected to V1 voltage, and the drain is connected to the first end of capacitor C. The gate of PMOS MP3 is connected to the output end of the current source, the drain is connected to V2 voltage, and the source is connected to the first end of capacitor C. The second end of capacitor C is connected to ground.

[0042] PMOS MP1, MP2 and MP3 are all switches of the same size, for example, Figure 7 As shown, the gate voltage of PMOS MP2 and MP3 can be changed by adjusting the number of parallel switch PMOS MP1 or changing the current of input PMOS, i.e. the size of current source, and PMOS MP2 and MP3 are used as on-off switches.

[0043] The technical features of the above embodiments can be combined in any way. In order to make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combination of the technical features does not exist contradictory, it should be considered as the scope of the present application.

[0044] The above embodiments only express several implementation ways of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be noted that for ordinary skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent of the present application should be subject to the appended claims.

Claims

1. An improved method for switched capacitor resistors, characterized in that, include: When reducing conduction, for an NMOS transistor used as a switch, the gate voltage of the switch is reduced from the power supply voltage VDD until it approaches or even falls below the threshold voltage. When using a PMOS transistor as a switch, the gate voltage of the switch is increased from ground (GND) until it approaches or even exceeds the threshold voltage. Using a low on-state voltage for switching resistors reduces the channel charge generated, which in turn reduces the charge accumulated at the input / output terminals.

2. The improved method for switched capacitor resistors as described in claim 1, characterized in that, The switching voltage on the switch is formed by the diode connection of the NMOS transistor, and its structure includes NMOS transistors MN1, MN2, and MN3 and a current source; The input terminal of the current source is connected to the power supply voltage, the output terminal is connected to the drain terminal of NMOS transistor MN1, the source terminal of NMOS transistor MN1 is grounded, and the gate terminal is connected to the output terminal of the current source. The gate of NMOS transistor MN2 is connected to the output of the current source, the source is connected to voltage V1, and the drain is connected to the first terminal of capacitor C. The gate of NMOS transistor MN3 is connected to the output of the current source, the drain is connected to the voltage V2, and the source is connected to the first terminal of capacitor C; the second terminal of capacitor C is grounded.

3. The improved method for switched capacitor resistors as described in claim 2, characterized in that, The gate voltages of NMOS transistors MN2 and MN3 can be changed by adjusting the number of NMOS transistors MN1 connected in parallel or by changing the magnitude of the current source.

4. The improved method for switched capacitor resistors as described in claim 2, characterized in that, The NMOS transistors MN1, MN2, and MN3 are of the same size.

5. The improved method for switched capacitor resistor as described in claim 1, characterized in that, The switching voltage on the switch is formed by the diode connection of the PMOS transistor, and its structure includes PMOS transistors MP1, MP2, MP3 and a current source; The input terminal of the current source is connected to the power supply voltage, the output terminal is connected to the drain terminal of PMOS transistor MP1, the source terminal of PMOS transistor MP1 is grounded, and the gate terminal is connected to the output terminal of the current source. The gate of PMOS transistor MP2 is connected to the output of the current source, the source is connected to voltage V1, and the drain is connected to the first terminal of capacitor C. The gate terminal of PMOS transistor MP3 is connected to the output terminal of the current source, the drain terminal is connected to the voltage V2, and the source terminal is connected to the first terminal of capacitor C; the second terminal of capacitor C is grounded.

6. The improved method for switched capacitor resistor as described in claim 5, characterized in that, The gate voltages of PMOS transistors MP2 and MP3 can be changed by adjusting the number of PMOS transistors MP1 connected in parallel or by changing the magnitude of the current source.

7. The improved method for switched capacitor resistor as described in claim 5, characterized in that, The PMOS transistors MP1, MP2, and MP3 are of the same size.

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