ZYNQ7000-based loudspeaker array sound field directivity controllable system and control method thereof

Abstract

The embodiment of the invention provides a loudspeaker array sound field directivity controllable system based on ZYNQ7000 and a control method thereof, which can be applied to the technical field of audio data processing. The system comprises a core processing module. Wherein the core processing module comprises a processing end and a logic end; the processing end is used for performing write-in operation on single-channel audio data corresponding to a target audio signal transmitted by the logic end, updating a receiving pointer and a plurality of sending pointers, and performing scaling operation on data of an address space pointed by each sending pointer; sending a read burst instruction to send the data of the memory space of the memory to the logic end for processing; the logic end is used for triggering a write burst operation, writing the received audio data into the memory and outputting the received multi-channel audio data in response to the trigger of a read burst operation, and the multi-channel audio data is determined through the single-channel audio data and the multi-channel sound field data.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of audio data processing, in particular to the technical field of audio-visual processing, and more particularly to a loudspeaker array sound field directivity controllable system based on ZYNQ7000 and a control method thereof. BACKGROUND

[0002] With the continuous improvement of the level of science and technology, the application scenarios of loudspeaker arrays in life are increasingly widespread. The research on loudspeaker array sound field controllable systems currently mainly focuses on the implementation on hardware platforms such as STM32, FPGA, DSP, etc. Although the hardware platforms provided by these existing solutions have certain advantages in processing complex signal processing algorithms, they also have obvious inherent drawbacks, making it difficult to strike a better balance between high precision, high reliability and development difficulty. SUMMARY

[0003] In view of at least one of the above problems, embodiments of the present application aim to provide a loudspeaker array sound field directivity controllable system based on ZYNQ7000 and a control method thereof, which are more efficient, have higher precision, are more stable and reliable, are easier to develop, and have better controllability.

[0004] One aspect of an embodiment of the present application provides a loudspeaker array sound field directivity controllable system based on ZYNQ7000, which includes a sound field data module, an audio sampling module, and a core processing module. The sound field data module is used to obtain multi-channel sound field data for the sound field of the loudspeaker array; the audio sampling module is used to collect a target audio signal; and the core processing module, based on a ZYNQ7000 chip as a main controller, is used to respectively receive the multi-channel sound field data of the sound field data module and the target audio signal of the audio sampling module and perform internal logical operations. The core processing module includes a processing end and a logic end. The processing end is implemented based on an advanced reduced instruction set microprocessor and is used to perform write operation on single-channel audio data corresponding to the target audio signal transmitted by the logic end, update a receiving pointer and multiple sending pointers, and perform proportional scaling operation on data in the address space pointed to by each sending pointer and send the data in the memory space of the memory to the logic end for processing by sending a read burst instruction. The logic end is implemented based on a field programmable gate array and is used to trigger write burst operation, write the received audio data into the memory, and in response to the trigger of the read burst operation, output the multi-channel audio data of the processing end, which is determined by the single-channel audio data and the multi-channel sound field data.

[0005] According to an embodiment of the present application, the ZYNQ7000-based speaker array sound field directivity controllable system further comprises a data interaction module. The data interaction module is configured to receive multi-channel sound field data of the sound field data module through a preset interaction interface, and forward the multi-channel sound field data to the core processing module, wherein the multi-channel sound field data comprises a delay parameter and a corresponding amplitude weight of the sound field of the speaker array.

[0006] According to an embodiment of the present application, the processing end comprises an Ethernet physical layer and a first processing core. The Ethernet physical layer is configured to receive the multi-channel sound field data forwarded by the data interaction module through a preset multiplexing function interface of the core processing module, and forward the multi-channel sound field data; and the first processing core is configured to receive the multi-channel sound field data forwarded by the Ethernet physical layer.

[0007] According to an embodiment of the present application, the core processing module further comprises a memory. The memory is configured to write the single-channel audio data and / or the multi-channel sound field data into a preset spatial data form according to a destination data space of a write burst operation of the processing end, and on this basis, perform scale transformation on the single-channel audio data and the multi-channel sound field data to generate multi-channel audio data, and then perform readout of the multi-channel audio data according to a control of a read burst operation of the processing end.

[0008] According to an embodiment of the present application, the processing end further comprises a second processing core. In the write burst operation process, the second processing core is configured to send a write instruction for the write of the single-channel audio data transmitted by the logic end, and update a receiving pointer; and in the read burst operation process, the second processing core is configured to update a sending pointer and perform a scaling operation on the address space data pointed to by the sending pointer, and send a read instruction for the output of the multi-channel audio data; wherein the second processing core is further configured to receive and forward the multi-channel sound field data sent by the first processing core of the processing end, to realize the write operation of the multi-channel sound field data to the memory.

[0009] According to an embodiment of the present application, the logic end comprises a bus interconnection unit and a direct memory access core. The bus interconnection unit is configured to forward the single-channel audio data corresponding to the audio sampling module to the second processing core of the processing end in the write burst operation process, and receive the multi-channel audio data forwarded by the second processing core in the read burst operation process; and the direct memory access core is configured to forward the single-channel audio data to the bus interconnection unit in the write burst operation process, and receive the multi-channel audio data forwarded by the bus interconnection unit in the read burst operation process.

[0010] According to an embodiment of the present application, the logic end further comprises an audio data write core. The audio data write core is configured to convert the target audio signal in the preset built-in audio bus format of the received audio sample module into single-channel audio data during the write burst operation and write and forward the single-channel audio data to the DMA core, and the conversion comprises: in response to the internal write data amount of the preset input / output queue reaching the preset amount threshold, receiving the write burst signal sent by the receiving processing end through the preset extended function interface; and performing burst data transmission of the preset bus stream according to the write burst signal to forward the single-channel audio data to the DMA core.

[0011] According to an embodiment of the present application, the logic end further comprises an audio data read core. The audio data read core is configured to output the multi-channel audio data received by the DMA core during the read burst operation, and the output comprises: receiving the multi-channel audio data transmitted by the bus interconnection unit of the logic end and the DMA core; in response to all the internal amounts of the preset input / output queues being non-empty, starting to read the multi-channel audio data of each preset input / output queue; and converting the multi-channel audio data of each preset input / output queue read to a multi-channel audio signal in the preset built-in audio bus format for output.

[0012] According to an embodiment of the present application, the ZYNQ7000-based speaker array sound field directivity controllable system further comprises an audio output module. The audio output module is configured to perform multi-channel digital-to-analog conversion on the multi-channel audio signal.

[0013] According to an embodiment of the present application, during the write burst operation, the second processing core of the processing end is configured to send a write instruction for the write of the single-channel audio data transmitted by the logic end and update the receiving pointer, and the update comprises: detecting that the internal write data amount of the audio data write core reaches the preset amount threshold, sending a write burst signal to the audio data write core through the preset extended function interface, performing write burst, and performing write burst counting; and when the write burst counting reaches the preset value, updating the multi-channel read burst address of the single-channel audio data.

[0014] Another aspect of the embodiment of the present application provides a control method of a ZYNQ7000-based speaker array sound field directivity controllable system, configured to realize speaker array sound field directivity control, and the method comprises: controlling the processing end to perform write operation on the single-channel audio data corresponding to the target audio signal transmitted by the logic end according to the write burst trigger of the logic end; and in response to the trigger of the read burst operation, controlling the logic end to output the multi-channel audio data received by the processing end, and the multi-channel audio data is determined by the single-channel audio data and the multi-channel sound field data corresponding to the speaker array sound field.

[0015] The loudspeaker array sound field directivity controllable system based on ZYNQ7000 provided by the embodiment of the application can at least partially solve the problem that the loudspeaker array sound field directivity controllable system cannot better achieve effective compatibility among high precision, high reliability and low development difficulty in the related art, and therefore can at least achieve one of the following technical effects:

[0016] (1) By integrating the processing end and the logic end interconnected by the internal bus based on the ZYNQ architecture in the same chip, direct communication is performed through the hard core bus AXI, without external physical pins, the data transmission path is short, and the data transmission delay is extremely low (nanosecond level).

[0017] (2) The bandwidth of the AXI bus can be more than 10 times that of the FSMC / FMC, and can meet the data processing of a large data amount scene (such as video processing and high-speed data acquisition).

[0018] (3) For the development of the ZYNQ system architecture, the AXI IP core generator (such as AXIDMA and AXI FIFO) can be provided, so that the interface logic can be automatically generated, and the software development is greatly simplified. In addition, the AXI can greatly reduce the development difficulty and shorten the project cycle through the automatic tool chain.

[0019] (4) The AXI interface is implemented by a hard core, and the logic resources of the logic end are less occupied, and the on-chip communication power consumption is significantly lower than that of the external bus (without driving the PCB wiring). The AXI based on the ZYNQ architecture in the embodiment of the application is obviously better in resource efficiency and power consumption.

[0020] (5) The loudspeaker array sound field directivity controllable system based on ZYNQ7000 in the embodiment of the application can facilitate the implementation of the loudspeaker array sound field directivity intelligent algorithm, can facilitate user debugging, and provide strong signal processing capability and stability.

[0021] Therefore, the speaker array sound field directivity controllable system based on ZYNQ7000 can have stronger timing control ability and stability compared with the traditional scheme based on STM32 (ARM) and DSP platform. In addition, compared with the traditional scheme based on FPGA platform only, the speaker array sound field directivity controllable system based on ZYNQ7000 can realize collaborative data processing between the logic end and the processing end, thereby significantly reducing the development difficulty and development cycle. Further, compared with the traditional solution based on two chips of FPGA+ARM, the speaker array sound field directivity controllable system based on ZYNQ7000 can achieve smaller size only through a single chip based on ZYNQ, and can guarantee higher stability and more faithful signals compared with the traditional scheme of external wiring of two chips.

[0022] In particular, compared with the traditional scheme based on two chips of FPGA+ARM in the prior art, the core processing module of the speaker array sound field directivity controllable system can directly avoid interconnection of the two chips through external leads (such as PCB copper foil wiring in physical sense), and can realize millimeter-level on-chip interconnection between modules through advanced packaging based on a single chip of ZYNQ through a hardware bus (AXI), thereby realizing efficient, stable and reliable large-scale data channel between the logic end and the processing end based on IP hard core and programmable logic based on the bus protocol.

[0023] Therefore, the speaker array sound field directivity controllable system based on ZYNQ7000 provided by the embodiment of the present application is used to realize speaker array sound field directivity control, and provides a technical solution capable of better realizing effective compatibility between high precision, high reliability and low development difficulty for the existing speaker array sound field directivity controllable system, so as to achieve a speaker array sound field directivity controllable audio data processing effect with shorter data transmission path and extremely low delay (nanosecond level), and to meet the data processing scene of large data volume (such as high-speed data acquisition), reduce resource occupancy and power consumption, guarantee lower development difficulty and more convenient debugging and development effect, and guarantee signal fidelity and system stability and reliability.

[0024] In summary, the speaker array sound field directivity controllable system based on ZYNQ7000 can be effectively applied to a speaker array sound field directivity controllable system, has great scientific value and theoretical guiding significance for the research of the sound field directivity control system of the online array loudspeaker, can meet the application in application scenes or fields including theaters, stadiums, vehicle sound systems and the like, has wide commercial application value, and can realize better industrial application.

[0025] It should be understood that the foregoing general description and the following detailed description are merely exemplary and explanatory and are not restrictive of the scope of the application as it is intended to be claimed. BRIEF DESCRIPTION OF DRAWINGS

[0026] The above and other objects, features and advantages of the present application will become more apparent from the following description when taken in conjunction with the accompanying drawings, in which:

[0027] Figure 1 Fig. 1 schematically shows a structural block diagram of a ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application;

[0028] Figure 2A Fig. 2 schematically shows a beam deflection schematic diagram of a sound field data module of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application;

[0029] Figure 2B Fig. 3 schematically shows a theater scene diagram based on the beam deflection schematic shown in Fig. 2 of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application; Figure 2A

[0030] Figure 3 Fig. 4 schematically shows a Chebyshev weighting and uniform weighting effect comparison diagram of the sound field data module of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application;

[0031] Figure 4 Fig. 5 schematically shows a channel update logic diagram of the memory 303 of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application;

[0032] Figure 5 Fig. 6 schematically shows another structural block diagram of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application;

[0033] Figure 6A Fig. 7 schematically shows a write flow direction diagram (as shown by the dashed arrows) of single-channel audio data of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application;

[0034] Figure 6B Fig. 8 schematically shows a write flow diagram (corresponding to the dashed arrows shown in Fig. 7) of single-channel audio data of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application, corresponding to the functions of the audio data write core; Figure 6A

[0035] ​​Figure 7A Fig. 8 schematically shows a read flow chart of multi-channel audio data of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application (corresponding to the dashed arrow shown in Fig. 7), corresponding to the function of the audio data read core;

[0036] Figure 7B Fig. 9 schematically shows a write flow chart of sound field data of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application (corresponding to the dashed arrow shown in Fig. 8), corresponding to the function of the processing end; Figure 7A

[0037] Figure 8A Fig. 10 schematically shows a write flow chart of sound field data of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application (corresponding to the dashed arrow shown in Fig. 9), corresponding to the delay amplitude weighting algorithm implementation of the second processing core of the processing end;

[0038] Figure 8B Figure 8A

[0039] Figure 9 Fig. 11 schematically shows a comparison chart of speaker unit simulation results and experimental structures of the speaker sound field directivity system applied by the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application; and

[0040] Figure 10 Fig. 12 schematically shows a flow chart of the control method of the ZYNQ7000-based speaker array sound field directivity controllable system according to an embodiment of the present application.

[0041] The above-mentioned drawings are part of the specification of the embodiments of the present application, which illustrate the example embodiments of the present application, and the accompanying drawings together with the description of the specification are used to illustrate the principles of the embodiments of the present application. It should be understood that the above description generally directed to the drawings and the following detailed embodiments are only exemplary and explanatory, and cannot limit the scope of the present application. DETAILED DESCRIPTION

[0042] In order to make the purposes, technical solutions and advantages of the embodiments of the present application more clear, the drawings and detailed description will be used to clearly illustrate the spirit of the present application. Any person skilled in the art can modify and modify the technology taught by the present application without departing from the spirit and scope of the present application.

[0043] ​​​The illustrative embodiments of the disclosure and their

[0044] As used herein, the terms "first", "second", etc. are used only to distinguish one element from another, and do not otherwise limit the elements. These terms are not otherwise used to limit the scope of the disclosure.

[0045] As used herein, the terms "first", "second", etc. are used only to distinguish one element from another, and do not otherwise limit the elements. These terms are not otherwise used to limit the scope of the disclosure.

[0046] As used herein, the terms "first", "second", etc. are used only to distinguish one element from another, and do not otherwise limit the elements. These terms are not otherwise used to limit the scope of the disclosure.

[0047] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0048] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0049] As used herein, the terms "first", "second", etc. are used only to distinguish one element from another, and do not otherwise limit the elements. These terms are not otherwise used to limit the scope of the disclosure.

[0050] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined. It should be noted that the terms used herein are to be interpreted as having a meaning that is consistent with how the term is interpreted in the context of the specification and not otherwise in an idealized or overly formal sense.

[0051] In the event that a usage similar to the expression "at least one of A, B, and C, etc." is used, in general, it should be interpreted that the meaning is the inclusion of at least one of A, B, or C in the group. For example, the expression "a system having at least one of A, B, or C" should be interpreted to include a system having A alone, a system having B alone, a system having C alone, a system having both A and B, a system having both A and C, a system having both B and C, and / or a system having A, B, and C, etc. In the event that a usage similar to the expression "at least one of A, B, or C etc." is used in this disclosure, it should be understood that simply stating such a phrase is meant to encompass the possibilities of either one of A, B, or C being present alone or in combination with any of the other options, and thus the phrase "at least one of A, B, or C" shall be interpreted to include A alone, B alone, C alone, A and B in combination, A and C in combination, B and C in combination, or A, B, and C in combination, etc.

[0052] Generally, the difficulty of developing a loudspeaker array control system using the STM32 platform is relatively low, and the cost is relatively low, and because it is C code, it is easy to deploy programming audio processing algorithms, and the development cycle is short. However, because the architecture used by the STM32 platform is the ARM architecture, it cannot perform parallel operation, and the timing control performance is weak, and it is difficult to achieve timing control capability with an accuracy of 20us. In this case, only by sacrificing accuracy can the development cycle be shortened, which cannot meet the high-precision timing control capability required by the directional loudspeaker system, and cannot well realize the requirements of sidelobe suppression, constant beam width, and beam deflection accuracy, which will inevitably cause a large deviation between experimental and theoretical data.

[0053] In addition, if the FPGA platform is used to develop a loudspeaker array sound field directivity system, although high-precision timing control can be well achieved, the difficulty of using only FPGA development is very great, and the development cycle will be very long, and because the development difficulty is great, it is also not convenient for later maintenance and upgrading.

[0054] Further, based on the joint development of the traditional ARM+FPGA two independent chips, ARM and FPGA can play their respective roles. Among them, the FPGA platform is simply used as a data interface to obtain external analog-to-digital conversion data (ADC data) and output digital-to-analog conversion data (DAC data), and the core algorithm is implemented through the ARM platform, so as to have both the short development cycle of ARM and the high-precision and high-reliability timing control capability of FPGA. However, the communication between the traditional ARM+FPGA two independent chips has become a problem, whether it is IIC, SPI, UART or FSMC / FMC communication, because it cannot directly communicate like the AXI bus of the hard core, so that the communication rate and reliability between the two are difficult to guarantee, resulting in poor signal fidelity.

[0055] In addition, based on the traditional DSP von Neumann architecture based on sequential execution, although it can be optimized for specific algorithms (such as FIR filtering, matrix operation), it is also difficult to achieve true parallel acceleration due to instruction cycle and serial processing.

[0056] In view of at least one of the above problems, embodiments of the present application aim to provide a more efficient, higher precision, more stable and reliable, easy-to-develop, and better controllable loudspeaker array sound field directivity controllable system and control method based on ZYNQ7000, for realizing loudspeaker array sound field directivity controllable, thereby providing a technical solution that can better realize the effective compatibility between high precision, high reliability and low development difficulty for existing loudspeaker array sound field directivity controllable systems, in order to achieve a loudspeaker array sound field directivity controllable audio data processing effect with shorter data transmission path and extremely low delay (nanosecond level), while being able to meet the data processing scene of large data volume scene (such as high-speed data acquisition), reduce resource occupancy and power consumption, ensure lower development difficulty and more convenient debugging and development effect, ensure signal fidelity and system stability and reliability.

[0057] The following will be described Figures 1-9 The ZYNQ7000-based loudspeaker array sound field directivity controllable system according to the disclosed embodiments will be described in detail.

[0058] As Figures 1-8B shown, an aspect of an embodiment of the present application provides a ZYNQ7000-based loudspeaker array sound field directivity controllable system 100 for realizing loudspeaker array sound field directivity controllable, which comprises a sound field data module 101, an audio sampling module 102 and a core processing module 103.

[0059] The sound field data module 101 is used to obtain multi-channel sound field data for the loudspeaker array sound field;

[0060] The audio sampling module 102 is used for collecting a target audio signal;

[0061] The core processing module 103 is based on a ZYNQ7000 chip as a host, and is used for receiving the multi-channel sound field data of the sound field data module 101 and the target audio signal of the audio sampling module 102 respectively and performing internal logical operation.

[0062] The core processing module 103 includes a processing end 301 and a logic end 302; the processing end 301 is based on an advanced reduced instruction set microprocessor, is used for performing write operation on single-channel audio data corresponding to the target audio signal transmitted by the logic end 302, updating a receiving pointer and multiple sending pointers, and performing proportional scaling operation on data in an address space pointed to by each sending pointer, and sending a read burst instruction to send data in a memory space of a memory to the logic end; and the logic end 302 is based on a field programmable gate array, is used for triggering write burst operation, writing received audio data into a memory, and in response to triggering of read burst operation, outputting received multi-channel audio data of the processing end, the multi-channel audio data being determined by the single-channel audio data and the multi-channel sound field data.

[0063] In the embodiment of the application, the loudspeaker array can be an electronic device or apparatus composed of loudspeaker units for audio playing, such as a sound system or a sound box product, and can be applied to a theater, a stadium or other application scenarios to achieve a directional playing effect of sound.

[0064] The sound field data module, as the loudspeaker array sound field directivity parameter calculation module in the embodiment of the application, can obtain multi-channel loudspeaker array parameters, and specifically can obtain a beam deflection effect by controlling a delay amount of each array element (i.e., loudspeaker unit) according to a sound wave superposition and interference principle of a sound field, and further can achieve a sidelobe suppression effect of an audio signal by amplitude weighting of each unit.

[0065] For obtaining the loudspeaker array sound field directivity parameters, the beam deflection principle and the sidelobe suppression principle can be used.

[0066] A phased array, also called a phase compensation array, is obtained by adding a corresponding delay phase shifter to each array element, and a beam deflection is obtained by adjusting a delay amount of each array element. Phasing is initially used for frequency scanning of an antenna array, and a transmission angle of the entire antenna array is controlled by controlling a delay of a single antenna element. In a case where a frequency of the antenna is reduced, the beam deflection principle of the phased array can be used for ultrasonic waves, and the same beam deflection effect of the overall structure transmission can be achieved. Therefore, the phased method can also be used for the loudspeaker array to achieve the beam deflection effect.

[0067] For example, as shown in FIG. 1, a sound field data module 101, an audio sampling module 102 and a core processing module 103 are connected to each other. Figure 2AAs shown, the loudspeaker array consists of elements S1 to S5, where d is the spacing between adjacent elements, and x corresponds to the path difference between other elements relative to the first element S5 due to the time delay. For example, the path difference between element S4 and element S5 is x, and the path difference between element S2 and element S5 is 3x. Therefore, the path difference satisfies: x = ct, where c is the speed of sound in a medium (such as air), t is the time delay of the corresponding element, and the deflection angle θ of the loudspeaker array satisfies the following formula (1):

[0068]

[0069] In this context, "beam deflection" can be understood as amplifying sound in a specific direction, thereby achieving directional sound coverage. To further describe the effect of beam deflection in detail, the following example illustrates this. Figure 2B The following example illustrates the application scenario in the theater field:

[0070] like Figure 2B As shown, in a theater setting, there are two linear speaker arrays, array A and array B, with array A positioned above array B. The sound field of array A points towards the upper seats at an angle of θ1; the sound field of array B points towards the lower seats at an angle of θ2. These angles θ1 and θ2 correspond to the following... Figure 2A The deflection angle θ is shown. Therefore, directional coverage of audio signals can be achieved through the above beam deflection calculation, which will not be elaborated further.

[0071] Specifically, the deflection can be implemented using computational tools such as Matlab to calculate the delay time t of each output channel. Then, the delay parameters of each channel are passed to the core processing module 103 through the data interaction module 104 described later. The processing terminal PS receives the multi-channel delay parameters and stores them. For example, the delay parameters can be delay_t1, delay_t2, ..., delay_t16.

[0072] Furthermore, the core idea behind sidelobe suppression is to optimize the beam pattern (i.e., radiation or reception mode) by adjusting the excitation amplitude distribution of each element in the loudspeaker array, thereby suppressing sidelobe energy while maintaining the signal strength of the main lobe pointing towards the target. Amplitude weighting controls the beamwidth and sidelobe level of the synthesized beam by setting different amplitude weights for each element. Common windowing methods include uniform weighting, cosine weighting, Blackman weighting, Kaiser weighting, Hamming window weighting, and Taylor weighting.

[0073] In the embodiments of the present application, Chebyshev polynomial can be used to realize sidelobe suppression of the final audio output. In the Chebyshev weighting, the directivity function of the N uniform linear array is approximated to the N-1 order Chebyshev polynomial, as shown in the following formula (2):

[0074]

[0075] In formula (2), x = cosθ, 0°≤θ≤90°, θ is the deflection angle, and N is the number of array elements.

[0076] In order to more specifically describe the effect of sidelobe suppression, in the case of far field distance of 25 meters, sound speed c = 343 m / s, array element number N = 28, array height 0.69 meters, and beam width 30°, the comparison of uniform weighting and Chebyshev weighting effects is shown in the following formula (3). Figure 3 Figure 3 As shown in the following formula (4), by using the Chebyshev weighting, the beam sidelobe is effectively suppressed, so that the sound directivity output can present a more uniform effect in the sound field.

[0077] It can be seen that, compared with other common weighting methods, the amplitude weighting based on the Chebyshev window has unique advantages in audio processing. The core characteristics are equal ripple sidelobe design and highly controllable sidelobe attenuation. The Chebyshev window is optimized by mathematics, so that all sidelobes have the same height (equal ripple characteristic), and the sidelobe attenuation is as low as-80dB to-120dB (specific parameters can be customized), which is much higher than the suppression capability of Blackman weighting (-61dB) or Hamming weighting (-42dB).

[0078] Therefore, after the scale transformation of the single-channel analog to digital conversion data (ADC data), the digital to analog conversion data (DAC data) can be output in 16 ways. For example, the ADC data of output channel 2 is scaled by 0.888 relative to a single-channel ADC data, so that the audio data of channel 2 becomes 1-channel ADC data * 0.888, and the scale transformation of other output channels is similar.

[0079] ​In the embodiment of the present application, the deflection of the beam can be realized by changing only the delay, or the optimization of the beam sidelobe (i.e. sidelobe suppression) can be realized by changing only the amplitude weight of each channel, and the two can be combined to realize the effect of beam deflection on the basis of further sidelobe suppression. Among them, the multi-channel sound field data can include the aforementioned delay parameters based on beam deflection (such as t1, t2, …, t16 of 16 channels) and amplitude weighting values based on sidelobe suppression (corresponding to w1, w2, …, w16 of 16 channels).

[0080] The target audio signal can be a reference audio signal that realizes the audio data processing function, or an application audio signal for specific scene application (such as a movie theater), such as a film theme song, etc., which is not limited in particular.

[0081] Among them, the target audio signal can be used as the sampling signal of the audio sampling module 102, and the target audio signal can be transmitted to the core processing module 103 through the audio sampling module 102. In the embodiment of the present application, the audio sampling module 102 can use a vehicle-grade PCM1820 chip, which can be used as an analog-to-digital converter (Analog to Digital Converter, ADC for short) to realize 32-bit audio resolution, and the audio sampling rate can be as high as 192kHz, so that high-precision collection of the sound source signal can be realized, and the high restoration of the target audio signal can be ensured. Among them, in the embodiment of the present application, an audio sampling rate of 50Khz can be used.

[0082] As shown in Figure 1 and Figure 5 The core processing module 103 can be based on Xilinx ZYNQ7000 series chip (Zynq-7000 All Programmable SoC, ZYNQ for short) as the main controller, and the corresponding audio data processing function can be realized through the on-board FT2232 chip as the core board card. Among them, based on the core processing module 103, the memory (such as DDR3) described later, QSPI FLASH, SD card adapter chip, gigabit Ethernet, JTAG, UART, audio sampling module, audio output module can be further integrated, and data interaction can be performed through the network port of the computer end (such as Personal Computer end, PC for short).

[0083] The core processing module 103 based on ZYNQ in the embodiment of the application can further include an internal interconnected processing end 301 and a logic end 302. The processing end 301 can be implemented based on an Advanced RISC Machines (ARM) platform, and is used as a processing system (PS) of the core board. The processing end 301 can be a SOC part based on an ARM architecture, and can be responsible for processing system-level tasks. The main function of the processing end 301 is to send write and read instructions of audio data, to update a receiving pointer and a sending pointer, and to perform scaling operation on data in an address space pointed to by the sending pointer.

[0084] Meanwhile, the logic end 302 can be implemented based on a Field Programmable Gate Array (FPGA) platform, and is used as a programmable logic (PL) of the core board. The FPGA is a chip that can be configured to have a logic function, and can be programmed according to needs, so as to implement a specific function. The main function of the logic end 302 is to be responsible for writing and reading of audio data, to cache the data, and to perform parsing of I2S format data. Generally, the processing end 301 can be responsible for sending instructions, and specific write and read operations can be performed based on the logic end 302.

[0085] The processing end 301 and the logic end 302 can be interconnected and communicated through an Advanced eXtensible Interface (AXI) bus, and are integrated on the core board of the core processing module 103. Therefore, the two ends do not need external physical pins for interconnection, the data transmission path is shorter, the data communication delay is extremely low (in the order of nanoseconds), and the bandwidth of the AXI can be more than 10 times of a Flexible Static Memory Controller (FSMC) or a FPGA Mezzanine Card (FMC), which is particularly suitable for a large data volume scenario. In addition, for development of the ZYNQ, a bus intellectual property core (AXI IP core) generator (such as AXI DMA and AXI FIFO) can be provided to automatically generate interface logic, so as to facilitate software development and shorten the project cycle. In addition, the AXI bus is also more advantageous in resource efficiency and power consumption.

[0086] The core processing module 103 can perform internal signal processing on the target audio signal data after being sampled by the audio sampling module 102 based on the processing end 301 and the logic end 302 of the bus AXI interconnection, and then output the sound field signal corresponding to the multi-channel audio data through the multi-channel audio output module 105 described below. The core processing module 103 can be implemented based on the hardware environment of the ZYNQ7000 series platform.

[0087] As shown in Figure 5 The core processing module 103 can adopt the overall architecture of the ZYNQ system, in which the logic end 302 can be responsible for simply making interfaces and direct memory access (Direct Memory Access, abbreviated as DMA) handling of data. The logic end 302 can perform analog-to-digital conversion on the target audio signal obtained from the external audio sampling module 102 to generate single-channel audio data (such as 32-bit single-channel audio data), and through a write burst trigger operation process, the single-channel audio data is transmitted to the processing end through the AXI bus to realize single-channel audio data writing. With the help of the processing end 301, the scale transformation of the single-channel audio data and the multi-channel sound field data can be realized to generate corresponding multi-channel audio data. In addition, the logic end 302 can also transmit the multi-channel audio data from the processing end 301 to the corresponding DAC output channels of the audio output module 105 described below through the AXI bus data stream (AXI-Stream). The processing end 301 can write the delay parameters and amplitude weighting values of the multi-channel sound field data based on the ZYNQ core board in advance. The processing end based on ARM can be responsible for the core audio processing and calculation process.

[0088] For the core processing module 103 based on the ZYNQ core board, the FT2232 chip can be on-board, and using this chip can complete the operation of JTAG (Joint Test Action Group) + UART (Universal Asynchronous Receiver / Transmitter). The USB port can use TYPEC, which contains an ESD (Electrostatic Discharge) + common mode filter and an ideal diode. In addition, the core board can perform remote sampling based on the SIC431 device, with a sampling efficiency of up to 97% (peak efficiency), and has a 24A power supply capability. Moreover, the SIC431 device can support internal compensation, without the need for an external ESR (Equivalent Series Resistance) network to achieve loop stability, and auxiliary power supply can be implemented based on TPS82130.

[0089] Therefore, finally the feasibility of the system software and hardware design of the above-mentioned ZYNQ7000-based speaker array sound field directivity controllable system based on the core processing module 103 can be verified based on the data as shown below Figure 5 Figure 9 According to the comparative experiments of uniform weighting, beam deflection and Chebyshev sidelobe suppression as shown below

[0090] The ZYNQ7000-based speaker array sound field directivity controllable system according to the embodiment of the present application can achieve a delay precision of at least 20us and an amplitude control precision of greater than 2.384x10 -7 Figure 1 Figures 5-9 The ZYNQ7000-based speaker array sound field directivity controllable system according to the embodiment of the present application can provide systematic software and hardware design modules, including software design and hardware design. The software design includes single-channel audio data writing process, multi-channel audio data reading process and implementation process of directivity algorithm, and the hardware design mainly includes core processing module 103 based on ZYNQ7000 core board, audio sampling module 102 and multi-channel audio output module 105 and other specific designs. In order to enable those skilled in the art to have a more clear understanding of the above-mentioned ZYNQ7000-based speaker array sound field directivity controllable system according to the embodiment of the present application, the following

[0091] Figures 1-8B According to an embodiment of the present application, the ZYNQ7000-based speaker array sound field directivity controllable system 100 further includes a data interaction module 104.

[0092] The data interaction module 104 is used to receive the multi-channel sound field data of the sound field data module 101 through the preset interaction interface, and forward it to the core processing module 103, wherein the multi-channel sound field data includes the delay parameter and the corresponding amplitude weight of the speaker array sound field and other sound field parameters.

[0093] The data interaction module 104 can be implemented based on the PC end, and has a corresponding preset interaction interface between the sound field data module 101 to realize data transmission between the two, which can be realized based on the data interface of the PC end (such as the data input interface provided by the visual interaction interface), and the specific description is omitted. The data interaction module 104 is used to realize the data interaction between the sound field parameters of the multi-channel sound field data of the speaker array sound field directivity and the core board of the core processing module 103.

[0094] ​​​​Wherein, on the basis of calculating the sound field parameters of the multi-channel loudspeaker array as the multi-channel sound field data by the sound field data module 101, the data interaction module 104 can send interaction instructions to configure the sound field parameters such as the delay parameters and amplitude weighting values of each output channel relative to the audio input channel. Specifically, the data interaction module can transmit the sound field parameters of each channel to the processing end 301 of the core processing module 103 based on ZYNQ7000 based on the multi-channel sound field data of the sound field data module 101 through calculation such as Matlab, so that the setting of the multi-channel audio data delay and amplitude weighting parameters can be completed by means of tools such as serial port assistant.

[0095] As shown in Figures 1-8B , according to an embodiment of the application, the processing end 301 includes an Ethernet physical layer 311 and a first processing core 312.

[0096] The Ethernet physical layer 311 is used to receive the multi-channel sound field data forwarded by the data interaction module 104 through the preset multiplexed input / output interface of the core processing module 103, and forward it;

[0097] The first processing core 312 is used to receive the multi-channel sound field data forwarded by the Ethernet physical layer 311.

[0098] The preset multiplexed input / output interface (MIO) as a multiplexed input / output interface can realize the communication between the processing end 301 and the external interface, which is mainly used as the interface of the processing end 301 to receive the multi-channel sound field data from the data interaction module 104. As shown in Figure 5 , an asynchronous transceiver (i.e. universal asynchronous receiver / transmitter, UART) can also be provided to realize data interaction between the preset multiplexed input / output interface and the first processing core 312, which can be realized based on the serial, asynchronous and full-duplex communication protocol widely used in embedded field, and details are not described.

[0099] The Ethernet physical layer 311 (Physical Layer, PHY) is a port physical layer defined based on the Ethernet transmission protocol, which can realize the data interconnection between the preset multiplexed input / output interface and the first processing core, forward the multi-channel sound field data, and specifically forward it to the first processing core 312.

[0100] The first processing core 312 can internally run based on a FreeRTOS operating system of a LWIP (Light weight IP, i.e., a lightweight TCP / IP protocol), and the first processing core 312 can be a processing core (such as an A1 core of an ARM Cortex-A9 processor, i.e., an ARM Cortex-A9_1 core) of the processing end 301. The FreeRTOS operating system can be used for a ZYNQ-based core board to receive configuration data (i.e., multi-channel sound field data) from the data interaction module 104 through a data network port of the Ethernet physical layer 311. The format of the configuration data can be "chx weight xdelay_20us", for example, "ch5 0.856 100" means that the amplitude of the audio signal of channel 5 is multiplied by 0.856, and the audio data of channel 5 is output with a delay of 2 ms.

[0101] As shown in Figure 1-8B According to an embodiment of the present application, the core processing module 103 further includes a memory 303.

[0102] The memory 303 is used to write single-channel audio data and / or multi-channel sound field data in a preset spatial data form according to a purpose data space of a write burst operation of the processing end 301, and on this basis, scale transform the single-channel audio data and the multi-channel sound field data to generate multi-channel audio data, and then read out the multi-channel audio data according to the control of a read burst operation of the processing end 301.

[0103] The memory 303 can be implemented based on a third-generation double data rate synchronous dynamic random access memory (DDR3 SDRAM), which is similar to a random access memory (RAM) and can be used to store running programs and variables and allocate stack space, etc. The storage location of the sound field parameters of the single-channel audio data and the multi-channel sound field data can not be in the stack space, but in the global Data area, and in addition, the data writing destination space of the write operation can belong to a read-write region of a general memory (such as a DDR).

[0104] The preset spatial data form is used to define the data writing or storage form of the data storage location of the memory 303. For example, for the writing of single-channel audio data, one address of each spatial data corresponds to 8 bits (i.e., bits), and 4 8-bit data correspond to 32-bit audio data, i.e., one single-channel audio data (data). Therefore, by means of the preset spatial data form, the corresponding address of each writing data can be determined to facilitate subsequent calculation and read burst operations.

[0105] Based on the data processing control of the processing terminal 301, the memory 303 can perform scale transformation calculations based on multi-channel sound field data for single-channel audio data. For example, scale transformation calculations can be performed on 256 audio data to obtain the corresponding multi-channel audio data, so as to realize data reading in response to the triggering of read burst operations.

[0106] like Figure 4 As shown, regarding the implementation of write burst operations and read burst operations at the aforementioned processing terminal 301 and logic terminal 302, the channel update logic diagram of the memory 303 of the speaker array sound field directivity controllable system based on ZYNQ7000 in this embodiment of the invention is further described in detail below:

[0107] like Figure 4 As shown, the data growth direction of memory 303 proceeds from the bottom (low address) to the top (high address). Multi-channel sound field data (including delay parameters and corresponding amplitude weighting values ​​w1, w2, ..., w16 for channels 16, such as t1, t2, ..., t16) transmitted through the first processing core 312 is controlled by the second processing core 314 to be written into memory 303. Simultaneously, when processing terminal 301 executes controlled writing of single-channel audio data transmitted from logic terminal 302 into memory 303, the above data update process is performed sequentially for channels 1 to 16. The size of the received data block is the same as the size of the transmitted data block. Figure 4 As shown in Figure ①, the reception of single-channel audio data starts from the bottom receiving pointer and proceeds upwards until reception is complete. The direction of the transmitting pointer is determined by the position of the receiving pointer combined with the delay parameter t of the corresponding channel.

[0108] Specifically, firstly, for channel 1, the distance between the send pointer 1 and the receive pointer is determined based on the magnitude of the corresponding delay parameter t1 (the larger the delay parameter t, the farther the distance between the send pointer and the corresponding receive pointer). The position of the send pointer 1 is then determined, and a data scale transformation is performed on the space pointed to by the send pointer 1, multiplying each audio data in that space by the corresponding amplitude weight w1. This allows for the read burst transmission process of channel 1. Next, for channel 2, the position of the corresponding send pointer 2 is determined based on the magnitude of the corresponding delay parameter t2. The data scale is then transformed on the space pointed to by the send pointer 2, multiplying each audio data in that space by the corresponding amplitude weight w2. This allows for the read burst transmission process of channel 2. This process continues until channel 16, where the position of the corresponding send pointer 16 is determined based on the magnitude of the corresponding delay parameter t16. The data scale is then transformed on the space pointed to by the send pointer 16, multiplying each audio data in that space by the corresponding amplitude weight w16. This allows for the read burst transmission process of channel 16.

[0109] It should be noted that, in this embodiment of the invention, in order to improve the efficiency of channel updates and prevent data update errors or loss, the read burst operation and write burst operation of each channel can be performed on the same spatial address at different times or in sequence, and the corresponding operation of the next channel is performed only after the write burst operation and read burst operation of each channel are completed.

[0110] like Figures 1-8B As shown, according to an embodiment of the present invention, the processing terminal 301 further includes a storage controller 313 and a second processing core 314.

[0111] The storage controller 313 is used to control the data write and data read operations of the processing terminal 301 for the memory 303;

[0112] During the write burst operation, the second processing core 314 is used to send a write instruction for writing single-channel audio data transmitted from the logic end and update the receive pointer; and during the read burst operation, the second processing core is used to update the send pointer and perform a scaling operation on the address space data pointed to by the send pointer, and send a read instruction for the output of multi-channel audio data.

[0113] The second processing core is also used to receive and forward multi-channel sound field data sent by the first processing core of the processing end, and to realize the writing operation of multi-channel sound field data to memory.

[0114] The storage controller 313 can be a memory controller for the memory, used to implement memory read and write access control for the memory 303, specifically a DDR3 memory controller. The storage controller 313 can control the memory 303 to perform write operations for multi-channel sound field data. Furthermore, during write burst operations, it can write single-channel audio data transmitted from the logic terminal 302 to the memory 303 via the AXI bus data stream and control the amplitude weighting and other calculation processes between the single-channel audio data and the multi-channel sound field data to generate multi-channel audio data. Further, during read burst operations, the storage controller 313 can also control the read operation of multi-channel audio data from the memory 303. The storage control function of the storage controller 313 can be understood as a built-in function of the processing terminal 301.

[0115] The second processing core 314 can be a processing core based on the ZYNQ7000 chip processing terminal 301, such as the A0 core of the ARM Cortex-A9 processor, i.e., the ARM Cortex-A9_0 core, which is the first core of the processing terminal 301. This second processing core 314 can internally run a bare-metal system, mainly including the following processing operations S1 to S4.

[0116] In operation S1, the state of the first-in first-out queue (FIFO) inside the logic-end audio data write core 323 (such as AXI_WR) is judged, and if the first-in first-out queue reaches a certain capacity, a data transmission of a write burst operation is performed;

[0117] In operation S2, the receiving pointer is updated after each data transmission of a write burst;

[0118] In operation S3, the sending pointer of the 16 paths is updated according to the receiving pointer, and a scale transformation processing is performed on the address content of the space data pointed by the sending pointer, to generate corresponding multi-channel audio data;

[0119] In operation S4, a read burst operation of the 16 channels based on the hard-core bus (such as AXI) is performed.

[0120] In the embodiment of the present application, the first processing core 312 and the second processing core 314 can constitute a dual-core of the processing end 301, and the second processing core 314 can be the first core of the dual-core. Wherein, the delay parameters and the weight parameters of each channel are updated, specifically, after the first processing core 312 receives the multi-channel sound field data, the multi-channel sound field data can be stored in the shared memory (OCM), and then a software interrupt is sent to the second processing core 314 to inform the second processing core 314 to control the memory 303 to update the delay parameters and the weight parameters (i.e. amplitude weighting value) of each channel. The specific data updating process is described in the channel updating logic of the memory 303 as shown in Figure 4 Therefore, the second processing core 314 can realize the control forwarding of the corresponding transmission data.

[0121] As shown in Figures 1-8B According to an embodiment of the present application, the logic end 302 includes a bus interconnection unit 321 and a direct memory access core 322.

[0122] The bus interconnection unit 321 is used to forward the single-channel audio data from the audio sampling module 102 to the second processing core 314 of the processing end 301 during the write burst operation, and receive the multi-channel audio data forwarded by the second processing core 314 during the read burst operation.

[0123] The direct memory access core 322 is used to forward the single-channel audio data to the bus interconnection unit 321 during the write burst operation, and receive the multi-channel audio data forwarded by the bus interconnection unit 321 during the read burst operation.

[0124] The bus interconnection unit 321 (such as AXI Interconnect) can serve as a data bridging unit between the processing end 301 and the logic end 302, and is implemented by a bus communication intellectual property core (such as AXI IP core) based on the FPGA architecture of the ZYNQ-based core board, and can be responsible for data interconnection management of multiple bus master and slave interfaces, realize the effect of the bus interconnection intellectual property core (i.e. AXI interconnection IP core), and ensure efficient data transmission and traffic management.

[0125] As shown in FIG. 4, the second processing core 314 can perform data interconnection with the bus interconnection unit 321 of the logic end 302 based on a bus slave interface (AXI high-performance purpose, referred to as S_AXI_HP0) as a high-performance bus slave interface. Figure 5 Correspondingly, the first processing core 312 can perform data interconnection with another bus interconnection unit 321' of the logic end 302 based on a bus master interface (AXI general purpose, referred to as M_AXI_GP0) as a high-performance bus master interface.

[0126] The direct memory access core 322 can be implemented based on an AXI Direct Memory Access IP (AXI DMA IP), and can be used for data transfer between the audio data readout core 324 and the audio data write-in core 323 of the logic end 302 and the memory 303 controlled by the processing end 301. Based on the overall design of the core processing module 103 of the ZYNQ architecture, the logic end 302 can be responsible for the data transfer of the direct memory access (Direct Memory Access, referred to as DMA) of the interface and data. The direct memory access core 322 can obtain single-channel audio data from the audio sampling module 102 through the AXI4 stream to memory-mapped (S2MM) interface based on the bus between the audio data write-in core 323, and transmit the single-channel audio data to the processing end 301 through the bus data stream (AXI Stream) based on the bus interconnection unit 321 when the write burst operation is triggered, and the processing end 301 performs storage control; in addition, the direct memory access core 322 can also obtain multi-channel audio data from the processing end 301 through the AXI4 memory-mapped to stream (MM2S) interface based on the bus between the audio data readout core 324 when the read burst operation is triggered, and transmit the multi-channel audio data to the audio data readout core 324 for audio output operation based on the bus data stream of the bus interconnection unit 321.

[0127] Therefore, the logic end 302 can effectively avoid occupying the resources of the processing end 301 by using the direct memory access core 322 to perform high-speed data transfer between the FPGA-based logic end 302 and the memory 303 controlled by the ARM-based processing end 301, and the development cycle and difficulty of the platform can be greatly reduced due to the use of the IP core development.

[0128] Through the bus interconnection unit and the direct memory access core 322, the processing end 301 and the logic end 302 can be interconnected and communicated based on the hard core bus, and integrated on the core board card of the core processing module 103. Therefore, the interconnection between the two does not require external physical pins, the data transmission path is shorter, the data communication delay is extremely low (in the nanosecond level), and considering that the bandwidth of AXI can reach more than 10 times that of FSMC or FMC, it is especially suitable for large data scenarios. In addition, for the development of ZYNQ, by providing a bus intellectual property core generator, the interface logic can be automatically generated, thereby facilitating the simplification of software development and the shortening of the project cycle. In addition, the AXI bus is also more efficient in terms of resource efficiency and power consumption.

[0129] As shown in Figures 1-8B According to an embodiment of the present application, the logic end 302 further includes an audio data write-in core 323.

[0130] The audio data write-in core 323 is configured to convert the target audio signal in the preset built-in audio bus format of the audio sampling module 102 received during the write burst operation into single-channel audio data and write-in and forward to the direct memory access core 322, which includes:

[0131] In response to the internal write-in data quantity of the preset input / output queue reaching a preset quantity threshold, the receiving processing end sends a write burst signal through the preset expansion function interface;

[0132] According to the write burst signal, a burst data transmission of a preset bus stream is performed, and the single-channel audio data is forwarded to the direct memory access core 322.

[0133] The preset built-in audio bus format can be a data format for realizing audio data transmission based on an integrated circuit built-in audio bus, such as the digital audio data format of the I2S (Inter-IC Sound) bus, for example, an analog-to-digital conversion master clock signal adc_mclk, an analog-to-digital conversion bit clock signal adc_bclk, an analog-to-digital conversion left and right channel signal adc_lrck, and an analog-to-digital conversion target audio signal adc_data.

[0134] The preset input / output queue can be implemented based on a first in first out (FIFO) queue, and is used for implementing in-sequence execution of data based on data caching, that is, data entered first is completed and retired first, and then subsequent data is executed, so that data loss and frequent bus operations can be effectively avoided.

[0135] The preset extended function interface can be an extended multiuse input / output function interface (EMIO) based on a ZYNQ architecture, which is different from the preset multiuse function interface of the configurable multifunction pin of the processing end 301, and can serve as the multifunction pin of the logic end 302. The processing end 301 can detect the internal write data quantity (i.e., data surplus) of the preset input / output queue of the audio data write-in core 323 through the preset extended function interface.

[0136] The audio data write-in core 323 can be a self-defined bus-based intellectual property core (AXIS WR IP core), which can receive the target audio signal adc_data conforming to the preset built-in audio bus format from the audio sampling module 102 as a data interface. The audio data write-in core 323 can convert the target audio signal to generate single-channel audio data that can be transmitted based on a bus and processed by the memory 303. Specifically, the audio data write-in core 323 can first perform the above signal analysis based on the preset built-in audio bus format (such as I2S) on the target audio signal (such as the analog-to-digital conversion master clock signal adc_mclk, the analog-to-digital conversion bit clock signal adc_bclk, the analog-to-digital conversion left and right channel signal adc_lrck, and the target audio signal adc_data of analog-to-digital conversion) to convert it into corresponding 32-bit single-channel audio data, and then cache the single-channel audio data through an internal first in first out queue (FIFO), and then transmit the single-channel audio data to the memory (i.e., the RAM space of the DDR3) of the processing end 301 through the write burst transmission of the direct memory access core 322 based on the triggering of the write burst operation, to complete the write-in. Therefore, based on the control logic (i.e., AXIS_WR Control Logic) of the audio data write-in core 323, the logic end 302 detects the high level of the write burst signal such as the flag_burst signal sent by the processing end 301 based on the preset extended function interface, at which time one burst write operation can be performed, and then the single-channel audio data of the FIFO is read to the memory 303 through the bus data stream AXI Stream.

[0137] As shown in FIGS. Figure 6A and Figure 6B In the embodiment of the present application, the write burst operation based on the audio data write-in core 323 specifically includes operations S601 to S605.

[0138] In operation S601, the target audio signal in I2S format (preset built-in audio bus format) of single bit is converted into corresponding 32-bit single-channel audio data from the FPGA interface of the audio data write core 323 interfaced with the audio sampling module 102.

[0139] In operation S602, the single-channel audio data is first stored in the internal FIFO of the audio data write core 323.

[0140] In operation S603, when the internal FIFO of the audio data write core 323 has a certain threshold (i.e., a preset number threshold) of remaining amount (i.e., internal write data amount), a threshold flag signal is transmitted to the processing end 301.

[0141] In operation S604, the logic end 302 detects the write burst signal (such as flag_burst signal) sent by the processing end 301 based on the preset extended function interface. When the flag_burst signal is high, it means that a write burst operation can be performed.

[0142] In operation S605, when the logic end 302 receives the write burst signal from the processing end 301 as high, a write burst data transmission of the bus data stream is performed, and the single-channel audio data is sent to the specified memory address of the memory 303. The write burst data transmission based on the bus data stream is a transmission of a stack of data, such as a transmission of 256 32-bit single-channel audio data at a time based on the bus AXI protocol.

[0143] It should be noted that in the above write burst operation process, assuming that the write burst pointer is rx_buffer_ptr, after a write burst is performed, the corresponding sending pointer is updated according to the delay time parameter of each channel of the multi-channel sound field data corresponding to the output channel of the analog-to-digital conversion of the audio output module 105. For example, for 2 channels, the delay time is delay_t2, and the corresponding sending pointer tx2_buffer_ptr = rx_buffer_ptr-delay_t2*4 is updated. Here, *4 is because the audio data is 32 bits, corresponding to 4 byte address spaces.

[0144] In addition, since the audio data write core 323 module can be implemented by the resources (such as FPGA platform resources) of the logic end, it has a time control accuracy of 20 ns for I2S signal format audio data, and the timing control ability is obviously stronger than that of the ARM platform or the DSP platform, so it can well guarantee the real-time performance of the system to the data processing.

[0145] As shown in FIG. 4, according to an embodiment of the present application, the logic end 302 further includes an audio data readout core 324. Figures 1-8B ​

[0146] The audio data readout core 324 is configured to output the multi-channel audio data received by the DMA core 322 during a read burst operation, which includes:

[0147] The receiving processing end 301 sends the burst data (i.e., multi-channel audio data) to the bus interconnection unit 321 and the DMA core 322 through the logic end 302;

[0148] In response to the internal margin of the preset input / output queue being all non-empty, the multi-channel audio data is read from each preset input / output queue (FIFO);

[0149] For each preset input / output queue (FIFO) of the multi-channel audio data read, the multi-channel audio data is converted into a preset built-in audio bus format multi-channel audio signal and output.

[0150] The audio data readout core 324 can be a custom bus-based intellectual property core (AXIS RD IP core), which can receive multi-channel audio data forwarded from the DMA core 322 as a data interface. The audio data readout core 324 can perform conversion on the multi-channel audio data, convert the multi-channel audio signal of the preset built-in audio bus format (I2S format) according to different channels, so that the audio output module 105 can output according to the multi-channel audio signal, which can include 16-channel audio signals of I2S format audio signal dac_data1, I2S format audio signal dac_data2, …, I2S format audio signal dac_data16, digital-to-analog conversion master clock signal dac_mclk, digital-to-analog conversion bit clock signal dac_bclk, and digital-to-analog conversion left and right channel clock signal dac_lrck.

[0151] As mentioned above, after the write burst operation of the single-channel audio data is completed, it can be detected that the data has been written into the memory 303. The pointer in the memory 303 can be updated to point to a 16-channel delay. The write data is scaled based on the sound field parameters of the multi-channel sound field data, for example, for 256 single-channel audio data, each data is scaled, for example, multiplied by 0.888, and the directivity algorithm, amplitude weighting and audio data synthesis calculation are performed to complete the scaling process.

[0152] After the sending pointer tx2_buffer_ptr is updated, the read burst can be performed. During the read burst operation, the processing end 301 can send the data of the space pointed by the sending pointer tx2_buffer_ptr to the custom audio data readout core 324 (AXIS_RD IP core) of the logic end 302 through the direct memory access core 322 (AXI DMA), and after the data is buffered in the FIFO in the audio data readout core 324, the data is converted into an I2S format audio signal. The I2S format audio signal can be output to an external digital-to-analog conversion audio output module 105. In this way, the delay delay_t2 time output based on the 2-channel audio data can be realized. The other digital-to-analog conversion output channels are similar. By means of the output of the audio signals by the audio output module 105, the deflection effect shown in FIG. 6 is realized. Figure 2A

[0153] As shown in FIG. 6 and FIG. 7, in the embodiment of the present application, the read burst operation based on the audio data readout core 324 specifically includes operations S701 to S705. Figure 7A Figure 7B In operation S701, whenever the processing end 301 receives a direct memory access (AXI DMA) interrupt from the logic end 302, the processing end 301 can store the received single-channel audio data in the storage space of the memory 303 corresponding to the write pointer.

[0154] In operation S702, the 16 read pointers can be determined according to the delay parameters of each channel. The processing end 301 can perform amplitude scaling operation on the single-channel audio data in the memory 303 of each channel to be output according to the amplitude scaling ratio of each output channel configured by the multi-channel sound field data.

[0155] In operation S703, the processing end 301 can control the direct memory access core 322 to perform 16 (corresponding to 16 channels) read bursts to transfer the data of each channel of the memory 303 to the corresponding 16 FIFOs.

[0156] In operation S704, when the 16 FIFOs are all non-empty, the FIFO data of each channel can be read, thereby realizing the aligned output of the data of each channel.

[0157] In operation S705, the 32-bit audio data output by each channel corresponding FIFO is converted into a multi-channel audio signal in I2S format, and is output through a multi-path digital-to-analog conversion channel.

[0158] In operation S705, the 32-bit audio data output by each channel corresponding FIFO is converted into a multi-channel audio signal in I2S format, and is output through a multi-path digital-to-analog conversion channel.

[0159] ​​The control logic (AXIS_RD Control Logic) of the custom IP core of the audio data readout core 324 can be described as follows: After a successful handshake based on the AXI Stream bus data stream, writing begins sequentially to the 16 channel FIFOs, from 1 to 16. The 16th channel is always the last to be filled. Therefore, the timing of reading all 16 FIFOs simultaneously can be determined by detecting the prog16_full and empty16 signals of the last channel. This simultaneous reading is possible because the read signals for all 16 FIFOs are the same, allowing them to be driven together, thus achieving aligned output of multi-channel audio data.

[0160] Specifically, the custom IP core function of the audio data readout core 324 may include the following operations S5 to S7.

[0161] In operation S5, wait for the successful handshake of the bus AXI signal, and perform 16 burst transmissions, transmitting sequentially from FIFO1 to FIFO16.

[0162] In operation S6, when the number of data written inside FIFO16 reaches the threshold and a read request signal of I2S format audio signal is received, 16 FIFO read signals are started simultaneously.

[0163] In operation S7, the 32-bit data output from the FIFO corresponding to each channel is converted into an I2S format audio signal and output through multiple DAC channels.

[0164] The audio data readout core 324 and the audio data write core 323 are similar and can both be implemented using FPGA resources in the logic terminal 302, which can better ensure the real-time performance of the system's data processing.

[0165] like Figures 1-8B As shown, according to an embodiment of the present invention, the speaker array sound field directivity controllable system based on ZYNQ7000 further includes an audio output module 105.

[0166] The audio output module 105 is used to output multi-channel digital-to-analog conversion signals.

[0167] In order to realize the high restoration of the sound source signal and the output of the multi-channel digital-analog conversion signal (i.e. the multi-channel audio signal), the audio output module 105 can be implemented by using the PCM1690 chip, which has the true four-channel audio data output capability, and the highest audio sampling rate can reach 192Khz, and can realize the 32-bit I2S timing audio resolution. Therefore, the audio output module 105 can be a digital-analog converter (Digital-to-Analog Converter, referred to as DAC) module of the audio signal. Through the audio signal output of the audio output module 105, the beam deflection as shown in Figure 2A can be realized, and finally the directivity output of the loudspeaker array sound field can be realized, which can ensure the directional playing and sound field uniformity of the sound field.

[0168] As shown in Figures 1-8B , according to an embodiment of the present application, during the write burst operation, the second processing core of the processing end is used to send a write instruction for the write of the single-channel audio data transmitted by the logic end, and update the receiving pointer, including:

[0169] When the internal write data quantity of the audio data write core 323 reaches the preset quantity threshold, a write burst signal is sent to the audio data write core 323 through the preset expansion function interface, and write burst counting is performed;

[0170] When the write burst counting reaches the preset value, the multi-path read burst address of the single-channel audio data is updated.

[0171] For the write process of the single-channel audio data, the sound field parameter data (i.e. multi-channel sound field data) from the data interaction module 104 is received by the core processing module 103 based on the ZYNQ7000 core board card, and the core algorithm is realized by the second processing core 314 (Cortex-A9_0) and the first processing core 312 (Cortex-A9_1) of the processing end 301. For details, please refer to Figure 8A and Figure 8B .

[0172] The Ethernet physical layer 311 (PHY) as a gigabit Ethernet interface can be used to connect the PC end as the data interaction module 104 and the ZYNQ7000 core board card as the core processing module 103, to realize the delay and amplitude parameters of the 16-way output channel (16-way DAC channel) compared with the 1-way input channel (1-way ADC channel) sound field parameters from the network port communication assistant of the PC end to the processing end 301.

[0173] The first processing core 312 can be used to receive the multi-channel sound field data including configuration amplitude and delay parameters from the data interaction module 104 through the network port of the Ethernet physical layer 311. The first processing core 312 on the processing side 301 internally runs a FreeRTOS operating system based on LWIP, wherein the format of the configuration data is “chx weight xdelay_20us”, for example, “ch50.856100” means that the amplitude of the audio signal of channel 5 is multiplied by 0.856, which can make the audio data of channel 5 be output with a delay of 2 ms.

[0174] After the first processing core 312 receives the above multi-channel sound field data, the data is stored in the shared memory (On Chip Memory, referred to as OCM), and then a software interrupt is sent to the second processing core 314 to inform the second processing core 314 to update the delay parameters and weight parameters of each channel.

[0175] As shown in FIGS. 8, 9 and 10, the second processing core 314 implements single-channel audio data writing and multi-channel audio data weighting and output, and the specific implementation includes operations S801 to S811. Figure 8A Figure 8B As shown in FIGS. 8, 9 and 10, the second processing core 314 implements single-channel audio data writing and multi-channel audio data weighting and output, and the specific implementation includes operations S801 to S811.

[0176] In operation S801, the receive pointer rx_buffer_ptr=(int32_t*)RX_BUFFER_BASE is initialized.

[0177] In operation S802, it is detected each time whether the FIFO of the audio data writing core 323 from the logic side 302 reaches a certain capacity, for example, prog_empty is 0.

[0178] In operation S803, an AXI-Stream write burst of bus data stream is started.

[0179] In operation S804, when the write burst operation is completed, the write burst count cnt_trans=cnt_trans+1.

[0180] In operation S805, it is judged whether the write burst count cnt_trans is equal to 201; wherein the write burst count threshold 201 is a preset value set in advance according to actual running conditions or processing scenarios.

[0181] In operation S806, if the write burst count cnt_trans is equal to 201, the write burst count cnt_trans=1 is updated, the 16-way read burst address is updated, and the data of the read burst address is scaled.

[0182] ​In operation S807, the last received address content is copied to the receiving base address, and the receiving pointer is updated = (int32_t) RX_BUFFER_BASE + 256.

[0183] In operation S808, a 16-way bus data stream AXI Stream read burst is started, and operation S802 is returned.

[0184] In operation S809, if the write burst count cnt_trans is not equal to 201, the 16-way read burst address is updated, and the data of the read burst address is scaled.

[0185] In operation S810, the receiving pointer rx_buffer_ptr is updated += 256.

[0186] In operation S811, a 16-way bus data stream AXI Stream read burst is started, and operation S802 is returned.

[0187] The second processing core 314 can process the updated delay parameter and weight parameter of each channel and the single-channel audio data written in operations S801 to S811 under the cooperation of the first processing core 312. Since the flow content of updating the delay parameter and weight parameter of each channel is very small, after the first processing core 312 receives the multi-channel sound field data, the multi-channel sound field data is stored in the shared area (i.e., shared memory, On Chip Memory, abbreviated as OCM) of the memory 303 and an interrupt is sent to the second processing core 314. The second processing core 314 can update the data of the shared area to the variable of the global variable area data of the memory 303 through the interrupt processing function corresponding to the interrupt, that is, the delay parameter and weight parameter of each channel are updated.

[0188] In the embodiment of the application, the processing of the processing end 301 is as shown in Figure 8A and Figure 8B The logic of the write burst operation of the single-channel audio data is relatively complex. If only the traditional FPGA is used to realize this part of the function, the development difficulty and period will be sharply increased. Therefore, the content shown in Figure 8B is realized based on the ARM architecture of the processing end 301, which can be used in the part with low real-time requirement, so that the development efficiency can be greatly improved. Benefited from the hard core bus AXI between the processing end 301 and the logic end 302, the communication rate and the reliability of the data can be guaranteed, which is a more suitable application scheme for the audio data processing of the loudspeaker array sound field directivity system.

[0189] Further, as shown in Figure 9The above-mentioned loudspeaker array sound field directivity controllable system based on ZYNQ7000 proposed by the embodiment of the application can realize higher precision control of the sound field and ensure more effective beam deflection and sidelobe suppression through the contrast experiment of the final uniform weighting (no delay), beam deflection and Chebyshev sidelobe suppression.

[0190] In order to realize multi-channel delay and amplitude accurate control of the audio signal and facilitate debugging, the core processing module 103 of the embodiment of the application takes the core board module of the Xilinx ZYNQ7000 series chip as a master, and simultaneously integrates the on-board FT2232 chip, the externally hung memory DDR3, the QSPIFLASH, the SD card switching chip, the Ethernet physical layer of the gigabit Ethernet, the JTAG, the UART, the audio sampling module of the externally preset audio ADC module, the audio output module of the DAC module interface and the like, so that the loudspeaker sound field directivity system audio data calculation and output application can be realized, and the data interaction module of the PC end can also be used to realize man-machine interaction through the network port.

[0191] In order to facilitate downloading and debugging, the core chip of the core processing module 103 of the loudspeaker array sound field directivity controllable system based on ZYNQ7000 can be FT2232, the operation of JTAG+UART can be completed by using the chip, the USB port uses TYPE-C, contains ESD+common mode filter and an ideal diode for preventing current backflow, so that one TYPE-C line can be used to realize debugging, power supply and burning, facilitating the development and debugging of users.

[0192] As shown in Figure 5 In the embodiment of the application, the loudspeaker array sound field directivity controllable system based on ZYNQ7000 can also provide a data verification module 106 corresponding to the audio output module 105, which is applied to data verification of the loudspeaker array sound field directivity system, and according to the audio signal output by the audio output module 105 received by the data verification module 106, the feasibility of the loudspeaker array sound field directivity controllable system based on ZYNQ7000 can be verified.

[0193] Wherein, the data verification is carried out in a listening room, the size of the mid-low frequency loudspeaker array is 0.405 m, the critical distance of the near field and far field is 0.956 m when the frequency is 1000 Hz, four mid-frequency loudspeakers are used, each observation point is 1.5 meters away from the center of the array, and the room size of the listening room is 9.4*6.5*3.2 m. In the listening room, the front panel center of the array loudspeaker is placed at the point as the array center, and the point is set as the center O. With the center as the center, an xOy plane is constructed on the vertical plane, a circular arc with a radius of r=1.5 m is drawn, the normal line of the loudspeaker array is taken as 0°, and each 5° is marked. The test range of 90° is drawn clockwise and counterclockwise. A multichannel signal source is used to synchronously input a delay signal to each array element of the measured loudspeaker linear array group, a sound level meter is used for measurement, a Z weighting method is used, the sound pressure level of the observation point is measured every 5°, and the experimental data is recorded. According to the limitation of the experimental site, the measurement angle range is-15°-60°, and the measurement results are shown in Tables 1 and 2 as follows:

[0194]

[0195] Table 1: Pressure level measurement results in the angle range of-15°-20°

[0196]

[0197] Table 2: Pressure level measurement results in the angle range of 25°-60°

[0198] The data in Tables 1 and 2 are analyzed by Matlab software, and the directivity diagram of each group of experiments can be drawn as shown in Figure 9 Comparison diagram of simulation results and measured results of the four-array mid-frequency loudspeaker unit

[0199] As shown in Figure 9 , there is a main lobe and a side lobe in the most left sound field basic directivity diagram, which is similar to the simulation results. Since the experimental environment is not anechoic, and there is basic noise, the reflected sound from the ceiling, the reflected sound from the surrounding objects such as the desktop, and the sound absorption of the human body and other factors will affect the accuracy of the experimental results. The measured results show that the approximate sound field directivity is consistent with the simulation results. According to the comparison experiments of uniform weighting (no delay), beam deflection and Chebyshev side lobe suppression, it is concluded that the architecture design of the loudspeaker array sound field directivity controllable system based on ZYNQ7000 can improve the high-precision control of the sound field, realize the deflection of the beam and the suppression of the side lobe.

[0200] As shown in Figure 9 , the comparison and analysis of the experimental results show that the main beam is deflected correspondingly, and the shape is basically consistent with the simulation results. After the Chebyshev weighting, the side lobe suppression of the audio signal can be realized.

[0201] Therefore, the ZYNQ7000-based loudspeaker array sound field directivity controllable system of the above-mentioned application of the loudspeaker array sound field directivity controllable system of the embodiment of the application based on the ZYNQ7000 architecture (ARM+FPGA) has the research and development of the system hardware and the development of the corresponding software system, and through the comparative experiments of the uniform weighting, the beam deflection and the Chebyshev sidelobe suppression, it can be seen that since the sampling frequency is 50KHz and the decimal part is 22 bits in the fixed floating point conversion process, the system can realize the delay precision of 20us and the control precision of greater than 2.384x10 -7 The actual measurement results show that the sound field directivity experiment is basically consistent with the simulation results, and the deflection of the beam and the suppression of the sidelobe can be effectively realized.

[0202] In summary, compared with the existing control scheme for realizing the loudspeaker array sound field directivity, the ZYNQ7000-based loudspeaker array sound field directivity controllable system of the embodiment of the application can at least achieve one of the following beneficial effects:

[0203] (1) The processing end and the logic end interconnected by the internal bus based on the ZYNQ architecture are integrated in the same chip, and direct communication is realized through the hard core bus AXI, without external physical pins, the data transmission path is short, and the data transmission delay is extremely low (nanosecond level).

[0204] (2) The bandwidth of the AXI bus can be more than 10 times that of the FSMC / FMC, and can meet the data processing of a large data amount scene (such as video processing, high-speed data acquisition).

[0205] (3) For the development of the ZYNQ system architecture, the AXI IP core generator (such as AXIDMA, AXI FIFO) can be provided, so that the interface logic can be automatically generated, greatly simplifying the software development. In addition, the AXI can greatly reduce the development difficulty and shorten the project cycle through the automatic tool chain.

[0206] (4) The AXI interface is realized by the hard core, and the logic resources of the logic end are less occupied, and the on-chip communication power consumption is significantly lower than that of the external bus (without driving the PCB wiring). The AXI based on the ZYNQ architecture in the embodiment of the application is obviously more excellent in resource efficiency and power consumption.

[0207] (5) The above-mentioned ZYNQ7000-based loudspeaker array sound field directivity controllable system of the embodiment of the application can facilitate the implementation of the loudspeaker array sound field directivity intelligent algorithm.

[0208] Therefore, compared with a traditional scheme based on an STM32 (ARM) and a DSP platform, the speaker array sound field directivity controllable system based on the ZYNQ7000 has stronger timing control capability and stability. In addition, compared with a traditional scheme based on only an FPGA platform, the speaker array sound field directivity controllable system based on the ZYNQ7000 can significantly reduce development difficulty and a development cycle because the logic end part of the speaker array sound field directivity controllable system based on the ZYNQ7000 can realize cooperative data processing with the processing end. Further, compared with a traditional solution based on two chips of an FPGA and an ARM, the speaker array sound field directivity controllable system based on the ZYNQ7000 can have a smaller size only by using a single chip based on the ZYNQ, and can have higher stability and more faithful signals than a traditional scheme of external wiring of two chips by means of bus data interaction between the internal processing end and the logic end.

[0209] In summary, the speaker array sound field directivity controllable system based on the ZYNQ7000 can be effectively applied to a speaker array sound field directivity controllable system, has great scientific value and theoretical guiding significance for research on a sound field directivity control system of an online array loudspeaker, can meet application in application scenarios or fields including a theater, a stadium, a vehicle-mounted sound system, and the like, has wide commercial application value, and can realize better industrial application.

[0210] Based on the speaker array sound field directivity controllable system based on the ZYNQ7000, the application further provides a control method of the speaker array sound field directivity controllable system based on the ZYNQ7000. The following will be described in detail in combination with Figure 10 the method.

[0211] As Figure 10 shown, one aspect of an embodiment of the application provides a control method of a speaker array sound field directivity controllable system based on a ZYNQ7000, for realizing speaker array sound field directivity control, where the method includes operations S1101 to S1102.

[0212] In operation S1101, the processing end is controlled to perform a write operation on single-channel audio data corresponding to a target audio signal transmitted by the logic end according to a write burst trigger of the logic end;

[0213] In operation S1102, in response to a trigger of a read burst operation, the logic end is controlled to output received multi-channel audio data of the processing end, and the multi-channel audio data is determined by single-channel audio data and multi-channel sound field data corresponding to a sound field of a loudspeaker array.

[0214] For the specific operation process and beneficial effects of the control method of the ZYNQ7000-based speaker array sound field directivity controllable system of the above embodiments of the application, reference can be made to the implementation of the ZYNQ7000-based speaker array sound field directivity controllable system of the above embodiments of the application, which will not be repeated here.

[0215] The flowcharts and block diagrams in the drawings illustrate the possible implementation architecture, function and operation of the systems, methods and computer program products according to various embodiments of the application. In this regard, each block in the flowcharts or block diagrams can represent a module, a program segment, or a portion of code that contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions noted in the blocks can occur in different orders than those noted in the drawings. For example, two blocks that are shown in succession can actually be executed substantially concurrently, or they can be executed in reverse order, depending on the functionality involved. It should also be noted that each block in the block diagrams or flowcharts, and combinations of blocks in the block diagrams or flowcharts, can be implemented by a dedicated hardware-based system that performs specified functions or operations, or can be implemented by a combination of special-purpose hardware and computer instructions.

[0216] In addition, all actions of obtaining information, signals or data in the present application are carried out in accordance with the corresponding data protection laws and regulations of the country where the data is located, and with the authorization of the owner of the corresponding device.

[0217] Those skilled in the art can understand that the features described in various embodiments and / or claims of the present application can be combined or / and integrated, even if such combinations or integrations are not explicitly described in the present application. In particular, the features described in various embodiments and / or claims of the present application can be combined and / or integrated in various combinations, without departing from the spirit and teachings of the present application. All such combinations and / or integrations fall within the scope of the present application.

[0218] The embodiments of the application are described above. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the application. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present application is defined by the appended claims and their equivalents. Without departing from the scope of the present application, those skilled in the art can make various substitutions and modifications, which should all fall within the scope of the present application.

Claims

1. A loudspeaker array sound field directivity controllable system based on ZYNQ7000, characterized in that, include: The sound field data module is used to acquire multi-channel sound field data for the sound field of the speaker array. Audio sampling module, used to acquire target audio signals; The core processing module, based on the ZYNQ7000 chip as the main controller, is used to receive the multi-channel sound field data from the sound field data module and the target audio signal from the audio sampling module, and to perform logical operations internally. The core processing module includes a processing end and a logic end. The processing end is implemented based on a high-level reduced instruction set microprocessor and is used to write the single-channel audio data corresponding to the target audio signal transmitted by the logic end, update a receive pointer and multiple send pointers, perform scaling operations on the data in the address space pointed to by each send pointer, and send a read burst instruction to send the data in the memory space of the memory to the logic end for processing. The logic terminal is implemented based on a field-programmable gate array (FPGA) and is used to trigger a write burst operation to write the received audio data into the memory. In response to the trigger of a read burst operation, it outputs the multi-channel audio data received from the processing terminal. The multi-channel audio data is determined by the single-channel audio data and the multi-channel sound field data.

2. The loudspeaker array sound field directivity controllable system according to claim 1, characterized in that, Also includes: The data interaction module is used to receive multi-channel sound field data from the sound field data module through a preset interaction interface and forward it to the core processing module, wherein the multi-channel sound field data includes the delay parameters and corresponding amplitude weights of the sound field of the speaker array.

3. The loudspeaker array sound field directivity controllable system according to claim 2, characterized in that, The processing terminal includes: The Ethernet physical layer is used to receive the multi-channel sound field data forwarded by the data interaction module through the preset multiplexing function interface of the core processing module, and to forward it. The first processing core is used to receive the multi-channel acoustic field data forwarded by the Ethernet physical layer.

4. The loudspeaker array sound field directivity controllable system according to claim 1, characterized in that, The core processing module also includes: The memory is used to write the single-channel audio data and / or multi-channel sound field data in a preset spatial data form according to the target data space of the write burst operation of the processing terminal, and on this basis, to perform scale transformation on the single-channel audio data and the multi-channel sound field data to generate multi-channel audio data, and then to read out the multi-channel audio data according to the control of the read burst operation of the processing terminal.

5. The loudspeaker array sound field directivity controllable system according to claim 4, characterized in that, The processing terminal also includes: The second processing core, during the write burst operation, is used to send a write instruction for the single-channel audio data transmitted by the logic terminal and update the receive pointer; and during the read burst operation, the second processing core is used to update the send pointer and perform a scaling operation on the address space data pointed to by the send pointer, and send a read instruction for the output of the multi-channel audio data. The second processing core is also used to receive and forward the multi-channel sound field data sent by the first processing core of the processing terminal, thereby realizing the write operation of the multi-channel sound field data to the memory.

6. The loudspeaker array sound field directivity controllable system according to claim 5, characterized in that, The logical terminal includes: The bus interconnect unit is used to forward single-channel audio data from the audio sampling module to the second processing core of the processing terminal during the write burst operation; and to receive multi-channel audio data forwarded by the second processing core during the read burst operation. A direct memory access core is used to forward single-channel audio data to the bus interconnect unit during the write burst operation and to receive multi-channel audio data forwarded by the bus interconnect unit during the read burst operation.

7. The loudspeaker array sound field directivity controllable system according to claim 6, characterized in that, The logic terminal also includes: An audio data writing core is used, during the write burst operation, to convert the target audio signal of the received audio sampling module in a preset built-in audio bus format into single-channel audio data and write it to the direct memory access core, including: When the number of data written inside the preset input / output queue reaches a preset threshold, the receiving processing end sends a write burst signal through the preset extended function interface. Based on the write burst signal, a burst data transmission of a preset bus stream is performed, and the single-channel audio data is forwarded to the direct memory access core.

8. The loudspeaker array sound field directivity controllable system according to claim 6, characterized in that, The logic terminal also includes: An audio data readout core is used to output multi-channel audio data received by the direct memory access core during the read burst operation, including: The receiving and processing end transmits multi-channel audio data through the bus interconnect unit and direct memory access core of the logic end; When all the internal reserves of the preset input / output queues are not empty, multi-channel audio data reading begins for each preset input / output queue; For each channel of multi-channel audio data read from the preset input / output queue, convert it into a multi-channel audio signal in the preset built-in audio bus format for output.

9. The loudspeaker array sound field directivity controllable system according to claim 8, characterized in that, Also includes: The audio output module is used to output the multi-channel audio signal through multiple digital-to-analog conversion channels.

10. The loudspeaker array sound field directivity controllable system according to claim 7, characterized in that, During the write burst operation, the second processing core of the processing terminal is used to send a write command for the single-channel audio data transmitted by the logic terminal and update the receive pointer, including: When the number of internal written data in the audio data writing core reaches a preset threshold, a write burst signal is sent to the audio data writing core through a preset extended function interface to perform a write burst and count the write bursts. When the write burst count reaches the pre-designed value, the multi-channel read burst address of the single-channel audio data is updated.

11. A control method for a loudspeaker array sound field directivity controllable system based on ZYNQ7000, characterized in that, include: The control processing terminal performs a write operation on the single-channel audio data corresponding to the target audio signal transmitted by the logic terminal based on the write burst trigger of the logic terminal. In response to the triggering of a read burst operation, the control logic terminal outputs the multi-channel audio data received from the processing terminal. The multi-channel audio data is determined by the single-channel audio data and the multi-channel sound field data corresponding to the sound field of the speaker array.

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