NAND type flash memory and manufacturing method thereof

Abstract

The invention provides an NAND type flash memory capable of reducing capacitive coupling between adjacent memory cells and a manufacturing method thereof. The NAND type flash memory comprises an active region and a gate region, wherein the active region is formed in a silicon substrate in a way of extending along a bit line direction; a trench isolation region for defining an active region; a charge storage layer formed on the active region corresponding to each memory cell and having a SiN layer sandwiched by an insulating layer stacked thereon; a first control gate formed on the charge accumulation layer corresponding to each memory cell; and the second control grid electrode extends along the word line direction and is formed on the first control grid electrode. The second control gates are electrically connected to the plurality of first control gates in the corresponding row direction, and the trench isolation regions are aligned with the first control gates and sidewalls of the charge accumulation layer.

Description

Technical Field

[0001] This invention relates to a non-volatile semiconductor memory device, and more particularly to a two-dimensional (2D) NAND flash memory and its manufacturing method. Background Technology

[0002] The cell structure of NAND flash memory employs a floating gate structure. The floating gate, for example, contains polysilicon and exhibits excellent charge retention characteristics. Furthermore, a highly reliable NAND flash memory that suppresses the effects of floating gate coupling between memory cells has also been disclosed (e.g., Japanese Patent Application Publication No. 2017-097927).

[0003] In existing FG-type two-dimensional NAND flash memory, due to size reduction, the coupling effect of parasitic capacitance between floating gates of adjacent memory cells or between floating gates and control gates increases. For example, the charge of the floating gate of an adjacent memory cell can sometimes cause changes in the threshold (Vth) of the programmed memory cell. As a result, there are problems such as a larger threshold distribution of memory cells and reduced reliability of NAND flash memory.

[0004] The purpose of this invention is to solve this existing problem and provide a NAND flash memory and a method for manufacturing the same, which can reduce capacitive coupling between adjacent memory cells. Summary of the Invention

[0005] The NAND flash memory of the present invention includes: an active region formed extending along a bit line direction within a semiconductor substrate; a trench isolation region defining the active region; a charge storage layer formed on the active region for each memory cell and comprising a nitride layer sandwiched between insulating layers; a first conductive layer formed on the charge storage layer for each memory cell; and a second conductive layer formed on the first conductive layer extending along a word line direction, the second conductive layer being electrically connected to a plurality of first conductive layers in a corresponding row direction, the trench isolation region being aligned with the sidewalls of the first conductive layer and the charge storage layer.

[0006] In one embodiment, the charge storage layer comprises an oxide-nitride-oxide (ONO) structure, or a stacked structure comprising multiple insulating films other than oxides between the silicon substrate and the nitride layer, or a stacked structure comprising multiple insulating films other than oxides between the nitride and the first conductive layer. In one embodiment, the first conductive layer comprises a polysilicon layer, the semiconductor substrate comprises a silicon region, and the charge storage layer comprises a silicon-oxide-nitride-oxide-silicon (SONOS) structure. In one embodiment, the trench isolation region is formed in a self-aligned manner during etching of the first conductive layer, the charge storage layer, and the semiconductor substrate. In one embodiment, the peripheral region of the NAND flash memory includes a gate insulating film and a gate material separate from the charge storage layer and the first conductive layer.

[0007] The method for manufacturing a NAND flash memory of the present invention includes: forming a stack of a charge accumulation layer comprising a nitride layer sandwiched between an insulating layer and a first conductive layer on a semiconductor substrate; simultaneously etching the first conductive layer, the charge accumulation layer and the semiconductor substrate, patterning the first conductive layer and the charge accumulation layer along the bit line direction, and forming a trench defining an active region on the semiconductor substrate; filling the trench with an insulating material; conformally forming a second conductive layer on the semiconductor substrate comprising the first conductive layer; simultaneously etching the second conductive layer, the first conductive layer and the charge accumulation layer, and patterning the second conductive layer, the first conductive layer and the charge accumulation layer along the word line direction; and forming a source / drain impurity region in the active region after removing the second conductive layer, the first conductive layer and the charge accumulation layer.

[0008] In one embodiment, the manufacturing method further includes: forming a mask pattern covering the cell array region; removing the charge accumulation layer and the first conductive layer on the peripheral region; and forming the gate insulating film and the gate material on the peripheral region, which are separate from the charge accumulation layer and the first conductive layer. In one embodiment, the manufacturing method further includes: conformally forming the gate insulating film and the gate material on a semiconductor substrate; and planarizing the gate insulating film and the gate material until the first conductive layer on the cell array region is exposed.

[0009] According to the present invention, a charge accumulation layer comprising a nitride layer is formed for each memory cell. Therefore, compared with FG-type memory cells, the capacitive coupling between adjacent memory cells can be reduced, and the threshold distribution of the memory cells can be narrowed. In addition, by aligning the trench isolation region used to define the active region with the charge accumulation layer and the first conductive layer, the capacitive coupling between adjacent memory cells can be reduced while achieving high integration of the cell array. Attached Figure Description

[0010] Figure 1 This is a schematic diagram of a cross-section of the cell array region of an existing two-dimensional NAND flash memory in a direction orthogonal to the bit lines.

[0011] Figure 2A , Figure 2B This is a diagram of a two-dimensional NAND flash memory according to an embodiment of the present invention, and Figure 2A It is a plan view of part of the cell array. Figure 2B yes Figure 2A A schematic diagram of the AA line cross section;

[0012] Figures 3A-3C This is a schematic diagram of the manufacturing process of the cell array region of the NAND flash memory according to an embodiment of the present invention;

[0013] Figures 4A to 4D This is a schematic diagram of the manufacturing process of the cell array region of the NAND flash memory according to an embodiment of the present invention;

[0014] Figure 5A This is a plan view of the substrate during the etching of the first control gate, charge storage layer, and substrate using a mask pattern. Figure 5B It is a plan view of the substrate when the height of the first control gate and the trench insulator are the same.

[0015] Figures 6A to 6D This is a schematic diagram illustrating the manufacturing process of the cell array region and peripheral region of the NAND flash memory in this embodiment;

[0016] Figure 6E , Figure 6F This is a schematic diagram illustrating another manufacturing process of the cell array region and peripheral region of the NAND flash memory in this embodiment;

[0017] Figures 7A to 7C This is a schematic diagram illustrating the manufacturing process of the cell array region and peripheral region of the NAND flash memory in this embodiment;

[0018] Figure 8 This is a schematic cross-sectional view of the cell array region of the NAND flash memory in this embodiment, showing the direction of the bit lines.

[0019] [Explanation of Symbols]

[0020] 10: Existing NAND flash memory

[0021] 20: Silicon substrate (P-type semiconductor substrate or P-type well)

[0022] 30, 202: Active area

[0023] 40: Trench isolation zone (trench)

[0024] 50: Gate oxide film (tunneling oxide film)

[0025] 60: Floating gate

[0026] 70: Control gate

[0027] 100: NAND flash memory

[0028] 110: Charge accumulation layer

[0029] 120, 220, 320, 450, CG1: First control gate

[0030] 130, 370A, 460, CG2: Second control gate

[0031] 200: Substrate (P-type silicon substrate or P-type well)

[0032] 210, 310, 440: Charge accumulation layer

[0033] 230: Mask material

[0034] 240, 350, 352: slots

[0035] 250: Interlayer insulating film (insulating film)

[0036] 250A: Slot insulator

[0037] 260: Gate insulating film

[0038] 270: Gate material

[0039] 300: Substrate (P-type silicon substrate)

[0040] 330: Gate insulating film

[0041] 340: Gate material

[0042] 360: Insulation Materials

[0043] 370: Conductive materials

[0044] 370B: Wiring layer

[0045] 400: P-type silicon substrate

[0046] 410: N-well

[0047] 420: P-trap

[0048] 430: N-type diffusion region

[0049] 430A: Diffusion region of bit-line side select transistor

[0050] 430B: Diffuse region of the source-line selected transistor

[0051] BL: Bitline

[0052] CT1, CT2: Contact elements

[0053] M1, M2, M3: Mask patterns

[0054] SL: Source Line Detailed Implementation

[0055] The two-dimensional NAND flash memory of the present invention uses silicon nitride (SiN) as a charge storage layer. For example, a SONOS-type (Si / oxide / nitride / oxide / Si) charge storage layer is used to achieve narrowing of the threshold distribution (Vth) of the memory cells. Furthermore, the NAND flash memory of the present invention is used as a storage medium in various semiconductor devices (e.g., microcontrollers, microprocessors, logic, etc., in which such flash memory is embedded).

[0056] Figure 1 This is a diagram showing a cross-section of the cell array of an existing two-dimensional NAND flash memory in the direction of intersection with the NAND string, i.e., the word line direction. For example... Figure 1 As shown, the existing NAND flash memory 10 forms active regions 30 extending along the bit line direction on a P-type semiconductor substrate or a P-type well 20, wherein each active region 30 is isolated by a trench 40.

[0057] The active region 30 provides a channel region or an N-type source / drain (S / D) diffusion region for the memory cell. A patterned floating gate 60 corresponding to each memory cell is formed on the active region 30, separated by a gate oxide film (or tunnel oxide film) 50. A control gate 70 extending along the word line direction is formed on the floating gate 60. The floating gate 60 may contain, for example, conductive polysilicon doped with impurities, and the control gate 70 may contain, for example, conductive polysilicon and a metal material such as tungsten. The floating gate 60 is capacitively coupled to the control gate 70 via an upper dielectric layer.

[0058] When the memory cell is programmed, the charge tunneling from the channel region of the active region 30 through the gate oxide film 50 is stored in the floating gate 60. When the memory cell is erased, the charge stored in the floating gate 60 tunnels through the gate oxide film 50 and is released to the channel region.

[0059] As the process shrinks, the distance between the floating gates 60 of adjacent memory cells becomes smaller, and the capacitive coupling between adjacent floating gates 60 becomes larger. For example, the charge accumulated in the floating gates 60 of the programmed memory cells can affect the threshold of adjacent memory cells.

[0060] Figure 2A , Figure 2B This is a diagram of a two-dimensional NAND flash memory according to an embodiment of the present invention.

[0061] In the NAND flash memory 100 of this embodiment, a charge storage layer 110, consisting of multiple insulating layers sandwiching a SiN layer, is formed on the active region 30 instead of a floating gate 60. Patterned charge storage layers are formed correspondingly on the active region 30 of each memory cell. The charge storage layer 110 may have an ONO structure, such as oxide / nitride / oxide, or multiple insulating films may be stacked between the silicon substrate and the nitride layer instead of a single oxide layer. Alternatively, multiple insulating films may be stacked between the nitride and the gate instead of a single oxide layer. A first control gate (CG1) 120 is formed on the charge storage layer 110 and is patterned to correspond to the charge storage layer 110. The first control gate 120 may contain, for example, conductive polysilicon doped with impurities, or multiple low-resistance materials (e.g., TaN) and other metal layers may be stacked. A patterned second control gate (CG2) 130 extending along the word line direction (row direction) is formed on the first control gate 120. The second control gate 130 is electrically connected to the first control gate 120. Ideally, the second control gate 130 has low resistance and is made of a metallic material such as Al or Cu.

[0062] Furthermore, the first control gate 120 may contain the same or different material as the second control gate 130.

[0063] As described above, the charge accumulation layer 110 has, for example, an oxide / nitride / oxide ONO structure, and the ONO structure together forms a SONOS structure between the silicon substrate (or silicon well) and the first control gate 120 containing polysilicon. During programming, the charge accumulation layer 110 accumulates the charge obtained from Fowler-Nordheim (FN) tunneling of the oxide layer through the channel region at the interface of the nitride layer. During erasing, the charge accumulated in the charge accumulation layer 110 is released to the channel region through FN tunneling of the oxide layer.

[0064] In this embodiment, the thickness of the nitride layer (SiN layer) of the charge storage layer 110 is relatively smaller than the thickness of the floating gate of the FG structure, and the nitride layer is an insulating film. Therefore, compared with the FG structure, the capacitive coupling between adjacent memory cells can be reduced, resulting in a narrower threshold distribution of the memory cells. Furthermore, when the nitride layer of the charge storage layer 110 is formed continuously along the word line direction (without being separated for each memory cell), if electrons held in the nitride layer are attracted to holes and move, or holes are attracted to electrons and move, there are problems such as changes in the threshold of the memory cells. However, by separating the charge storage layer according to each memory cell as in this embodiment, the aforementioned problems can be eliminated.

[0065] Next, refer to Figures 3A to 5B The manufacturing process of the cell array section of the NAND flash memory in this embodiment will be described. For example... Figure 3A As shown, a charge storage layer 210 with a three-layer structure is formed on the surface of a P-type silicon substrate or a P-type well 200 (hereinafter referred to as the substrate for convenience) by a process such as chemical vapor deposition (CVD). This layer may include, for example, an oxide film such as SiO2, a nitride film such as Si3N4, and an oxide film such as SiO2. Furthermore, a first control gate 220, for example made of polysilicon, is formed on the charge storage layer 210.

[0066] Next, as Figure 3B As shown, a mask material 230 can be formed to act as a resist. Next, the mask material 230 is patterned using a photolithography process, such as... Figure 3C As shown, a mask pattern M1 is formed that extends along the bit line direction at certain intervals.

[0067] Next, as Figure 4A As shown, through the mask pattern M1, the exposed first control gate 220, charge storage layer 210 and substrate 200 are simultaneously anisotropically etched to form a patterned stack of charge storage layer 210 and first control gate 220 on substrate 200, and at the same time a trench 240 is formed in substrate 200 to define active region 202. Figure 5A This is a plan view of the substrate during the etching of the first control gate 220, charge storage layer 210, and substrate 200 using mask pattern M1. Figure 4A Corresponding to Figure 5A BB line profile.

[0068] The stack of charge storage layer 210 and first control gate 220 extends along the bit line direction, and the trench 240 is self-aligned with the sidewalls of the stack of charge storage layer 210 and first control gate 220. Therefore, the trench 240 is formed with good precision between the stack of charge storage layer 210 and first control gate 220 without positional error. In addition, since the charge storage layer 210 is covered by the first control gate 220, it is protected from etching.

[0069] Next, as Figure 4B As shown, an insulating film 250 is conformally formed on a substrate 200 including a trench 240. Subsequently, the insulating film 250 is etched to the vicinity of the surface of the substrate 200 so that the trench insulator 250A is retained within the trench 240. At this time, the mask pattern M1 protects the first control gate 220 from etching.

[0070] Next, as Figure 4C As shown, the groove insulator 250A is planarized using surface grinding, exposing the surface of the mask pattern M1. Next, as... Figure 4D As shown, the mask pattern M1 is removed, and the surface of the trench insulator 250A is ground so that the height of the trench insulator 250A is approximately the same as the height of the first control gate 220. In this way, the active region 202 extending along the bit line direction is isolated by the trench insulator 250A, and a stack of charge accumulation layer 210 and first control gate 220 is formed on the active region 202. Figure 5B This is a plan view of the substrate when the heights of the first control gate 220 and the trench insulator 250A are approximately the same. Figure 4D Corresponding to Figure 5B The CC line profile. Furthermore, in some embodiments, it may not be necessary. Figure 4D The process shown.

[0071] Next, refer to Figures 6A to 6F and Figures 7A to 7C The manufacturing process of the cell array region and peripheral region in the flash memory of this embodiment will be described. For example... Figure 6A As shown, a charge storage layer 310 and a first control gate (CG1) 320 are conformally formed on a P-type silicon substrate 300, followed by the formation of a mask pattern M2 covering the cell array region. Then, as... Figure 6B As shown, a mask pattern M2 is used as an etching mask to remove the charge accumulation layer 310 and the first control gate 320 on the peripheral region by etching.

[0072] Next, after removing the mask pattern M2, as follows: Figure 6CAs shown, a gate insulating film 330 is conformally formed on a substrate 200, including a peripheral region. The gate insulating film 330 is, for example, a silicon oxide film. Page buffers / sensor amplifiers or decoders, etc., are formed in the peripheral region. These circuits include transistors driven by high voltage or low voltage. Therefore, the gate insulating film 330 is formed in various thicknesses, such as thick films suitable for high voltage and thin films suitable for low voltage. After the gate insulating film 330 is formed, a gate material 340 for transistors in the peripheral region is conformally formed on the substrate 200. The gate material 340 is, for example, polysilicon.

[0073] Next, the gate insulating film 330 and the gate material 340 are subjected to etch-back or planarization treatment, such as... Figure 6D As shown, the first control gate 320 is exposed on the cell array region, and the gate material 340 is exposed on the peripheral region. Through these processes, the charge accumulation layer 310 and the first control gate 320 of the cell array region can be formed separately from the gate insulating film 330 and the gate material 340 of the peripheral region. It should be noted that in existing FG-type flash memory, the floating gate of the cell array region is connected to the floating gate of the peripheral region (the floating gate is electrically connected to the control gate and serves as the gate of the transistor).

[0074] In the aforementioned process, after removing the mask pattern M2, a gate insulating film 330 and a gate material 340 are formed. However, this is just one example; the mask pattern M2 can also be retained. Figure 6E As shown, a gate insulating film 330A and a gate material 340A are conformally formed on a substrate including a mask pattern M2. In this case, when the gate insulating film 330A in the peripheral region is a thick insulating film with high voltage withstand capability, the height of the mask pattern M2 in the cell array region is set to be approximately the same as the height of the gate material 340A. Furthermore, the gate insulating film 330 at the boundary between the cell array region and the peripheral region is set to a thick insulating film with high voltage withstand capability.

[0075] Then, as Figure 6F As shown, after planarization to expose the mask pattern M2 of the cell array region and the gate material 340A of the peripheral region, the mask pattern M2 is removed. Through these processes, the charge storage layer 310 and the first control gate 320 of the cell array region can be formed separately from the gate insulating film 330A and the gate material 340A of the peripheral region.

[0076] After forming the first control gate 320 of the unit array region and the gate material 340 of the peripheral region respectively, as shown in the figure Figure 7A The mask pattern M3 shown simultaneously etches the gate material, gate insulating film, and silicon of the cell array region and the peripheral region, forming trenches 350 and 352 on the substrate 300. The trenches 350 in the cell array region may have different sizes and / or different depths than the trenches 352 in the peripheral region.

[0077] After removing the mask pattern M3, as follows Figure 7B As shown, insulating material 360 is filled into trenches 350 and 352. The insulating material 360 is, for example, a silicon oxide film. Subsequently, the insulating material 360 is planarized to expose the surfaces of the first control gate 320 and the gate material 340.

[0078] Next, as Figure 7B As shown, a conductive material 370 serving as a precursor for the second control gate is conformally formed on a substrate 300 including a first control gate 320 and a gate material 340. The conductive material 370 is not particularly limited and can be, for example, a metallic material such as Al or Cu. The conductive material 370 is electrically connected to the first control gate 320 and the gate material 340. Alternatively, a silicide metal may be formed between the conductive material 370 and the first control gate 320 and the gate material 340.

[0079] Next, as Figure 7C As shown, a conductive material 370 in the region of the cell array where the charge storage layer 310 and the first control gate 320 are formed is patterned in a manner extending along the word line direction using a mask pattern (not shown) to form a second control gate 370A. The second control gate 370A is electrically connected to a plurality of first control gates 320 in the corresponding row direction and provides word lines. In addition, by patterning the conductive material 370, the first control gate 320 and the charge storage layer 310 beneath it are simultaneously etched, exposing the active region. On the other hand, by patterning the conductive material 370, a wiring layer 370B electrically connected to the gate material 340 is formed on the peripheral region.

[0080] After patterning the second control gate 370A, ion implantation is performed in the exposed active region 202 to form N-type impurities for the source / drain. Furthermore, similar to existing NAND flash memory, bit lines BL and source lines SL are formed in the cell array region.

[0081] Figure 8 It is a cross-section along the bit line direction in the cell array region, that is, with Figure 2A A cross-section in a direction orthogonal to line AA. For example... Figure 8As shown, an N-well 410 is formed on a P-type silicon substrate 400, and a P-well 420 is formed within the N-well 410. An N-type diffusion region 430 for forming the memory cells, bit-line selected transistors, and source / drain electrodes of the source-line selected transistors (NAND) strings is formed on the surface of the P-well 420. A charge accumulation layer 440 is formed on the P-well 420, and a first control gate 450 and a second control gate 460 are formed on the charge accumulation layer 440. The diffusion region 430A of the bit-line selected transistor is electrically connected to the bit line BL via contact CT1, and the diffusion region 430B of the source-line selected transistor is electrically connected to the source line SL via contact CT2.

[0082] This embodiment of the two-dimensional NAND flash memory has an insulating stack (charge accumulation layer) between silicon and the control gate, containing an insulating layer such as a SiN layer for accumulating charge. The control gate consists of two layers: a first control gate CG1 formed on the insulating stack and a second control gate CG2 formed on the first control gate CG1. The insulating stack and the first control gate CG1 are sequentially deposited on silicon, and the first control gate CG1, the insulating stack, and the silicon are simultaneously etched, using insulating material to fill trenches, thereby forming a self-aligned shallow trench isolation region. After planarizing the trench-filled insulating material, the second control gate CG2 is deposited on the first control gate CG1, and the first control gate CG1 and the second control gate CG2 are electrically connected to each other.

[0083] The second control gate, the first control gate, and the charge accumulation layer are simultaneously etched to form multiple rectangular word lines (WL). This isolates the charge accumulation layer from adjacent cells. The ends of the word lines in the cell array region are connected to the row decoder, which applies a bias voltage to the word lines (WL) for read / write (programming) / erase operations.

[0084] This embodiment illustrates a charge storage layer consisting of a three-layer structure of oxide / nitride / oxide, but it is not limited to this; it can also be a charge storage layer with four or more layers containing nitrides. Furthermore, the storage cell can be a single-level cell (SLC) type storing 1 bit (binary data), or it can be a type storing multiple bits.

[0085] The preferred embodiments of the present invention have been described in detail, but the present invention is not limited to specific embodiments and can be modified and altered in various ways within the scope of the spirit of the invention as described in the claims.

Claims

1. A NAND flash memory, comprising: The active region is formed within the semiconductor substrate, extending along the bit line direction. The slot isolation region is used to define the active region; A charge accumulation layer is formed on the active region for each storage cell and includes a nitride layer sandwiched between insulating layers; A first conductive layer is formed on the charge accumulation layer for each memory cell; as well as A second conductive layer is formed on the first conductive layer, extending along the direction of the word line. The second conductive layer is electrically connected to a plurality of first conductive layers in the corresponding row direction. The trench isolation region is aligned with the sidewalls of the first conductive layer and the charge storage layer.

2. The NAND flash memory according to claim 1, wherein, The charge storage layer includes an oxide-nitride-oxide structure, or a structure in which multiple insulating films other than oxides are stacked between the silicon substrate and the nitride layer, or a structure in which multiple insulating films other than oxides are stacked between the nitride and the first conductive layer.

3. The NAND flash memory according to claim 2, wherein, The first conductive layer includes a polycrystalline silicon layer, the semiconductor substrate includes a silicon region, and the charge storage layer includes a silicon-oxide-nitride-oxide-silicon structure.

4. The NAND flash memory according to claim 1, wherein, The trench isolation region is formed in a self-aligned manner during the etching of the first conductive layer, the charge storage layer, and the semiconductor substrate.

5. The NAND flash memory according to claim 1, wherein, The peripheral region of the NAND flash memory includes a gate insulating film and a gate material that are separate from the charge storage layer and the first conductive layer.

6. A method for manufacturing a NAND flash memory, comprising: A charge storage layer sandwiched between an insulating layer and a first conductive layer are formed on a semiconductor substrate; The first conductive layer, the charge storage layer, and the semiconductor substrate are simultaneously etched, the first conductive layer and the charge storage layer are patterned along the bit line direction, and a trench defining the active region is formed on the semiconductor substrate. The groove is filled with insulating material; A second conductive layer is conformally formed on a semiconductor substrate containing the first conductive layer; The second conductive layer, the first conductive layer, and the charge storage layer are simultaneously etched, and the second conductive layer, the first conductive layer, and the charge storage layer are patterned along the word line direction; as well as The active region after the removal of the second conductive layer, the first conductive layer and the charge accumulation layer forms the source / drain impurity region.

7. The method for manufacturing a NAND flash memory according to claim 6 further includes: A mask pattern is formed covering the cell array area, and the charge accumulation layer and the first conductive layer on the peripheral area are removed; as well as A gate insulating film and gate material, separate from the charge storage layer and the first conductive layer, are formed on the peripheral region.

8. The method for manufacturing a NAND flash memory according to claim 6 further includes: A gate insulating film and gate material are conformally formed on a semiconductor substrate; as well as The gate insulating film and the gate material are planarized until the first conductive layer on the cell array region is exposed.

9. The method for manufacturing a NAND flash memory according to claim 6, wherein, The charge storage layer includes an oxide-nitride-oxide structure, or a structure in which multiple insulating films other than oxides are stacked between the silicon substrate and the nitride layer, or a structure in which multiple insulating films other than oxides are stacked between the nitride and the first conductive layer.

10. The method for manufacturing a NAND flash memory according to claim 9, wherein, The first conductive layer includes a polycrystalline silicon layer, the semiconductor substrate includes a silicon region, and the charge storage layer includes a silicon-oxide-nitride-oxide-silicon structure.

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