Three-dimensional chip stacking device and preparation method thereof

Abstract

The invention provides a three-dimensional chip stacking device and a preparation method thereof, and relates to the technical field of semiconductors, and the three-dimensional chip stacking device comprises a plurality of layers of three-dimensional laminated fan-out packaging devices which are sequentially stacked; the three-dimensional laminated fan-out packaging device comprises a pre-supporting electric connecting frame, at least one layer of first chip and at least one layer of second chip, the first chip and the second chip are stacked in a chip containing area defined by the pre-supporting electric connecting frame, and the functional surfaces of the first chip and the second chip face opposite directions. The encapsulation layer encapsulates the first chip, the second chip and the pre-supporting electric connection frame; every two adjacent layers of three-dimensional laminated fan-out packaging devices are electrically connected, and orthographic projections of the multiple layers of three-dimensional laminated fan-out packaging devices are overlapped. According to the three-dimensional chip stacking device and the preparation method thereof, multiple layers of three-dimensional stacked fan-out packaging devices can be stacked, the capacity of the devices is effectively expanded, warping is small, and PoP packaging is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, in particular to a three-dimensional chip stacking device and a preparation method thereof. BACKGROUND

[0002] With the continuous development of technology fields such as games, artificial intelligence, machine learning, data centers, and virtual reality, the demand for data transmission volume is rising, which has also driven the explosive demand for high-bandwidth memory (HBM) integrated in high-performance chips.

[0003] In HBM, multiple DRAM chips need to be highly accurately stacked together. This requires very high manufacturing process levels to ensure the alignment accuracy of each layer of chips and avoid loss of electrical performance. Moreover, the Through-Silicon Via (TSV) manufacturing process involves precise etching and filling techniques, and any slight mistake can cause electrical connection problems or thermal stress problems.

[0004] CoWoS (Chip-on-Wafer-on-Substrate) is an advanced packaging technology developed by TSMC for 2.5D and 3D, including the CoW part (stacking chips together) and the WoS part (packaging stacked chips on a substrate). This packaging method can make the chip smaller in size, meeting the application scenarios of various electronic devices with high space requirements. First, the system-on-a-chip (SoC) and high-bandwidth memory (HBM) are placed on an interposer, connected by micro bumps, so that the metal lines in the interposer can electrically connect different SoCs and HBMs to realize electrical signal transmission between chips, and then the TSV technology is used to connect the PCB substrate below to package the entire multi-chip.

[0005] However, CoWoS also faces problems such as high technical difficulty, low yield, high cost, and poor heat dissipation. SUMMARY

[0006] The present application aims to address the shortcomings of the prior art by providing a three-dimensional chip stacking device and a preparation method thereof, which can stack multiple three-dimensional layer fan-out packaging devices, effectively expand the capacity of the device, have small warping, and realize PoP packaging.

[0007] To achieve the above-mentioned purposes, the technical solutions adopted by the embodiments of the present application are as follows: In an aspect of the embodiments of the present application, a three-dimensional chip stacking device is provided, which comprises a plurality of three-dimensional stacked fan-out packaging devices arranged in sequence; each three-dimensional stacked fan-out packaging device comprises a pre-supporting electrical connection frame and at least one layer of first chips and at least one layer of second chips stacked in a chip accommodating region defined by the pre-supporting electrical connection frame, the functional surfaces of the first chips and the second chips face in opposite directions, the abutting first chips and second chips are attached to each other through the functional surfaces, a packaging layer encapsulates the first chips, the second chips and the pre-supporting electrical connection frame, and further comprises a first redistribution layer outside the packaging layer for electrical connection with the first chips and one end of the pre-supporting electrical connection frame, and a second redistribution layer outside the packaging layer for electrical connection with the second chips and the other end of the pre-supporting electrical connection frame; the adjacent two three-dimensional stacked fan-out packaging devices are electrically connected, and the orthographic projections of the plurality of three-dimensional stacked fan-out packaging devices overlap.

[0008] Optionally, the orthographic projections of the pre-supporting electrical connection frames in the stacked plurality of three-dimensional stacked fan-out packaging devices overlap.

[0009] Optionally, ball grid array package ball is planted outside the first redistribution layer of the three-dimensional stacked fan-out packaging device at the bottom.

[0010] Optionally, the adjacent two three-dimensional stacked fan-out packaging devices are electrically connected through a reflow solder layer.

[0011] Optionally, the number of the first chips in the plurality of three-dimensional stacked fan-out packaging devices is the same, and / or the number of the second chips in the plurality of three-dimensional stacked fan-out packaging devices is the same.

[0012] In another aspect of the embodiments of the present application, a preparation method of a three-dimensional chip stacking device is provided, which comprises: arranging a three-dimensional stacked fan-out packaging device as a bottom device on a temporary carrier; sequentially stacking and attaching at least one three-dimensional stacked fan-out packaging device on the bottom device, electrically connecting the adjacent two three-dimensional stacked fan-out packaging devices, and forming a stacking device by overlapping the orthographic projections of the stacked plurality of three-dimensional stacked fan-out packaging devices; removing the temporary carrier at the bottom, and attaching a temporary carrier to the top of the stacking device; planting ball grid array package ball on the bottom surface of the three-dimensional stacked fan-out packaging device after removing the temporary carrier; and removing the temporary carrier at the top.

[0013] Optionally, the method of preparing the three-dimensional stacked fan-out package device on the temporary carrier as the bottom layer device comprises: preparing a pre-supporting electrical connection frame on the temporary carrier, and defining a chip accommodating area on the temporary carrier by the pre-supporting electrical connection frame; stacking at least one layer of first chips and at least one layer of second chips in the chip accommodating area, the functional surfaces of the first chips and the second chips facing opposite directions, the abutting first chips and second chips being attached by the functional surfaces, and the first chips, the second chips and the pre-supporting electrical connection frame being encapsulated by an encapsulation layer, a first redistribution layer being formed outside the encapsulation layer to electrically connect the first chips and one end of the pre-supporting electrical connection frame, and a second redistribution layer being formed to electrically connect the second chips and the other end of the pre-supporting electrical connection frame, so as to form a wafer-level packaged three-dimensional stacked fan-out package device on the temporary carrier as the bottom layer device.

[0014] Optionally, the method of sequentially stacking the at least one layer of three-dimensional stacked fan-out package devices on the bottom layer device comprises: removing the temporary carrier at the bottom of the three-dimensional stacked fan-out package device of the bottom layer device; attaching a temporary carrier on the top of the three-dimensional stacked fan-out package device and electroplating solder on the bottom of the three-dimensional stacked fan-out package device to be electrically connected with the first redistribution layer; removing the temporary carrier on the top of the three-dimensional stacked fan-out package device; cutting to form single packages of the three-dimensional stacked fan-out package device; and sequentially stacking the at least one layer of single packages of the three-dimensional stacked fan-out package device on the bottom layer device, the adjacent two layers of single packages of the three-dimensional stacked fan-out package device being electrically connected, and the orthographic projections of the stacked multiple layers of single packages of the three-dimensional stacked fan-out package device being overlapped.

[0015] Optionally, the method of sequentially stacking the at least one layer of single packages of the three-dimensional stacked fan-out package device on the bottom layer device comprises: applying a fluxing agent between the bottom layer device and the single packages of the three-dimensional stacked fan-out package device, so as to wafer-level bond the bottom layer device and the single packages of the three-dimensional stacked fan-out package device.

[0016] Optionally, when the at least two layers of single packages of the three-dimensional stacked fan-out package device are sequentially stacked on the bottom layer device, the fluxing agent is applied between the adjacent two layers of single packages of the three-dimensional stacked fan-out package device, so as to wafer-level bond the adjacent two layers of single packages of the three-dimensional stacked fan-out package device.

[0017] Optionally, after the temporary carrier at the top is removed, the method further comprises: cutting to form a plurality of single packages of the three-dimensional chip stacking device.

[0018] The beneficial effects of the present application include: The three-dimensional chip stacking device provided by the embodiment of the present application comprises a plurality of three-dimensional stacked fan-out package devices arranged in sequence. The three-dimensional stacked fan-out package device comprises a pre-supporting electrical connection frame and at least one layer of first chips and at least one layer of second chips stacked in a chip accommodating area defined by the pre-supporting electrical connection frame, the functional surfaces of the first chips and the second chips face opposite directions, the abutting first chips and second chips are attached to each other through the functional surfaces, the first chips, the second chips and the pre-supporting electrical connection frame are encapsulated by an encapsulation layer, and the three-dimensional stacked fan-out package device further comprises a first redistribution layer outside the encapsulation layer for electrical connection with the first chips and one end of the pre-supporting electrical connection frame, and a second redistribution layer outside the encapsulation layer for electrical connection with the second chips and the other end of the pre-supporting electrical connection frame. Each three-dimensional stacked fan-out package device can comprise a plurality of layers of first chips and second chips, and the connection between the chip redistribution layers can be achieved through the pre-supporting electrical connection frame and the arrangement of the direction and position of the chips, and the fine pitch or ultra-fine pitch redistribution can be achieved. In the plurality of three-dimensional stacked fan-out package devices arranged in sequence, the two adjacent three-dimensional stacked fan-out package devices are electrically connected, and the orthographic projections of the plurality of three-dimensional stacked fan-out package devices are overlapped, thereby further increasing the device capacity and the number of IOs. Each three-dimensional stacked fan-out package device has been encapsulated, so that the device can be tested individually before the preparation of the stacked device, so that the yield of the device is controllable. The number of chips in the three-dimensional stacked fan-out package device and the number of stacked layers of the three-dimensional stacked fan-out package device can be set according to the requirements, so that the capacity of the three-dimensional chip stacking device is flexible. BRIEF DESCRIPTION OF DRAWINGS

[0019] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0020] Figure 1 FIG. 1 is a structural schematic diagram of a three-dimensional chip stacking device provided by an embodiment of the present application; Figure 2 FIG. 2 is another structural schematic diagram of a three-dimensional chip stacking device provided by an embodiment of the present application; Figure 3 FIG. 3 is a flowchart of a preparation method of a three-dimensional chip stacking device provided by an embodiment of the present application; Figure 4 FIG. 4 is a step structural diagram of a preparation method of a three-dimensional chip stacking device provided by an embodiment of the present application; Figure 5Step structure diagram two of a preparation method of a three-dimensional chip stacking device provided by an embodiment of the present application; Figure 6 Step structure diagram three of a preparation method of a three-dimensional chip stacking device provided by an embodiment of the present application; Figure 7 Flowchart two of a preparation method of a three-dimensional chip stacking device provided by an embodiment of the present application; Figure 8 Step structure diagram one of a preparation flow of a three-dimensional chip stacking device; Figure 7 Figure 9 Step structure diagram two of a preparation flow of a three-dimensional chip stacking device; Figure 7 Figure 10 Step structure diagram three of a preparation flow of a three-dimensional chip stacking device; Figure 7 Figure 11 Flowchart three of a preparation method of a three-dimensional chip stacking device provided by an embodiment of the present application; Figure 12 Step structure diagram one of a preparation flow of a three-dimensional chip stacking device; Figure 11 Figure 13 Step structure diagram two of a preparation flow of a three-dimensional chip stacking device; Figure 11 Figure 14 Step structure diagram three of a preparation flow of a three-dimensional chip stacking device; Figure 11 Step structure diagram four of a preparation flow of a three-dimensional chip stacking device; Figure 15 Figure 11 Figure 16 Flowchart four of a preparation method of a three-dimensional chip stacking device provided by an embodiment of the present application; Figure 17 Step structure diagram of a preparation flow of a three-dimensional chip stacking device; Figure 16

[0021] Icon: 100-three-dimensional laminated fan-out packaging device; 101-pre-supporting electrical connection frame; 102-ball planting; 103-soldering immersion layer; 110-first chip; 120-second chip; 130-encapsulation layer; 140-first rewiring layer; 150-second rewiring layer; 201, 202-temporary carrier plate; AA-chip accommodating area. DETAILED DESCRIPTION

[0022] ​​​​​​​​In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. It should be noted that, in the case of no conflict, each feature in the embodiments of the present application can be combined with each other, and the combined embodiments are still within the protection scope of the present application.

[0023] In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like is based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly placed when the product of the present application is used, and is only for the convenience of describing the present application and simplifying the description, and does not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first", "second", "third" and the like are only used to distinguish the description, and cannot be understood as indicating or implying relative importance.

[0024] In the description of the present application, it should be noted that, unless otherwise explicitly specified and limited, the terms "set", "mount", "connected", "connected" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0025] In one aspect of the embodiments of the present application, a three-dimensional chip stacking device is provided, which refers to Figure 1The three-dimensional chip stacking device of this application embodiment includes a multi-layer three-dimensional stacked fan-out package device 100 stacked sequentially; the three-dimensional stacked fan-out package device 100 includes a pre-support electrical connector 101 and at least one first chip 110 and at least one second chip 120 stacked within a chip accommodating area AA defined by the pre-support electrical connector 101. The functional surfaces of the first chip 110 and the second chip 120 face opposite directions, and adjacent first chips 110 and second chips 120 are bonded together through their functional surfaces. Encapsulation layer 130 encapsulates the first chip 110, the second chip 120, and the pre-support electrical connector 101. It also includes a first rewiring layer 140 outside the encapsulation layer 130 for electrical connection to one end of the first chip 110 and the pre-support electrical connector 101, and a second rewiring layer 150 outside the encapsulation layer 130 for electrical connection to the other end of the second chip 120 and the pre-support electrical connector 101. Two adjacent three-dimensional stacked fan-out package devices 100 are electrically connected, and the orthographic projections of the multiple three-dimensional stacked fan-out package devices 100 overlap.

[0026] The three-dimensional chip stacking device of this application embodiment is formed by sequentially stacking multiple layers of three-dimensional stacked fan-out package devices 100. For example... Figure 1 As shown below, Figure 1 The two-layer three-dimensional stacked fan-out package device 100 shown in the figure will be described in detail.

[0027] The three-dimensional stacked fan-out package device 100 includes a pre-support electrical connector 101 and at least one first chip 110 and at least one second chip 120 stacked within a chip accommodating region AA defined by the pre-support electrical connector 101. The functional surfaces of the first chip 110 and the second chip 120 face opposite directions. Adjacent first chips 110 and second chips 120 are bonded together through their functional surfaces. An encapsulation layer 130 encapsulates the first chip 110, the second chip 120, and the pre-support electrical connector 101. The package also includes a first rewiring layer 140 outside the encapsulation layer 130 for electrical connection with one end of the first chip 110 and the pre-support electrical connector 101. The pins of the first chip 110 face downward. When multiple layers of the first chip 110 are provided, the multiple layers of the first chip 110 are staggered so that the pins of each layer of the first chip 110 are exposed for electrical connection with the first rewiring layer 140 and the pre-support electrical connector 101. A second rewiring layer 150 is provided outside the encapsulation layer 130 for electrical connection to the other end of the second chip 120 and the pre-support electrical connector 101. The pins of the second chip 120 face upward. When multiple layers of the second chip 120 are provided, the multiple layers of the second chip 120 are staggered so that the pins of each layer of the second chip 120 are exposed for electrical connection to the second rewiring layer 150 and to the pre-support electrical connector 101.

[0028] Thus, the first chip 110 and the second chip 120 in each three-dimensional stacked fan-out packaging device 100 can be provided with multiple layers to improve the capacity of the three-dimensional stacked fan-out packaging device 100, and due to the symmetrical disassembly form of the first chip 110 and the second chip 120, the warping of the three-dimensional stacked fan-out packaging device 100 during preparation is effectively reduced, so that the three-dimensional stacked fan-out packaging device 100 can still be thinned under the premise of stacking multiple chips.

[0029] The stacked multiple-layer three-dimensional stacked fan-out packaging device 100 is electrically connected between adjacent two layers of the three-dimensional stacked fan-out packaging device 100, which is equivalent to realizing repeatable stacking on the basis of the chip stacking of the three-dimensional stacked fan-out packaging device 100. The orthographic projection of the multiple-layer three-dimensional stacked fan-out packaging device 100 is overlapped, which ensures that the adjacent three-dimensional stacked fan-out packaging devices 100 are directly electrically connected through the hierarchical surface. Moreover, since each three-dimensional stacked fan-out packaging device 100 is a packaging structure, each three-dimensional stacked fan-out packaging device 100 can be tested individually before stacking, so that the yield of the three-dimensional chip stacking device of the embodiment of the present application is effectively improved, and the capacity elasticity is better.

[0030] The three-dimensional chip stacking device provided by the embodiments of the present application comprises a plurality of three-dimensional stacked fan-out package devices 100 arranged in sequence. The three-dimensional stacked fan-out package device 100 comprises a pre-supporting electrical connection frame 101, at least one layer of first chips 110 and at least one layer of second chips 120 stacked in a chip accommodating area AA defined by the pre-supporting electrical connection frame 101, the functional surfaces of the first chips 110 and the functional surfaces of the second chips 120 face opposite directions, the abutting first chips 110 and the second chips 120 are attached to each other through the functional surfaces, an encapsulation layer 130 encapsulates the first chips 110, the second chips 120 and the pre-supporting electrical connection frame 101, and further comprises a first redistribution layer 140 outside the encapsulation layer 130 for electrical connection with the first chips 110 and one end of the pre-supporting electrical connection frame 101, and a second redistribution layer 150 outside the encapsulation layer 130 for electrical connection with the second chips 120 and the other end of the pre-supporting electrical connection frame 101. Each of the three-dimensional stacked fan-out package devices 100 can comprise a plurality of layers of the first chips 110 and the second chips 120, and the connection between the chip redistribution layers can be achieved through the pre-supporting electrical connection frame 101 and the arrangement of the directions and positions of the chips, and the fine pitch or ultra-fine pitch redistribution can be achieved. In the plurality of three-dimensional stacked fan-out package devices 100 arranged in sequence, the two adjacent three-dimensional stacked fan-out package devices 100 are electrically connected, and the orthographic projections of the plurality of three-dimensional stacked fan-out package devices 100 are overlapped, thereby further increasing the device capacity and the number of IOs. Each of the plurality of three-dimensional stacked fan-out package devices 100 has been encapsulated, so that each of the three-dimensional stacked fan-out package devices 100 can be tested individually before the preparation of the stacked device, so that the yield of the device is controllable. The number of chips arranged in the three-dimensional stacked fan-out package device 100 and the number of stacked layers of the three-dimensional stacked fan-out package device 100 can be arranged according to the requirements, so that the capacity of the three-dimensional chip stacking device is flexible.

[0031] Optionally, referring to FIG. 1, Figure 1 The orthographic projections of the pre-supporting electrical connection frames 101 in the plurality of three-dimensional stacked fan-out package devices 100 are overlapped.

[0032] In the three-dimensional stacked fan-out package device 100, the pre-supporting electrical connection frame 101 is used to define a chip accommodating area AA in the device, and the chips are arranged in layers in the chip accommodating area AA. In addition, the pre-supporting electrical connection frame 101 can also play a role in structural support, so as to prevent the mold flow caused by the excessive tangential force of the plastic encapsulation material during the encapsulation of the three-dimensional stacked fan-out package device 100 from causing the lateral displacement of the first chips 110 or the second chips 120 in the stack, thereby ensuring the structural stability of the three-dimensional stacked fan-out package device 100 and the performance of the device.

[0033] When the orthographic projections of the pre-support electrical connector 101 overlap between the stacked multi-layer three-dimensional fan-out packaged devices 100, the chip accommodating regions AA in the stacked three-dimensional fan-out packaged devices 100 correspond in the orthographic projection direction. Thus, the multi-layer three-dimensional fan-out packaged devices 100 can be interconnected with the shortest distance, making the structure of the three-dimensional chip stacked device of this application embodiment compact. Moreover, even if different chip stacking forms and packaging structures are used in the multi-layer three-dimensional fan-out packaged devices 100, the planar structure of the three-dimensional chip stacked device can still have the best space utilization and the optimal planar structure size.

[0034] Optionally, such as Figure 2 As shown, ball grid array packaged balls 102 are placed outside the first redistribution layer 140 of the bottom three-dimensional stacked fan-out packaged device 100.

[0035] In the fabricated three-dimensional chip stacked device, the ball grid array packaged ball 102 is placed on the outer side of the first redistribution layer 140 of the bottom three-dimensional stacked fan-out packaged device 100, so that the signals of the stacked multi-layer three-dimensional stacked fan-out packaged device 100 can be led out through the ball 102, and the three-dimensional chip stacked device is packaged as a whole.

[0036] Optionally, such as Figure 2 As shown, two adjacent three-dimensional stacked fan-out packaged devices are electrically connected through a solder dip layer 103.

[0037] In the fabrication process of the three-dimensional chip stacked device in this application embodiment, the stacked three-dimensional stacked fan-out packaged devices 100 are electrically connected through a solder dip layer 103. In the three-dimensional stacked fan-out packaged device 100, a first rewiring layer 140 and a second rewiring layer 150 are respectively provided on the two outer sides of the encapsulation layer 130. The solder dip layer 103 is provided between two adjacent three-dimensional stacked fan-out packaged devices 100. That is, the electrical connection between the two three-dimensional stacked fan-out packaged devices 100 can be achieved by the solder dip layer 103 itself, without the need to set up additional layers or traces for electrical connection between different levels.

[0038] Optionally, such as Figure 2 As shown, the number of first chips 110 in the multilayer three-dimensional stacked fan-out package device 100 is the same, and / or the number of second chips 120 in the multilayer three-dimensional stacked fan-out package device 100 is the same.

[0039] When the three-dimensional chip stacking device of the embodiment of the present application is used as a high-performance high-storage memory device, for example, the first chip 110 and the second chip 120 in the three-dimensional stacked fan-out package device 100 are both storage chips, the three-dimensional chip stacking device is prepared by sequentially stacking and signal connecting the multiple layers of three-dimensional stacked fan-out package devices 100, the number of the first chips 110 in the multiple layers of three-dimensional stacked fan-out package devices 100 is the same, and the number of the second chips 120 in the multiple layers of three-dimensional stacked fan-out package devices 100 is also the same, that is, the multiple layers of three-dimensional stacked fan-out package devices 100 are prepared in the form of a module unit, and the three-dimensional stacked fan-out package devices 100 in the form of a module unit are tested by a module test, and then stacked to obtain the three-dimensional chip stacking device of the embodiment of the present application. The preparation, test and stacking process in the form of a module unit can simplify the preparation process of the three-dimensional chip stacking device of the embodiment of the present application, reduce the process difficulty, control the cost and yield, and improve the working stability of the prepared three-dimensional chip stacking device.

[0040] Of course, it should be noted that the three-dimensional stacked fan-out package device 100 in the embodiment of the present application is not strictly limited to the design and structure function of the same in the form of a module unit, and in some special application scenarios, the stacked multiple layers of three-dimensional stacked fan-out package devices 100 can also be designed to have different capacities according to actual needs, which are all within the overall design idea of the embodiment of the present application.

[0041] In another aspect of the embodiment of the present application, a preparation method of a three-dimensional chip stacking device is provided, as shown in Figure 3 The preparation method includes: S101, disposing a three-dimensional stacked fan-out package device 100 on a temporary carrier 201 as a bottom layer device. The bottom layer device can be a three-dimensional stacked fan-out package device 100 with multiple single package structures disposed on the temporary carrier 201, or a wafer with an array of three-dimensional stacked fan-out package devices 100 that have not been cut. It can also be understood that the three-dimensional stacked fan-out package devices 100 are arrayed and packaged on a wafer master to form multiple three-dimensional stacked fan-out package devices 100.

[0042] S102, sequentially stacking and attaching at least one three-dimensional stacked fan-out package device 100 on the bottom layer device, electrically connecting the adjacent two layers of three-dimensional stacked fan-out package devices 100, and overlapping the orthographic projection of the stacked multiple layers of three-dimensional stacked fan-out package devices 100 to form a stacked device.

[0043] As Figure 4As shown, the temporary carrier board 201 serves as a support structure during the fabrication process, providing planar support strength whether it is used as the bottom layer of a three-dimensional stacked fan-out package 100 or when at least one layer of three-dimensional stacked fan-out package 100 is further stacked on top of the bottom layer, effectively suppressing warpage that may occur during the process. While effectively suppressing warpage, it supports multi-layer stacking and allows for direct implementation of PoP packaging, effectively expanding the storage capacity of the three-dimensional chip stack device when used as memory. It also allows for the integration of other controllers and NPU / GPU, achieving chiplet packaging.

[0044] S103. Remove the temporary carrier board 201 at the bottom and attach the temporary carrier board 202 on the top layer of the stacked devices.

[0045] like Figure 5 As shown, in order to fabricate the bottom in subsequent processes, the temporary carrier plate 201 at the bottom needs to be removed. On this basis, in order to ensure that the warping problem can still be effectively suppressed in subsequent processes, a temporary carrier plate 202 is attached to the top layer of the stacked device so that when the bottom of the stacked device is processed in the next step, the temporary carrier plate 202 can still provide effective support on the plane to suppress the warping problem.

[0046] S104, the ball grid array packaged balls 102 are placed on the bottom surface of the three-dimensional stacked fan-out packaged device 100 after removing the temporary carrier board 201.

[0047] like Figure 6 As shown, the ball grid array package 102 on the bottom surface of the stacked device has a better effect on the premise of effectively suppressing warpage. The ball 102 can effectively achieve electrical interconnection with the first chip 110 and the second chip 120 in the first redistribution layer 140 and the encapsulation layer 130 of the three-dimensional stacked fan-out package device 100, ensuring stable signal transmission.

[0048] S105. Remove the top temporary carrier plate 202. After the machining process is completed, remove the top temporary carrier plate 202, which is used to prevent warping during the process. Please refer to... Figure 2 .

[0049] The method for fabricating a three-dimensional chip stacked device provided in this application embodiment effectively suppresses warpage throughout the entire fabrication process by using a temporary carrier board. Warpage during the process can be effectively controlled, and it can be directly extended to panel-level packaging, which has a significant cost reduction advantage. Moreover, the three-dimensional stacked fan-out packaging device 100 is fabricated and stacked in the form of unit modules to achieve chiplet packaging.

[0050] Optionally, such as Figure 7As shown, S101, setting a three-dimensional stacked fan-out package device 100 as the bottom layer device on the temporary carrier board 201 includes: S1011, such as Figure 8 As shown, a pre-support electrical connector 101 is prepared on a temporary carrier 201, and the chip accommodating area AA is defined on the temporary carrier 201 by the pre-support electrical connector 101.

[0051] S1012, such as Figure 9 As shown, at least one first chip 110 and at least one second chip 120 are stacked within the chip accommodating area AA. The functional surfaces of the first chip 110 and the second chip 120 face opposite directions, and adjacent first chips 110 and second chips 120 are bonded together through their functional surfaces. For example, a combination of upright and flip-chip methods can be used to stack the first chip 110 and the second chip 120 with opposite functional surface orientations. The first chip 110 is placed on a temporary carrier board 201 using a flip-chip process, with its functional surface facing upwards. Two layers of second chips 120 are stacked on the first chip 110 using an upright process, with their functional surfaces facing downwards, and the two layers of second chips 120 are staggered by a certain distance in the orthographic projection direction.

[0052] like Figure 10 As shown, the first chip 110, the second chip 120, and the pre-support electrical connector 101 are encapsulated by the encapsulation layer 130. A first rewiring layer 140 is formed outside the encapsulation layer 130 to electrically connect one end of the first chip 110 and the pre-support electrical connector 101, and a second rewiring layer 150 is formed to electrically connect the second chip 120 and the other end of the pre-support electrical connector 101. The two layers of second chips 120 are staggered to ensure that both second chips 120 can be directly connected to the second rewiring layer 150, thereby forming a three-dimensional stacked fan-out packaged device 100 of wafer-level packaging on the temporary carrier board 201 as the bottom device.

[0053] Optionally, such as Figure 11 As shown, S102, stacking at least one layer of three-dimensional stacked fan-out packaged device sequentially on the underlying device includes: S1021, such as Figure 12 As shown, the temporary substrate 201 at the bottom of the three-dimensional stacked fan-out package device 100 is removed. The temporary substrate 201 at the bottom is removed first in order to perform the fabrication process on the bottom of the three-dimensional stacked fan-out package device 100 in the next step.

[0054] S1022, such as Figure 13As shown, a temporary carrier 202 is attached to the top of the three-dimensional laminated fan-out packaging device 100, and the solder plated on the bottom of the three-dimensional laminated fan-out packaging device 100 is electrically connected to the first redistribution layer 140. In order to avoid the warping problem as much as possible in the solder plating process on the bottom of the three-dimensional laminated fan-out packaging device 100, a temporary carrier 202 is attached to the top of the three-dimensional laminated fan-out packaging device 100, and the temporary carrier 202 on the top ensures the flatness of the surface during the solder plating process, thereby avoiding warping.

[0055] S1023, as shown in Figure 14 The temporary carrier 202 on the top of the three-dimensional laminated fan-out packaging device 100 is removed. After the above steps are completed, the temporary carrier 202 on the top of the three-dimensional laminated fan-out packaging device 100 is removed.

[0056] S1024, as shown in Figure 15 The three-dimensional laminated fan-out packaging device 100 is cut to form a single package. The three-dimensional laminated fan-out packaging device 100 stacked on the bottom device is stacked in the form of a single package. Therefore, before stacking, the single package of the three-dimensional laminated fan-out packaging device 100 is cut in advance.

[0057] S1025, as shown in Figure 6 The single package of the three-dimensional laminated fan-out packaging device 100 is attached to the bottom device in sequence, the single package of the three-dimensional laminated fan-out packaging device 100 is electrically connected between adjacent two layers, and the single package of the three-dimensional laminated fan-out packaging device 100 is orthographically overlapped between multiple stacked layers.

[0058] The bottom device is prepared integrally on a wafer, which is a wafer-level package. The bottom device is a wafer-level package, and the single package of the three-dimensional laminated fan-out packaging device 100 is attached to the top of the bottom device. When multiple single packages of the three-dimensional laminated fan-out packaging device 100 are attached and stacked, the single package of the three-dimensional laminated fan-out packaging device 100 is electrically connected between adjacent two layers of the stacked single packages, and is also electrically connected to the bottom device. Moreover, in the same projection direction, the single package of the three-dimensional laminated fan-out packaging device 100 is orthographically overlapped between multiple stacked layers, and is orthographically overlapped with the corresponding unit of the bottom device. The single package of the three-dimensional laminated fan-out packaging device 100 has a smaller degree of warping when it is attached and stacked on the bottom device of the wafer-level package. Moreover, the wafer-level package of the bottom device can achieve higher preparation efficiency and reduce costs.

[0059] In the single package structure preparation process of the three-dimensional laminated fan-out packaging device 100, the carrier support is always provided, the single structure of the three-dimensional laminated fan-out packaging device 100 is not easy to warp, and in the three-dimensional laminated fan-out packaging device 100, the electrical connection between the first chip 110 and the first redistribution layer 140 and the electrical connection between the second chip 120 and the second redistribution layer 150 are directly realized in the projection direction, so that the thickness of the three-dimensional laminated fan-out packaging device 100 can be made smaller, so that the three-dimensional chip stacking device prepared by using the preparation method of the embodiment of the present application realizes wafer-level packaging and has a relatively thin overall thickness size, has a relatively high packaging efficiency, and is not easy to warp in the preparation process.

[0060] Optionally, S1025, sequentially stacking and attaching at least one single package of the three-dimensional laminated fan-out packaging device 100 on the bottom layer device includes: coating the immersion soldering agent between the bottom layer device and the single package of the three-dimensional laminated fan-out packaging device 100 to enable wafer-level bonding of the bottom layer device and the single package of the three-dimensional laminated fan-out packaging device 100.

[0061] As shown in Figure 2 , the immersion soldering agent is coated between the bottom layer device and the single package of the three-dimensional laminated fan-out packaging device 100 to form an immersion soldering agent layer 103 between the bottom layer device and the three-dimensional laminated fan-out packaging device 100 stacked thereon, and then the bottom layer device and the single package of the three-dimensional laminated fan-out packaging device 100 are bonded at the wafer level through the immersion soldering agent layer 103.

[0062] Optionally, when at least two single packages of the three-dimensional laminated fan-out packaging device 100 are sequentially stacked and attached on the bottom layer device, the immersion soldering agent is coated between the two adjacent single packages of the three-dimensional laminated fan-out packaging device 100 to enable wafer-level bonding between the two adjacent single packages of the three-dimensional laminated fan-out packaging device 100.

[0063] Similarly, when at least two single packages of the three-dimensional laminated fan-out packaging device 100 are sequentially stacked and attached on the bottom layer device, after stacking and attaching one single package of the three-dimensional laminated fan-out packaging device 100, the immersion soldering agent is coated to form an immersion soldering agent layer 103, and then the next single package of the three-dimensional laminated fan-out packaging device 100 is stacked and attached, so that the two adjacent single packages of the three-dimensional laminated fan-out packaging device 100 are bonded at the wafer level through the immersion soldering agent layer 103.

[0064] Optionally, as shown in Figure 16 , after the temporary carrier 202 of the top layer is removed, the method further includes: S106, cutting to form a three-dimensional chip stacking device with multiple single packages.

[0065] After the single package stack of the three-dimensional stacked fan-out package device 100 is completed, the temporary carrier 202 of the top layer is removed, and finally the bottom layer device is cut, as shown in Figure 17 , a plurality of single package three-dimensional chip stacked devices are finally formed.

[0066] The above only describes the preferred embodiments of the present application and is not intended to limit the present application. Various modifications and changes can be made by those skilled in the art based on the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A three-dimensional chip-stacked device, comprising: The three-dimensional laminated fan-out packaging device comprises a plurality of layers of three-dimensional laminated fan-out packaging devices arranged in sequence. The three-dimensional laminated fan-out packaging device comprises a pre-supporting electrical connection frame and at least one layer of first chips and at least one layer of second chips stacked in a chip accommodating area defined by the pre-supporting electrical connection frame, the functional surfaces of the first chips and the second chips face opposite directions, the abutting first chips and second chips are attached by the functional surfaces, the first chips, the second chips and the pre-supporting electrical connection frame are encapsulated by an encapsulation layer, and the three-dimensional laminated fan-out packaging device further comprises a first redistribution layer outside the encapsulation layer for electrical connection with the first chips and one end of the pre-supporting electrical connection frame, and a second redistribution layer outside the encapsulation layer for electrical connection with the second chips and the other end of the pre-supporting electrical connection frame. The three-dimensional laminated fan-out packaging devices of adjacent two layers are electrically connected, and the orthographic projections of the three-dimensional laminated fan-out packaging devices of multiple layers are overlapped.

2. The three-dimensional chip-stacked device of claim 1, wherein, The orthographic projections of the pre-supporting electrical connection frames in the stacked multiple layers of the three-dimensional laminated fan-out packaging devices are overlapped.

3. The three-dimensional chip-stacked device of claim 1, wherein, Ball grid array packaging is planted on the outside of the first redistribution layer of the three-dimensional laminated fan-out packaging device of the bottom layer.

4. The three-dimensional chip-stacked device of claim 1, wherein, The two adjacent three-dimensional laminated fan-out packaging devices are electrically connected through a reflow solder layer.

5. The three-dimensional chip-stacked device of any one of claims 1 to 4, wherein, The number of first chips in the multiple layers of three-dimensional laminated fan-out packaging devices is the same, and / or the number of second chips in the multiple layers of three-dimensional laminated fan-out packaging devices is the same.

6. A method of fabricating a three-dimensional chip-stacked device, comprising: The method comprises: arranging a three-dimensional laminated fan-out packaging device on a temporary carrier as a bottom layer device; stacking at least one three-dimensional laminated fan-out packaging device on the bottom layer device in sequence, electrically connecting the three-dimensional laminated fan-out packaging devices of adjacent two layers, and overlapping the orthographic projections of the stacked multiple layers of the three-dimensional laminated fan-out packaging devices to form a stacked device; removing the temporary carrier at the bottom of the three-dimensional laminated fan-out packaging device, and planting a temporary carrier on the top layer of the stacked device; planting ball grid array packaging on the bottom surface of the three-dimensional laminated fan-out packaging device after removing the temporary carrier; removing the temporary carrier on the top layer.

7. The production method according to claim 6, wherein The arrangement of a three-dimensional laminated fan-out packaging device on a temporary carrier as a bottom layer device comprises: preparing a pre-supporting electrical connection frame on a temporary carrier, and defining a chip accommodating area on the temporary carrier through the pre-supporting electrical connection frame; stacking at least one layer of first chips and at least one layer of second chips in the chip accommodating area, the functional surfaces of the first chips and the second chips face opposite directions, the abutting first chips and second chips are attached by the functional surfaces, the first chips, the second chips and the pre-supporting electrical connection frame are encapsulated by an encapsulation layer, and the first redistribution layer is formed outside the encapsulation layer to electrically connect the first chips and one end of the pre-supporting electrical connection frame, and the second redistribution layer is formed to electrically connect the second chips and the other end of the pre-supporting electrical connection frame, to form a three-dimensional laminated fan-out packaging device on a wafer level packaging on a temporary carrier as the bottom layer device.

8. The production method according to claim 7, wherein The stacking of at least one three-dimensional laminated fan-out packaging device on the bottom layer device in sequence comprises: removing the temporary carrier at the bottom of the three-dimensional laminated fan-out packaging device of the bottom layer device; attaching a temporary carrier on top of the three-dimensional stacked fan-out package device, and electroplating solder on the bottom of the three-dimensional stacked fan-out package device to electrically connect with the first redistribution layer; removing the temporary carrier on top of the three-dimensional stacked fan-out package device; cutting to form single packages of the three-dimensional stacked fan-out package device; stacking at least one single package of the three-dimensional stacked fan-out package device on the bottom layer device, electrically connecting between two adjacent single packages of the three-dimensional stacked fan-out package device, and overlapping in orthographic projection between the stacked single packages of the three-dimensional stacked fan-out package device.

9. The production method according to claim 8, wherein The stacking at least one single package of the three-dimensional stacked fan-out package device on the bottom layer device comprises: applying fluxing agent between the bottom layer device and the single package of the three-dimensional stacked fan-out package device for wafer-level bonding.

10. The production method according to claim 9, wherein When there are at least two single packages of the three-dimensional stacked fan-out package device stacked on the bottom layer device, applying fluxing agent between two adjacent single packages of the three-dimensional stacked fan-out package device for wafer-level bonding.

11. The production method according to claim 6, wherein After removing the temporary carrier on the top layer, the method further comprises: cutting to form a plurality of single packages of the three-dimensional chip stack device.

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