Semiconductor device, manufacturing method thereof and electronic equipment

Abstract

A semiconductor device and a manufacturing method thereof, and an electronic apparatus, the semiconductor device comprising: a semiconductor layer disposed on a substrate, the semiconductor layer being formed with a cylindrical structure comprising a bottom wall and a side wall; a first electrode and a second electrode stacked on the substrate; the first sub-electrode of the first electrode surrounds the side wall of the semiconductor layer, and the second sub-electrode of the first electrode surrounds the first sub-electrode; the third sub-electrode of the second electrode surrounds the side wall of the semiconductor layer, and the fourth sub-electrode of the second electrode surrounds the third sub-electrode; the oxidation resistance of the first sub-electrode is better than that of the second sub-electrode, and the oxidation resistance of the third sub-electrode is better than that of the fourth sub-electrode. According to the scheme provided by the embodiment of the invention, the electrode is divided into the two sub-electrodes, and the material with better oxidation resistance is connected with the semiconductor layer, so that an oxidation layer can be prevented from being generated between the electrode and the semiconductor, the contact resistance is reduced, the on-state current of the device is improved, and in addition, the resistance of the electrode is favorably regulated and controlled.

Description

TECHNICAL FIELD

[0001] The embodiments of the present disclosure relate to, but are not limited to, device design and manufacturing in the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof, and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of the device is increasingly reduced, and the types and quantities of devices contained in a single chip are also increasing, so that any slight difference in process production can affect the performance of the device.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, various semiconductor structure designs and process optimizations have been proposed in the industry to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the claims.

[0005] The present application provides a semiconductor device and a manufacturing method thereof, and an electronic device, which can improve the on-state current of the device.

[0006] The present application provides a semiconductor device, comprising:

[0007] a substrate, a semiconductor layer, the semiconductor layer being formed with a cylindrical structure comprising a bottom wall and a side wall, the opening of the cylindrical structure facing away from the substrate;

[0008] a first electrode and a second electrode stacked in a direction perpendicular to the substrate on the substrate; the first electrode comprises a first sub-electrode and a second sub-electrode, and the second electrode comprises a third sub-electrode and a fourth sub-electrode; the first sub-electrode surrounds and contacts the side wall of the semiconductor layer, and the second sub-electrode surrounds and connects the first sub-electrode; the third sub-electrode surrounds and contacts the side wall of the semiconductor layer, and the fourth sub-electrode surrounds and connects the third sub-electrode; the oxidation resistance of the first sub-electrode is better than that of the second sub-electrode, and the oxidation resistance of the third sub-electrode is better than that of the fourth sub-electrode.

[0009] In some embodiments, the contact resistance between the first sub-electrode and the semiconductor layer is less than the contact resistance between the second sub-electrode and the semiconductor layer, and the contact resistance between the third sub-electrode and the semiconductor layer is less than the contact resistance between the fourth sub-electrode and the semiconductor layer.

[0010] In some embodiments, the first sub-electrode wraps the bottom wall of the cylindrical structure and the side wall adjacent to the bottom wall.

[0011] In some embodiments, the first sub-electrode overlaps with the outer boundary of the third sub-electrode in the orthographic projection of the substrate.

[0012] In some embodiments, the second sub-electrode overlaps with the fourth sub-electrode in the orthographic projection of the substrate.

[0013] In some embodiments, the second sub-electrode overlaps with the fourth sub-electrode in the orthographic projection of the substrate, and the second sub-electrode is at least partially located outside the fourth sub-electrode in the orthographic projection of the substrate, and the fourth sub-electrode is at least partially located outside the second sub-electrode in the orthographic projection of the substrate.

[0014] In some embodiments, the semiconductor device further comprises: a hole extending in a direction perpendicular to the substrate, and the first sub-electrode and the third sub-electrode, the semiconductor layer, the gate insulating layer and the gate electrode are sequentially arranged in the hole from outside to inside, and the gate electrode fills the hole, the gate insulating layer surrounds the gate electrode, and the semiconductor layer surrounds the gate insulating layer.

[0015] Embodiments of the present disclosure provide a manufacturing method of a semiconductor device, comprising:

[0016] forming a stack structure comprising a first insulating layer, a first sacrificial layer, a second insulating layer, a second sacrificial layer, and a third insulating layer, sequentially stacked on a substrate;

[0017] forming a hole penetrating through the first sacrificial layer, the second insulating layer, the second sacrificial layer, and the third insulating layer; forming a first sub-electrode in a first sub-hole of the hole located in the first sacrificial layer, and forming a third sub-electrode in a second sub-hole of the hole located in the second sacrificial layer;

[0018] forming a semiconductor layer in the hole, the semiconductor layer is formed as a cylindrical structure comprising a bottom wall and a side wall, and the opening direction of the cylindrical structure is away from the substrate, the first sub-electrode surrounds and contacts the side wall of the semiconductor layer, and the third sub-electrode surrounds and contacts the side wall of the semiconductor layer;

[0019] replacing the first sacrificial layer and the second sacrificial layer with a conductive thin film to form a second sub-electrode surrounding the first sub-electrode, and a fourth sub-electrode surrounding the third sub-electrode, wherein the oxidation resistance of the first sub-electrode is better than that of the second sub-electrode, and the oxidation resistance of the third sub-electrode is better than that of the fourth sub-electrode.

[0020] In some embodiments, the forming the hole through the first sacrificial layer, the second insulating layer, the second sacrificial layer, and the third insulating layer comprises:

[0021] The third insulating layer, the second sacrificial layer, the second insulating layer, and the first sacrificial layer are etched along a direction perpendicular to the substrate direction to form an initial via, the first sacrificial layer is etched laterally based on the initial via to form a first lateral recess, and the second sacrificial layer is etched laterally based on the initial via to form a second lateral recess, and the hole comprising the initial via, the first lateral recess, and the second lateral recess is formed;

[0022] The first sub-electrode is formed in a first sub-hole of the hole in the first sacrificial layer, and the third sub-electrode is formed in a second sub-hole of the hole in the second sacrificial layer comprises:

[0023] A conductive thin film is deposited in the hole, the conductive thin film in the initial via is etched and removed, the first sub-electrode in the first lateral recess is formed, and the third sub-electrode in the second lateral recess is formed.

[0024] In some embodiments, the replacing the first sacrificial layer and the second sacrificial layer with a conductive thin film to form a second sub-electrode surrounding the first sub-electrode and a fourth sub-electrode surrounding the third sub-electrode comprises:

[0025] A first trench through the third insulating layer, the second insulating layer, and the first sacrificial layer, and a second trench through the third insulating layer, the second sacrificial layer, and the second insulating layer are formed, and the first trench and the second trench are located on opposite sides of the initial via; the first sacrificial layer is etched and removed laterally based on the first trench to form a first region, and the second sacrificial layer is etched and removed laterally based on the second trench to form a second region;

[0026] A conductive thin film is deposited to fill the first trench, the second trench, the first region, and the second region, and the conductive thin film in the first trench and the second trench is etched and removed to form the second sub-electrode in the first region and the fourth sub-electrode in the second region.

[0027] In some embodiments, the forming the hole through the first sacrificial layer, the second insulating layer, the second sacrificial layer, and the third insulating layer comprises: etching the third insulating layer, the second sacrificial layer, the second insulating layer, and the first sacrificial layer along a direction perpendicular to the substrate direction to form the hole;

[0028] The first sub-electrode is formed in a first sub-hole of the hole in the first sacrificial layer, and the third sub-electrode is formed in a second sub-hole of the hole in the second sacrificial layer comprises:

[0029] sequentially depositing a conductive thin film and a sacrificial layer thin film to form a first conductive layer covering the bottom wall and the sidewall of the hole, the third insulating layer away from the substrate side, and a third sacrificial layer filling the hole;

[0030] forming a first trench penetrating through the third sacrificial layer, the first conductive layer, the third insulating layer, the second sacrificial layer, the second insulating layer, and the first sacrificial layer, and a second trench penetrating through the third sacrificial layer, the first conductive layer, the third insulating layer, the second sacrificial layer, the second insulating layer, and the first sacrificial layer, and the first trench and the second trench are located on opposite sides of the hole; based on lateral etching of the first trench and the second trench, the third insulating layer, the second insulating layer, and the first conductive layer covering the sidewall of the second insulating layer in the hole, covering the sidewall of the third insulating layer, and covering the first conductive layer away from the substrate side of the third insulating layer are removed, to form a first sub-electrode located in the first sub-hole and a third sub-electrode located in the second sub-hole.

[0031] In some embodiments, the use of the conductive thin film to replace the first sacrificial layer and the second sacrificial layer to form a second sub-electrode surrounding the first sub-electrode and a fourth sub-electrode surrounding the third sub-electrode includes:

[0032] based on lateral etching of the first trench, the first sacrificial layer is removed to form a first region, and based on lateral etching of the second trench, the second sacrificial layer is removed to form a second region;

[0033] depositing a conductive thin film to fill the first trench, the second trench, the first region, and the second region, and etching to remove the conductive thin film in the first trench and the second trench to form the second sub-electrode located in the first region and the fourth sub-electrode located in the second region.

[0034] The electronic device provided by the embodiments of the present disclosure includes the semiconductor device described above, or is formed according to the manufacturing method of the semiconductor device described above.

[0035] This application includes a semiconductor device comprising: a semiconductor layer disposed on a substrate, the semiconductor layer having a cylindrical structure including a bottom wall and sidewalls, the opening of the cylindrical structure facing away from the substrate; a first electrode and a second electrode stacked on the substrate in a direction perpendicular to the substrate; the first electrode including a first sub-electrode and a second sub-electrode, the second electrode including a third sub-electrode and a fourth sub-electrode, the first sub-electrode surrounding and contacting the sidewall of the semiconductor layer, the second sub-electrode surrounding and connecting to the first sub-electrode; the third sub-electrode surrounding and contacting the sidewall of the semiconductor layer, the fourth sub-electrode surrounding and connecting to the third sub-electrode; the oxidation resistance of the first sub-electrode being superior to that of the second sub-electrode, and the oxidation resistance of the third sub-electrode being superior to that of the fourth sub-electrode. The solution provided in this embodiment, by dividing the first electrode and the second electrode into two parts and connecting them to the semiconductor layer with materials that have better oxidation resistance, can avoid the formation of an oxide layer between the electrode and the semiconductor during the formation of the semiconductor layer, thereby reducing the contact resistance between the first electrode and the semiconductor layer, as well as reducing the contact resistance between the second electrode and the semiconductor layer, significantly improving the on-state current of the device, without increasing the thickness of the electrodes, and with low process difficulty. In addition, it is not necessary to replace all the electrodes with materials that have better oxidation resistance, which is beneficial for controlling the resistance of the electrodes.

[0036] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the application. Other advantages of this application can be realized and obtained by means of the solutions described in the description and the accompanying drawings.

[0037] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0038] The accompanying drawings are used to provide an understanding of the technical solutions of this application and constitute a part of the specification. They are used together with the embodiments of this application to explain the technical solutions of this application and do not constitute a limitation on the technical solutions of this application.

[0039] Figure 1A Cross-sectional views of a semiconductor device provided for some embodiments, along a direction perpendicular to the substrate. Figure 1B for Figure 1A A cross-sectional view of a transistor along the AA' direction parallel to the substrate. Figure 1C for Figure 1A A cross-sectional view of a transistor along the BB' direction parallel to the substrate; Figure 1D A cross-sectional view of the semiconductor device along a direction perpendicular to the substrate, provided for other embodiments;

[0040] Figure 2A cross-sectional view along a direction perpendicular to the substrate direction after forming the first and second sacrificial layers is provided for some embodiments.

[0041] Figure 3 A cross-sectional view along a direction perpendicular to the substrate direction after forming the first hole, the first lateral recess, and the second lateral recess is provided for some embodiments.

[0042] Figure 4 A cross-sectional view along a direction perpendicular to the substrate direction after forming the first conductive layer is provided for some embodiments.

[0043] Figure 5 A cross-sectional view along a direction perpendicular to the substrate direction after forming the first and third sub-electrodes is provided for some embodiments.

[0044] Figure 6 A cross-sectional view along a direction perpendicular to the substrate direction after forming the semiconductor layer, the gate insulating layer, and the gate electrode is provided for some embodiments.

[0045] Figure 7 A cross-sectional view along a direction perpendicular to the substrate direction after forming the first and second trenches is provided for some embodiments.

[0046] Figure 8 A cross-sectional view along a direction perpendicular to the substrate direction after forming the second and fourth sub-electrodes is provided for some embodiments.

[0047] Figure 9 A cross-sectional view along a direction perpendicular to the substrate direction after forming the fifth insulating layer is provided for some embodiments.

[0048] Figure 10 A cross-sectional view along a direction perpendicular to the substrate direction after forming the first and second sacrificial layers and the first hole is provided for some embodiments.

[0049] Figure 11 A cross-sectional view along a direction perpendicular to the substrate direction after forming the first conductive layer is provided for some embodiments.

[0050] Figure 12 A cross-sectional view along a direction perpendicular to the substrate direction after forming the first and second trenches is provided for some embodiments.

[0051] Figure 13 A cross-sectional view along a direction perpendicular to the substrate direction after forming the first and third sub-electrodes is provided for some embodiments.

[0052] Figure 14 A cross-sectional view along a direction perpendicular to the substrate direction after forming the sixth insulating layer is provided for some embodiments.

[0053] Figure 15 A cross-sectional view along a direction perpendicular to the substrate direction after etching to remove the first and second sacrificial layers is provided for some embodiments.

[0054] Figure 16 a cross-sectional view taken along a line perpendicular to a substrate direction after forming the second and fourth sub-electrodes is provided for some embodiments;

[0055] Figure 17 a cross-sectional view taken along a line perpendicular to a substrate direction after forming the seventh insulating layer is provided for some embodiments;

[0056] Figure 18 a cross-sectional view taken along a line perpendicular to a substrate direction after forming the semiconductor layer, the gate insulating layer, and the gate electrode is provided for some embodiments. DETAILED DESCRIPTION

[0057] Hereinafter, the embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. The features of the embodiments of the present disclosure and the embodiments can be arbitrarily combined with each other unless otherwise contraindicated.

[0058] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the same meaning as those understood by a person of ordinary skill in the art to which the present disclosure belongs.

[0059] The embodiments of the present disclosure are not necessarily limited to the shapes and sizes of the components shown in the drawings, and the shapes and sizes of the components shown in the drawings can be illustrated schematically. Further, the embodiments of the present disclosure are not limited to the shapes or numerical values shown in the drawings.

[0060] In the present disclosure, ordinal numbers such as "first", "second", "third", and the like are used to avoid confusion among components, and do not indicate any order, number, or importance.

[0061] In the present disclosure, for convenience, words indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", and the like are used to describe the positional relationship of components with reference to the drawings, and are only for the convenience of describing the present specification and simplifying the description, and thus cannot be understood as indicating or implying that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus cannot be understood as a limitation on the present disclosure. The positional relationship of the components is appropriately changed according to the direction in which each component is described. Therefore, it is not limited to the words described in the disclosure, and can be appropriately replaced according to the situation.

[0062] In the present disclosure, unless explicitly defined and limited otherwise, the terms "mount", "connected", "connection" should be interpreted broadly. For example, it can be a physical connection or a signal connection, can be a contact connection or an integrally connected connection; can be directly connected, or indirectly connected through an intermediate, or communication between two elements inside. For those skilled in the art, the specific meaning of the above terms in the present disclosure can be understood according to the specific circumstances.

[0063] In the present disclosure, a transistor refers to an element including at least three terminals of a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between the drain electrode (a drain electrode terminal, a drain region, or a drain electrode) and the source electrode (a source electrode terminal, a source region, or a source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. In the present disclosure, the channel region refers to a region through which current mainly flows.

[0064] In the present disclosure, it can be that the first electrode is the drain electrode and the second electrode is the source electrode, or it can be that the first electrode is the source electrode and the second electrode is the drain electrode. In the case of using a transistor with opposite polarity or in the case of changing the direction of current in circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes exchanged with each other. Therefore, in the present disclosure, the "source electrode" and the "drain electrode" can be exchanged with each other.

[0065] In the present disclosure, "connection" includes a case where constituent elements are connected together through an element having a certain electrical action. The element having a certain electrical action is not particularly limited as long as it can perform transmission and reception of an electrical signal between the connected constituent elements. Examples of the element having a certain electrical action include not only electrodes and wiring but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0066] In the present disclosure, "parallel" means approximately parallel or almost parallel, such as a state where the angle formed by two straight lines is -10° or more and 10° or less, and thus also includes a state where the angle is -5° or more and 5° or less. In addition, "perpendicular" means approximately perpendicular, such as a state where the angle formed by two straight lines is 80° or more and 100° or less, and thus also includes a state where the angle is 85° or more and 95° or less.

[0067] In the present disclosure, "the orthogonal projection of B is within the range of the orthogonal projection of A" means that the boundary of the orthogonal projection of B falls within the boundary range of the orthogonal projection of A, or the boundary of the orthogonal projection of A overlaps with the boundary of the orthogonal projection of B.

[0068] The general Schottky contact is formed between the source-drain and channel material of the vertical channel type indium gallium zinc oxide (IGZO) device, mainly due to the oxidized component in the IGZO deposition process, so that an oxide layer is easily generated between the IGZO and the electrode during the growth of the deposited IGZO, which affects the on-state current of the IGZO device and limits the miniaturization of the device size. One solution is to increase the area of the source-drain metal or to change the electrode material of the source-drain as a whole. For the vertical channel device, increasing the area of the source-drain metal is achieved by increasing the thickness of the metal layer, which is difficult to achieve due to stress and etching process limitations, and changing the electrode material as a whole often changes the overall resistance of the metal wiring.

[0069] In the embodiments of the present disclosure, the electrode is divided into two sub-electrodes, and the sub-electrode in contact with the semiconductor layer uses a material with good oxidation resistance, so that the formation of an oxide layer on the electrode during the deposition of the semiconductor layer can be avoided, thereby increasing the on-state current of the device and facilitating the miniaturization of the device. In addition, replacing the entire electrode material is avoided, which is convenient for controlling the resistance of the electrode.

[0070] Figure 1A A semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction perpendicular to the substrate, Figure 1B A semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction perpendicular to the substrate, Figure 1A A semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction parallel to the substrate, Figure 1C A semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction parallel to the substrate, Figure 1A A semiconductor device provided for some embodiments is shown in a cross-sectional view along a direction parallel to the substrate, Figure 1A 、 Figure 1B and Figure 1CAs shown, the semiconductor device provided by the embodiment of the present disclosure can include at least one transistor, which is a vertical transistor, and the transistor can include: a semiconductor layer 23, which can be formed with a first cylindrical structure including a bottom wall and a side wall, and the opening direction of the first cylindrical structure is away from the substrate 1, and the transistor further includes a first electrode 51 and a second electrode 52 stacked in a direction perpendicular to the substrate 1 and arranged on the substrate 1, the second electrode 52 is arranged on the side of the first electrode 51 away from the substrate 1, the first electrode 51 can include a first sub-electrode 511 and a second sub-electrode 512, the second electrode 52 includes a third sub-electrode 521 and a fourth sub-electrode 522, the first sub-electrode 511 can surround the side wall of the semiconductor layer 23 and be in contact with the side wall of the semiconductor layer 23, the second sub-electrode 512 surrounds and connects the first sub-electrode 511, the second sub-electrode 512 is distributed on the side of the first sub-electrode 511 away from the semiconductor layer 23, and the second sub-electrode 512 is in contact with the side of the first sub-electrode 511 away from the semiconductor layer 23; the third sub-electrode 521 surrounds the side wall of the semiconductor layer 23 and is in contact with the side wall of the semiconductor layer 23, the fourth sub-electrode 522 surrounds and connects the third sub-electrode 521, the fourth sub-electrode 522 is distributed on the side of the third sub-electrode 521 away from the semiconductor layer 23, and the fourth sub-electrode 522 is in contact with the side of the third sub-electrode 521 away from the semiconductor layer 23; the oxidation resistance of the first sub-electrode 511 is better than that of the second sub-electrode 512, and the oxidation resistance of the third sub-electrode 521 is better than that of the fourth sub-electrode 522. The first sub-electrode 511 and the second sub-electrode 521 surround different side wall regions of the semiconductor layer 23, respectively.

[0071] The scheme provided by the embodiment can avoid the formation of an oxidation layer between the electrode and the semiconductor layer when the semiconductor layer is formed by dividing the first electrode and the second electrode into two parts, respectively, and connecting the material with better oxidation resistance to the semiconductor layer, thereby reducing the contact resistance between the first electrode and the semiconductor layer, reducing the contact resistance between the second electrode and the semiconductor layer, significantly improving the on-state current of the device, and without the need to increase the thickness of the electrode, the process difficulty is low, in addition, without the need to replace the electrode with a material with better oxidation resistance, which is conducive to regulating the resistance of the electrode.

[0072] In some embodiments, the contact resistance between the first sub-electrode 511 and the semiconductor layer 23 is smaller than the contact resistance between the second sub-electrode 512 and the semiconductor layer 23, and the contact resistance between the third sub-electrode 521 and the semiconductor layer 23 is smaller than the contact resistance between the fourth sub-electrode 522 and the semiconductor layer 23. Here, it is referred to that the first sub-electrode 511 and the third sub-electrode 521 are made of materials with smaller contact resistance, and it is not referred to that there is contact between the second sub-electrode 512 and the semiconductor layer 23, nor is it referred to that there is contact between the fourth sub-electrode 522 and the semiconductor layer 23.

[0073] In some embodiments, the semiconductor layer 23 can further include an extension extending from the opening of the first cylindrical structure in a direction parallel to the substrate 1.

[0074] In some embodiments, the semiconductor device can further include a gate insulating layer 24 disposed on the side of the semiconductor layer 23 away from the substrate 1, and a gate electrode 26 disposed on the side of the gate insulating layer 24 away from the substrate 1, the gate insulating layer 24 covering the side of the semiconductor layer 23 away from the substrate 1, and the gate electrode 26 covering the side of the gate insulating layer 24 away from the substrate 1 and filling the first cylindrical structure. The gate electrode 26 can include a horizontal portion extending in a direction parallel to the substrate 1, and a vertical portion extending from the horizontal portion into the first cylindrical structure and filling the first cylindrical structure.

[0075] In some embodiments, the semiconductor device can include a hole extending in a direction perpendicular to the substrate 1, and the first sub-electrode 511 and the third sub-electrode 521, the semiconductor layer 23, the gate insulating layer 24, and the gate electrode 26 are sequentially arranged in the hole from the outside to the inside, wherein the first sub-electrode 511 and the third sub-electrode 521 are both arranged on the outside of the semiconductor layer 23. The scheme provided in this embodiment can form the first sub-electrode 511, the third sub-electrode 521, the semiconductor layer 23, the gate insulating layer 24, and the gate electrode 26 in one hole, facilitate the formation of the first sub-electrode 511 and the third sub-electrode 521 by one process, and simplify the process.

[0076] In some embodiments, the first sub-electrode 511 can surround the side wall of the semiconductor layer 23 in a full or partial manner, i.e., the cross section of the first sub-electrode 511 in a direction parallel to the substrate 1 can be a closed loop or an open loop.

[0077] In some embodiments, the second sub-electrode 512 can surround the first sub-electrode 511 in a full or partial manner, i.e., the cross section of the second sub-electrode 512 in a direction parallel to the substrate 1 can be a closed loop or an open loop.

[0078] In some embodiments, the third sub-electrode 521 may fully or partially surround the sidewall of the semiconductor layer 23, that is, the cross-section of the third sub-electrode 521 along the direction parallel to the substrate 1 may be a closed loop or an open loop.

[0079] In some embodiments, the fourth sub-electrode 522 may surround the third sub-electrode 521 in a fully encircling or partially encircling manner, that is, the cross-section of the fourth sub-electrode 522 along the direction parallel to the substrate 1 may be a closed loop or an open loop.

[0080] In some embodiments, the first sub-electrode 511 may wrap around the bottom wall of the first cylindrical structure and the sidewall adjacent to the bottom wall. The solution provided in this embodiment can maximize the contact area between the first sub-electrode 511 and the semiconductor layer 23, thereby reducing the contact resistance between them. In this case, the first sub-electrode 511 forms a second cylindrical structure with an opening facing away from the substrate 1, and the semiconductor layer 23 is distributed on the bottom wall and sidewall of the second cylindrical structure formed by the first sub-electrode 511. In other embodiments, the first sub-electrode 511 may not wrap around the bottom wall, but only surround the sidewall of the semiconductor layer 23.

[0081] In some embodiments, the outer boundary of the orthographic projection of the first sub-electrode 511 onto the substrate 1 may overlap with the outer boundary of the orthographic projection of the third sub-electrode 521 onto the substrate 1. The orthographic projection of the third sub-electrode 521 onto the substrate 1 may be, for example, an annular shape, with its outer boundary being the boundary of the outer ring of the annular shape. The orthographic projection of the first sub-electrode 511 onto the substrate 1 may be an annular shape, or a circle, square, ellipse, etc., and its outer boundary may be the boundary of the outer ring of the annular shape, or a circle, square, ellipse, etc. The solution provided in this embodiment facilitates the simultaneous formation of the first sub-electrode 511 and the third sub-electrode 521.

[0082] In some embodiments, such as Figure 1A As shown, the orthographic projection of the second sub-electrode 512 onto the substrate 1 overlaps with the orthographic projection of the fourth sub-electrode 522 onto the substrate 1, and the orthographic projection of the second sub-electrode 512 onto the substrate 1 is at least partially located outside the orthographic projection of the fourth sub-electrode 522 onto the substrate 1, and the orthographic projection of the fourth sub-electrode 522 onto the substrate 1 is at least partially located outside the orthographic projection of the second sub-electrode 512 onto the substrate 1. However, the embodiments disclosed herein are not limited to this; in some embodiments, such as... Figure 1D As shown, the orthographic projection of the second sub-electrode 512 on the substrate 1 and the orthographic projection of the fourth sub-electrode 522 on the substrate 1 can overlap, that is, the orthographic projection of the second sub-electrode 512 on the substrate 1 and the orthographic projection of the fourth sub-electrode 522 on the substrate 1 are completely consistent.

[0083] In some embodiments, the first sub-electrode 511 can extend in a direction parallel to the substrate 1.

[0084] In some embodiments, the second sub-electrode 512 can extend in a direction parallel to the substrate 1.

[0085] In some embodiments, the third sub-electrode 521 can extend in a direction parallel to the substrate 1.

[0086] In some embodiments, the fourth sub-electrode 522 can extend in a direction parallel to the substrate 1.

[0087] In some embodiments, the first sub-electrode 511 can have the same size in a direction perpendicular to the substrate 1 as the second sub-electrode 512, and the first sub-electrode 511 and the second sub-electrode 512 can have the same distance from the substrate 1 in a direction perpendicular to the substrate 1.

[0088] In some embodiments, the third sub-electrode 521 can have the same size in a direction perpendicular to the substrate 1 as the fourth sub-electrode 522, and the third sub-electrode 521 and the fourth sub-electrode 522 can have the same distance from the substrate 1 in a direction perpendicular to the substrate 1.

[0089] In some embodiments, the shape of the outer boundary of the first sub-electrode 511 in the projection of the substrate 1 can be the same as the shape of the side wall of the semiconductor layer 23 in the projection of the substrate 1. Referring to Figure 1B , the shape of the outer boundary of the first sub-electrode 511 in the projection of the substrate 1 can be circular, and the shape of the side wall of the semiconductor layer 23 in the projection of the substrate 1 can be circular. This is merely an example, and embodiments of the present disclosure are not limited thereto, and can be square.

[0090] In some embodiments, the shape of the outer boundary of the third sub-electrode 521 in the projection of the substrate 1 can be the same as the shape of the side wall of the semiconductor layer 23 in the projection of the substrate 1. Referring to Figure 1B and Figure 1C , the shape of the outer boundary of the third sub-electrode 521 in the projection of the substrate 1 can be circular, and the shape of the side wall of the semiconductor layer 23 in the projection of the substrate 1 can be circular. This is merely an example, and embodiments of the present disclosure are not limited thereto, and can be square.

[0091] Figures 1A-1DThe transistor structure shown is only an example, and embodiments of the present disclosure are not limited thereto. The shapes of the first sub-electrode 511, the second sub-electrode 512, the third sub-electrode 521, and the fourth sub-electrode 522 can be changed, and the shape of the semiconductor layer 23 can be changed, for example, the semiconductor layer 23 can extend only in a direction perpendicular to the substrate 1, the cross-sectional size and shape of the sidewall of the semiconductor layer 23 at different positions can be different, and the like.

[0092] The technical solutions of the embodiments are further described below through the manufacturing process of the semiconductor device of the embodiments. The "patterning process" in the embodiments includes deposition of a film layer, coating of photoresist, mask exposure, development, etching, and stripping of photoresist, and is a mature manufacturing process in the related art. The "photolithography process" in the embodiments includes coating of a film layer, mask exposure, and development, and is a mature manufacturing process in the related art. Deposition can be performed by using known processes such as sputtering, evaporation, and chemical vapor deposition, coating can be performed by using known coating processes, and etching can be performed by using known methods, and no specific limitation is made herein. In the description of the embodiments, it needs to be understood that "film" refers to a film layer of a certain material manufactured on a substrate by using a deposition or coating process. If the "film" does not need to be subjected to a patterning process or a photolithography process in the entire manufacturing process, the "film" can also be referred to as a "layer". If the "film" still needs to be subjected to a patterning process or a photolithography process in the entire manufacturing process, the "film" is referred to as a "film" before the patterning process and as a "layer" after the patterning process. The "layer" after the patterning process or the photolithography process includes at least one "pattern".

[0093] In some embodiments, the manufacturing process of the semiconductor device can include:

[0094] 101) forming a first sacrificial layer 2 and a second sacrificial layer 3;

[0095] depositing a first insulating film on the substrate 1 to form a first insulating layer 11;

[0096] depositing a first sacrificial layer film on the first insulating layer 11 and patterning to form a first sacrificial layer 2;

[0097] depositing a second insulating film on the first sacrificial layer 2 to form a second insulating layer 12 covering the first sacrificial layer 2 and the first insulating layer 11;

[0098] depositing a second sacrificial layer film on the second insulating layer 12 and patterning to form a second sacrificial layer 3; the first sacrificial layer 2 and the second sacrificial layer 3 have overlapping projections on the substrate 1;

[0099] depositing a third insulating film on the second sacrificial layer 3 to form a third insulating layer 13 covering the second sacrificial layer 3 and the second insulating layer 12, as Figure 2as shown, Figure 2 A cross-sectional view of the first and second sacrificial layers 2, 3 along a direction perpendicular to the substrate 1 is shown for some embodiments.

[0100] In some embodiments, the footprint of the first sacrificial layer 2 on the substrate 1 can be partially outside the footprint of the second sacrificial layer 3 on the substrate 1, and the footprint of the second sacrificial layer 3 on the substrate 1 can be partially outside the footprint of the first sacrificial layer 2 on the substrate 1. However, embodiments of the present disclosure are not limited thereto, and the footprint of the first sacrificial layer 2 on the substrate 1 and the footprint of the second sacrificial layer 3 on the substrate 1 can overlap.

[0101] In some embodiments, the first, second, and third insulating layers 11, 12, 13 can be low-K dielectric layers, i.e., dielectric layers with a dielectric constant K < 3.9, including but not limited to silicon oxide, such as silicon dioxide (SiO2), etc. The materials of the subsequent fourth, fifth, sixth, seventh, and eighth insulating layers 14, 15, 16, 17, 18 are similar and will not be described again.

[0102] In some embodiments, the first and second sacrificial layers 2, 3 can be insulating materials with etching selectivity to the first, second, and third insulating layers 11, 12, 13, including but not limited to silicon nitride (SiN).

[0103] The first sacrificial layer 2 is parallel to the substrate 1, and the second sacrificial layer 3 is parallel to the substrate 1. The shapes of the first and second sacrificial layers 2, 3 can be determined according to the shapes of the first and second electrodes of the transistor to be formed.

[0104] 102) forming a first hole K1, a first lateral recess A1, and a second lateral recess A2;

[0105] The third insulating layer 13, the second sacrificial layer 3, the second insulating layer 12, and the first sacrificial layer 2 are etched along a direction perpendicular to the substrate 1 to form a first hole K1 that penetrates through the third insulating layer 13, the second sacrificial layer 3, the second insulating layer 12, and the first sacrificial layer 2; the footprint of the first hole K1 on the substrate 1 is located within the footprint of the first sacrificial layer 2 on the substrate 1, so that the subsequent first sub-electrode 511 fully surrounds the semiconductor layer 23, and is located within the footprint of the second sacrificial layer 3 on the substrate 1, so that the subsequent third sub-electrode 521 fully surrounds the semiconductor layer 23;

[0106] etching the first and second sacrificial layers 2, 3 based on the first hole K1, respectively forming a first lateral recess A1 and a second lateral recess A2, the first lateral recess A1 surrounding the first hole K1, the second lateral recess A2 surrounding the first hole K1, and the bottom wall of the first lateral recess A1 being the first sacrificial layer 2, the first lateral recess A1 in orthographic projection on the substrate 1 being within the contour of the first sacrificial layer 2 in orthographic projection on the substrate 1, so that the subsequent second sub-electrode 512 fully surrounds the first sub-electrode 511; the bottom wall of the second lateral recess A2 being the second sacrificial layer 3, the second lateral recess A2 in orthographic projection on the substrate 1 being within the contour of the second sacrificial layer 3 in orthographic projection on the substrate 1, so that the subsequent fourth sub-electrode 522 fully surrounds the third sub-electrode 521, as shown in Figure 3 Figure 3 A cross-sectional view along a direction perpendicular to the substrate 1 after forming the first hole K1, the first lateral recess A1 and the second lateral recess A2 is provided for some embodiments.

[0107] The first sub-electrode 511 can be formed in the first lateral recess A1, and the third sub-electrode 521 can be formed in the second lateral recess A2 subsequently.

[0108] In some embodiments, the orthographic projection of the first hole K1 on a plane parallel to the substrate 1 can be circular, square, elliptical, etc.

[0109] 103) forming a first conductive layer 20;

[0110] A first conductive thin film is deposited on the substrate 1 with the foregoing structure to form a first conductive layer 20, the first conductive layer 20 covering the side wall and bottom wall of the first hole K1, covering the bottom wall and side wall of the first lateral recess A1, and covering the bottom wall and side wall of the second lateral recess A2. The first conductive layer 20 can fill the first and second lateral recesses A1, A2, and not completely fill the first hole K1, as shown in Figure 4 Figure 4 A cross-sectional view along a direction perpendicular to the substrate 1 after forming the first conductive layer 20 is provided for some embodiments.

[0111] In some embodiments, the first conductive thin film can be a material with a contact resistance to the subsequent semiconductor layer 23 less than the contact resistance of the second sub-electrode 512, the fourth sub-electrode 522 to the semiconductor layer 23, and not easy to oxidize, such as tin-doped indium oxide (ITO), indium-doped zinc oxide (IZO), etc.

[0112] 104) forming a first sub-electrode 511 and a third sub-electrode 521;

[0113] ​​etching the first conductive layer 20, the first conductive layer 20 distributed on the surface of the third insulating layer 13 away from the substrate 1 is removed by etching, and the first conductive layer 20 covering the sidewall of the first hole K1 is removed by etching, the first conductive layer 20 in the first lateral recess A1 and the second lateral recess A2 is reserved, the first sub-electrode 511 in the first lateral recess A1 and the bottom wall of the first hole K1 and the third sub-electrode 521 in the second lateral recess A2 are formed to be disconnected from each other; the first sub-electrode 511 can fill the first lateral recess A1, and the third sub-electrode 521 can fill the second lateral recess A2, as shown in Figure 5 Figure 5 The cross-sectional view of some embodiments after forming the first sub-electrode 511 and the third sub-electrode 521 in the direction perpendicular to the substrate 1 is provided.

[0114] In some embodiments, the first sub-electrode 511 can be located only in the first lateral recess A1, that is, when the first conductive layer 20 is etched, the first conductive layer 20 covering the bottom wall of the first hole K1 is removed by etching, and the first sub-electrode 511 in the form of a ring is formed.

[0115] 105) forming a semiconductor layer 23, a gate insulating layer 24 and a gate electrode 26;

[0116] The semiconductor thin film, the gate insulating thin film and the second conductive thin film are sequentially deposited on the substrate 1 with the foregoing structure, and are patterned to form the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26; the semiconductor 23 covers the bottom wall and the sidewall of the first hole K1 and extends from the first hole K1 to the side of the third insulating layer 13 away from the substrate 1, the gate electrode 26 fills the first hole K1, and the gate insulating layer 24 is arranged between the semiconductor layer 23 and the gate electrode 26 to isolate the semiconductor layer 23 and the gate electrode 26, as shown in Figure 6 Figure 6 The cross-sectional view of some embodiments after forming the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 in the direction perpendicular to the substrate 1 is provided. When manufacturing a semiconductor device including a plurality of transistors, the semiconductor thin film, the gate insulating thin film and the second conductive thin film are patterned, and the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 of the transistors at different positions in the same layer can be disconnected.

[0117] In some embodiments, the material of the semiconductor layer 23 can be silicon or polycrystalline silicon and the like with a band gap less than 1.65 eV.

[0118] In some embodiments, the material of the semiconductor layer 23 can be a wide band gap material, such as a metal oxide material with a band gap greater than 1.65 eV.

[0119] ​​For example, the material of the metal oxide semiconductor layer or channel can include a metal oxide of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, and the like. Of course, the metal oxide can also include compounds containing other elements, such as N, Si, and the like; and can also include other small amounts of doped elements.

[0120] In some embodiments, the material of the metal oxide semiconductor layer or channel can include one or more of the following: indium gallium zinc oxide (IGZO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxynitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), and the like, as long as the leakage current of the transistor meets the requirements, and the specific material can be adjusted according to the actual situation.

[0121] These materials have a wide band gap and low leakage current. For example, when the metal oxide material is IGZO, the leakage current of the transistor is less than or equal to 10 -15 A. Thus, the working performance of the dynamic memory can be improved.

[0122] The above-mentioned material of the metal oxide semiconductor layer or channel only emphasizes the type of elements in the material, and does not emphasize the atomic percentage in the material and the film quality of the material.

[0123] In the exemplary embodiments of the present disclosure, the material of the gate insulating layer 24 can include one or more layers of High-K dielectric materials, such as dielectric materials with a dielectric constant K≥3.9. In some embodiments, one or more oxides of hafnium, aluminum, lanthanum, zirconium, and the like can be included. For example, the High-K material can include, but is not limited to, at least one of the following: hafnium oxide (HfO2), aluminum oxide (Al2O3), hafnium aluminum oxide (HfAlO), hafnium lanthanum oxide (HfLaO), zirconium oxide (ZrO2), and the like.

[0124] In some embodiments, the second conductive thin film can be one or more of the following different types of materials:

[0125] For example, metals such as tungsten, aluminum, titanium, copper, nickel, platinum, ruthenium, molybdenum, gold, iridium, rhodium, tantalum, cobalt, etc.; or metal alloys containing the metals mentioned above;

[0126] Alternatively, it can be a conductive metal oxide, metal nitride, metal silicide, metal carbide, etc., such as conductive metal oxide materials such as indium tin oxide (ITO), indium zinc oxide (IZO), indium oxide (InO), etc.; for example, conductive metal nitride materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium aluminum nitride (TiAlN), etc.

[0127] Alternatively, it can be doped polycrystalline silicon, silicon, germanium, silicon germanium, etc.

[0128] 106) Forming a first trench T1 and a second trench T2;

[0129] Depositing a fourth insulating thin film to form a fourth insulating layer 14 covering the gate electrode 26;

[0130] Etching to form a first trench T1 and a second trench T2, the first trench T1 penetrating the fourth insulating layer 14, the third insulating layer 13, the second insulating layer 12 and the first sacrificial layer 2 in the direction perpendicular to the substrate 1, and the second trench T2 penetrating the fourth insulating layer 14, the third insulating layer 13, the second sacrificial layer 3 and the second insulating layer 12 in the direction perpendicular to the substrate 1; etching stops on the first insulating layer 11. When the semiconductor device includes a plurality of arrayed transistors, the first trench T1 and the second trench T2 can be distributed along the row direction of the memory array, respectively disposed on both sides of the first hole K1, the orthographic projection of the first trench T1 on the substrate 1 is located outside the orthographic projection of the second sacrificial layer 3 on the substrate 1, and the orthographic projection of the second trench T2 on the substrate 1 is located outside the orthographic projection of the first sacrificial layer 2 on the substrate 1. When forming a memory array including a plurality of transistors, the first trench T1 and the second trench T2 can be used to separate two adjacent columns of transistors.

[0131] Based on the lateral etching of the first trench T1, the first sacrificial layer 2 is removed to form a first region A3; based on the lateral etching of the second trench T2, the second sacrificial layer 3 is removed to form a second region A4, as shown in Figure 7 Figure 7 The cross-sectional view of some embodiments after forming the first trench T1 and the second trench T2 along the direction perpendicular to the substrate 1 is provided.

[0132] 107) Forming a second sub-electrode 512 and a fourth sub-electrode 522;

[0133] ​A third conductive film is deposited on the substrate 1 having the above structure, and the third conductive film fills the first trench Tl, the first region A3, the second trench T2, and the second region A4. The third conductive film in the first trench Tl and the second trench T2 is removed by etching, and the third conductive film in the first region A3 and the second region A4 is left, thereby forming the second sub-electrode 512 and the fourth sub-electrode 522, as shown in Figure 8 Figure 8 A cross-sectional view of the second sub-electrode 512 and the fourth sub-electrode 522 formed in a direction perpendicular to the substrate 1 is provided for some embodiments. The second sub-electrode 512 surrounds the first sub-electrode 511, and the fourth sub-electrode 522 surrounds the third sub-electrode 521. Figure 8 When there are a plurality of transistors, the second sub-electrode 512 of the plurality of transistors can be included in the first region A3, and the second sub-electrode 512 of the transistors in two adjacent columns can be disconnected when the third conductive film in the first trench Tl is removed by etching. The fourth sub-electrode 522 of the plurality of transistors can be included in the second region A4, and the fourth sub-electrode 522 of the transistors in two adjacent columns can be disconnected when the third conductive film in the second trench T2 is removed by etching.

[0134] The first sub-electrode 511 and the second sub-electrode 512 constitute the first electrode 51, and the third sub-electrode 521 and the fourth sub-electrode 522 constitute the second electrode 52.

[0135] 108) forming a fifth insulating layer 15;

[0136] A fifth insulating film is deposited on the substrate 1 having the above structure, and a fifth insulating layer 15 is formed, which fills the first trench Tl and the second trench T2, as shown in Figure 9 Figure 9 A cross-sectional view of the fifth insulating layer 15 formed in a direction perpendicular to the substrate 1 is provided for some embodiments.

[0137] ​​In some embodiments, the semiconductor device can include a plurality of transistors arrayed along a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. Before step 102, a trench extending along the first direction X can be formed through the third insulating layer 13, the second sacrificial layer 3, the second insulating layer 12, and the first sacrificial layer 2, dividing the first sacrificial layer 2 into a plurality of strips spaced along the second direction and dividing the second sacrificial layer 3 into a plurality of strips spaced along the second direction, so that after the first sacrificial layer 2 and the second sacrificial layer 3 are subsequently replaced, the second sub-electrodes 512 and the fourth sub-electrodes 522 of the plurality of transistors in the same layer and the same column can be disconnected. However, embodiments of the present disclosure are not limited thereto. The trench extending along the first direction X and perpendicular to the substrate 1 direction (which can not pass through the first insulating layer 11) of the structure shown can be formed after the second sub-electrodes 512 and the fourth sub-electrodes 522 are formed, and the second sub-electrodes 512 and the fourth sub-electrodes 522 of the plurality of transistors in the same layer and the same column can be disconnected. Figure 8 The trench extending along the first direction X and perpendicular to the substrate 1 direction of the structure shown can be formed after the second sub-electrodes 512 and the fourth sub-electrodes 522 are formed, and the second sub-electrodes 512 and the fourth sub-electrodes 522 of the plurality of transistors in the same layer and the same column can be disconnected.

[0138] In the above scheme, the disconnection between the first sub-electrodes 511 and the third sub-electrodes 521 of the first conductive layer is achieved by inner etching. In other embodiments, the disconnection between the first sub-electrodes 511 and the third sub-electrodes 521 of the first conductive layer can be achieved by outer etching. In other embodiments, the manufacturing process of the semiconductor device can include:

[0139] 201) forming the first sacrificial layer 2, the second sacrificial layer 3, and the first hole K1;

[0140] depositing a first insulating film on the substrate 1 to form the first insulating layer 11;

[0141] depositing a first sacrificial layer film on the first insulating layer 11 to form the first sacrificial layer 2;

[0142] depositing a second insulating film on the first sacrificial layer 2 to form the second insulating layer 12 covering the first sacrificial layer 2 and the first insulating layer 11;

[0143] depositing a second sacrificial layer film on the second insulating layer 12 to form the second sacrificial layer 3, and depositing a third insulating film on the second sacrificial layer 3 to form the third insulating layer 13 covering the second sacrificial layer 3 and the second insulating layer 12;

[0144] A first hole K1 is formed by etching the third insulating layer 13, the second sacrificial layer 3, the second insulating layer 12, the first sacrificial layer 2 in a direction perpendicular to the substrate 1. The first hole K1 is located within the projection of the first sacrificial layer 2 on the substrate 1 and within the projection of the second sacrificial layer 3 on the substrate 1, so that the second sub-electrode 512 will surround the first sub-electrode 511 and the fourth sub-electrode 522 will surround the third sub-electrode 521. Figure 10 As shown in Figure 10 A cross-sectional view of some embodiments after forming the first sacrificial layer 2, the second sacrificial layer 3 and the first hole K1 in a direction perpendicular to the substrate 1 is provided.

[0145] 202) Forming the first conductive layer 20;

[0146] A first conductive film and a third sacrificial layer film are sequentially deposited on the substrate 1 with the above structure to form the first conductive layer 20 and the third sacrificial layer 4. The first conductive layer 20 covers the bottom wall and the sidewall of the first hole K1 and covers the surface of the third insulating layer 13 away from the substrate 1. The third sacrificial layer 4 fills the first hole K1 and covers the surface of the first conductive layer 20 away from the substrate 1. Figure 11 As shown in Figure 11 A cross-sectional view of some embodiments after forming the first conductive layer 20 in a direction perpendicular to the substrate 1 is provided.

[0147] In some embodiments, the third sacrificial layer film can be a material such as polysilicon and the first conductive layer 20 has etching selectivity.

[0148] 203) Forming the first trench T1 and the second trench T2;

[0149] The first trench T1 and the second trench T2 are formed by etching the third sacrificial layer 4, the first conductive layer 20, the third insulating layer 13, the second sacrificial layer 3, the second insulating layer 12 and the first sacrificial layer 2 in a direction perpendicular to the substrate 1. The etching stops on the first insulating layer 11. The first trench T1 and the second trench T2 can be distributed along the first direction X and arranged on both sides of the first hole K1. In the manufacture of a memory array including transistors arranged along the first direction X and the second direction Y, the first trench T1 and the second trench T2 can extend along the second direction Y to separate two adjacent columns of transistors. Figure 12 As shown in Figure 12 A cross-sectional view of some embodiments after forming the first trench T1 and the second trench T2 in a direction perpendicular to the substrate 1 is provided.

[0150] 204) forming the first sub-electrode 511 and the third sub-electrode 521;

[0151] Based on the first trench T1 and the second trench T2, the second insulating layer 12, the third insulating layer 13 and the first conductive layer 20 are etched laterally to remove the second insulating layer 12 and the third insulating layer 13, and remove the first conductive layer 20 covering the sidewall of the second insulating layer 12, and remove the first conductive layer 20 covering the sidewall of the third insulating layer 13 and the surface away from the substrate 1, forming a lateral recess, and forming the first sub-electrode 511 and the third sub-electrode 521 which are independent of each other, wherein the first sub-electrode 511 is arranged in the sub-hole of the first hole K1 in the first sacrificial layer 2, the first sub-electrode 511 surrounds the third sacrificial layer 4, and the first sub-electrode 511 can also cover the bottom wall of the first hole K1, that is, the first sub-electrode 511 forms a second cylindrical structure including the bottom wall and the sidewall, and the third sacrificial layer 4 fills the second cylindrical structure; the third sub-electrode 521 is arranged in the sub-hole of the first hole K1 in the second sacrificial layer 3, and the third sub-electrode 521 surrounds the third sacrificial layer 4, as shown in Figure 13 Figure 13 The cross-sectional view along the direction perpendicular to the substrate 1 after forming the first sub-electrode 511 and the third sub-electrode 521 is provided for some embodiments. In this step, the first sub-electrode 511 and the third sub-electrode 521 which are disconnected from each other are formed by the outer digging method, which can avoid damaging the contact surface of the first sub-electrode 511, the third sub-electrode 521 and the semiconductor layer, and improve the performance of the device.

[0152] 205) forming the sixth insulating layer 16;

[0153] The sixth insulating film is deposited on the substrate 1 with the above structure, the sixth insulating film fills the first trench T1 and the second trench T2, and fills the lateral recess formed by etching the second insulating layer 12, the third insulating layer 13 and the first conductive layer 20 in step 204), the sixth insulating film in the first trench T1 and the second trench T2 is etched to form the sixth insulating layer 16, as shown in Figure 14 Figure 14 The cross-sectional view along the direction perpendicular to the substrate 1 after forming the sixth insulating layer 16 is provided for some embodiments. Here, the first trench T1 and the second trench T2 are exposed to facilitate subsequent etching and replacement of the first sacrificial layer 2 and the second sacrificial layer 3.

[0154] 206) etching to remove the first sacrificial layer 2 and the second sacrificial layer 3;

[0155] ​​The first and second trenches T1 and T2 are used to remove the first and second sacrificial layers 2 and 3 by lateral etching, and the first and second regions A3 and A4 are formed, as shown in Figure 15 Figure 15 The cross-sectional view of some embodiments after the first and second sacrificial layers 2 and 3 are removed by etching along the direction perpendicular to the substrate 1 is provided.

[0156] 207) Forming the second and fourth sub-electrodes 512 and 522;

[0157] A third conductive film is deposited on the substrate 1 with the above structure, which can fill the first and second trenches T1 and T2 and the first and second regions A3 and A4. The third conductive film in the first and second trenches T1 and T2 is removed by etching, and the third conductive film in the first and second regions A3 and A4 is retained, forming the second and fourth sub-electrodes 512 and 522, as shown in Figure 16 Figure 16 The cross-sectional view of some embodiments after the second and fourth sub-electrodes 512 and 522 are formed along the direction perpendicular to the substrate 1 is provided. The second sub-electrode 512 surrounds the first sub-electrode 511, and the fourth sub-electrode 522 surrounds the third sub-electrode 521.

[0158] 208) Forming the seventh insulating layer 17;

[0159] A seventh insulating film is deposited on the substrate 1 with the above structure, forming the seventh insulating layer 17, which fills the first and second trenches T1 and T2. The third sacrificial layer 4 covering the side of the sixth insulating layer 16 away from the substrate 1 is removed by polishing, as shown in Figure 17 Figure 17 The cross-sectional view of some embodiments after the seventh insulating layer 17 is formed along the direction perpendicular to the substrate 1 is provided.

[0160] 209) Forming the semiconductor layer 23, the gate insulating layer 24, and the gate electrode 26;

[0161] The third sacrificial layer 4 is removed by etching, exposing the first hole K1, and the side wall of the first hole K1 exposes the first and third sub-electrodes 511 and 521.

[0162] ​​​A semiconductor thin film, a gate insulating thin film and a second conductive thin film are sequentially deposited on the substrate 1 to form a semiconductor layer 23, a gate insulating layer 24 and a gate electrode 26; the semiconductor layer 23 covers the bottom wall and the sidewall of the first hole K1 and extends from the first hole K1 to the third insulating layer 13 away from the substrate 1, the gate electrode 26 fills the first hole K1 and extends from the first hole K1 to the third insulating layer 13 away from the substrate 1, and the gate insulating layer 24 is arranged between the semiconductor layer 23 and the gate electrode 26 to separate the semiconductor layer 23 and the gate electrode 26;

[0163] An eighth insulating thin film is deposited and polished to form an eighth insulating layer 18, which can be flush with the gate electrode 26 and covers the seventh insulating layer 17 and the sixth insulating layer 16, as shown in Figure 18 Figure 18 The cross-sectional view of the semiconductor layer 23, the gate insulating layer 24 and the gate electrode 26 formed in some embodiments is shown in the direction perpendicular to the substrate 1.

[0164] In other embodiments, the eighth insulating layer 18 can cover the side of the gate electrode 26 away from the substrate 1, and whether to cover the side of the gate electrode 26 away from the substrate 1 can be determined according to subsequent processes, which are not limited in the embodiments of the present disclosure.

[0165] In some embodiments, the semiconductor device can include a plurality of transistors arranged in a first direction X parallel to the substrate 1 and a second direction Y parallel to the substrate 1. Before the first hole K1 is formed, a trench extending in the first direction X and penetrating the third insulating layer 13, the second sacrificial layer 3, the second insulating layer 12 and the first sacrificial layer 2 can be formed to divide the first sacrificial layer 2 into a plurality of strips arranged in the second direction Y and divide the second sacrificial layer 3 into a plurality of strips arranged in the second direction Y. After the first sacrificial layer 2 and the second sacrificial layer 3 are replaced, the second sub-electrodes 512 and the fourth sub-electrodes 522 of the plurality of transistors in the same layer and the same column can be disconnected. However, the embodiments of the present disclosure are not limited thereto. The trench extending in the first direction X and penetrating the structure shown in the direction perpendicular to the substrate 1 (which can not penetrate the first insulating layer 11) can be formed after the second sub-electrodes 512 and the fourth sub-electrodes 522 are formed to disconnect the second sub-electrodes 512 and the fourth sub-electrodes 522 of the plurality of transistors in the same layer and the same column, thereby spacing the different transistors in the same layer. Figure 18

[0166] The embodiments of the present disclosure provide a manufacturing method of a semiconductor device, which includes:

[0167] ​​forming a stack structure including a first insulating layer, a first sacrificial layer, a second insulating layer, a second sacrificial layer, a third insulating layer, sequentially stacked on a substrate;

[0168] forming a hole penetrating through the first sacrificial layer, the second insulating layer, the second sacrificial layer, and the third insulating layer; forming a first sub-electrode in a first sub-hole of the hole located in the first sacrificial layer, and forming a third sub-electrode in a second sub-hole of the hole located in the second sacrificial layer;

[0169] forming a semiconductor layer in the hole, the semiconductor layer being formed with a cylindrical structure including a bottom wall and a side wall, and an opening direction of the cylindrical structure being away from the substrate, the first sub-electrode surrounding and contacting the side wall of the semiconductor layer, and the third sub-electrode surrounding and contacting the side wall of the semiconductor layer;

[0170] replacing the first sacrificial layer and the second sacrificial layer with a conductive thin film, forming a second sub-electrode surrounding the first sub-electrode, and a fourth sub-electrode surrounding the third sub-electrode, wherein an oxidation resistance of the first sub-electrode is superior to that of the second sub-electrode, and an oxidation resistance of the third sub-electrode is superior to that of the fourth sub-electrode.

[0171] The semiconductor device manufacturing method provided by the embodiment can reduce the contact resistance by dividing the electrode into two sub-electrodes and contacting the sub-electrode with better oxidation resistance with the semiconductor layer, improve the on-state current of the device, and facilitate control of the overall resistance of the electrode.

[0172] In some embodiments, the forming of the hole penetrating through the first sacrificial layer, the second insulating layer, the second sacrificial layer, and the third insulating layer includes:

[0173] etching the third insulating layer, the second sacrificial layer, the second insulating layer, and the first sacrificial layer in a direction perpendicular to the substrate to form an initial via hole, etching the first sacrificial layer based on the initial via hole to form a first lateral recess, and etching the second sacrificial layer based on the initial via hole to form a second lateral recess, the hole including the initial via hole, the first lateral recess, and the second lateral recess;

[0174] The forming of the first sub-electrode in the first sub-hole of the hole located in the first sacrificial layer, and the forming of the third sub-electrode in the second sub-hole of the hole located in the second sacrificial layer include:

[0175] depositing a conductive thin film in the hole, and etching to remove the conductive thin film in the initial via hole to form the first sub-electrode located in the first lateral recess, and the third sub-electrode located in the second lateral recess.

[0176] In some embodiments, the replacing the first and second sacrificial layers with the conductive thin film, forming the second sub-electrode surrounding the first sub-electrode, and the fourth sub-electrode surrounding the third sub-electrode comprises:

[0177] forming a first trench through the third insulating layer, the second insulating layer and the first sacrificial layer, and a second trench through the third insulating layer, the second sacrificial layer and the second insulating layer, and the first trench and the second trench are located on opposite sides of the initial via; removing the first sacrificial layer based on lateral etching of the first trench to form a first region, and removing the second sacrificial layer based on lateral etching of the second trench to form a second region;

[0178] depositing a conductive thin film to fill the first trench, the second trench, the first region and the second region, and etching to remove the conductive thin film in the first trench and the second trench to form the second sub-electrode located in the first region and the fourth sub-electrode located in the second region.

[0179] In some embodiments, the forming the hole through the first sacrificial layer, the second insulating layer, the second sacrificial layer and the third insulating layer comprises: etching the third insulating layer, the second sacrificial layer, the second insulating layer and the first sacrificial layer in a direction perpendicular to the substrate to form the hole.

[0180] the forming the first sub-electrode in the first sub-hole where the hole is located in the first sacrificial layer, and the third sub-electrode in the second sub-hole where the hole is located in the second sacrificial layer comprises:

[0181] sequentially depositing a conductive thin film and a sacrificial layer thin film to form a first conductive layer covering the bottom wall and the side wall of the hole, the third insulating layer away from the substrate side and a third sacrificial layer filling the hole;

[0182] forming a first trench through the third sacrificial layer, the first conductive layer, the third insulating layer, the second sacrificial layer, the second insulating layer, and the first sacrificial layer, and a second trench through the third sacrificial layer, the first conductive layer, the third insulating layer, the second sacrificial layer, the second insulating layer, and the first sacrificial layer, and the first trench and the second trench are located on opposite sides of the hole; based on the first trench and the second trench, laterally etching to remove the third insulating layer, the second insulating layer, and the first conductive layer covering the sidewall of the second insulating layer in the hole, covering the sidewall of the third insulating layer, and covering the side of the third insulating layer away from the substrate, to form a first sub-electrode located in the first sub-hole and a third sub-electrode located in the second sub-hole. The scheme provided by the embodiment can form the first sub-electrode and the third sub-electrode disconnected from each other by the outer digging method, can avoid damaging the contact surface of the first sub-electrode, the third sub-electrode, and the semiconductor layer, and improves the performance of the device.

[0183] In some embodiments, the use of the conductive thin film to replace the first sacrificial layer and the second sacrificial layer, to form the second sub-electrode surrounding the first sub-electrode, and the fourth sub-electrode surrounding the third sub-electrode includes:

[0184] based on the first trench, laterally etching to remove the first sacrificial layer to form a first region, and based on the second trench, laterally etching to remove the second sacrificial layer to form a second region;

[0185] depositing a conductive thin film to fill the first trench, the second trench, the first region, and the second region, and etching to remove the conductive thin film in the first trench and the second trench, to form the second sub-electrode located in the first region, and the fourth sub-electrode located in the second region.

[0186] The embodiments of the present disclosure also provide an electronic device including the semiconductor device of any one of the preceding embodiments or the semiconductor device formed by the manufacturing method of any one of the preceding embodiments. The electronic device can be a storage device, a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0187] Although the embodiments of the present disclosure are as described above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present disclosure, and is not intended to limit the present disclosure. Any person skilled in the art of the present disclosure can make any modification and change in the form and details without departing from the spirit and scope of the present disclosure, but the patent protection scope of the present disclosure shall be subject to the scope defined by the appended claims.

Claims

1. A semiconductor device, characterized by, Comprising: a semiconductor layer disposed on a substrate, the semiconductor layer being formed with a cylindrical structure comprising a bottom wall and a side wall, the cylindrical structure having an opening facing away from the substrate; a first electrode and a second electrode stacked in a direction perpendicular to the substrate on the substrate; the first electrode comprising a first sub-electrode and a second sub-electrode, the second electrode comprising a third sub-electrode and a fourth sub-electrode, the first sub-electrode surrounding and contacting the side wall of the semiconductor layer, the second sub-electrode surrounding and connecting the first sub-electrode; the third sub-electrode surrounding and contacting the side wall of the semiconductor layer, the fourth sub-electrode surrounding and connecting the third sub-electrode; the first sub-electrode having better oxidation resistance than the second sub-electrode, the third sub-electrode having better oxidation resistance than the fourth sub-electrode.

2. The semiconductor device according to claim 1, wherein The contact resistance between the first sub-electrode and the semiconductor layer is less than the contact resistance between the second sub-electrode and the semiconductor layer, and the contact resistance between the third sub-electrode and the semiconductor layer is less than the contact resistance between the fourth sub-electrode and the semiconductor layer.

3. The semiconductor device of claim 1, wherein The first sub-electrode wraps the bottom wall and the side wall adjacent to the bottom wall of the cylindrical structure.

4. The semiconductor device of claim 1, wherein The outer boundary of the first sub-electrode in the orthographic projection of the substrate overlaps with the outer boundary of the third sub-electrode in the orthographic projection of the substrate.

5. The semiconductor device of claim 1, wherein The second sub-electrode in the orthographic projection of the substrate overlaps with the fourth sub-electrode in the orthographic projection of the substrate.

6. The semiconductor device of claim 1, wherein The second sub-electrode in the orthographic projection of the substrate overlaps with the fourth sub-electrode in the orthographic projection of the substrate, and the second sub-electrode in the orthographic projection of the substrate is at least partially located outside the fourth sub-electrode in the orthographic projection of the substrate, and the fourth sub-electrode in the orthographic projection of the substrate is at least partially located outside the second sub-electrode in the orthographic projection of the substrate.

7. The semiconductor device according to any one of claims 1 to 6, wherein The semiconductor device further comprises: a hole extending in a direction perpendicular to the substrate, the first sub-electrode and the third sub-electrode, the semiconductor layer, a gate insulating layer and a gate electrode are sequentially distributed from the outside to the inside in the hole, and the gate electrode fills the hole, the gate insulating layer surrounds the gate electrode, and the semiconductor layer surrounds the gate insulating layer.

8. A method of manufacturing a semiconductor device, characterized by Comprising: forming a stack structure comprising a first insulating layer, a first sacrificial layer, a second insulating layer, a second sacrificial layer, a third insulating layer sequentially stacked on a substrate; forming a hole penetrating through the first sacrificial layer, the second insulating layer, the second sacrificial layer, and the third insulating layer; forming a first sub-electrode in a first sub-hole of the hole located in the first sacrificial layer, and forming a third sub-electrode in a second sub-hole of the hole located in the second sacrificial layer; forming a semiconductor layer in the hole, the semiconductor layer being formed with a cylindrical structure comprising a bottom wall and a side wall, and the cylindrical structure having an opening direction facing away from the substrate, the first sub-electrode surrounding and contacting the side wall of the semiconductor layer, and the third sub-electrode surrounding and contacting the side wall of the semiconductor layer; The first sacrificial layer and the second sacrificial layer are replaced by a conductive thin film to form a second sub-electrode surrounding the first sub-electrode and a fourth sub-electrode surrounding the third sub-electrode, wherein the first sub-electrode has better oxidation resistance than the second sub-electrode, and the third sub-electrode has better oxidation resistance than the fourth sub-electrode.

9. The method of manufacturing a semiconductor device according to claim 8, wherein The forming of the hole penetrating through the first sacrificial layer, the second insulating layer, the second sacrificial layer and the third insulating layer comprises: The third insulating layer, the second sacrificial layer, the second insulating layer and the first sacrificial layer are etched along a direction perpendicular to the substrate to form an initial via hole, the first sacrificial layer is etched based on the initial via hole to form a first lateral groove, and the second sacrificial layer is etched based on the initial via hole to form a second lateral groove, and the hole comprising the initial via hole, the first lateral groove and the second lateral groove is formed; The first sub-electrode is formed in a first sub-hole of the hole in the first sacrificial layer, and the third sub-electrode is formed in a second sub-hole of the hole in the second sacrificial layer, and the first sub-electrode and the third sub-electrode are formed by depositing a conductive thin film in the hole and etching to remove the conductive thin film in the initial via hole. The first sub-electrode in the first lateral groove and the third sub-electrode in the second lateral groove are formed by depositing a conductive thin film in the hole and etching to remove the conductive thin film in the initial via hole.

10. The method of manufacturing a semiconductor device according to Claim 9, wherein The first sacrificial layer and the second sacrificial layer are replaced by a conductive thin film to form a second sub-electrode surrounding the first sub-electrode and a fourth sub-electrode surrounding the third sub-electrode, wherein the first sub-electrode has better oxidation resistance than the second sub-electrode, and the third sub-electrode has better oxidation resistance than the fourth sub-electrode. A first groove penetrating through the third insulating layer, the second insulating layer and the first sacrificial layer, and a second groove penetrating through the third insulating layer, the second sacrificial layer and the second insulating layer are formed, and the first groove and the second groove are located on opposite sides of the initial via hole; the first sacrificial layer is removed by lateral etching based on the first groove to form a first region, and the second sacrificial layer is removed by lateral etching based on the second groove to form a second region; The first sub-electrode in the first region and the fourth sub-electrode in the second region are formed by depositing a conductive thin film to fill the first groove, the second groove, the first region and the second region, and etching to remove the conductive thin film in the first groove and the second groove.

11. The method of manufacturing a semiconductor device according to Claim 8, wherein The forming of the hole penetrating through the first sacrificial layer, the second insulating layer, the second sacrificial layer and the third insulating layer comprises: etching the third insulating layer, the second sacrificial layer, the second insulating layer and the first sacrificial layer along a direction perpendicular to the substrate to form the hole; The first sub-electrode is formed in a first sub-hole of the hole in the first sacrificial layer, and the third sub-electrode is formed in a second sub-hole of the hole in the second sacrificial layer, and the first sub-electrode and the third sub-electrode are formed by depositing a conductive thin film in the hole and etching to remove the conductive thin film in the initial via hole. A conductive thin film and a sacrificial layer thin film are sequentially deposited to form a first conductive layer covering the bottom wall and the side wall of the hole, the third insulating layer away from the substrate side and a third sacrificial layer filling the hole. forming a first trench through the third sacrificial layer, the first conductive layer, the third insulating layer, the second sacrificial layer, the second insulating layer, the first sacrificial layer, and a second trench through the third sacrificial layer, the first conductive layer, the third insulating layer, the second sacrificial layer, the second insulating layer, the first sacrificial layer, the first trench and the second trench being located on opposite sides of the hole; removing the third insulating layer, the second insulating layer, and the first conductive layer covering the sidewalls of the second insulating layer, the sidewalls of the third insulating layer, and the side of the third insulating layer facing away from the substrate based on lateral etching of the first trench and the second trench, to form a first sub-electrode in the first sub-hole and a third sub-electrode in the second sub-hole.

12. The method of manufacturing a semiconductor device according to Claim 11, wherein The use of the conductive thin film to replace the first sacrificial layer and the second sacrificial layer includes: removing the first sacrificial layer based on lateral etching of the first trench to form a first region, and removing the second sacrificial layer based on lateral etching of the second trench to form a second region; depositing a conductive thin film to fill the first trench, the second trench, the first region, and the second region, and etching to remove the conductive thin film in the first trench and the second trench to form the second sub-electrode in the first region and the fourth sub-electrode in the second region.

13. An electronic device, comprising: The semiconductor device includes the semiconductor device as claimed in any one of claims 1 to 7, or the semiconductor device formed by the manufacturing method as claimed in any one of claims 8 to 12.

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