Semiconductor structure and forming method thereof

Abstract

The invention discloses a semiconductor structure and a forming method thereof. The isolation lamination layer is located on the substrate, and the isolation lamination layer comprises a plurality of isolation layers which are spaced in the longitudinal direction; the channel layer structure is located on the isolation lamination layer, the channel layer structure comprises a plurality of channel layers which are spaced in the longitudinal direction, the side walls of the adjacent channel layer structures define a groove which penetrates through the channel layer structure in the longitudinal direction, and the groove extends into the isolation lamination layer in the longitudinal direction. The performance of the semiconductor structure can be guaranteed.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and in particular, to a semiconductor structure and a forming method thereof. BACKGROUND

[0002] A field effect transistor (FET) of a gate-all-around nanosheet (GAA NS) structure, or GAA-FET, is capable of carrying larger current while maintaining a small size. GAA transistors are evolved from fin field effect transistors. Fin field effect transistors are also known as FinFETs. Compared with fin field effect transistors, GAA transistors reduce the supply voltage and enhance the current driving capability, thereby further improving the performance. In particular, GAA-FETs have better electrostatic characteristics than FinFETs.

[0003] The use of GAA transistors in large-scale, even super-large-scale integrated circuits can cause serious bottom parasitic channel leakage. In order to solve this problem, a bottom dielectric isolation (BDI) layer is provided below the source, drain, gate and other regions of the GAA transistor. SUMMARY

[0004] The problem solved by embodiments of the present application is to provide a semiconductor structure and a forming method thereof, which is beneficial to guarantee the performance of the semiconductor structure.

[0005] To solve the above problems, embodiments of the present application provide a semiconductor structure, comprising: a substrate; an isolation stack on the substrate, the isolation stack comprising a plurality of isolation layers spaced apart along a longitudinal direction; a channel layer structure on the isolation stack, the channel layer structure comprising a plurality of channel layers spaced apart along the longitudinal direction, the side walls of adjacent channel layer structures forming a groove extending through the channel layer structure along the longitudinal direction, the groove extending into the isolation stack along the longitudinal direction.

[0006] Optionally, the groove extends along the longitudinal direction to expose the bottommost isolation layer.

[0007] Optionally, the groove does not extend through the isolation stack, so that the bottommost isolation layer in adjacent isolation stacks is connected.

[0008] Optionally, the semiconductor structure further comprises: a gate structure on the substrate and across the channel layer structure, the gate structure surrounding the channel layer and filling between longitudinally adjacent channel layers.

[0009] Optionally, the gate structure further spans the isolation stack and surrounds the isolation layer and fills between longitudinally adjacent isolation layers.

[0010] Optionally, the material of the isolation layer comprises one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon carbon nitride and silicon carbon oxynitride.

[0011] The present application also provides a method for forming a semiconductor structure, comprising: providing a substrate; forming a channel layer structure suspended above the substrate, the channel layer structure comprising a plurality of channel layers spaced apart along a longitudinal direction, side walls of adjacent channel layer structures enclosing a groove extending through the channel layer structure along the longitudinal direction; and forming an isolation stack between the channel layer structure and the substrate, the isolation stack comprising a plurality of isolation layers spaced apart along the longitudinal direction, the groove extending into the isolation stack along the longitudinal direction.

[0012] Optionally, the step of forming the channel layer structure suspended above the substrate, the channel layer structure comprising a plurality of channel layers spaced apart along a longitudinal direction, comprises: forming a first material stack suspended above the substrate, the first material stack comprising channel material layers and first sacrificial layers alternately stacked, wherein a bottommost layer of the first material stack is a channel material layer, and the first sacrificial layers have an etch resistance less than that of the channel material layers; and patterning the first material stack to form a groove extending through the first material stack, the groove dividing the first material stack into a plurality of first stack structures, and leaving channel material layers in the first stack structures as channel layers, the plurality of channel layers in the first stack structures constituting the channel layer structure.

[0013] Optionally, before the step of forming the first material stack suspended above the substrate, the method further comprises: forming a second material stack covering the substrate, the second material stack comprising second sacrificial layers and third sacrificial layers alternately stacked, wherein topmost and bottommost layers of the second material stack are second sacrificial layers, and the second sacrificial layers have an etch resistance less than that of the third sacrificial layers; in the step of forming the first material stack suspended above the substrate, the first material stack covers the second material stack; before the step of patterning the first material stack, the method further comprises: forming an isolation layer at a position of the second sacrificial layer; and in the step of patterning the first material stack, the method further comprises: patterning the third sacrificial layers at a bottom of the channel layer structure and the isolation layer to form a second stack structure at the bottom of the first stack structure, the plurality of isolation layers in the second stack structure constituting an isolation stack, and the groove extending into the isolation stack along the longitudinal direction.

[0014] Optionally, in the step of forming the second material stack covering the substrate, the third sacrificial layers and the first sacrificial layers are of the same material.

[0015] Optionally, in the step of patterning the third sacrificial layers at the bottom of the channel layer structure and the isolation layer to form the second stack structure at the bottom of the first stack structure, the groove extends into a bottommost isolation layer along the longitudinal direction, and the bottommost isolation layer is exposed.

[0016] Optionally, the third sacrificial layer and the isolation layer at the bottom of the patterned channel layer structure are formed in the step of forming the second stack structure at the bottom of the first stack structure, and the bottommost isolation layer in the adjacent isolation layers is connected.

[0017] Optionally, the step of forming the isolation layer at the position of the second sacrificial layer comprises: removing the second sacrificial layer to form a first trench exposing the bottom of the first material stack, the top surface of the substrate, and the third sacrificial layer in the second material stack; and forming the isolation layer to fill the first trench.

[0018] Optionally, before forming the isolation layer at the position of the second sacrificial layer, the forming method further comprises: forming a dummy gate structure across the first material stack and the second material stack, the dummy gate structure covering part of the top and part of the sidewall of the first material stack, and covering part of the sidewall of the second material layer; in the step of patterning the first material stack, the first material stack is patterned along the dummy gate structure, and the first material stack on both sides of the dummy gate structure is removed; and after forming the isolation stack between the channel layer structure and the substrate, the forming method further comprises: removing the dummy gate structure to expose the first stack structure and the second stack structure.

[0019] Optionally, after removing the dummy gate structure, the forming method further comprises: removing the first sacrificial layer in the first stack structure to form a second trench exposing the channel layer; and forming a gate structure across the channel layer structure and filling the second trench, the gate structure surrounding the channel layer.

[0020] Optionally, in the step of removing the first sacrificial layer in the first stack structure, the method further comprises: removing the third sacrificial layer in the second stack structure to form a third trench exposing the isolation layer; and in the step of forming the gate structure across the channel layer structure and filling the second trench, the gate structure further crosses the isolation stack and fills the third trench.

[0021] Optionally, the first material stack suspended above the substrate is formed by an epitaxial growth process.

[0022] Optionally, in the step of forming the first material stack suspended above the substrate, the material of the first sacrificial layer comprises silicon germanium, and the material of the channel material layer comprises silicon.

[0023] Optionally, the second material stack covering the substrate is formed by an epitaxial growth process.

[0024] Optionally, in the step of forming the second material stack covering the substrate, the material of the second sacrificial layer comprises silicon germanium, and the material of the third sacrificial layer comprises silicon germanium, wherein the molar concentration of germanium in the second sacrificial layer is greater than the molar concentration of germanium in the third sacrificial layer.

[0025] Compared with the prior art, the technical scheme of the embodiment of the present application has the following advantages:

[0026] The semiconductor structure provided by the embodiment of the present application is characterized in that: the isolation stack is located on the substrate, the isolation stack comprises a plurality of isolation layers which are spaced apart along the longitudinal direction, the channel layer structure is located on the isolation stack, the channel layer structure comprises a plurality of channel layers which are spaced apart along the longitudinal direction, the side walls of adjacent channel layer structures enclose a groove which penetrates through the channel layer structure along the longitudinal direction, and the groove extends into the isolation stack along the longitudinal direction; in the embodiment of the present application, the groove enclosed by the side walls of adjacent channel layer structures extends into the isolation stack along the longitudinal direction, and the isolation stack is a stack structure comprising a plurality of isolation layers which are spaced apart, so that the depth of the groove extending into the isolation stack is adjusted to be relatively large, the depth of the groove extending into the isolation stack is made to be relatively large, so that the side walls of the channel layer structure are located at positions which are relatively far away from the bottom of the groove in the groove, which is beneficial to reduce the probability that the side walls close to the bottom of the groove are prone to have a slope due to the influence of the process, is beneficial to improve the verticality of the side walls of the channel layer structure, is correspondingly beneficial to improve the consistency of the channel lengths of the plurality of channel layers, thereby is beneficial to reduce the probability that the semiconductor structure is unstable in performance or generates noise, and at the same time, is correspondingly beneficial to ensure sufficient space between the channel layers of the bottommost layer in adjacent channel layer structures. The source / drain doped layer of sufficient size is formed, thereby is beneficial to ensure the mobility of the semiconductor structure, and in turn, is beneficial to ensure the performance of the semiconductor structure.

[0027] In the forming method provided by the embodiment of the present application, the channel layer structure suspended above the substrate is formed, the channel layer structure comprises a plurality of channel layers which are spaced apart along the longitudinal direction, the side walls of adjacent channel layer structures enclose a groove which penetrates through the channel layer structure along the longitudinal direction, the isolation stack is formed between the channel layer structure and the substrate, the isolation stack comprises a plurality of isolation layers which are spaced apart along the longitudinal direction, and the groove extends into the isolation stack along the longitudinal direction; in the embodiment of the present application, the groove enclosed by the side walls of adjacent channel layer structures extends into the isolation stack along the longitudinal direction, and the isolation stack is a stack structure comprising a plurality of isolation layers which are spaced apart, so that the depth of the groove extending into the isolation stack is adjusted to be relatively large, the depth of the groove extending into the isolation stack is made to be relatively large, so that the side walls of the channel layer structure are located at positions which are relatively far away from the bottom of the groove in the groove, which is beneficial to reduce the probability that the side walls close to the bottom of the groove are prone to have a slope due to the influence of the process, is beneficial to improve the verticality of the side walls of the channel layer structure, is correspondingly beneficial to improve the consistency of the channel lengths of the plurality of channel layers, thereby is beneficial to reduce the probability that the semiconductor structure is unstable in performance or generates noise, and at the same time, is correspondingly beneficial to ensure sufficient space between the channel layers of the bottommost layer in adjacent channel layer structures. The source / drain doped layer of sufficient size is formed, thereby is beneficial to ensure the mobility of the semiconductor structure, and in turn, is beneficial to ensure the performance of the semiconductor structure. BRIEF DESCRIPTION OF DRAWINGS

[0028] Figure 1 It is a structural schematic diagram of a semiconductor structure;

[0029] Figures 2-3 is a structure diagram of an embodiment of the semiconductor structure of the present application;

[0030] Figures 4-12 is a structure diagram of each step in an embodiment of the forming method of the semiconductor structure of the present application. DETAILED DESCRIPTION

[0031] The performance of the current semiconductor structure is difficult to guarantee. The reasons why the performance of the semiconductor structure is difficult to guarantee are analyzed.

[0032] Figure 1 is a structure diagram of an embodiment of the semiconductor structure of the present application;

[0033] Reference Figure 1 The semiconductor structure comprises: a substrate 10; an isolation layer 34 located on the substrate 10; a channel layer structure 21 located on the isolation layer 34, the channel layer structure 21 comprising a plurality of channel layers 35 spaced apart along a longitudinal direction (as indicated by the Z direction in the figure). Figure 1 A gate structure 60 crosses the channel layer structure 21 and surrounds each channel layer 35; a source-drain doped layer 50 is located on the substrate 10 on both sides of the gate structure 60, and the source-drain doped layer 50 is in contact with the end of the channel layer structure 21.

[0034] Since the isolation layer 34 is thin, when the channel layer structure 21 is etched, the distance between the side wall of the channel layer structure 21 and the bottom of the etching is very close. Due to the influence of the etching process, the verticality of the side wall of the channel layer structure 21 is poor, especially the side wall at the lower part of the channel layer structure 21 close to the isolation layer 34 has a large slope, which easily leads to inconsistent channel lengths of the plurality of channel layers 35, thereby causing the performance of the semiconductor structure to be unstable or generating noise problems, and also easily leading to insufficient space between the channel layers 35 of the bottom layer of the adjacent channel layer structures 21, resulting in insufficient size of the source-drain doped layer 50 formed between the adjacent channel layer structures 21, thereby affecting the mobility of the semiconductor structure, and further affecting the performance of the semiconductor structure.

[0035] In order to solve the technical problem, an embodiment of the present application provides a semiconductor structure, comprising: a substrate; an isolation stack layer located on the substrate, the isolation stack layer comprising a plurality of isolation layers spaced apart along a longitudinal direction; a channel layer structure located on the isolation stack layer, the channel layer structure comprising a plurality of channel layers spaced apart along the longitudinal direction, the side walls of adjacent channel layer structures surrounding a groove extending through the channel layer structure along the longitudinal direction, and the groove extending to the isolation stack layer along the longitudinal direction.

[0036] In this embodiment of the invention, the grooves formed by the sidewalls of adjacent channel layer structures extend longitudinally into the isolation stack, and the isolation stack is a multilayer isolation structure with spaced-apart isolation layers. Therefore, the depth adjustment window for the grooves extending into the isolation stack is large. By allowing the grooves to extend to a greater depth into the isolation stack, the sidewalls of the channel layer structures are positioned further away from the bottom of the grooves. This helps reduce the probability of defects with an inclined profile appearing on the sidewalls of the channel layer structures due to process influences, thus improving the verticality of the sidewalls and consequently improving the consistency of the channel lengths of multiple channel layers. This helps reduce the probability of performance instability or noise generation in the semiconductor structure. Simultaneously, it helps ensure sufficient space between the bottommost channel layers of adjacent channel layer structures. This is used to form source / drain doped layers of sufficient size, thereby helping to ensure the mobility of the semiconductor structure and ultimately, the performance of the semiconductor structure.

[0037] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0038] Figures 2-3 This is a schematic diagram of a semiconductor structure according to one embodiment of the present invention.

[0039] Reference Figure 2 and Figure 3 , Figure 3 for Figure 2 A cross-sectional view along the AA direction shows a semiconductor structure including: a substrate 100; and an isolation stack 222 located on the substrate 100, the isolation stack 222 comprising a plurality of longitudinally (e.g., ...) Figure 3 (As shown in the Z direction) Spacing layers 340; Channel layer structure 212, located on isolation stack 222, the channel layer structure 212 includes a plurality of longitudinally spaced channel layers 350, the sidewalls of adjacent channel layer structures 212 form a longitudinally penetrating groove 400 through the channel layer structure 222, the groove 400 extending longitudinally into the isolation stack 222.

[0040] Substrate 100 provides the basis for the process operation of semiconductor structure formation.

[0041] In this embodiment, the substrate 100 is made of silicon. In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium dihydrogen phosphate, or other materials. The substrate may also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The substrate material may be suitable for process requirements or easy to integrate.

[0042] The channel layer structure 212 includes a plurality of longitudinally spaced channel layers 350, which are used as channels for transistors.

[0043] In this embodiment, the material of the channel layer 350 includes silicon, germanium, silicon germanium, or a group III-V semiconductor material. As an example, the material of the channel layer 350 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0044] The isolation stack 222 is used to isolate the channel layer structure 212 from the substrate 100, and the gate structure surrounding the channel layer 350 from the substrate 100, effectively isolating the channel layer 350 from the substrate 100 and the gate structure from the substrate 100, thereby reducing the probability of leakage current between the gate structure and the substrate 100, while reducing or avoiding the situation that the substrate 100 causes the parasitic capacitance to increase due to being turned on when the channel layer 350 is turned on.

[0045] In this embodiment, the groove 400 formed by the sidewall of the adjacent channel layer structure 212 extends longitudinally into the isolation stack 222, and the isolation stack 222 is a stack structure with multiple isolation layers 340 spaced apart, so the depth of the groove 400 extending into the isolation stack 222 is large. By making the depth of the groove 400 extending into the isolation stack 222 large, the sidewall of the channel layer structure 212 is located in the groove 400 far away from the bottom of the groove 400, which is beneficial to reduce the probability that the sidewall close to the bottom of the groove 400 has a slope due to process influence, and is beneficial to improve the verticality of the sidewall of the channel layer structure 212, and accordingly is beneficial to improve the consistency of the channel length of the multiple channel layers 350, thereby reducing the probability of instability or noise of the semiconductor structure. At the same time, it is also beneficial to ensure sufficient space between the bottommost channel layer 350 in the adjacent channel layer structure 212. It is beneficial to ensure the mobility of the semiconductor structure by forming a source / drain doping layer of sufficient size, and further is beneficial to ensure the performance of the semiconductor structure.

[0046] In this embodiment, the groove 400 extends longitudinally to expose the bottommost isolation layer 340.

[0047] The groove 400 extends longitudinally to expose the bottommost isolation layer 340, so that the depth of the groove 400 extending into the isolation stack 222 is large, which is beneficial to further make the sidewall of the channel layer structure 212 away from the bottom of the groove 400, and is beneficial to further improve the verticality of the sidewall of the channel layer structure 212, and accordingly is beneficial to further improve the consistency of the channel length of the multiple channel layers 350, thereby further reducing the probability of instability or noise of the semiconductor structure. At the same time, it is also beneficial to further ensure sufficient space between the bottommost channel layer 350 in the adjacent channel layer structure 212. It is beneficial to further ensure the mobility of the semiconductor structure by forming a source / drain doping layer of sufficient size.

[0048] In the embodiment, the groove 400 does not penetrate the isolation stack 222, so that the bottommost isolation layer 340 in the adjacent isolation stack 222 is connected.

[0049] The groove 400 penetrates the isolation stack 222, and the bottommost isolation layer 340 in the adjacent isolation stack 222 is connected, so that the substrate 100 between the adjacent channel layer structures 212 is reserved with the isolation layer 340, so that the source / drain doped layer formed on the substrate 100 between the adjacent channel layer structures 212 is insulated from the substrate 100, thereby facilitating reducing the leakage probability between the source / drain doped layer and the substrate 100.

[0050] In the embodiment, the material of the isolation layer 340 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0051] The isolation layer 340 formed by one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride has good insulation performance.

[0052] In the embodiment, the semiconductor structure further includes: a gate structure 600 located on the substrate 100 and crossing the channel layer structure 212, the gate structure 600 surrounding the channel layer 350 and filling between the longitudinally adjacent channel layers 350.

[0053] The gate structure 600 is used to control the opening and closing of the channel of the transistor.

[0054] The gate structure 600 surrounds and covers the channel layer 350, so that the top, bottom and sidewall of the channel layer 350 can all serve as a channel, thereby increasing the area of the channel layer 350 used as a channel and increasing the working current of the semiconductor structure.

[0055] Specifically, in the embodiment, the gate structure 600 includes a gate dielectric layer surrounding the channel layer 350 along the extension direction of the gate structure 600, and a gate electrode layer located on the gate dielectric layer.

[0056] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 350 and the substrate 100.

[0057] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. The high-k dielectric material refers to a dielectric material with a relative dielectric constant greater than that of silicon oxide. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc.

[0058] It should be noted that the gate dielectric layer can also include a gate oxide layer, and the gate oxide layer is located between the high-k gate dielectric layer and the channel layer 350. Specifically, the material of the gate oxide layer can be silicon oxide.

[0059] In this embodiment, the gate structure 600 is a metal gate structure, and therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC.

[0060] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) located on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical property of the metal gate structure.

[0061] In other embodiments, the gate electrode layer can also only include the work function layer.

[0062] In this embodiment, the gate structure 600 also spans the isolation stack 340, surrounds the isolation layer 340, and is filled between the longitudinally adjacent isolation layers 340.

[0063] The gate structure 600 surrounding the isolation layer 340 and filled between the longitudinally adjacent isolation layers 340 does not play a working role, and the gate structure 600 filled between the longitudinally adjacent isolation layers 340 makes the plurality of isolation layers 340 longitudinally spaced apart, thereby forming the isolation stack 222.

[0064] In this embodiment, the semiconductor structure further includes: on the substrate 100 on both sides of the gate structure 600, in the extension direction of the channel layer structure 212, the source-drain doped layer 500 is in contact with the end of the channel layer structure 212.

[0065] The source-drain doped layer 500 is used as a source region or a drain region of the transistor. Specifically, the doping type of the source-drain doped layer 500 is the same as the channel conduction type of the corresponding transistor.

[0066] In the embodiment, the verticality of the sidewall of the channel layer structure 212 is good, and correspondingly, there is sufficient space between the bottommost channel layers 350 in the adjacent channel layer structures 212 to form source-drain doped layers 500 of sufficient size, thereby facilitating the guarantee of the mobility of the semiconductor structure and further facilitating the guarantee of the performance of the semiconductor structure.

[0067] Figures 4-12 FIG. 1 is a structural schematic diagram of the semiconductor structure according to an embodiment of the present application.

[0068] Referring to Figure 4 , a substrate 100 is provided.

[0069] The substrate 100 provides a process operation basis for the forming process of the semiconductor structure.

[0070] In the embodiment, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium, silicon carbide, gallium arsenide, or indium gallium, or other materials, and the substrate can also be a silicon-on-insulator substrate or a germanium-on-insulator substrate, or other types of substrates. The material of the substrate can be a material suitable for process needs or easy to integrate.

[0071] Referring to Figures 4-9 , a channel layer structure 212 suspended above the substrate 100 is formed, and the channel layer structure 212 includes a plurality of channel layers 350 spaced apart along the longitudinal direction (as indicated by the Z direction in FIG. 1). Figure 9 The sidewalls of the adjacent channel layer structures 212 enclose a groove 400 that penetrates the channel layer structure 212 along the longitudinal direction.

[0072] The channel layer structure 212 includes a plurality of channel layers 350 spaced apart along the longitudinal direction, and the channel layers 350 are used as the channel of the transistor.

[0073] In the embodiment, the material of the channel layer 350 includes silicon, germanium, silicon germanium, or a III-V semiconductor material. As an example, the material of the channel layer 350 is silicon. In other embodiments, the material of the channel layer is determined according to the type and performance of the transistor.

[0074] Referring to Figure 4 , the step of forming the channel layer structure 212 suspended above the substrate 100 includes: forming a first material stack 210 suspended above the substrate 100, and the first material stack 210 includes channel material layers 300 and first sacrificial layers 310 alternately stacked, wherein the bottommost layer of the first material stack 210 is the channel material layer 300, and the etch resistance of the first sacrificial layer 310 is less than the etch resistance of the channel material layer 300.

[0075] The first material stack 210 is used to form a first stack structure, and a corresponding channel layer structure 212 is formed, the channel material layer 300 is used to form a channel layer 350, and the first sacrificial layer 310 is used to occupy a space position for a subsequent gate structure, wherein the etching resistance of the first sacrificial layer 310 is less than the etching resistance of the channel material layer 300, and the channel material layer 300 needs to be reserved while the first sacrificial layer 310 is removed subsequently, so that the etching resistance of the first sacrificial layer 310 is less than the etching resistance of the channel material layer 300, which is beneficial to facilitate the subsequent removal of the first sacrificial layer 310 and reduce damage to the channel layer 350 when the first sacrificial layer 310 is removed.

[0076] In the embodiment, in the step of forming the first material stack 210 suspended above the substrate 100, the material of the first sacrificial layer 310 includes silicon germanium, and the material of the channel material layer 300 includes silicon.

[0077] The material of the first sacrificial layer 310 includes silicon germanium, and the material of the channel material layer 300 includes silicon, which can make the etching resistance of the first sacrificial layer 310 less than the etching resistance of the channel material layer 300.

[0078] In the embodiment, an epitaxial growth process is used to form the first material stack 210 suspended above the substrate 100.

[0079] The epitaxial growth process can better control the process parameters, has high process controllability, is easy to obtain a more accurate film thickness size, and is easy to form a film layer with less impurities, so that the quality of the channel material layer 300 is higher. Moreover, the material of the first sacrificial layer 310 is silicon germanium, and the material of the channel material layer 300 is silicon. Therefore, the epitaxial growth process can grow the first sacrificial layer 310 on the channel material layer 300, and grow the channel material layer 300 on the first sacrificial layer 310, so that the first material stack 210 is formed in the same process.

[0080] With reference to Figure 4 Before the first material stack 210 suspended above the substrate 100 is formed, the forming method further includes: forming a second material stack 220 covering the substrate 100, the second material stack 220 including second sacrificial layers 320 and third sacrificial layers 330 stacked alternately, wherein the topmost layer and the bottommost layer of the second material stack 220 are the second sacrificial layers 320, and the etching resistance of the second sacrificial layers 320 is less than the etching resistance of the third sacrificial layers 330.

[0081] The second material stack 220 is used for subsequent formation of a second stack structure, and a corresponding reformation of an isolation stack. The second sacrificial layer 320 is used for subsequent formation of an isolation layer. The third sacrificial layer 330 is used for subsequent formation of a gate structure. The topmost layer and the bottommost layer of the second material stack 220 are the second sacrificial layer 320. The topmost layer and the bottommost layer of the subsequently formed second stack structure are the isolation layer. The topmost isolation layer can isolate the channel layer structure 212. The bottommost isolation layer can isolate the gate structure. The second sacrificial layer 320 needs to be removed while the third sacrificial layer 330 is retained. The etch resistance of the second sacrificial layer 320 is less than that of the third sacrificial layer 330. This facilitates easy removal of the second sacrificial layer 320 and reduces damage to the third sacrificial layer 330.

[0082] In this embodiment, in the step of forming the second material stack 220 covering the substrate 100, the material of the second sacrificial layer 320 includes silicon germanium, and the material of the third sacrificial layer 330 includes silicon germanium. The molar concentration of germanium in the second sacrificial layer 320 is greater than that in the third sacrificial layer 330.

[0083] The material of the second sacrificial layer 320 includes silicon germanium, and the material of the third sacrificial layer 330 includes silicon germanium. The molar concentration of germanium in the second sacrificial layer 320 is greater than that in the third sacrificial layer 330. This can make the etch resistance of the second sacrificial layer 320 less than that of the third sacrificial layer 330.

[0084] In this embodiment, the epitaxial growth process is used to form the second material stack 220 suspended above the substrate 100.

[0085] The epitaxial growth process can better control the process parameters, has high process controllability, and is easy to obtain precise film thickness dimensions. The epitaxial growth process is also easy to form a film layer with less impurities, so that the quality of the second sacrificial layer 320 and the third sacrificial layer 330 is high. In addition, the material of the second sacrificial layer 320 is silicon germanium, and the material of the third sacrificial layer 330 is silicon. Therefore, the epitaxial growth process can grow the third sacrificial layer 330 on the second sacrificial layer 320 and grow the second sacrificial layer 320 on the third sacrificial layer 330, so that the second material stack 220 is formed in the same process.

[0086] In this embodiment, in the step of forming the first material stack 210 suspended above the substrate 100, the first material stack 210 covers the second material stack 220.

[0087] Correspondingly, in this embodiment, the epitaxial growth process is used to form the second material stack 220 and the first material stack 210 covering the second material stack 220 in the same process.

[0088] In the embodiment, the third sacrificial layer 330 has the same material as the first sacrificial layer 310.

[0089] The third sacrificial layer 330 has the same material as the first sacrificial layer 310, which can realize that the etching resistance of the first sacrificial layer 310 is less than that of the channel material layer 300, the etching resistance of the second sacrificial layer 320 is less than that of the third sacrificial layer 330, while reducing the introduction of too many different elements, and also can remove the third sacrificial layer 330 and the first sacrificial layer 310 at the same time to form a gate structure, which simplifies the process flow and improves the process efficiency.

[0090] It should be noted that in the embodiment, the top layer of the second material stack 220 is the second sacrificial layer 320, the bottom layer of the first material stack 210 is the channel material layer 300, the etching resistance of the first sacrificial layer 310 is less than that of the channel material layer 300, the etching resistance of the second sacrificial layer 320 is less than that of the third sacrificial layer 330, and the third sacrificial layer 330 has the same material as the first sacrificial layer 310, which is beneficial to reduce the damage to the channel material layer 300 when the second sacrificial layer 320 is removed subsequently, thereby being beneficial to protect the film quality of the channel layer structure 212.

[0091] In combination with reference Figure 5 and Figure 6 , Figure 6 for Figure 5 The cross-sectional view along the AA direction, before the isolation layer is formed at the position of the second sacrificial layer 320, the forming method further comprises: forming a pseudo-gate structure 200 which spans the first material stack 210 and the second material stack 220, the pseudo-gate structure 200 covers part of the top and part of the sidewall of the first material stack 210, and covers part of the sidewall of the second material layer 220.

[0092] The pseudo-gate structure 200 is used to occupy a space position for the subsequent formation of a gate structure.

[0093] In the embodiment, the material of the pseudo-gate structure 200 includes silicon.

[0094] In combination with reference Figure 7 and Figure 8 , before the first material stack 210 is patterned, the forming method further comprises: forming an isolation layer 340 at the position of the second sacrificial layer 320.

[0095] The isolation layer 340 is used to isolate the channel layer structure 212 from the substrate 100, and the gate structure surrounding the channel layer 350 from the substrate 100 which is formed subsequently.

[0096] In the step of forming the isolation layer 340 at the position of the second sacrificial layer 320, the material of the isolation layer 340 is an insulating material, including one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride.

[0097] The isolation layer 340 formed by one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon oxycarbonitride has good isolation performance.

[0098] Reference Figure 7 The step of forming the isolation layer 340 at the position of the second sacrificial layer 320 includes: removing the second sacrificial layer 320 to form a first trench 410 exposing the bottom of the first material stack 210, the top surface of the substrate 100, and the third sacrificial layer 330 in the second material stack 220.

[0099] The first trench 410 is used to provide a spatial position for forming the isolation layer 340.

[0100] In this embodiment, the second sacrificial layer 320 is removed by a wet etching process.

[0101] The wet etching process has relatively low cost and simple operation steps, and can also achieve a large etching selectivity, which is conducive to reducing damage to the third sacrificial layer 330 and the first material stack 210 during the removal of the second sacrificial layer 320.

[0102] Reference Figure 8 The isolation layer 340 filling the first trench 410 is formed.

[0103] The isolation layer 340 filling the first trench 410 is formed, and a plurality of isolation layers 340 spaced apart in the longitudinal direction are obtained.

[0104] In this embodiment, the isolation layer 340 filling the first trench 410 is formed by an atomic layer deposition process.

[0105] The atomic layer deposition process has good step coverage capability, so that the isolation layer 340 can be well conformally filled in the first trench 410.

[0106] Reference Figure 9 The first material stack 210 is patterned to form a groove 400 penetrating the first material stack 210, the groove 400 divides the first material stack 210 into a plurality of discrete first stack structures 211, and the channel material layer 300 in the first stack structure 211 is reserved as a channel layer 350, and the plurality of channel layers 350 in the first stack structure 211 constitute a channel layer structure 212.

[0107] The groove 400 is used to provide a spatial position for forming a source-drain doping layer later.

[0108] Specifically, in the embodiment, in the step of patterning the first material stack 211, the first material stack 211 is patterned along the dummy gate structure 200, and the first material stack 211 on both sides of the dummy gate structure 200 is removed.

[0109] Continuing to refer to Figure 9 An isolation stack 222 is formed between the channel layer structure 212 and the substrate 100, and the isolation stack 222 includes a plurality of isolation layers 350 spaced apart along the longitudinal direction, and the groove 400 extends into the isolation stack 222 along the longitudinal direction.

[0110] The isolation stack 222 is used to isolate the channel layer structure 212 from the substrate 100, and the gate structure from the substrate 100 around the channel layer 350, effectively isolating the channel layer 350 from the substrate 100 and the gate structure from the substrate 100, thereby reducing the probability of leakage current between the gate structure and the substrate 100, and reducing or avoiding the situation that the substrate 100 causes the parasitic capacitance to increase due to being turned on when the channel layer 350 is turned on.

[0111] In the embodiment, the groove 400 surrounded by the sidewalls of the adjacent channel layer structures 212 extends into the isolation stack 222 along the longitudinal direction, and the isolation stack 222 is a stack structure having a plurality of isolation layers 340 spaced apart, and the depth of the groove 400 extending into the isolation stack 222 is adjusted to be larger, so that the sidewalls of the channel layer structure 212 are located in the groove 400 at a position farther away from the bottom of the groove 400, which is beneficial to reduce the probability that the sidewalls close to the bottom of the groove 400 have a slope due to process effects, and is beneficial to improve the verticality of the sidewalls of the channel layer structure 212, and accordingly is beneficial to improve the consistency of the channel lengths of the plurality of channel layers 350, thereby reducing the probability of instability or noise of the semiconductor structure, and at the same time, it is also beneficial to ensure sufficient space between the bottommost channel layers 350 in the adjacent channel layer structures 212. for forming a source-drain doping layer of sufficient size, thereby being beneficial to ensure the mobility of the semiconductor structure, and further being beneficial to ensure the performance of the semiconductor structure.

[0112] In the embodiment, in the step of patterning the first material stack 211, the third sacrificial layer 330 and the isolation layer 340 at the bottom of the channel layer structure 212 are also patterned, and a second stack structure 221 is formed at the bottom of the first stack structure 211, and the plurality of isolation layers 340 in the second stack structure 221 constitute the isolation stack 222, and the groove 400 extends into the isolation stack 222 along the longitudinal direction.

[0113] In this embodiment, in the step of forming a second stacked structure 221 located at the bottom of the first stacked structure 211 by the third sacrificial layer 330 and the isolation layer 340 at the bottom of the patterned channel layer structure 212, the groove 400 extends longitudinally into the bottommost isolation layer 340 and exposes the isolation layer 340.

[0114] The groove 400 extends longitudinally to expose the bottommost isolation layer 340, resulting in a greater depth of the groove 400 within the isolation stack 222. This facilitates further reducing the distance between the sidewalls of the channel layer structure 212 and the bottom of the groove 400, thereby improving the verticality of the sidewalls and consequently enhancing the channel length consistency of the multiple channel layers 350. This helps to further reduce the probability of performance instability or noise generation in the semiconductor structure. Simultaneously, it also helps to ensure sufficient space between the bottommost channel layers 350 of adjacent channel layer structures 212. This allows for the formation of source / drain doped layers of sufficient size, further ensuring the mobility of the semiconductor structure.

[0115] In this embodiment, in the step of forming a second stacked structure 221 located at the bottom of the first stacked structure 211 by the third sacrificial layer 330 and the isolation layer 340 at the bottom of the patterned channel layer structure 212, the bottommost isolation layer 340 of the adjacent isolation stacks 222 are connected.

[0116] The groove 400 extends through the isolation stack 222, while retaining the bottom isolation layer 340 of the adjacent isolation stack 222 connected. This ensures that while the groove 400 extends to a greater depth in the isolation stack 222, the bottom isolation layer 340 of the adjacent isolation stack 222 is connected. Thus, the isolation layer 340 is retained on the substrate 100 between the adjacent channel layer structures 212, so that the source and drain doped layers formed on the substrate 100 between the adjacent channel layer structures 212 are isolated from the substrate 100, thereby helping to reduce the leakage probability between the source and drain doped layers and the substrate 100.

[0117] refer to Figure 10 A source / drain doped layer 500 is formed in the groove 400, and the source / drain doped layer 500 is in contact with the end of the channel layer structure 212.

[0118] The source / drain doped layer 500 is used as the source or drain region of the transistor. Specifically, the doping type of the source / drain doped layer 500 is the same as the channel conductivity type of the corresponding transistor.

[0119] In this embodiment, the verticality of the sidewalls of the channel layer structure 212 is good. Correspondingly, there is sufficient space between the bottommost channel layer 350 of the adjacent channel layer structures 212 to form a source / drain doped layer 500 of sufficient size, which is beneficial to ensuring the mobility of the semiconductor structure and thus to ensuring the performance of the semiconductor structure.

[0120] Reference Figure 11 After the isolation stack 222 is formed between the channel layer structure 212 and the substrate 100, the forming method further comprises: removing the dummy gate structure 200 to expose the first stack structure 211 and the second stack structure 221.

[0121] The removal of the dummy gate structure 200 exposes the first stack structure 211 and the second stack structure 221, and prepares for the removal of the first sacrificial layer 310 and the third sacrificial layer 330.

[0122] With reference to Figure 11 After the removal of the dummy gate structure 200, the forming method further comprises: removing the first sacrificial layer 310 in the first stack structure 211 to form a second trench 420 exposing the channel layer 350.

[0123] The second trench 420 is used to provide a spatial position for the subsequent formation of a gate structure.

[0124] In this embodiment, the first sacrificial layer 310 is removed by a wet etching process.

[0125] The wet etching process has relatively low cost and simple operation steps, and can also achieve a large etching selectivity, which is conducive to reducing the damage to the channel layer 350 in the process of removing the first sacrificial layer 310.

[0126] In this embodiment, the step of removing the first sacrificial layer 310 in the first stack structure 211 further comprises: removing the third sacrificial layer 330 in the second stack structure 221 to form a third trench 430 exposing the isolation layer 340.

[0127] The third trench 430 is used to provide a spatial position for the subsequent formation of a gate structure.

[0128] In this embodiment, the third sacrificial layer 330 is removed by a wet etching process.

[0129] The wet etching process has relatively low cost and simple operation steps, and can also achieve a large etching selectivity, which is conducive to reducing the damage to the channel layer 350 in the process of removing the third sacrificial layer 330.

[0130] In this embodiment, the first sacrificial layer 310 and the third sacrificial layer 330 are made of the same material, so that the first sacrificial layer 310 and the third sacrificial layer 330 can be removed in the same step, which simplifies the process steps and improves the process efficiency.

[0131] With reference to Figure 12 The gate structure 600 is formed to span the channel layer structure 212 and fill the second trench 420, and the gate structure 600 surrounds the channel layer 350.

[0132] The gate structure 600 is used to control the opening and closing of the channel of the transistor.

[0133] The gate structure 600 surrounds the channel layer 350, thus, the top, bottom and sidewall of the channel layer 350 can all serve as the channel, increasing the area of the channel layer 350 used as the channel, thereby increasing the working current of the semiconductor structure.

[0134] Specifically, in this embodiment, the gate structure 600 includes a gate dielectric layer surrounding the channel layer 350 along the extending direction of the gate structure 600, and a gate electrode layer on the gate dielectric layer.

[0135] The gate dielectric layer is used to isolate the gate electrode layer from the channel layer 350 and the substrate 100.

[0136] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2and La2O3. In this embodiment, the gate dielectric layer includes a high-k gate dielectric layer, and the material of the high-k gate dielectric layer includes a high-k dielectric material. Specifically, the material of the high-k gate dielectric layer includes HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO or Al2O3, etc.

[0137] It should be noted that the gate dielectric layer can also include a gate oxide layer, which is between the high-k gate dielectric layer and the channel layer 350. Specifically, the material of the gate oxide layer can be silicon oxide.

[0138] In this embodiment, the gate structure 600 is a metal gate structure, thus, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN and TiAlC.

[0139] Specifically, the gate electrode layer includes a work function layer (not shown) and an electrode layer (not shown) on the work function layer. The work function layer is used to adjust the threshold voltage of the transistor, and the electrode layer is used to lead out the electrical property of the metal gate structure.

[0140] In other embodiments, the gate electrode layer can also only include the work function layer.

[0141] In this embodiment, in the step of forming the gate structure 600 across the channel layer structure 212 and filling the second trench 420, the gate structure 600 also crosses the isolation layer 340 and fills in the third trench 430.

[0142] The gate structures 600 across the isolation stack 340 and filled in the third trenches 430 do not function as working, and the gate structures 600 filled between the longitudinally adjacent isolation layers 340 make the plurality of isolation layers 340 longitudinally spaced, constituting the isolation stack 222.

[0143] Although the present application has been disclosed with reference to the above embodiments, the present application is not limited to the above examples. Any person skilled in the art can make various modifications and changes without departing from the spirit and scope of the present application, and the scope of protection of the present application should be defined by the scope of claims.

Claims

1. A semiconductor structure, characterized in that, include: Base; An isolation stack is located on the substrate, the isolation stack comprising a plurality of isolation layers spaced apart along the longitudinal direction; A channel layer structure is located on the isolation stack. The channel layer structure includes a plurality of longitudinally spaced channel layers. The sidewalls of adjacent channel layer structures form a groove that extends longitudinally through the channel layer structure and into the isolation stack.

2. The semiconductor structure as described in claim 1, characterized in that, The groove extends longitudinally to expose the bottommost insulating layer.

3. The semiconductor structure as described in claim 1, characterized in that, The groove does not penetrate the isolation stack so that the bottommost isolation layer in the adjacent isolation stacks is connected.

4. The semiconductor structure as described in claim 1, characterized in that, The semiconductor structure further includes a gate structure located on the substrate and spanning the channel layer structure, the gate structure surrounding the channel layer and filling the space between longitudinally adjacent channel layers.

5. The semiconductor structure as described in claim 4, characterized in that, The gate structure also spans the isolation stack, surrounds the isolation stack, and fills the spaces between longitudinally adjacent isolation stacks.

6. The semiconductor structure as described in claim 1, characterized in that, The material of the isolation layer includes one or more of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxynitride, and silicon carbonitride.

7. A method for forming a semiconductor structure, characterized in that, include: Provide a base; A channel layer structure is formed suspended above the substrate. The channel layer structure includes a plurality of longitudinally spaced channel layers, and the sidewalls of adjacent channel layer structures form a groove that penetrates the channel layer structure longitudinally. An isolation stack is formed between the channel layer structure and the substrate, the isolation stack comprising a plurality of longitudinally spaced isolation layers, and the groove extending longitudinally into the isolation stack.

8. The method for forming a semiconductor structure as described in claim 7, characterized in that, The step of forming a channel layer structure suspended above the substrate, the channel layer structure comprising a plurality of longitudinally spaced channel layers includes: forming a first material stack suspended above the substrate, the first material stack comprising alternately stacked channel material layers and a first sacrificial layer, wherein the bottom layer of the first material stack is the channel material layer, and the etching resistance of the first sacrificial layer is less than the etching resistance of the channel material layer. The first material stack is graphically represented to form a groove that penetrates the first material stack. The groove divides the first material stack into a plurality of discrete first stack structures, and retains the channel material layer in the first stack structure as the channel layer. The plurality of channel layers in the first stack structure constitute the channel layer structure.

9. The method for forming a semiconductor structure as described in claim 8, characterized in that, Before forming the first material stack suspended above the substrate, the forming method further includes: forming a second material stack covering the substrate, the second material stack including alternately stacked second sacrificial layers and third sacrificial layers, wherein the top and bottom layers of the second material stack are the second sacrificial layers, and the etching resistance of the second sacrificial layer is less than that of the third sacrificial layer; In the step of forming a first material stack suspended above the substrate, the first material stack covers the second material stack; Before graphically representing the first material stack, the forming method further includes: forming the isolation layer at the location of the second sacrificial layer; The step of graphically representing the first material stack further includes: graphically representing the third sacrificial layer and the isolation layer at the bottom of the channel layer structure to form a second stack structure located at the bottom of the first stack structure, wherein a plurality of isolation layers in the second stack structure constitute the isolation stack, and the groove extends longitudinally into the isolation stack.

10. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming a second material stack covering the substrate, the third sacrificial layer is made of the same material as the first sacrificial layer.

11. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of graphically representing the third sacrificial layer and the isolation layer at the bottom of the channel layer structure to form a second stacked structure located at the bottom of the first stacked structure, the groove extends longitudinally into the bottommost isolation layer and exposes the isolation layer.

12. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of graphically representing the third sacrificial layer and the isolation layer at the bottom of the channel layer structure to form a second stacked structure located at the bottom of the first stacked structure, the bottommost isolation layer of the adjacent isolation stacks is connected.

13. The method for forming a semiconductor structure as described in claim 9, characterized in that, The step of forming the isolation layer at the location of the second sacrificial layer includes: removing the second sacrificial layer to form a first trench exposing the bottom of the first material stack, the top surface of the substrate, and the third sacrificial layer in the second material stack; An isolation layer is formed to fill the first trench.

14. The method for forming a semiconductor structure as described in claim 9, characterized in that, Before forming the isolation layer at the location of the second sacrificial layer, the forming method further includes: forming a pseudo-gate structure spanning the first material stack and the second material stack, the pseudo-gate structure covering a portion of the top and a portion of the sidewalls of the first material stack, and covering a portion of the sidewalls of the second material layer; In the step of graphically representing the first material stack, the first material stack is graphically represented along the pseudo-gate structure, and the first material stacks on both sides of the pseudo-gate structure are removed. After forming an isolation stack between the channel layer structure and the substrate, the forming method further includes: removing the pseudo-gate structure to expose the first stack structure and the second stack structure.

15. The method for forming a semiconductor structure as described in claim 14, characterized in that, After removing the pseudo-gate structure, the forming method further includes: removing the first sacrificial layer in the first stacked structure to form a second trench exposing the channel layer; A gate structure is formed that spans the channel layer structure and fills the second trench, the gate structure surrounding the channel layer.

16. The method for forming a semiconductor structure as described in claim 15, characterized in that, The step of removing the first sacrificial layer in the first stacked structure further includes: removing the third sacrificial layer in the second stacked structure to form a third trench exposing the isolation layer; In the step of forming a gate structure that spans the channel layer structure and fills the second trench, the gate structure also spans the isolation stack and fills the third trench.

17. The method for forming a semiconductor structure as described in claim 8, characterized in that, An epitaxial growth process is used to form a first material stack suspended above the substrate.

18. The method for forming a semiconductor structure as described in claim 8, characterized in that, In the step of forming a first material stack suspended above the substrate, the material of the first sacrificial layer includes silicon germanide, and the material of the channel material layer includes silicon.

19. The method for forming a semiconductor structure as described in claim 9, characterized in that, A second material stack covering the substrate is formed using an epitaxial growth process.

20. The method for forming a semiconductor structure as described in claim 9, characterized in that, In the step of forming a second material stack covering the substrate, the material of the second sacrificial layer includes silicon germanide, and the material of the third sacrificial layer includes silicon germanide, wherein the molar concentration of germanium in the second sacrificial layer is greater than the molar concentration of germanium in the third sacrificial layer.

Images