Cascode device based on conversion from pGaN to UGaN and preparation method thereof
By introducing a pGaN to UGaN structure into the Cascode device, the problems of gate leakage and threshold voltage drift are solved, thereby improving the stability and reliability of the device.
Patent Information
- Application Number
- CN202511019561.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-23
- Publication Date
- 2025-11-04
AI Technical Summary
In existing Cascode devices, the gate metal of D-mode HEMT devices is in direct contact with the barrier layer, resulting in large gate leakage current. Furthermore, the threshold voltage drift is significant after the addition of an insulating dielectric layer, which affects the stability of the device.
A pGaN-to-UGaN structure is adopted, in which UGaN is placed between the gate metal and the barrier layer, and unintentionally doped GaN is formed by hydrogen annealing. This reduces gate leakage current, lowers interface trap density, and controls threshold voltage drift.
It effectively reduces gate leakage current and improves device stability. The interface trap density between UGaN and the barrier layer is lower than that of the insulating layer dielectric, ensuring that the device is more stable during operation.
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Figure CN120897504A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The application belongs to the technical field of semiconductors, and particularly relates to a Cascode device based on pGaN conversion UGaN and a preparation method thereof. BACKGROUND
[0002] The Cascode device, namely a common-source common-gate device, is a circuit structure in which two or more transistors are connected in a specific manner. The Cascode structure can effectively solve the problems of parasitic inductance and capacitance, insufficient gate voltage safety margin, limited high-frequency performance and complex packaging in the traditional cascade structure by integrating a low-voltage enhancement-mode (E-mode) GaN device and a high-voltage depletion-mode (D-mode) GaN device.
[0003] In recent years, GaN (gallium nitride) has become an important material for a new generation of power devices due to its high critical breakdown field, high electron mobility and high operating temperature, etc. as a third-generation semiconductor material. In particular, the Cascode structure integrating a low-voltage enhancement-mode (E-mode) GaN device and a high-voltage depletion-mode (D-mode) GaN device together optimizes device performance, reduces parasitic effects, improves voltage safety margin and simplifies packaging design, thereby providing a more optimal power conversion solution for modern electronic systems.
[0004] Generally, the gate metal of the D-mode HEMT (high electron mobility transistor) device in the Cascode device is deposited on the barrier layer, and the direct contact between the gate metal and the barrier layer results in a large gate leakage. The commonly used method to reduce the leakage is to add an insulating layer medium between the gate metal and the barrier layer in the D-mode, which can reduce the leakage through the insulating layer medium. However, the addition of the insulating layer medium causes the threshold voltage to drift, resulting in a large threshold voltage offset during device operation, which affects the stability of the device operation. SUMMARY
[0005] In order to solve the above problems in the prior art, the application provides a Cascode device based on pGaN conversion UGaN and a preparation method thereof. The technical problems to be solved by the application are solved by the following technical solutions. In a first aspect, the application provides a Cascode device based on pGaN conversion UGaN, which comprises a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a first passivation layer, a second passivation layer, a third step passivation layer, pGaN, UGaN, ohmic metal, gate metal and interconnection metal. The substrate, the nucleation layer, the buffer layer, the channel layer, the barrier layer, the first passivation layer, the second passivation layer and the third passivation layer are sequentially stacked, the pGaN and the UGaN are located on the barrier layer, the gate metal is deposited on the pGaN and the UGaN respectively, and the ohmic metal is deposited in the source and drain regions and is in contact with the inside of the channel layer. In an embodiment of the present application, the gate includes the pGaN and the gate metal on the pGaN, and the Schottky gate includes the UGaN and the gate metal on the UGaN. The two ohmic metals are the source ohmic metal and the drain ohmic metal respectively, the ohmic metal close to the pGaN side is the source ohmic metal, and the ohmic metal close to the UGaN side is the drain ohmic metal. The device further includes the interconnection metal, the interconnection metal is deposited on the second passivation layer, one end of the interconnection metal is connected with the source ohmic metal, and the other end of the interconnection metal is connected with the gate metal on the UGaN.
[0006] In an embodiment of the present application, the device further includes the active region, and the region between the two ohmic metals outside is referred to as the active region. The device further includes the two ion implantation regions, the ion implantation regions are located on the two sides of the active region respectively, and the ion implantation regions are vertically from the first passivation layer to the inside of the channel layer.
[0007] In an embodiment of the present application, the substrate is one of sapphire, SiC, Si and GaN.
[0008] In an embodiment of the present application, the nucleation layer is one of GaN, AlN and AlGaN.
[0009] In an embodiment of the present application, the buffer layer is one or more of GaN, AlN and AlGaN.
[0010] In an embodiment of the present application, the channel layer is one of GaN, AlN and AlGaN.
[0011] In an embodiment of the present application, the barrier layer is AlGaN or AlN.
[0012] In an embodiment of the present application, an insertion layer for improving the carrier mobility can be inserted between the barrier layer and the channel layer, and the material of the insertion layer includes AlN, InAlN and AlGaN.
[0013] In a second aspect, the present application provides a preparation method of the Cascode device based on the conversion of the pGaN to the UGaN, which is applied to the Cascode device based on the conversion of the pGaN to the UGaN provided in the above-mentioned scheme, and the method includes: The substrate is provided, the nucleation layer is deposited and grown on the substrate by using the MOCVD process; On the nucleation layer, a buffer layer and a channel layer are deposited in sequence by using a MOCVD process; On the channel layer, a barrier layer is deposited by using a MOCVD process; On the barrier layer, a pGaN layer is grown by using a MOCVD process; The pGaN layer is etched by using a mask, and two pGaN structures required by the gate and the Schottky gate are left; A SiO2 layer is grown on the barrier layer and the pGaN; A photolithography pattern is transferred to the SiO2 layer as a hard mask, and the pGaN required by the Schottky gate is exposed, and annealing is performed in a hydrogen environment, so that hydrogen ions combine with magnesium ions in the pGaN required by the Schottky gate to form a UGaN structure; An ALD device or a PECVD device is used to grow a first passivation layer on the surfaces of the barrier layer, the pGaN and the UGaN; A mask is made on the epitaxial layer, and ion implantation is performed on the regions other than the active region; A mask is made on the first passivation layer, and a gate window and a Schottky gate window are formed, the gate window corresponds to the pGaN, and the Schottky gate window corresponds to the UGaN; The first passivation layer in the gate window and the Schottky gate window is etched, the sample is placed in an electron beam evaporation reaction chamber, an electron beam evaporation process is used to deposit a gate metal layer on the surface, a mask is used to etch the excess metal, and the gate metal required by the gate and the Schottky gate is left, the gate metal layer is a metal stack structure composed of TiN, Ti, Al and TiN in four layers; Two ohmic windows are formed by using a mask, the two ohmic windows are etched, and the etching depth stops at the channel layer, after etching, the sample is placed in an electron beam evaporation device, an electron beam evaporation process is used to deposit an ohmic metal layer on the surface, a mask is used to etch the excess metal, and the source ohmic metal and the drain ohmic metal are left, and annealing is performed at 500°C for 1 min to form a low-temperature ohmic contact, a first device structure is formed, and the ohmic metal layer is a Ti / Al-based metal combination; An ALD device or a PECVD device is used to grow a second passivation layer on the surface of the first device structure; The source ohmic metal and the Schottky gate gate metal window on the second passivation layer are opened by using a mask to obtain an interconnection metal window, the second passivation layer in the interconnection metal window is etched, the sample is placed in an electron beam evaporation device, an electron beam evaporation process is used to deposit an ohmic metal layer on the surface, a mask is used to etch the excess metal to obtain an interconnection metal, and a second device structure is formed, and the interconnection metal is a Ti / Al-based metal combination; A third passivation layer is grown on the surface of the second device structure using an ALD apparatus or a PECVD apparatus.
[0014] Compared with the prior art, the application has the following beneficial effects: In the above scheme of the application, the cascode device includes a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a first passivation layer, a second passivation layer, a third passivation layer, a pGaN, a UGaN, an ohmic metal, a gate metal, and an interconnection metal; the substrate, the nucleation layer, the buffer layer, the channel layer, the barrier layer, the first passivation layer, the second passivation layer, and the third passivation layer are designed in a stacked manner, the pGaN and the UGaN are both located on the barrier layer, the gate metal is deposited on the surfaces of the pGaN and the UGaN, respectively, the ohmic metal is deposited on the source and drain regions and contacts the inside of the channel layer, and the ohmic metal contacts the barrier layer, the first passivation layer, and the second passivation layer, the interconnection metal is deposited on the second passivation layer, one end of the interconnection metal is connected to the source ohmic metal, and the other end of the interconnection metal is connected to the gate metal on the UGaN. With this structure, the UGaN is arranged between the gate metal and the barrier layer, and the UGaN can reduce the gate current. Compared with the structure in which an insulating layer medium is arranged, the good interface state between the UGaN and the barrier layer is more friendly to the drift of the threshold voltage, the interface trap density between the UGaN and the barrier layer is much lower than the interface trap density between the insulating layer medium and the barrier layer, the threshold voltage of the device can be effectively controlled, and the device works more stably.
[0015] The application will be further described in detail below with reference to the accompanying drawings and embodiments. SCHEMATIC DRAWINGS
[0016] Figure 1 is a schematic diagram of a cascode device provided by an embodiment of the application; Figure 2 is a schematic diagram of etching a pGaN layer in an embodiment of the application; Figure 3 is a schematic diagram of forming two pGaN after etching a pGaN layer in an embodiment of the application; Figure 4 is a schematic diagram of growing a SiO2 layer in an embodiment of the application; Figure 5 is a schematic diagram of forming a UGaN in an embodiment of the application; Figure 6 is a schematic diagram of cleaning a SiO2 layer in an embodiment of the application; Figure 7 is a schematic diagram of growing a first passivation layer in an embodiment of the application; Figure 8 is a schematic diagram of ion implantation in an embodiment of the application; Figure 9is a schematic diagram after depositing gate metal in the embodiment of the present application; Figure 10 is a schematic diagram after depositing ohmic metal in the embodiment of the present application; Figure 11 is a schematic diagram when growing a second passivation layer in the embodiment of the present application; Figure 12 is a schematic diagram after depositing interconnection metal in the embodiment of the present application; Figure 13 is a schematic diagram when growing a third passivation layer in the embodiment of the present application. DETAILED DESCRIPTION
[0017] The present application will be further described in conjunction with specific embodiments, but the embodiments of the present application are not limited thereto.
[0018] Embodiment one: Please refer to Figure 1 The embodiment of the present application provides a Cascode device based on pGaN conversion UGaN, which comprises a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, a first passivation layer 9, a second passivation layer 15, a third passivation layer 17, a pGaN 6, a UGaN 7, ohmic metal, gate metal, interconnection metal 16, the ohmic metal comprises source ohmic metal 13 and drain ohmic metal 14, and the gate metal comprises gate metal 11 and Schottky gate metal 12; the substrate 1, the nucleation layer 2, the buffer layer 3, the channel layer 4, the barrier layer 5, the first passivation layer 9, the second passivation layer 15 and the third passivation layer 17 are designed in sequence, the pGaN 6 and the UGaN 7 are located on the barrier layer 5, the gate metal is deposited on the surface of the pGaN 6 and the UGaN 7, the ohmic metal is deposited in the source and drain regions and contacts the inside of the channel layer 4, and the ohmic metal contacts the barrier layer 5, the first passivation layer 9 and the second passivation layer 15, the interconnection metal 16 is deposited on the second passivation layer 15, one end of the interconnection metal is connected with the source ohmic metal 13, and the other end is connected with the gate metal on the UGaN.
[0019] In some embodiments of the present application, only the basic structure of the Cascode is described in the embodiment, and the field plate structure and the passivation layer can be realized on the basis.
[0020] In some embodiments of the present application, the Cascode structure in the present embodiment is applied in the field of power electronics, mainly applied in the fields of 5G communication, new energy vehicles, data center power supply, renewable energy systems, fast charging technology, industrial motor drives, aerospace and defense, etc. This integrated solution can meet the needs of high efficiency, high frequency, high power density and high reliability in these fields, optimize device performance, reduce parasitic effects, improve voltage safety margin and simplify packaging design, providing a better power conversion solution for modern electronic systems.
[0021] In the above scheme of the present application, the Cascode device includes a substrate 1, a nucleation layer 2, a buffer layer 3, a channel layer 4, a barrier layer 5, a first passivation layer 9, a second passivation layer 15, a third passivation layer 17, a pGaN 6, a UGaN 7, an ohmic metal, a gate metal, and an interconnection metal 16; the substrate 1, the nucleation layer 2, the buffer layer 3, the channel layer 4, the barrier layer 5, the first passivation layer 9, the second passivation layer 15, and the third passivation layer 17 are designed in sequence, the pGaN 6 and the UGaN 7 are located on the barrier layer 5, the gate metal is deposited on the surface of the pGaN 6 and the UGaN 7, the ohmic metal is deposited in the source and drain regions and contacts the inside of the channel layer 4, and simultaneously contacts the barrier layer 5, the first passivation layer 9, and the second passivation layer 15, the interconnection metal 16 is deposited on the second passivation layer 15, one end of the interconnection metal is connected with the source ohmic metal 13, and the other end is connected with the gate metal 12 on the UGaN. With this structure, the present application sets the UGaN 7 between the gate metal and the barrier layer 5, which can reduce the gate current. Compared with the existing structure with an insulating layer medium, the good interface state between the UGaN 7 and the barrier layer 5 in the present application is more friendly to the drift of the threshold voltage, and the interface trap density between the UGaN structure 7 and the barrier layer 5 is much lower than that between the insulating layer medium and the barrier layer, which can effectively control the threshold voltage of the device, making the device work more stably.
[0022] It can be understood that the pGaN epitaxial layer is used skillfully in the present application, and the pGaN is reserved between the D-mode gate metal and the barrier layer, and the pGaN is converted into unintentionally doped GaN (UGaN) through hydrogen annealing. This structure effectively reduces the gate leakage current compared with the existing structure, and the interface trap density between the UGaN and the barrier layer is much lower than that between the insulating layer medium and the barrier layer, which can effectively control the threshold voltage of the device, making it stable.
[0023] In one embodiment of the present application, as shown in Figure 1 The gate electrode includes a pGaN and a gate metal on the pGaN, and the Schottky gate electrode includes a UGaN and a gate metal on the UGaN.
[0024] In an embodiment of the present application, the two ohmic metals are source ohmic metal 13 and drain ohmic metal 14, respectively. The ohmic metal close to the pGaN side is the source ohmic metal 13, and the ohmic metal close to the UGaN side is the drain ohmic metal 14.
[0025] In an embodiment of the present application, as shown in Figure 1 , it further includes interconnection metal 16. The interconnection metal 16 is deposited on the second passivation layer, one end of the interconnection metal 16 is connected with the source ohmic metal 13, and the other end is connected with the gate metal on the UGaN.
[0026] In an embodiment of the present application, as shown in Figure 1 , it further includes an active region. The region between the two ohmic metals on the outside is called the active region.
[0027] In an embodiment of the present application, as shown in Figure 1 , it further includes two ion implantation regions 10. The ion implantation regions 10 are located on both sides of the active region, and the ion implantation regions 10 vertically start from the first passivation layer 9 and end inside the channel layer 4.
[0028] In some embodiments of the present application, the substrate is one of sapphire, SiC, Si and GaN.
[0029] In some embodiments of the present application, the nucleation layer is one of GaN, AlN and AlGaN.
[0030] In some embodiments of the present application, the buffer layer is one or more of GaN, AlN and AlGaN.
[0031] In some embodiments of the present application, the channel layer is one of GaN, AlN and AlGaN.
[0032] In some embodiments of the present application, the barrier layer is AlGaN or AlN, and the Al component x is variable.
[0033] In some embodiments of the present application, an insertion layer for improving carrier mobility is provided between the barrier layer and the channel layer, and the material of the insertion layer includes but is not limited to AlN, InAlN and AlGaN.
[0034] Embodiment two: Please refer to Figures 2 to 13 , the embodiment of the present application further provides a preparation method of the Cascode device based on the conversion of pGaN to UGaN, which is applied to the Cascode device based on the conversion of pGaN to UGaN provided in the above-mentioned scheme, and the method comprises: A substrate 1 is provided, and a nucleation layer 2 is deposited and grown on the substrate 1 using MOCVD process. The nucleation layer 2 is made of AlN and has a thickness of 10nm~500nm. On the nucleation layer 2, a buffer layer 3 and a channel layer 4 are sequentially deposited using MOCVD process. The buffer layer 3 is made of GaN and has a thickness of 2μm to 8μm. The channel layer 4 is also made of GaN and has a thickness of 10nm to 500nm. On the channel layer 4, a barrier layer 5 is deposited using MOCVD process. The composition of the barrier layer 5 is AlxGa(1-x)N, and the Al composition in the AlxGa(1-x)N barrier layer 5 is 0.1~0.5, with a deposition thickness of 10nm~50nm. like Figure 2 As shown, a pGaN layer is deposited on barrier layer 5 using MOCVD process, and the thickness of the pGaN layer is 50nm~200nm. like Figure 3 As shown, the pGaN layer is etched using a mask to leave two pGaN islands required for the gate and Schottky gate regions; like Figure 4 As shown, SiO2 layer 8 is grown on barrier layer 5 and pGaN island; like Figure 5 As shown, the photolithographic pattern is transferred onto the SiO2 layer 8 as a hard mask, exposing the pGaN required for the Schottky gate. Annealing is then performed in a hydrogen atmosphere, allowing hydrogen ions to combine with magnesium ions in the pGaN to form UGaN 7. Figure 6 This diagram shows a schematic of the SiO2 layer 8 after cleaning in this embodiment; like Figure 7 As shown, a first passivation layer 9 is grown on the surface of barrier layer 5, pGaN 6 and UGaN 7 using an ALD device or a PECVD device. like Figure 8 As shown, a mask is fabricated on the epitaxial layer, and ion implantation is performed on the region outside the active region to obtain the ion implantation region 10. like Figure 9 As shown, a mask is fabricated on the first passivation layer 9, and a gate window and a Schottky gate window are formed thereon. The gate window corresponds to pGaN 6, and the Schottky gate window corresponds to UGaN 7. like Figure 9As shown, the first passivation layer inside the gate window and the Schottky gate window is etched. The sample is placed in the E-Beam electron beam evaporation reaction chamber. The gate metal layer is deposited on the surface using electron beam evaporation. The excess metal is etched off using a mask, leaving the gate metal 11 and the Schottky gate metal 12. The gate metal layer is a four-layer metal stack structure composed of TiN, Ti, Al and TiN respectively. The thicknesses of TiN, Ti, Al and TiN are 40nm, 20nm, 250nm and 30nm respectively. like Figure 10 As shown, two ohmic windows are formed by a mask, and the two ohmic windows are etched. The etching depth stops at the channel layer. After etching, the sample is placed in an E-Beam electron beam evaporation device. Using electron beam evaporation, an ohmic metal layer is deposited on the surface. The excess metal is etched away using a mask, leaving the source ohmic metal 13 and the drain ohmic metal 14. The sample is then annealed at 500°C for 1 minute to form a low-temperature ohmic contact, thus forming the first device structure. The ohmic metal layer is a Ti / Al based metal combination, where the thickness of Ti is 20 nm and the thickness of Al is 200 nm. like Figure 11 As shown, a second passivation layer 15 is grown on the surface of the first device structure using an ALD device or a PECVD device. like Figure 12 As shown, the source ohmic metal and Schottky gate metal windows are opened on the second passivation layer through a mask to obtain the interconnect metal window. The second passivation layer inside the interconnect metal window is etched. The sample is placed in an E-Beam electron beam evaporation device, and an ohmic metal layer is deposited on the surface using the electron beam evaporation process. The excess metal is etched off using a mask to obtain the interconnect metal 16 and form the second device structure. The interconnect metal is a Ti / Al based metal combination. like Figure 13 As shown, a third passivation layer 17 is grown on the surface of the second device structure using an ALD device or a PECVD device.
[0035] In some embodiments of this application, the etching process can be either wet etching or dry etching.
[0036] In some embodiments of this application, the metal etching process can be replaced by a metal stripping process.
[0037] In some embodiments of this application, the metal thickness can be adjusted according to the differences between devices.
[0038] In some embodiments of this application, the metal annealing temperature is appropriately adjusted according to the differences between the equipment.
[0039] In some embodiments of the present application, the interconnect metal 16 can be replaced with other metal combinations based on Ni / Au.
[0040] In some embodiments of the present application, the hard mask SiO2may be replaced with photoresist, nitride or oxide.
[0041] In some embodiments of the present application, the passivation layer can be replaced with SiO2, SiN, Al2O3.
[0042] In some embodiments of the present application, the Cascode fabrication process sequence can be changed, the deposition sequence of gate metal and ohmic metal can be exchanged, the metal combination of Ti / Al / Ni / Au can be used to form high-temperature ohmic contact at 850°C for 30s, and then etching of the gate region and deposition of gate metal are performed.
[0043] In the description of the present application, it needs to be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.
[0044] In addition, the terms "first", "second" are only for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, the features defined with "first", "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise explicitly specified and limited.
[0045] In the present application, unless otherwise explicitly specified and limited, "on" or "under" of the first feature to the second feature can include that the first and second features are in direct contact, or can include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, "on", "above" and "over" of the first feature to the second feature includes that the first feature is directly above and obliquely above the second feature, or only indicates that the horizontal height of the first feature is higher than that of the second feature. "Below", "under" and "underneath" of the first feature to the second feature includes that the first feature is directly below and obliquely below the second feature, or only indicates that the horizontal height of the first feature is less than that of the second feature.
[0046] The above is further detailed description of the present application in combination with specific preferred embodiments, and cannot be deemed as limitation of the specific implementation of the present application to these descriptions. For those skilled in the art to which the present application belongs, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, and all of them shall be deemed as falling within the protection scope of the present application.
Claims
1. A Cascode device based on pGaN to UGaN conversion, characterized in that, It includes a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer, a first passivation layer, a second passivation layer, a third passivation layer, an ohmic metal, a gate metal, pGaN, and UGaN; The substrate, nucleation layer, buffer layer, channel layer, barrier layer, first passivation layer, second passivation layer and third passivation layer are stacked sequentially. The pGaN and UGaN are both located on the barrier layer. Gate metal is deposited on the pGaN and UGaN respectively. Ohmic metal is deposited in the source and drain regions and contacts the inside of the channel layer.
2. The Cascode device based on pGaN to UGaN conversion according to claim 1, characterized in that, The device includes a gate and a Schottky gate, the gate including pGaN and gate metal on pGaN, and the Schottky gate including UGaN and gate metal on UGaN; The two ohmic metals are the source ohmic metal and the drain ohmic metal, respectively. The ohmic metal closer to the pGaN side is the source ohmic metal, and the ohmic metal closer to the UGaN side is the drain ohmic metal. The device also includes interconnect metal deposited on a second passivation layer, with one end of the interconnect metal connected to the source ohmic metal and the other end connected to the gate metal on UGaN.
3. The Cascode device based on pGaN to UGaN conversion according to claim 1, characterized in that, The region between the outer sides of two ohmic metals is called the active region; The device also includes two ion implantation regions located on either side of the active region. The ion implantation regions extend vertically from the first passivation layer to the interior of the channel layer.
4. The Cascode device based on pGaN to UGaN conversion according to claim 1, characterized in that, The substrate is one of sapphire, SiC, Si, and GaN.
5. The Cascode device based on pGaN to UGaN conversion according to claim 1, characterized in that, The nucleation layer is one of GaN, AlN, and AlGaN.
6. The Cascode device based on pGaN to UGaN conversion according to claim 1, characterized in that, The buffer layer is one or more of GaN, AlN, and AlGaN.
7. The Cascode device based on pGaN to UGaN conversion according to claim 1, characterized in that, The channel layer is one of GaN, AlN, and AlGaN.
8. The Cascode device based on pGaN to UGaN conversion according to claim 1, characterized in that, The barrier layer is AlGaN or AlN.
9. The Cascode device based on pGaN to UGaN conversion according to claim 1, characterized in that, An insert layer for improving carrier mobility may be inserted between the barrier layer and the channel layer, and the insert layer may be made of materials including AlN, InAlN and AlGaN.
10. A method for fabricating a Cascode device based on pGaN-to-UGaN conversion, characterized in that, The method, applied to a Cascode device based on pGaN-to-UGaN conversion as described in any one of claims 1 to 9, comprises: A substrate is provided, and a nucleation layer is deposited and grown on the substrate using an MOCVD process; A buffer layer and a channel layer are sequentially deposited on the nucleation layer using an MOCVD process; A barrier layer is deposited on the channel layer using an MOCVD process; A pGaN layer is deposited and grown on the barrier layer using MOCVD technology; The pGaN layer is etched using a mask to leave the two pGaN structures required for the gate and Schottky gate regions; A SiO2 layer is grown on the barrier layer and the pGaN; The photolithographic pattern is transferred onto the SiO2 layer as a hard mask to expose the pGaN required for the Schottky gate. Annealing is performed in a hydrogen atmosphere to allow hydrogen ions to combine with magnesium ions in the pGaN required for the Schottky gate, thus transforming it into UGaN. A first passivation layer is grown on the surface of the barrier layer, pGaN and UGaN using an ALD device or a PECVD device. A mask is fabricated on the epitaxial layer to perform ion implantation on the region outside the active region; A mask is fabricated on the first passivation layer to form a gate window and a Schottky gate window, wherein the gate window corresponds to the pGaN and the Schottky gate window corresponds to the UGaN; The first passivation layer inside the gate window and the Schottky gate window is etched. The sample is placed in the electron beam evaporation reaction chamber. The gate metal layer is deposited on the surface using the electron beam evaporation process. The excess metal is etched away using a mask, leaving the gate metal required for the gate and Schottky gate regions. The gate metal layer is a four-layer metal stack structure composed of TiN, Ti, Al and TiN respectively. Two ohmic windows are formed by a mask, and the two ohmic metal windows are etched. The etching depth stops inside the channel layer. After etching, the sample is placed in an electron beam evaporation device. An ohmic metal layer is deposited on the surface using an electron beam evaporation process. Excess metal is etched away using a mask, leaving the source ohmic metal and drain ohmic metal. The sample is then annealed at 500°C for 1 minute to form a low-temperature ohmic contact, thus forming the first device structure. The ohmic metal layer is a Ti / Al based metal combination. A second passivation layer is grown on the surface of the first device structure using an ALD or PECVD device. By using a mask to open the source ohmic metal and Schottky gate metal windows on the second passivation layer, an interconnect metal window is obtained. The second passivation layer inside the interconnect metal window is etched. The sample is placed in an electron beam evaporation device, and an interconnect metal layer is deposited on the surface using an electron beam evaporation process. Excess metal is etched away using a mask to obtain the interconnect metal and form a second device structure. The interconnect metal is a Ti / Al based metal combination. A third passivation layer is grown on the surface of the second device structure using an ALD or PECVD device.