Integrated passive device, manufacturing method thereof and electronic device

Abstract

The invention discloses an integrated passive device, a manufacturing method thereof and an electronic device. The integrated passive device comprises a substrate, a first capacitor and a second capacitor. The first capacitor is located on one side of the substrate. The second capacitor is located on one side of the first capacitor away from the substrate. The orthographic projection of the second capacitor on the substrate is at least partially overlapped with the orthographic projection of the first capacitor on the substrate. The at least two capacitors in the integrated passive device are arranged in the different film layers, and the orthographic projections of the two capacitors on the substrate are at least partially overlapped, so that the area occupied by the plurality of capacitors in the integrated passive device on a plane can be reduced, and the plane size of the integrated passive device is further reduced.

Description

Technical Field

[0001] This invention relates to the field of electronic technology, and in particular to an integrated passive device and its manufacturing method, as well as electronic devices. Background Technology

[0002] Integrated passive devices (IPDs) reduce device size and manufacturing costs by integrating multiple passive components such as resistors, inductors, and / or capacitors into a single device. With the trend towards miniaturization of integrated circuits, further reducing the size of integrated passive devices has become a hot research topic. Summary of the Invention

[0003] This invention provides an integrated passive device and its manufacturing method, as well as an electronic device, to reduce the size of the device.

[0004] A first aspect of the present invention provides an integrated passive device, comprising:

[0005] Substrate;

[0006] The first capacitor is located on one side of the substrate;

[0007] The second capacitor is located on the side of the first capacitor that is away from the substrate; the orthographic projection of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the first capacitor on the substrate.

[0008] In the integrated passive device provided by the present invention, the first capacitor includes a first electrode plate and a second electrode plate stacked sequentially along a direction away from the substrate; the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the first electrode plate on the substrate have a first overlapping area;

[0009] The second capacitor includes a third electrode plate and a fourth electrode plate stacked sequentially in a direction away from the substrate; the orthographic projection of the fourth electrode plate on the substrate has a second overlapping region with the orthographic projection of the third electrode plate on the substrate; the second overlapping region at least partially overlaps with the first overlapping region.

[0010] In the integrated passive device provided by the present invention, the second overlapping region falls entirely within the range of the first overlapping region; or, the first overlapping region falls entirely within the range of the second overlapping region.

[0011] In the integrated passive device provided by the present invention, the orthographic projection of the second electrode plate on the substrate falls entirely within the orthographic projection of the first electrode plate on the substrate.

[0012] The orthographic projection of the third electrode plate onto the substrate falls entirely within the orthographic projection of the second electrode plate onto the substrate;

[0013] The orthographic projection of the fourth electrode plate onto the substrate falls entirely within the orthographic projection of the third electrode plate onto the substrate.

[0014] In the integrated passive device provided by the present invention, the integrated passive device further includes a third capacitor; the third capacitor includes a fifth plate and a sixth plate;

[0015] The fifth electrode plate is located on the same layer as one of the first, second, third, or fourth electrode plates;

[0016] The sixth electrode is located on the same layer as one of the first, second, third, or fourth electrodes, but on a different layer from the fifth electrode.

[0017] In the integrated passive device provided by the present invention, the capacitance value of the third capacitor is different from the capacitance value of the first capacitor;

[0018] The capacitance value of the third capacitor is different from that of the second capacitor.

[0019] In the integrated passive device provided by the present invention, there is a first gap between the first electrode plate and the second electrode plate; there is a second gap between the third electrode plate and the fourth electrode plate; and there is a third gap between the fifth electrode plate and the sixth electrode plate.

[0020] The third spacing is different from the second spacing;

[0021] The third spacing is different from the first spacing.

[0022] In the integrated passive device provided by the present invention, the second electrode plate is reused as the third electrode plate; the second electrode plate and the first electrode plate constitute the first capacitor, and the second electrode plate and the fourth electrode plate constitute the second capacitor.

[0023] The integrated passive device provided by this invention further includes:

[0024] The first dielectric layer is located on the side of the second capacitor that is away from the substrate;

[0025] A connection layer is located on the side of the first dielectric layer facing away from the substrate; the connection layer includes at least one connection structure; one connection structure is connected to a plate of a capacitor in an integrated passive device through a via at least through the first dielectric layer; the connection structure is used to connect the capacitor to other components.

[0026] The integrated passive device provided by this invention further includes:

[0027] A redistribution layer is located between the second capacitor and the first dielectric layer. The redistribution layer includes a transition structure that corresponds one-to-one with the connection structure. The connection structure is connected to the corresponding transition structure through a via penetrating the first dielectric layer, and is connected to the capacitor plate through the transition structure.

[0028] The second dielectric layer is located between the second capacitor and the redistribution layer; the transition structure is connected to the capacitor plates through a via penetrating the second dielectric layer.

[0029] In the integrated passive device provided by the present invention, the redistribution layer includes a plurality of sub-wiring layers stacked along a direction away from the substrate; a third dielectric layer is disposed between adjacent sub-wiring layers;

[0030] Each adapter structure includes multiple adapter sections disposed in multiple sub-routing layers; two adjacent adapter sections of the same adapter structure located in different sub-routing layers are connected by a via passing through a third dielectric layer located between the two adjacent adapter sections.

[0031] In the integrated passive device provided by the present invention, the integrated passive device further includes at least one inductor and / or at least one resistor.

[0032] The integrated passive device provided by this invention further includes:

[0033] The fourth dielectric layer is located between the first electrode plate and the second electrode plate;

[0034] The fifth dielectric layer is located between the second and third electrodes;

[0035] The sixth dielectric layer is located between the third and fourth plates.

[0036] A second aspect of the present invention provides an electronic device comprising an integrated passive device according to any of the preceding claims.

[0037] In the electronic device provided by this invention, the electronic device is a filter.

[0038] A third aspect of the present invention provides a method for fabricating an integrated passive device, comprising:

[0039] The first capacitor is fabricated on one side of the substrate;

[0040] A second capacitor is fabricated on the side of the first capacitor facing away from the substrate; the orthographic projection of the second capacitor onto the substrate at least partially overlaps with the orthographic projection of the first capacitor onto the substrate.

[0041] The beneficial effects of this invention are as follows:

[0042] This invention provides an integrated passive device and its manufacturing method, as well as an electronic device. The integrated passive device includes a substrate, a first capacitor, and a second capacitor. The first capacitor is located on one side of the substrate. The second capacitor is located on the side of the first capacitor facing away from the substrate. The orthographic projection of the second capacitor onto the substrate at least partially overlaps with the orthographic projection of the first capacitor onto the substrate. By placing at least two capacitors in different film layers in the integrated passive device, and ensuring that the orthographic projections of the two capacitors at least partially overlap on the substrate, the area occupied by multiple capacitors in the integrated passive device on a plane can be reduced, further reducing the planar dimensions of the integrated passive device. Attached Figure Description

[0043] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0044] Figure 1 This is one of the schematic cross-sectional structures of an integrated passive device provided in an embodiment of the present invention;

[0045] Figure 2 A second schematic diagram of the cross-sectional structure of an integrated passive device provided in an embodiment of the present invention;

[0046] Figure 3 This is one of the schematic diagrams of a planar structure for capacitor stacking in an integrated passive device provided in an embodiment of the present invention;

[0047] Figure 4 One of the schematic diagrams of a planar structure in which capacitors are arranged in the same layer in an integrated passive device;

[0048] Figure 5a The third schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0049] Figure 5b Fourth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0050] Figure 5c Fifth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0051] Figure 6 Sixth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0052] Figure 7 This is a second schematic diagram of a planar structure for capacitor stacking in an integrated passive device provided in an embodiment of the present invention;

[0053] Figure 8 Schematic diagram 2 of a planar structure for integrating passive components with capacitors arranged on the same layer;

[0054] Figure 9a Seventh schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0055] Figure 9b Eighth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0056] Figure 9c A schematic diagram of the cross-sectional structure of an integrated passive device provided in an embodiment of the present invention (number nine).

[0057] Figure 9d The tenth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0058] Figure 10a Eleventh schematic diagram of the cross-sectional structure of an integrated passive device provided in an embodiment of the present invention;

[0059] Figure 10b The twelfth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0060] Figure 10c Thirteenth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0061] Figure 10d Fourteenth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention;

[0062] Figure 11 A flowchart illustrating the fabrication method of an integrated passive device provided in an embodiment of the present invention. Detailed Implementation

[0063] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction in the present invention are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of the present invention. The accompanying drawings of the present invention are for illustrative purposes only and do not represent actual proportions.

[0064] Integrated passive devices (IPDs) reduce the size of devices by more than 80% by integrating multiple passive components such as resistors, inductors, and / or capacitors into a single device, thereby reducing device size and manufacturing costs. With the trend towards miniaturization of integrated circuits, further reducing the size of integrated passive devices has become a hot research topic.

[0065] A first aspect of the present invention provides an integrated passive device that can further reduce the device size.

[0066] Figure 1 This is one of the cross-sectional structural schematic diagrams of an integrated passive device provided in an embodiment of the present invention.

[0067] In embodiments of the present invention, such as Figure 1 As shown, the integrated passive device includes: substrate 10, first capacitor 100 and second capacitor 200.

[0068] Substrate 10 is disposed at the bottom of the integrated passive device to support and carry the film layer located thereon. The shape of substrate 10 is adapted to the overall shape of the integrated passive device, and can be square, rectangular, or circular, etc., without limitation. Substrate 10 can be made of substrate materials commonly used in integrated circuit manufacturing processes, such as glass substrate, silicon substrate, or low-temperature co-fired ceramic substrate. Glass substrate has advantages such as lower dielectric loss and low cost and easy availability. In this embodiment of the invention, substrate 10 can specifically be made of glass substrate, without limitation.

[0069] The first capacitor 100 is located on one side of the substrate 10. The first capacitor 100 includes a first electrode 101 and a second electrode 102. The first electrode 101 and the second electrode 102 are stacked sequentially in a direction away from the substrate 10. The materials of the first electrode 101 and the second electrode 102 are both conductive materials, specifically metal materials with good conductivity, such as gold (Au), silver (Ag), copper (Cu), aluminum (Al), or titanium (Ti) and their alloys. Either the first electrode 101 or the second electrode 102 can be a single-layer structure or a multi-layer structure. For example, in some embodiments, the first electrode 101 can be a single-layer Cu metal film structure. For example, in some embodiments, the first electrode 101 can be a Ti / Cu / Ti triple-layer structure with one Ti metal film, one Cu metal film, and one Ti metal film stacked sequentially. The first electrode 101 can also adopt other numbers of stacked structures, which are not limited here. The film structure of the second electrode plate 102 may be the same as or different from the film structure of the first electrode plate 101, and no limitation is made here.

[0070] like Figure 1 As shown, the orthographic projection of the second electrode 102 onto the substrate 10 and the orthographic projection of the first electrode 101 onto the substrate 10 have a first overlapping region S1. Within the first overlapping region S1, the first substrate 101 and the second electrode 102 are disposed opposite each other. It can be understood that, with the spacing and dielectric material remaining unchanged, the larger the area of ​​the first overlapping region S1, that is, the larger the area of ​​the first electrode 101 and the second electrode 102 facing each other, the larger the capacitance value of the first capacitor 100.

[0071] The second capacitor 200 is located on the side of the first capacitor 100 away from the substrate 10. The second capacitor 200 includes a third electrode 201 and a fourth electrode 202. The third electrode 201 and the fourth electrode 202 are stacked sequentially in a direction away from the substrate 10. For either the third electrode 201 or the fourth electrode 202, its material and film structure may be the same as or different from the first electrode 101, which is not limited here.

[0072] like Figure 1 As shown, the orthographic projection of the fourth electrode 202 onto the substrate 10 and the orthographic projection of the third electrode 201 onto the substrate 10 have a second overlapping region S2. Within the second overlapping region S2, the fourth electrode 202 and the third electrode 201 are positioned opposite each other. It can be understood that, given a fixed spacing and dielectric material, the larger the area of ​​the second overlapping region S2, i.e., the larger the area of ​​the fourth electrode 202 and the third electrode 201 facing each other, the larger the capacitance value of the second capacitor 200.

[0073] In embodiments of the present invention, such as Figure 1As shown, the orthographic projection of the second capacitor 200 on the substrate 10 at least partially overlaps with the orthographic projection of the first capacitor 100 on the substrate 10. It should be noted that, specifically, the orthographic projection of the second capacitor 200 on the substrate 10 at least partially overlaps with the orthographic projection of the first capacitor 100 on the substrate 10 in this embodiment of the invention means that the orthographic projection of at least one of the third plate 201 and the fourth plate 202 of the second capacitor 200 on the substrate 10 at least partially overlaps with the orthographic projection of at least one of the first plate 101 and the second plate 102 of the first capacitor 100 on the substrate 10. Specifically, the cases in which the orthographic projection of the second capacitor 200 on the substrate 10 at least partially overlaps with the orthographic projection of the first capacitor 100 on the substrate 10 may include: the orthographic projection of the third electrode 201 on the substrate 10 at least partially overlapping with the orthographic projection of the first electrode 101 on the substrate 10, and / or the orthographic projection of the third electrode 201 on the substrate 10 at least partially overlapping with the orthographic projection of the second electrode 102 on the substrate 10, and / or the orthographic projection of the fourth electrode 202 on the substrate 10 at least partially overlapping with the orthographic projection of the first electrode 101 on the substrate 10, and / or the orthographic projection of the fourth electrode 202 on the substrate 10 at least partially overlapping with the orthographic projection of the second electrode 102 on the substrate 10, etc., are not limited here.

[0074] In the integrated passive device provided in this embodiment of the invention, by disposing of at least two capacitors, such as a first capacitor 100 and a second capacitor 200, in different film layers, and by setting the orthographic projection of the first capacitor 100 on the substrate 10 to at least partially overlap with the orthographic projection of the second capacitor 200 on the substrate 10, the area occupied by multiple capacitors in the integrated passive device on the plane can be reduced, thereby further reducing the planar size of the integrated passive device. It should be noted that the planar size of the integrated passive device described in this embodiment of the invention specifically refers to the side length, diagonal length, or area of ​​the orthographic projection of the integrated passive device on the plane, or other dimensions that characterize the dimensional features of the orthographic projection of the integrated passive device on the plane. This plane is perpendicular to the direction in which the first capacitor 100 and the second capacitor 200 are stacked, and will not be elaborated further in the following content. It is understood that, to further reduce the planar size of the integrated passive device, when the integrated passive device has multiple capacitors, an additional number of capacitors can be stacked along the direction in which the first capacitor 100 and the second capacitor 200 are stacked, which is not limited here.

[0075] In some embodiments, such as Figure 1 As shown, the second overlapping region S2 at least partially overlaps with the first overlapping region S1. That is to say, the orthographic projection of the region directly opposite the fourth electrode 202 and the third electrode 201 on the substrate 10 at least partially overlaps with the orthographic projection of the region directly opposite the second electrode 102 and the first electrode 101 on the substrate 10, which is beneficial to further reduce the planar size of the integrated passive device.

[0076] Figure 2 This is the second schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention.

[0077] In some embodiments, such as Figure 2 As shown, the second overlapping region S2 falls entirely within the range of the first overlapping region S1. That is to say, the orthographic projection of the area directly opposite the fourth electrode 202 and the third electrode 201 on the substrate 10 falls entirely within the orthographic projection of the area directly opposite the second electrode 102 and the first electrode 101 on the substrate 10, which is beneficial to further reduce the planar size of the integrated passive device.

[0078] In some embodiments, the first overlapping region S1 may be configured to fall entirely within the range of the second overlapping region S2. That is, the orthographic projection of the area directly opposite the second electrode 102 and the first electrode 101 onto the substrate 10 falls entirely within the orthographic projection of the area directly opposite the fourth electrode 202 and the third electrode 201 onto the substrate 10. This is beneficial for further reducing the planar size of the integrated passive device, and is not limited here.

[0079] In some embodiments, such as Figure 2 As shown, the orthographic projection of the second electrode 102 onto the substrate 10 falls entirely within the orthographic projection of the first electrode 101 onto the substrate 10. That is, during the fabrication of the second electrode 102, it is entirely formed on the surface of the first electrode 101. The relatively flat surface of the first electrode 101 helps improve the flatness of the second electrode 102, thereby ensuring a uniform spacing between the first electrode 101 and the second electrode 102, and consequently making the capacitance value of the first capacitor 100 more accurate.

[0080] In some embodiments, such as Figure 2 As shown, the orthographic projection of the third electrode 201 onto the substrate 10 falls entirely within the orthographic projection of the second electrode 102 onto the substrate 10. That is to say, during the fabrication of the third electrode 201, it is entirely formed on the surface of the second electrode 102. The relatively flat surface of the second electrode 102 helps improve the flatness of the third electrode 201, which in turn helps ensure uniform spacing between the third and fourth electrode plates during subsequent fabrication of the fourth electrode 202, thereby making the capacitance value of the second capacitor 200 more accurate.

[0081] In some embodiments, such as Figure 2As shown, the orthographic projection of the fourth electrode 202 onto the substrate 10 falls entirely within the orthographic projection of the third electrode 201 onto the substrate 10. That is to say, during the fabrication of the fourth electrode 202, the fourth electrode 202 is entirely formed on the surface of the third electrode 201. The relatively flat surface of the third electrode 201 helps improve the flatness of the fourth electrode 202, thereby ensuring a uniform spacing between the third electrode 201 and the fourth electrode 202, and consequently making the capacitance value of the second capacitor 200 more accurate.

[0082] Figure 3 This is one of the schematic diagrams of a planar structure for capacitor stacking in an integrated passive device provided in an embodiment of the present invention; Figure 4 This is one of the schematic diagrams of a planar structure in which capacitors are arranged on the same layer in an integrated passive device.

[0083] For example, in some embodiments, such as Figure 3 As shown, the integrated passive device includes a first capacitor 100, a second capacitor 200, and an inductor 400. The two ends of the inductor 400 are connected to the second plate 102 of the first capacitor 100 and the third plate 201 of the second capacitor 200, respectively. The second capacitor 200 and the first capacitor 100 are disposed in different layers, thus allowing them to be disposed on the same side of the inductor 400. Furthermore, the orthographic projection of the second capacitor 200 onto the substrate 10 at least partially overlaps with the orthographic projection of the first capacitor 100 onto the substrate 10, thereby reducing the area occupied by the first capacitor 100 and the second capacitor 200. In specific implementation, by setting the orthographic projection of the second electrode 102 on the substrate 10 to fall entirely within the orthographic projection of the first electrode 101 on the substrate 10, the orthographic projection of the third electrode 201 on the substrate 10 to fall entirely within the orthographic projection of the second electrode 102 on the substrate 10, and the orthographic projection of the fourth electrode 202 on the substrate 10 to fall entirely within the orthographic projection of the third electrode 201 on the substrate 10, the shape and size of the orthographic projection of the first capacitor 100 and the second capacitor 200 as a whole on the substrate 10 are the same as the shape and size of the orthographic projection of the first electrode 101 of the first capacitor 100 on the substrate 10. This can minimize the area occupied by the first capacitor 100 and the second capacitor 200 and reduce the planar size of the integrated passive device.

[0084] In contrast, in an integrated passive device, such as Figure 4 As shown, the second capacitor 200 and the first capacitor 100 are disposed in the same film layer. Specifically, the first electrode 101 and the third electrode 201 are disposed in the same layer, and the second electrode 102 and the fourth electrode 202 are disposed in the same layer. It should be noted that, in this embodiment of the invention, the two electrodes being disposed in the same layer specifically refers to the two electrodes being obtained by patterning the same film layer in the same mask process. Figure 4The integrated passive device includes a first capacitor 100, a second capacitor 200, and an inductor 400. The two ends of the inductor 400 are connected to the second plate 102 of the first capacitor 100 and the fourth plate 202 of the second capacitor 200, respectively. The second capacitor 200 and the first capacitor 100 are respectively disposed on different sides of the inductor 400. Since the second capacitor 200 and the first capacitor 100 are disposed in the same layer, they cannot be overlapped on a plane. The area occupied by the second capacitor 200 and the first capacitor 100 is the sum of the areas occupied by the second capacitor 200 and the first capacitor 100 individually. The large area occupied by the capacitors makes it difficult to further reduce the size of the integrated passive device.

[0085] As can be seen from the above comparison, the integrated passive device provided by the embodiments of the present invention can greatly reduce the size of the integrated passive device by setting at least two capacitor stacks.

[0086] Figure 5a The third schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention; Figure 5b Fourth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention; Figure 5b The fifth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention.

[0087] In some embodiments, such as Figures 5a-5c As shown, the integrated passive device also includes a third capacitor 300. The third capacitor 300 includes a fifth plate 301 and a sixth plate 302. In a specific implementation, the fifth plate 301 is located on the same layer as one of the first plate 101, the second plate 102, the third plate 201, or the fourth plate 202. The sixth plate 302 is located on the same layer as one of the first plate 101, the second plate 102, the third plate 201, or the fourth plate 202, but on a different layer than the fifth plate 302. For example, as... Figures 5a-5c As shown, the fifth electrode 301 can be located on the same layer as the first electrode 101, and the sixth electrode 302 can be located on the same layer as the third substrate 201. That is, the fifth electrode 301 shares a film layer with the first electrode 101, and the sixth electrode 302 shares a film layer with the third substrate 201. This allows for the creation of more capacitors without increasing the number of film layers, simultaneously meeting the requirements for small size and multiple capacitors in integrated passive devices. In some embodiments, the fifth electrode 301 and the sixth electrode 302 can also be disposed in other layers. For example, the fifth electrode 301 can be located on the same layer as the second electrode 102, and the sixth electrode 302 can be located on the same layer as the fourth electrode 202; this is not limited here.

[0088] In some embodiments, capacitor plates located on the same layer can be spaced apart from each other to form independent capacitor plates. For example, in Figure 5a In the embodiment shown, the fifth electrode plate 301 and the first electrode plate 101 are separated by a certain distance and are not connected to each other, and the sixth electrode plate 302 and the third electrode plate 201 are separated by a certain distance and are not connected to each other.

[0089] In some embodiments, capacitor plates located on the same layer can be interconnected. For example, in Figure 5b In the illustrated embodiment, the fifth electrode plate 301 and the first electrode plate 101 are located on the same layer and are interconnected, while the sixth electrode plate 302 and the third electrode plate 201 are located on the same layer and are spaced apart from each other, but are not interconnected. For example, in Figure 5c In the illustrated embodiment, the sixth electrode 302 and the third electrode 201 are located on the same layer and are interconnected, while the fifth electrode 301 and the first electrode 101 are located on the same layer and are spaced apart from each other but are not interconnected. In specific implementations, the configuration can be adjusted according to actual needs to form a specific capacitor structure, and no limitation is made here.

[0090] In some embodiments, the capacitance value of the third capacitor 300 is different from that of the first capacitor 100, thereby increasing the size specification of the capacitor in the integrated passive device.

[0091] In some embodiments, the capacitance value of the third capacitor 300 is different from that of the second capacitor 200, thereby increasing the size specification of the capacitor in the integrated passive device.

[0092] The capacitance value of the third capacitor 300 can be adjusted by adjusting the size of the area directly opposite the fifth plate 301 and the sixth plate 302 and by adjusting the spacing between the fifth plate 301 and the sixth plate 302 within the directly opposite area, which is not limited here.

[0093] In this embodiment of the invention, a first gap exists between the first electrode plate 101 and the second electrode plate 102. A second gap exists between the third electrode plate 201 and the fourth electrode plate 202. A third gap exists between the fifth electrode plate 301 and the sixth electrode plate 302. In some embodiments, the third gap is different from the first gap, so that in addition to adjusting the capacitance value by adjusting the facing area, the gap between the fifth electrode plate 301 and the sixth electrode plate 302 can be adjusted to make the third capacitor 300 have a different capacitance value than the first capacitor 100, increasing the degree of freedom in adjusting the capacitance value. In some embodiments, the third gap is different from the second gap, so that in addition to adjusting the capacitance value by adjusting the facing area, the gap between the fifth electrode plate 301 and the sixth electrode plate 302 can be adjusted to make the third capacitor 300 have a different capacitance value than the second capacitor 100, increasing the degree of freedom in adjusting the capacitance value.

[0094] The size of the third gap between the fifth electrode 301 and the sixth electrode 302 depends on the film layers respectively disposed on the fifth electrode 301 and the sixth electrode 302. For example, such as Figures 5a-5c As shown, the integrated passive device also includes a fourth dielectric layer 4 disposed between the first electrode 101 and the second electrode 102, a fifth dielectric layer 5 disposed between the second electrode 102 and the third electrode 201, and a sixth dielectric layer 6 disposed between the third electrode 201 and the fourth electrode 202. The fourth dielectric layer 4, the fifth dielectric layer 5, and the sixth dielectric layer 6 are all made of insulating material. Figures 5a-5c As shown, when the fifth electrode 301 and the first electrode 101 are disposed on the same layer, and the sixth electrode 302 and the third electrode 201 are disposed on the same layer, the spacing between the fifth electrode 301 and the sixth electrode 302 is the sum of the thickness of the fourth dielectric layer 4 and the thickness of the fifth dielectric layer 5. When the fifth electrode 301 and the second electrode 102 are disposed on the same layer, and the sixth electrode 302 and the fourth electrode 202 are disposed on the same layer, the spacing between the fifth electrode 301 and the sixth electrode 302 is the sum of the thickness of the fifth dielectric layer 5 and the thickness of the sixth dielectric layer 6. In specific implementation, the film layers disposed on the fifth electrode 301 and the sixth electrode 302 can be selected according to the capacitance value requirement of the third capacitor 300, which is not limited here. The thicknesses of the fourth dielectric layer 4, the fifth dielectric layer 5, and the sixth dielectric layer 6 can be set to be the same or different, which is not limited here.

[0095] Figure 6 Sixth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention; Figure 7 This is a second schematic diagram of a planar structure for capacitor stacking in an integrated passive device provided in an embodiment of the present invention; Figure 8 The second schematic diagram shows a planar structure in which capacitors are arranged on the same layer in an integrated passive device.

[0096] In some embodiments, such as Figure 6 As shown, the second electrode 102 is reused as the third electrode 201. Specifically, the second electrode 102 and the first electrode 101 form the first capacitor 100, while the second electrode 102 and the fourth electrode 202 form the second capacitor 200. The first capacitor 100 and the second capacitor 200 form a series capacitor. Reusing the second electrode 102 helps to reduce the number of film layers. Furthermore, combined with… Figure 7 As shown, the first capacitor 100 and the second capacitor 200 are stacked, and the orthographic projections of the first capacitor 100 and the second capacitor 200 on the substrate 10 can overlap, thereby reducing the planar dimensions of the integrated passive device. In comparison... Figure 8In the integrated passive device shown, the first capacitor 100 and the second capacitor 200 are located on the same layer, and therefore can only be arranged horizontally on a plane. The first electrode 101 and the fourth electrode 202 are located on the same layer, and the second electrode 102 (third electrode 201) is located on the same side of the first electrode 101 and the fourth electrode 202. A part of the second electrode 102 (third electrode 201) is arranged opposite to the first electrode 101 to form the first capacitor 100, and the other part of the second electrode 102 (third electrode 201) is arranged opposite to the fourth electrode 202 to form the second capacitor 200. The area occupied by the first capacitor 100 and the second capacitor 200 on the plane is the sum of the areas occupied by the first capacitor 100 and the second capacitor 200 respectively and the area occupied by the gap area between the first capacitor 100 and the second capacitor 200. Compared with the integrated passive device provided in the embodiment of the present invention, the capacitor occupies a larger area, making it difficult to further reduce the planar size of the integrated passive device.

[0097] Figure 9a Seventh schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention; Figure 9b Eighth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention; Figure 9c A schematic diagram of the cross-sectional structure of an integrated passive device provided in an embodiment of the present invention (number nine). Figure 9d This is the tenth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention.

[0098] In some embodiments, such as Figures 9a to 9d As shown, the integrated passive device also includes: a first dielectric layer 1 and a connection layer 400.

[0099] The first dielectric layer 1 is located on the side of the second capacitor 200 facing away from the substrate 10. The first dielectric layer 1 is made of an insulating material and serves to provide insulation and protection. In specific implementations, the material of the first dielectric layer 1 can be a resin material such as polyimide (PI), and there is no limitation on this. The first dielectric layer 1 can also serve as a planarization layer. The first dielectric layer 1 can have a certain thickness to fill the step difference formed by the edge of the capacitor plate, thereby forming a flat surface on the side of the first dielectric layer 1 facing away from the substrate 10.

[0100] A connection layer 400 is located on the side of the first dielectric layer 1 facing away from the substrate 10. The connection layer 400 includes at least one connection structure. The connection structure is connected to a plate of a capacitor in an integrated passive device via a via that penetrates at least through the first dielectric layer 1. The connection structure is used to connect the capacitor it connects to to other components. For example, such as... Figure 9aIn the embodiments, the connection layer 400 includes a first connection structure 401, a second connection structure 402, and a third connection structure 403. The first connection structure 401 is connected to the fourth electrode 202 of the second capacitor 200 through a via penetrating the first dielectric layer 1. The second connection structure 402 is connected to the third electrode 201 of the second capacitor 200 through a via penetrating the first dielectric layer 1 and the sixth dielectric layer 6. The third connection structure 403 is connected to the first electrode 101 of the first capacitor 100 through a via penetrating the first dielectric layer 1, the sixth dielectric layer 6, the fifth dielectric layer 5, and the fourth dielectric layer 4. Figure 9b In the embodiments, compared to Figure 9a The illustrated embodiment also includes a fourth connection structure 404, which is connected to the sixth electrode 302 of the third capacitor 300 through a via penetrating the first dielectric layer 1 and the sixth dielectric layer 6. Figure 9c In the embodiments, with Figure 9a The difference in the illustrated embodiment is that the second connection structure 402 is connected to the second electrode plate 102 through a through-hole penetrating the first dielectric layer 1, the sixth dielectric layer 6, and the third electrode plate 201. Simultaneously, the side of the second connection structure 402 contacts the wall of the through-hole portion in the third electrode plate 201, thus the second connection structure 402 is simultaneously connected to both the second electrode plate 102 and the third electrode plate 201. Figure 9d In this embodiment, the second electrode 102 is reused as the third electrode 201. The connection layer 400 includes a first connection structure 401 and a second connection structure 403. The first connection structure 401 is connected to the fourth electrode 202 of the second capacitor 200 through a via penetrating the first dielectric layer 1. Since the second electrode 102 and the third electrode 201 are identical, Figure 9d In the illustrated embodiment, a fifth dielectric layer 5 is not provided. The third connection structure 403 is connected to the first electrode 101 of the first capacitor 100 through vias penetrating the first dielectric layer 1, the sixth dielectric layer 6, and the fourth dielectric layer 4. By connecting to the capacitor inside the integrated passive device through the connection structure and extending it to the surface of the integrated passive device, the connection structure can connect the capacitor inside the integrated passive device to other components outside and / or inside the integrated passive device, ultimately forming a complete circuit structure or electronic device structure that fulfills specific functional requirements. In specific implementations, the number of connection structures can be adjusted according to the specific structure of the integrated passive device and the number of capacitor electrodes to be connected, and is not limited here. The material of the connection layer 400 is a conductive material, such as a metal or its alloy with good conductivity, and is not limited here. The connection layer 400 can be a single conductive film layer structure or a stacked structure of multiple conductive film layers, and is not limited here.

[0101] Figure 10a Eleventh schematic diagram of the cross-sectional structure of an integrated passive device provided in an embodiment of the present invention; Figure 10b The twelfth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention; Figure 10c Thirteenth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention; Figure 10d This is the fourteenth schematic diagram of the cross-sectional structure of the integrated passive device provided in the embodiment of the present invention.

[0102] In some embodiments, such as Figures 10a to 10d As shown, the integrated passive device also includes: a redistribution layer 500 and a second dielectric layer 2.

[0103] The redistribution layer 500 is located between the second capacitor 200 and the first dielectric layer 1. The redistribution layer 500 is made of a conductive material such as metal and can be used to route signal lines in integrated passive devices, form inductors and / or resistors, etc. In some embodiments, such as... Figures 10a to 10d As shown, the redistribution layer 500 also includes a transition structure 50 corresponding to the connection structure. The connection structure is connected to the corresponding transition structure 50 through a via penetrating the first dielectric layer 1, and is connected to the capacitor plate through the transition structure 50.

[0104] The second dielectric layer 2 is located between the second capacitor 200 and the redistribution layer 500. The transition structure 50 is connected to the capacitor plates through a via penetrating the second dielectric layer 2. The second dielectric layer 2 can be made of an insulating material to provide insulation and protection. In specific implementations, the second dielectric layer 2 can be made of resin materials such as polyimide. The second dielectric layer 2 can have a certain thickness to fill the step difference formed at the edge of the capacitor plates, thus achieving a planarization effect.

[0105] For example, such as Figure 10a and Figure 10b In the embodiment, the first connection structure 401 is connected to the corresponding adapter structure 50 in the redistribution layer 500 through a via penetrating the first dielectric layer 1. This adapter structure 50 is connected to the fourth electrode 202 of the second capacitor 200 through a via penetrating the second dielectric layer 2. The second connection structure 402 is connected to the corresponding adapter structure 50 in the redistribution layer 500 through a via penetrating the first dielectric layer 1. This adapter structure 50 is connected to the third electrode 201 of the second capacitor 200 through a via penetrating the second dielectric layer 2 and the sixth dielectric layer 6. The third connection structure 403 is connected to the corresponding adapter structure 50 in the redistribution layer 500 through a via penetrating the first dielectric layer 1. This adapter structure 50 is connected to the first electrode 101 of the first capacitor 100 through a via penetrating the second dielectric layer 2, the sixth dielectric layer 6, the fifth dielectric layer 5, and the fourth dielectric layer 4. Figure 10c In the embodiments, compared to Figure 10a and Figure 10bIn the embodiments described, the integrated passive device further includes a fourth connection structure 404 and a third capacitor 300. The fourth connection structure 404 is connected to a corresponding adapter structure 50 in the redistribution layer 500 via a via penetrating the first dielectric layer 1. The adapter structure 50 is connected to the sixth electrode 302 of the third capacitor 300 via a via penetrating the second dielectric layer 2 and the sixth dielectric layer 6. Figure 10c In this embodiment, the second electrode 102 is reused as the third electrode 201. The first connection structure 401 is connected to the adapter structure 50 corresponding to the first connection structure 401 in the redistribution layer 500 through a via penetrating the first dielectric layer 1. The adapter structure 50 is connected to the fourth electrode 202 of the second capacitor 200 through a via penetrating the second dielectric layer 2. The third connection structure 403 is connected to the adapter structure 50 corresponding to the third connection structure 403 in the redistribution layer 500 through a via penetrating the first dielectric layer 1. The adapter structure 50 is connected to the first electrode 101 of the first capacitor 100 through a via penetrating the second dielectric layer 2, the sixth dielectric layer 6, and the fourth dielectric layer 4. Figures 10a-10d Examples illustrate several scenarios where the connection structure is connected to the capacitor's plates via an adapter structure. In actual implementation, the number and connection method of the connection structure can be adjusted according to the specific structure of the integrated passive device, and are not limited here.

[0106] In some embodiments, such as Figure 10a As shown, the redistribution layer 500 includes only one conductive layer, which arranges the signal traces of the integrated passive device, forms inductors and / or resistors, and forms the transition structure 50, etc., which are not limited here.

[0107] In some embodiments, the redistribution layer 500 includes a plurality of sub-wiring layers stacked along a direction away from the substrate 1. A third dielectric layer is disposed between adjacent sub-wiring layers. Each transition structure includes a plurality of transition portions disposed in the plurality of sub-wiring layers; two adjacent transition portions of the same transition structure located in different sub-wiring layers are connected by a via passing through the third dielectric layer located between the two adjacent transition portions. For example, such as Figures 10b-10d As shown, the redistribution layer 500 includes two sub-wiring layers stacked along a direction away from the substrate 1, namely a first sub-wiring layer 501 and a second sub-wiring layer 502. Each transition structure includes a first portion 510 disposed in the first sub-wiring layer 501 and a second portion 520 disposed in the second sub-wiring layer 502. A third dielectric layer 3 made of an insulating material is disposed between the first sub-wiring layer 501 and the second sub-wiring layer 502. Figures 10b-10dAs shown, for example, in the adapter structure connected to the first connection structure 401, the first part 510 and the second part 520 are respectively located in the adjacent first sub-wiring layer 501 and the second sub-wiring layer 502, and the first part 510 and the second part 520 are connected by a via through the third dielectric layer 3 located between the first part 510 and the second part 520.

[0108] In some embodiments, the integrated passive device further includes at least one inductor and / or at least one capacitor. The inductor and / or capacitor may be formed in at least one conductive film layer such as the film layer where the first electrode 101 is located, the film layer where the second electrode 102 is located, the film layer where the third electrode 201 is located, the film layer where the fourth electrode 202 is located, and the redistribution layer 500 (including at least one sub-wiring layer), without limitation herein.

[0109] A second aspect of the present invention provides an electronic device. The electronic device provided by the present invention includes the integrated passive device provided in any of the foregoing embodiments. The principle by which this electronic device solves the problem is similar to that of the foregoing integrated passive device; therefore, the implementation of this electronic device can refer to the implementation of the foregoing integrated passive device, and the repeated parts will not be described again here.

[0110] In some embodiments, the electronic device may be a filter. In some embodiments, the electronic device may also be other devices, which are not limited here.

[0111] Figure 11 A flowchart illustrating the fabrication method of an integrated passive device provided in an embodiment of the present invention.

[0112] A third aspect of this invention provides a method for fabricating an integrated passive device. For example... Figure 11 As shown, the method for fabricating an integrated passive device provided in this embodiment of the invention includes the following steps:

[0113] S111: Fabricate the first capacitor on one side of the substrate;

[0114] S112: A second capacitor is fabricated on the side of the first capacitor away from the substrate; the orthographic projection of the second capacitor on the substrate at least partially overlaps with the orthographic projection of the first capacitor on the substrate.

[0115] In the method for fabricating an integrated passive device provided in this embodiment of the invention, at least two capacitors in the integrated passive device are stacked, thereby allowing the orthogonal projections of the two stacked capacitors on the substrate to at least partially overlap, thereby reducing the area occupied by the capacitors on the plane and helping to reduce the planar size of the integrated passive device.

[0116] In some embodiments, the structure of the integrated passive device is as follows: Figure 10b As shown, the fabrication process of integrated passive devices specifically includes the following steps:

[0117] 1. Cleaning and drying of substrate 1 to keep substrate 1 clean and dry; for example, if substrate 1 is a glass substrate, acetone, isopropanol (IPA), deionized water, etc. can be used to clean the glass surface by means of ultrasonication, quick dump rinsing (QDR), etc., and then the glass can be dried by oven or hot nitrogen to ensure that the glass surface is clean and dry.

[0118] 2. Fabrication of the first electrode 101 and the fourth dielectric layer 4: Specifically, a Ti metal layer, a Cu metal layer, and a Ti metal layer can be sequentially deposited on the surface of the substrate 1 by sputtering deposition or other methods to form a Ti / Cu / Ti triple-layer structure of the first metal conductive layer. The first metal conductive layer can have a relatively thin thickness. Specifically, the thickness of the two Ti metal layers can be set to 20μm to 50μm, for example, 30μm, and the thickness of the Cu metal can be set to 250μm to 350μm, for example, 300μm, without limitation. Then, the first metal conductive layer is patterned by dry etching or wet etching to form the first electrode 101. At the same time, the structure of other components located on the same layer as the first electrode 101 in the integrated passive device can also be formed, such as inductors and resistors, without limitation. After the first metal conductive layer is patterned, the fourth dielectric layer 4 is formed by plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

[0119] 3. Prepare the second electrode plate 102 and the fifth dielectric layer 5; the fabrication process of this step can refer to the fabrication process of step 2 above, and will not be repeated here;

[0120] 4. Prepare the third electrode plate 201 and the sixth dielectric layer 6; the fabrication process of this step can refer to the fabrication process of step 2 above, and will not be repeated here;

[0121] 5. Fabrication of the fourth electrode plate 202 and dry etching of the openings; specifically, the fourth electrode plate 202 can be fabricated using the same method as the first electrode plate 101; patterned photoresist is formed on the side of the fourth electrode plate 202 away from the substrate through processes such as coating, exposure, and development; then, through dry etching processes such as RIE or ICP, openings are made in the dielectric layer above the capacitor electrode plate that needs to be connected to the connection structure located on the outer surface of the integrated passive device, so as to expose the electrode plate that needs to be connected to the connection structure; the openings are made uniformly after the fourth dielectric layer 4, the fifth dielectric layer 5, and the sixth dielectric layer 6 are completed, thereby reducing the number of opening steps; by adjusting the size of the photoresist opening diameter, over-etching is avoided; such as Figure 10b As shown, the fourth electrode 202 is connected to the first connection structure 401. Since the dielectric layer has not yet been formed on the surface of the fourth substrate 202, no holes are required. A via is made in the sixth dielectric layer 6 to expose the third electrode 201, which facilitates the subsequent connection of the third electrode 201 to the second connection structure 402. A via is made in the sixth dielectric layer 6, the fifth dielectric layer 5, and the fourth dielectric layer 4 to expose the first electrode 101, which facilitates the subsequent connection of the first electrode 101 to the third connection structure 403. The photoresist is removed after the holes are made.

[0122] 6. Fabricate the second dielectric layer 2; specifically, a thick PI layer can be formed on the side of the fourth electrode plate 202 away from the substrate 1 by spin coating or other methods. The thickness of the PI layer is sufficient to cover the electrode plates of each capacitor and fill the step difference formed at the edge of each electrode plate. Then, through exposure, development and other processes, PI layer vias corresponding to the vias opened in step 5 are opened in the PI layer, and the PI layer is cured by high temperature process to form the second dielectric layer 2.

[0123] 7. Fabricate the first sub-wiring layer 501; specifically, a Ti / Cu metal seed layer can be fabricated on the side of the second dielectric layer 2 away from the substrate 1 using processes such as sputtering deposition. The thickness can be 50nm / 300nm respectively, which is not limited here; part of the metal seed layer is formed within the vias of the second dielectric layer 2, thereby connecting with the capacitor plate; then, a photoresist spin coating, exposure, and development process is performed to pattern the photoresist, forming a pattern corresponding to the first part 510 of the transition structure, as well as patterns corresponding to other circuit structures located in the first sub-wiring layer 501. The photoresist thickness should be slightly higher than the thickness of the first sub-wiring layer 501 to facilitate subsequent electroplating processes; then, an electroplating process is performed to grow the metal pattern of the first sub-wiring layer 501; finally, a photoresist stripping and etching process is performed to remove the photoresist and excess metal seed layer, ultimately forming the patterned first sub-wiring layer 501 (including the pattern of the first part 510 and the patterns of other structures located in this layer);

[0124] 8. Fabricate the third dielectric layer 3; the specific fabrication process of the third dielectric layer 3 can be referred to the second dielectric layer 2, and will not be elaborated here;

[0125] 9. Fabricate the second sub-routing layer 502; In specific implementation, the fabrication process of the second sub-routing layer 502 can refer to the first sub-routing layer 501, and will not be repeated here; The second part 520 of the same transition structure located in the second sub-routing layer 502 and the first part 510 located in the first sub-routing layer 501 are connected by a via through the third dielectric layer 3.

[0126] 10. Fabricate the first dielectric layer 1; the fabrication process of the first dielectric layer 1 can be referred to the second dielectric layer 2 in the specific implementation, and will not be described in detail here;

[0127] 11. Fabrication of the connection structure; Specifically, a metal seed layer can be fabricated on the side of the first dielectric layer 1 away from the substrate 1 using processes such as sputtering deposition. Part of the metal seed layer is formed within the vias of the first dielectric layer 1 and connected to the second part 520 of the transition structure. Then, photoresist spin coating, exposure, and development processes are performed to pattern the photoresist, forming a pattern corresponding to the connection structure and patterns corresponding to other circuit structures located on the connection layer. Then, Cu / Ni / SnAg (or Sn) metal electroplating is performed respectively, where the Cu metal thickness can be 20μm to 60μm, for example, 30μm, and the SnAg or Sn metal thickness can be selected from 20μm to 50μm, for example, 30μm, without limitation. A Ni layer is added as a barrier layer to prevent Sn from penetrating into Cu. The Ni thickness can be selected from 3μm to 10μm, for example, 5μm, without limitation. Finally, the photoresist is removed, excess seed layer is etched away by wet etching, and a reflow process is performed to form the connection structure and other circuit structures located on this layer.

[0128] In some embodiments, the structure of the integrated passive device is as follows: Figure 10c As shown, its manufacturing process is similar to Figure 10b The fabrication process of the integrated passive device in the illustrated embodiment is similar, the difference being that... Figure 10c In the embodiment shown, the fifth electrode plate 301 is fabricated at the same time as the first electrode plate 101, the sixth electrode plate 302 is fabricated at the same time as the third electrode plate 201, and the adapter structure and the fourth connection structure 404 connected to the sixth electrode plate 302 are fabricated in subsequent processes.

[0129] In some embodiments, the structure of the integrated passive device is as follows: Figure 10d As shown, its manufacturing process is similar to that of the integrated passive device in the embodiment shown in 10b. The difference is that the second electrode plate 102 is reused as the third electrode plate 201, so there is no need to make the fifth dielectric layer 5 and the third electrode plate 201. Furthermore, the adapter structure and the second connection structure 402 connected to the third electrode plate 201 are not made in the subsequent process.

[0130] The above embodiments are only for reference. Figures 10b-10d Taking the integrated passive device structure shown as an example, the fabrication process of the integrated passive device provided in this embodiment of the invention will be illustrated. In specific implementations, the fabrication process can be adjusted accordingly based on the specific structure of the integrated passive device, and will not be elaborated here.

[0131] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the invention.

[0132] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An integrated passive device, characterized in that, include: Substrate; The first capacitor is located on one side of the substrate; The second capacitor is located on the side of the first capacitor that is away from the substrate; The orthographic projection of the second capacitor onto the substrate at least partially overlaps with the orthographic projection of the first capacitor onto the substrate.

2. The integrated passive device as described in claim 1, characterized in that, The first capacitor includes a first electrode plate and a second electrode plate stacked sequentially along a direction away from the substrate; the orthographic projection of the second electrode plate on the substrate and the orthographic projection of the first electrode plate on the substrate have a first overlapping area; The second capacitor includes a third electrode plate and a fourth electrode plate stacked sequentially in a direction away from the substrate; the orthographic projection of the fourth electrode plate on the substrate and the orthographic projection of the third electrode plate on the substrate have a second overlapping region; the second overlapping region at least partially overlaps the first overlapping region.

3. The integrated passive device as described in claim 2, characterized in that, The second overlapping region falls entirely within the range of the first overlapping region; or, the first overlapping region falls entirely within the range of the second overlapping region.

4. The integrated passive device as described in claim 3, characterized in that, The orthographic projection of the second electrode plate onto the substrate falls entirely within the orthographic projection of the first electrode plate onto the substrate; The orthographic projection of the third electrode plate onto the substrate falls entirely within the orthographic projection of the second electrode plate onto the substrate; The orthographic projection of the fourth electrode plate onto the substrate falls entirely within the orthographic projection of the third electrode plate onto the substrate.

5. The integrated passive device as described in claim 2, characterized in that, The integrated passive device also includes a third capacitor; the third capacitor includes a fifth plate and a sixth plate; The fifth electrode plate is located on the same layer as one of the first electrode plate, the second electrode plate, the third electrode plate, or the fourth electrode plate; The sixth electrode plate is located on the same layer as one of the first electrode plate, the second electrode plate, the third electrode plate, or the fourth electrode plate, but on a different layer from the fifth electrode plate.

6. The integrated passive device as described in claim 5, characterized in that, The capacitance value of the third capacitor is different from the capacitance value of the first capacitor; The capacitance value of the third capacitor is different from that of the second capacitor.

7. The integrated passive device as described in claim 5, characterized in that, The first electrode plate and the second electrode plate have a first gap; the third electrode plate and the fourth electrode plate have a second gap; the fifth electrode plate and the sixth electrode plate have a third gap; The third spacing is different from the second spacing; The third spacing is different from the first spacing.

8. The integrated passive device as described in claim 2, characterized in that, The second electrode plate is reused as the third electrode plate; the second electrode plate and the first electrode plate constitute the first capacitor, and the second electrode plate and the fourth electrode plate constitute the second capacitor.

9. The integrated passive device according to any one of claims 1 to 8, characterized in that, The integrated passive device also includes: The first dielectric layer is located on the side of the second capacitor that is away from the substrate; A connection layer is located on the side of the first dielectric layer opposite to the substrate; the connection layer includes at least one connection structure; one of the connection structures is connected to a plate of a capacitor in the integrated passive device through a via at least through the first dielectric layer; the connection structure is used to connect the capacitor to other components.

10. The integrated passive device as described in claim 9, characterized in that, The integrated passive device also includes: A redistribution layer is located between the second capacitor and the first dielectric layer; the redistribution layer includes a transition structure corresponding to each of the connection structures; the connection structure is connected to the corresponding transition structure through a via penetrating the first dielectric layer, and is connected to the capacitor plate through the transition structure; The second dielectric layer is located between the second capacitor and the redistribution layer; the transition structure is connected to the capacitor plates through a via penetrating the second dielectric layer.

11. The integrated passive device as described in claim 10, characterized in that, The redistribution layer includes a plurality of sub-wiring layers stacked along a direction away from the substrate; a third dielectric layer is disposed between adjacent sub-wiring layers; Each of the aforementioned transition structures includes multiple transition portions disposed in multiple of the aforementioned sub-routing layers; two adjacent transition portions of the same transition structure located in different of the aforementioned sub-routing layers are connected by a via passing through the third dielectric layer located between the two adjacent transition portions.

12. The integrated passive device according to any one of claims 1 to 8, characterized in that, The integrated passive device also includes at least one inductor and / or at least one resistor.

13. The integrated passive device according to any one of claims 1 to 7, characterized in that, The integrated passive device also includes: The fourth dielectric layer is located between the first electrode plate and the second electrode plate; The fifth dielectric layer is located between the second electrode plate and the third electrode plate; The sixth dielectric layer is located between the third electrode plate and the fourth electrode plate.

14. An electronic device, characterized in that, Including the integrated passive device as described in any one of claims 1 to 13.

15. The electronic device as claimed in claim 14, characterized in that, The electronic device is a filter.

16. A method for manufacturing an integrated passive device, characterized in that, include: The first capacitor is fabricated on one side of the substrate; A second capacitor is fabricated on the side of the first capacitor that is away from the substrate; The orthographic projection of the second capacitor onto the substrate at least partially overlaps with the orthographic projection of the first capacitor onto the substrate.

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