Co-packaged optical device and transceiver

Abstract

An assembly for co-packaging photonic and electronic integrated circuits. In some embodiments, the assembly comprises: a photonic integrated circuit (PIC, 105); and an electronic integrated circuit (IC, 110). The front surface of the photonic integrated circuit abuts the front surface of the electronic integrated circuit in an overlap region (135). A first portion (125) of the photonic integrated circuit protrudes beyond a first edge (130) of the electronic integrated circuit, and a first portion (115) of the electronic integrated circuit protrudes beyond a first edge (120) of the photonic integrated circuit. The conductors on the front surface of the electronic integrated circuit are connected to the conductors on the front surface of the photonic integrated circuit in the overlap region.

Description

This application is a divisional application of the patent application filed on April 24, 2020, with application number 202080046470.5 and invention title "Commonly Packaged Optical Device and Transceiver". Technical Field

[0001] One or more aspects of embodiments of this disclosure relate to optoelectronic systems, and more particularly to systems and methods for co-packaging optical devices and transceiver components. Background Technology

[0002] Some systems used for packaging photonic integrated circuits and electronic integrated circuits (such as fan-out wafer-level packages (FOWLP)) may include a redistribution layer (RDL) on one or both surfaces of the electronic integrated circuit and through-vias (through the electronic integrated circuit) for routing signals from the front surface of the electronic integrated circuit to the rear surface. Such systems may have certain disadvantages. For example, the thickness of the RDL can increase the interconnect path length between the photonic integrated circuit and the electronic integrated circuit. This increased length increases the inductance of the connection and reduces the bandwidth of circuits (e.g., circuitry for a photodetector on the photonic integrated circuit and circuitry for a transimpedance amplifier on the electronic integrated circuit). This limits the data rate achievable when using an RDL. Moreover, if the rear surface of the electronic integrated circuit is used for electrical interconnection, the presence of this interconnection can be an obstacle to placing a heat sink directly on the electronic integrated circuit, and heat can instead flow through the photonic integrated circuit to the heat sink, resulting in increased thermal resistance and potentially higher operating temperatures for temperature-sensitive devices in the photonic integrated circuit.

[0003] Therefore, there is a need for improved systems and methods for co-packaging optical devices and transceiver components. Summary of the Invention

[0004] According to an embodiment of the present invention, a component is provided, the component comprising: a photonic integrated circuit; and an electronic integrated circuit, the front surface of the photonic integrated circuit being adjacent to the front surface of the electronic integrated circuit in an overlapping region, a first portion of the photonic integrated circuit protruding beyond a first edge of the electronic integrated circuit, and the first portion of the electronic integrated circuit protruding beyond the first edge of the photonic integrated circuit, and a conductor on the front surface of the electronic integrated circuit being connected to a conductor on the front surface of the photonic integrated circuit in the overlapping region.

[0005] In some embodiments, the first edge of the electronic integrated circuit is opposite to the first portion of the electronic integrated circuit, and the first edge of the photonic integrated circuit is opposite to the first portion of the photonic integrated circuit.

[0006] In some embodiments, conductors on the front surface of an electronic integrated circuit are connected to conductors on the front surface of a photonic integrated circuit in an overlapping region via metal bumps. The metal bumps are one of a plurality of metal bumps arranged on a grid on a rectangular array, and the metal bumps are not present at grid points at the corners of the rectangular array.

[0007] In some embodiments, in the overlapping region: there is no redistribution layer on the electronic integrated circuit and no redistribution layer on the photonic integrated circuit.

[0008] In some embodiments, the component further includes a printed circuit board adjacent to a first portion of the electronic integrated circuit.

[0009] In some embodiments, the component further includes a compressible membrane connector between a first portion of the electronic integrated circuit and a printed circuit board, wherein conductors on the first portion of the electronic integrated circuit are connected to conductors on the printed circuit board via conductors in the compressible membrane connector.

[0010] In some embodiments, the component further includes a digital integrated circuit on a printed circuit board, which is connected to an electronic integrated circuit via conductors on the printed circuit board and conductors in a compressible membrane connector.

[0011] In some embodiments, the component further includes: a heat sink on a digital integrated circuit; and a heat sink on an electronic integrated circuit.

[0012] In some embodiments, the components are configured to allow replacement of the photonic integrated circuit and the electronic integrated circuit without removing the heat sink from the digital integrated circuit.

[0013] In some embodiments, the photonic integrated circuit includes a photodetector, and the electronic integrated circuit includes an amplifier connected to the photodetector via a conductive path having a length of less than 500 micrometers.

[0014] In some embodiments, the length of the conduction path is less than 200 micrometers.

[0015] In some embodiments, the length of the conduction path is less than 100 micrometers.

[0016] In some embodiments: the photonic integrated circuit includes a photodetector, and the electronic integrated circuit includes an amplifier connected to the photodetector; and wherein the signal path from the optical input carrying amplitude-modulated light to the photodetector to the output of the amplifier of the electrical signal corresponding to the amplitude modulation has a bandwidth of at least 3 dB of 10 GHz.

[0017] In some embodiments, the signal path has a 3dB bandwidth of at least 60 GHz.

[0018] In some embodiments, the photonic integrated circuit includes a modulator, and the electronic integrated circuit includes an amplifier connected to the modulator via a conductive path having a length of less than 500 micrometers.

[0019] In some embodiments, the length of the conduction path is less than 200 micrometers.

[0020] In some embodiments, the length of the conduction path is less than 100 micrometers.

[0021] In some embodiments: the photonic integrated circuit includes a modulator, and the electronic integrated circuit includes an amplifier connected to the modulator; and wherein the signal path from the input of an electrical signal to the amplifier to the output of the modulator carrying light with amplitude modulation corresponding to the electrical signal has a bandwidth of at least 3 dB of 10 GHz.

[0022] In some embodiments, the signal path has a 3dB bandwidth of at least 40 GHz. Attached Figure Description

[0023] These and other features and advantages of this disclosure will be recognized and understood by referring to the specification, claims, and drawings, wherein: Figure 1A This is a side view of a flip-chip assembly according to an embodiment of the present disclosure; Figure 1B This is a bottom view of a flip-chip assembly according to an embodiment of the present disclosure; Figure 2A This is a top view of a flip-chip assembly according to an embodiment of the present disclosure; Figure 2B This is a pinout diagram according to an embodiment of the present disclosure; Figure 3 This is a side view of a component according to an embodiment of the present disclosure; Figure 4 This is an assembly flowchart according to an embodiment of the present disclosure; Figure 5 A side view of a component according to an embodiment of this disclosure; and Figure 6 This is a perspective view of components according to embodiments of the present disclosure. Detailed Implementation

[0024] The detailed description set forth below in conjunction with the accompanying drawings is intended as a description of exemplary embodiments of systems and methods for co-packaging optical devices and transceiver components provided according to this disclosure, and is not intended to represent the only forms in which this disclosure can be constructed or utilized. This description elucidates the features of this disclosure in conjunction with the illustrated embodiments. However, it will be understood that the same or equivalent functions and structures can be implemented by different embodiments that are also intended to be included within the scope of this disclosure. As referred to elsewhere herein, the same element numbers are intended to indicate the same elements or features.

[0025] refer to Figure 1A and Figure 1B In some embodiments, a short electrical connection between components (e.g., photodetectors and / or modulators) on (i) the photonic integrated circuit 105 (PIC) and components or circuits (e.g., transimpedance amplifiers and / or modulator drivers) on (ii) the electronic integrated circuit 110 can be formed by flip-chip bonding the photonic integrated circuit 105 to the electronic integrated circuit 110 to form a flip-chip assembly. The photonic integrated circuit may include a substrate (e.g., a silicon substrate) having a front surface (on... Figure 1A In the orientation of the photonic integrated circuit 105, the upper surface, or the front surface of the photonic integrated circuit 105, may be a V-groove (for passive alignment with the optical fiber, not shown for illustration purposes), an optical waveguide, an optoelectronic device (e.g., a photodetector and modulator), and one or more metal layers forming conductive traces for routing electrical signals to and from the optoelectronic device. The optical waveguide may include a mode converter (e.g., a tapered section) for switching, for example, between a mode that can propagate in a 3-micrometer-wide waveguide and (i) a mode that can propagate in a single-mode optical fiber or (ii) a mode that can produce a useful intensity distribution in the optoelectronic device. The electronic integrated circuit 110 may have a length between 5 mm and 15 mm (e.g., a length of 10.2 mm) and a width between 2 mm and 9 mm (e.g., a width of 4.4 mm), and the photonic integrated circuit 105 may have a length between 7 mm and 30 mm (e.g., a length of 15 mm) and a width between 3 mm and 11 mm (e.g., a width of 5.5 mm).

[0026] The electronic integrated circuit 110 can be a silicon integrated circuit, and the front surface of the electronic integrated circuit 110 (on...) Figure 1AThe lower surface of the integrated circuit 110 may include interface circuitry for interfacing with optoelectronic devices (e.g., a transimpedance amplifier for amplifying the photocurrent generated by a photodetector on the photonic integrated circuit 105 and a modulator driver for driving a modulator (e.g., an electroabsorption (EA) modulator) on the photonic integrated circuit 105). Each of these interface circuits may be part of a corresponding high-speed channel on the front surface of the integrated circuit 110. Each high-speed channel may include (in addition to the interface circuitry) a serial receiver circuit (for connecting to the high-speed channel of the modulator) or a serial transmitter circuit (for connecting to the high-speed channel of the photodetector). These serial receiver and serial transmitter circuits may be, for example, XSR or USR receiver or transmitter circuits, and they may be used to exchange data with digital electronic circuitry (e.g., a switch application-specific integrated circuit (ASIC)) as discussed in more detail below. Each high-speed channel may also include circuitry for connecting the interface circuitry to the serial receiver or serial transmitter circuitry (e.g., clock and data recovery circuitry connected to the transimpedance amplifier in the case of a high-speed channel connected to the photodetector). The circuitry on the electronic integrated circuit 110 may occupy a relatively small portion of the area of ​​the electronic integrated circuit 110 (e.g., less than half or less than a quarter), and in some embodiments, for example, additional areas may be used to fabricate a microcontroller on a first portion 115 of the electronic integrated circuit 110.

[0027] In some embodiments, the electrical connection between the optoelectronic device on the photonic integrated circuit 105 and the corresponding interface circuit (e.g., an amplifier) ​​on the electronic integrated circuit 110 may have a length of less than 500 micrometers, less than 200 micrometers, or less than 100 micrometers. In some embodiments, this length may be almost as small as the height of the metal bump 140 (e.g., a copper pillar bump, which is discussed in more detail below) forming the connection between the photonic integrated circuit 105 and the electronic integrated circuit 110. In some embodiments, the analog portion of the receiving channel (e.g., a photodetector and a transimpedance amplifier connected to the photodetector) may have a bandwidth (e.g., a 3 dB bandwidth) of at least 10 GHz, at least 20 GHz, or at least 60 GHz, defined according to a transfer function from the amplitude modulation of the light received by the photodetector to the corresponding signal at the output of the transimpedance amplifier. This bandwidth may be a relatively sensitive function of the interconnect length between the PIC 140 and IC 110, as mentioned above; for example, a relatively small increase in interconnect length may result in a significant decrease in bandwidth. Similarly, the analog portion of the transmit channel (e.g., the modulator and the drive amplifier in the modulator driver connected to the modulator) can have a bandwidth of at least 10 GHz, or at least 20 GHz, or at least 60 GHz (e.g., 3 dB bandwidth), where the bandwidth is defined according to the transfer function from the electrical signal at the input of the drive amplifier to the corresponding amplitude modulation generated by the modulator. This bandwidth can be a relatively sensitive function of the interconnect length between PIC 140 and IC 110, as mentioned earlier; for example, a relatively small increase in interconnect length can lead to a significant reduction in bandwidth. In some embodiments, Figure 1A and Figure 1B The configuration makes it unnecessary for the electronic integrated circuit 110 (or photonic integrated circuit 105) to have a redistribution layer on either surface; instead, it may be sufficient to have a relatively small number of patterned metal layers (e.g., 10 or fewer metal layers) on one or both of the electronic integrated circuit 110 and the photonic integrated circuit 105.

[0028] The photonic integrated circuit 105 and the electronic integrated circuit 110 can be offset from each other, such that... Figure 1A Each of the photonic integrated circuit 105 and the electronic integrated circuit 110 shown protrudes beyond the other. Specifically, a first portion 115 of the electronic integrated circuit 110 may protrude beyond a first edge 120 of the photonic integrated circuit 105, and a first portion 125 of the photonic integrated circuit 105 may protrude beyond a first edge 130 of the electronic integrated circuit 110. (See reference...) Figure 1BThe photonic integrated circuit 105 and the electronic integrated circuit 110 can overlap in the overlap region 135. In some embodiments, the first portion 125 of the photonic integrated circuit 105 and the first portion 115 of the electronic integrated circuit 110 are located on opposite sides of the overlap region 135 (e.g., in...). Figure 1B As shown in the diagram, the overlapping region 135 is generally located between the first portion 115 of the electronic integrated circuit 110 and the first portion 125 of the photonic integrated circuit 105. In other embodiments, the relative positions may be different; for example, the first portion 115 of the electronic integrated circuit 110 may extend away from the overlapping region 135 along a first direction, and the first portion 125 of the photonic integrated circuit 105 may extend away from the overlapping region 135 along a second direction perpendicular to the first direction.

[0029] In the overlap region 135, the photonic integrated circuit 105 and the electronic integrated circuit 110 can be fastened together and electrically connected by a plurality of metal bumps. For example, a plurality of solder-topped copper pillar bumps 140 (e.g., Cu / Ni / SnAg bumps) can be formed on the front surface of the photonic integrated circuit 105, and a corresponding plurality of pads 145 (e.g., Ni / Au pads) can be formed on the front surface of the electronic integrated circuit 110; then, the photonic integrated circuit 105 can be soldered to the electronic integrated circuit 110, wherein each solder-topped copper pillar bump 140 of the photonic integrated circuit 105 in the overlap region is soldered to a corresponding pad on the electronic integrated circuit 110. Soldering can be performed, for example, using thermocompression bonding.

[0030] Each of the copper pillar bumps 140 may have a diameter between 25 μm and 100 μm and a height between 25 μm and 100 μm. Each of the copper pillar bumps 140 may be formed on a pad opening (e.g., an opening in an insulating (e.g., silicon dioxide) layer on the front surface of the photonic integrated circuit 105) having a diameter between 10 μm and 70 μm.

[0031] refer to Figure 2AThe copper pillar bumps 140 in the overlapping region 135 can be located on a grid that substantially fills the overlapping region 135 (e.g., a grid with a spacing between 50 μm and 150 μm), as shown, and the overlapping region 135 can be rectangular. In some embodiments, as shown, corner bumps can be omitted to relieve stress. The pads 145 on the electronic integrated circuit 110 (e.g., Ni / Au pads) can have a diameter greater than 100 μm (in embodiments where the grid spacing is greater than 100 μm). The spacing of the copper pillar bumps 140 can be selected based on the design channel count and density. For example, reducing the bump spacing (and correspondingly reducing the channel spacing) reduces the width of the PIC 105 and the electronic integrated circuit 110. The reduction in chip width increases bandwidth density and reduces the overall product form factor within high-volume manufacturing constraints. For example, in some embodiments, the optical engine discussed herein fills the edges of the printed circuit board 310, which can form the substrate of a switch ASIC package ( Figure 5 The substrate form factor is ultimately determined by the width of the PIC105 and the electronic integrated circuit 110, which depends on the bump pitch. Furthermore, reducing the substrate form factor improves the aforementioned serializer-deserializer performance and reduces the cost for high-volume production. This is discussed in more detail below. Each of the high-speed channels 150 can be connected via a pair of conductive traces on the front surface of the electronic integrated circuit 110 to a corresponding pair of pads, or “connector bumps” (e.g., Ni / Au pads), in the first portion 115 of the front surface of the electronic integrated circuit 110 as part of a connection to, for example, a switching ASIC (e.g., an XSR or USR connection, or other suitable serial electrical connection), as discussed in more detail below. The pads in the first portion 115 of the front surface of the electronic integrated circuit 110 can be similar to the pads on the front surface of the electronic integrated circuit 110 in the overlapping region 135, although the pads in the first portion 115 of the front surface of the electronic integrated circuit 110 may have different dimensions than the pads on the front surface of the electronic integrated circuit 110 in the overlapping region 135. Figure 2B An example of candidate pin assignment for a connector bump is shown. Corner connector bumps may not exist (e.g., ...). Figure 2A (as shown) or exist (as shown) Figure 2B As shown in the diagram).

[0032] The optoelectronic device can be located at a distance of 120 from the first edge 105 of the photonic integrated circuit (in Figure 2A In the orientation of the lower edge, there is a row of approximately 700µm, and each of the high-speed channels 150 can extend from the corresponding optoelectronic device in the overlapping region 135 into the first portion 115 of the electronic integrated circuit 110, such as Figure 2AAs shown in the illustration. For ease of explanation, not shown in Figure 2A The image shows a V-shaped groove.

[0033] In some embodiments, Figure 1A , Figure 1B and Figure 2A The components are made like Figure 3 Part of the larger component shown. A compressible diaphragm connector 305 (e.g., a compressible diaphragm connector forming multiple conductive paths between pads 145 on the front surface of the first portion 115 of the electronic integrated circuit 110 and corresponding pads on the printed circuit board 310 (which may form a connection to a switching ASIC, as discussed in more detail below). A carrier 315 may be secured to the rear surface of the electronic integrated circuit 110 (the surface opposite the front surface of the electronic integrated circuit 110). The carrier 315 may have one or more alignment ridges 320, which can be used to align the electronic integrated circuit 110 with the carrier 315 during assembly. The carrier 315 may provide mechanical reinforcement to the electronic integrated circuit 110 and the photonic integrated circuit 105 to reduce the risk of damage during assembly, and in operation, the carrier 315 may provide a heat flow path for conducting heat dissipated in the electronic integrated circuit 110. The carrier 315 may be made of copper or another thermally conductive material.

[0034] In some embodiments, all optoelectronic devices on the photonic integrated circuit 105 are identical. For example, on the photonic integrated circuit 105, which may be referred to as a receiving PIC (Rx PIC), all optoelectronic devices are photodetectors, and on the electronic integrated circuit 110 connected to the PIC (which may be referred to as an Rx IC), all interface circuits are transimpedance amplifiers. Similarly, on the photonic integrated circuit 105, which may be referred to as a transmitting PIC (Tx PIC), all optoelectronic devices can be modulators, and on the electronic integrated circuit 110 connected to the PIC (which may be referred to as a Tx IC), all interface circuits are modulator drivers.

[0035] Figure 4The manufacturing process is illustrated in some embodiments. Tx ICs are fabricated using steps including bumping (using Ni / Au pads 145), back-side grinding, and dicing, and Rx ICs are similarly fabricated using steps including bumping (using Ni / Au pads 145), back-side grinding, and dicing. Back-side grinding can be used to reduce the overall thickness of the Tx or Rx IC, while also reducing the case-junction thermal resistance between the IC and the ASIC heatsink, discussed in more detail below. Tx PICs are fabricated using steps including III-V microtransfer printing (to place a modulator (which may be a III-V device) on the PIC), bumping (using copper pillar bumps 140), and dicing, and Rx PICs are fabricated using steps including bumping (using copper pillar bumps 140), and dicing. Tx ICs are then soldered to Tx PICs to form an assembly that may be referred to as a "Tx sub-assembly," and Rx ICs are then soldered to Rx PICs to form an assembly that may be referred to as an "Rx sub-assembly." The Tx and Rx sub-assemblies are then fastened to carrier 315, and fiber optic tails are attached to the PIC to form an assembly that can be referred to as an optical engine. Among these sub-assemblies, especially when the IC undergoes back-side grinding during wafer fabrication, the PIC can be substantially thicker than the IC. A thicker PIC reduces warpage to support the fine-pitch bump assembly in 135 and improves component rigidity after the fiber optic tail assembly. In some embodiments, the photonic integrated circuit 105 has a thickness between 500 and 1000 micrometers, for example, approximately 680 micrometers, and the electronic integrated circuit 110 has a thickness between 100 and 700 micrometers, for example, 580 micrometers.

[0036] One or more optical engines can be used to direct light to objects such as... Figure 5 The illustrated digital integrated circuit 505 (e.g., a switching ASIC) provides the optical interface. An ASIC heatsink 510 conducts heat away from the digital integrated circuit 505 (e.g., to a heat pipe-based cooling system). A top clamp 515 (together with the bottom portion 517) secures the optical engine and compressible diaphragm connector 305 to the printed circuit board 310 and conducts heat flowing through the carrier 315 away from the optical engine; the top clamp is thermally connected to the removable heatsink section 520 via a layer of compliant thermal interface material 525. Figure 5 In the embodiment, the carrier 315 lacks Figure 3 The alignment ridge 320 shown is illustrated; however, in other embodiments, one or more alignment ridges 320 may be present, and the structure may otherwise resemble... Figure 5 The structure shown is illustrated. The printed circuit board 310 can form a substrate for a package, the substrate including... Figure 5The substrate shown can be secured and connected to another printed circuit board (e.g., a motherboard) via an array of conductors 530 on the lower surface of printed circuit board 310. Such a motherboard may have holes or cutouts for accommodating the bottom portion 517 of a clamp. A second beachfront 540 may be used to accommodate another optical engine (not shown) or, for example, an edge connector for serial electrical connection to the digital integrated circuit 505 (as discussed in more detail below).

[0037] Figure 5 Not drawn to scale. In some embodiments, the digital integrated circuit 505 is rectangular (e.g., square) and large enough to accommodate one or more optical engines on each of its four edges, thereby providing multiple optical interfaces to the digital integrated circuit 505. In some embodiments, the digital integrated circuit 505 has multiple electrical serial transmitters and receivers, and the package provides direct electrical connections to the first plurality of electrical serial transmitters and receivers of the digital integrated circuit 505 (e.g., at the second landing portion 540) and (as in...) Figure 5 As shown on the right, optical connections are established through one or more optical engines to a second plurality of high-speed channels of the digital integrated circuit 505. In embodiments with multiple optical engines, it may be advantageous to be able to replace any of the optical engines (e.g., to install a different version of the optical engine, or to replace a faulty optical engine) without, for example, removing the ASIC heatsink 510 from the digital integrated circuit 505. Figure 5 The configuration makes such a replacement of the optical engine possible. Figure 6 This is a perspective view of the optical engine in which optical fibers are installed. The optical engine includes a Tx PIC 605, a Tx IC 610, an Rx PIC 615, and an Rx IC 620. An exemplary implementation provides a throughput of up to 1.6T. If FR4 is used, the maximum number of optical fibers can be 20 Tx fibers and 4 Rx fibers.

[0038] As used herein, the word “or” is inclusive, such that “A or B” means, for example, (i) A, (ii) B, and (iii) either A or B. As used herein, the term “rectangle” includes, as a special case, a square, i.e., a square is an example of a rectangle. It will be understood that when an element or layer is referred to as “located on another element or layer,” “connected to,” “coupled to,” “adjacent to,” or “adjacent to another element or layer,” it may be directly located on, connected to, coupled to, adjacent to, or adjacent to another element or layer, or one or more intermediate elements or layers may exist. In contrast, when an element or layer is referred to as “directly located on another element or layer,” “directly connected to,” “directly coupled to,” “directly adjacent to,” or “adjacent to,” there are no intermediate elements or layers.

[0039] Any numerical range described herein is intended to include all subranges of the same numerical precision that fall within the described range. For example, the range “1.0 to 10.0” or “between 1.0 and 10.0” is intended to include all subranges between the described minimum value 1.0 and the described maximum value 10.0 (and includes both the described minimum value 1.0 and the described maximum value 10.0), that is, a minimum value equal to or greater than 1.0 and a maximum value equal to or less than 10.0, such as, for example, 2.4 to 7.6. Any maximum numerical limit described herein is intended to include all lower numerical limits that fall within it, and any minimum numerical limit described in this specification is intended to include all higher numerical limits that fall within it.

[0040] Although exemplary embodiments of systems and methods for co-packaging optics and transceiver components have been specifically described and illustrated herein, many modifications and variations will be apparent to those skilled in the art. Therefore, it will be understood that systems and methods for co-packaging optics and transceiver components constructed according to the principles of this disclosure may be embodied differently than those specifically described herein. The invention is also defined in the following claims and their equivalents.

Claims

1. A component comprising: Printed circuit boards; Photonic integrated circuits; as well as Electronic integrated circuits The front surface of the photonic integrated circuit is close to the front surface of the electronic integrated circuit in the overlapping region. The first portion of the photonic integrated circuit protrudes beyond the first edge of the electronic integrated circuit, and the first portion of the electronic integrated circuit protrudes beyond the first edge of the photonic integrated circuit. The conductor on the front surface of the electronic integrated circuit is connected to the conductor on the front surface of the photonic integrated circuit in the overlapping region. The printed circuit board is attached to the first portion of the electronic integrated circuit.

2. The component of claim 1, wherein the first edge of the electronic integrated circuit is opposite to the first portion of the electronic integrated circuit, and the first edge of the photonic integrated circuit is opposite to the first portion of the photonic integrated circuit.

3. The component according to claim 1 or claim 2, wherein the conductor on the front surface of the electronic integrated circuit is connected to the conductor on the front surface of the photonic integrated circuit via a metal bump in the overlapping region, the metal bump being one of a plurality of metal bumps arranged on a grid on a rectangular array, the metal bumps not present at grid points at the corners of the rectangular array.

4. The component of claim 1, wherein in the overlapping region: There is no redistribution layer on the electronic integrated circuit, and There is no redistribution layer on the photonic integrated circuit.

5. The component of claim 1, further comprising a compressible membrane connector between the first portion of the electronic integrated circuit and the printed circuit board, wherein a conductor on the first portion of the electronic integrated circuit is connected to a conductor on the printed circuit board via a conductor in the compressible membrane connector.

6. The component of claim 5, further comprising a digital integrated circuit on the printed circuit board, the digital integrated circuit being connected to the electronic integrated circuit via: The conductors on the printed circuit board, and The conductor in the compressible diaphragm connector.

7. The component of claim 6, further comprising: The heat sink on the digital integrated circuit; as well as The heat sink on the electronic integrated circuit.

8. The component of claim 7, wherein the component is configured to allow replacement without removing the heatsink from the digital integrated circuit: The photonic integrated circuit, and The electronic integrated circuit.

9. The component according to claim 1, wherein: The photonic integrated circuit includes a photodetector, and The electronic integrated circuit includes an amplifier connected to the photodetector via a conductive path having a length of less than 500 micrometers.

10. The component of claim 9, wherein the length of the conductive path is less than 200 micrometers.

11. The component of claim 9, wherein the length of the conductive path is less than 100 micrometers.

12. The component according to claim 1, wherein: The photonic integrated circuit includes a photodetector, and The electronic integrated circuit includes an amplifier connected to the photodetector; and The signal path from the light input carrying amplitude modulation of the photodetector to the output of the amplifier of the electrical signal corresponding to the amplitude modulation has a bandwidth of at least 3 dB of 10 GHz.

13. The component of claim 12, wherein the signal path has a 3dB bandwidth of at least 60 GHz.

14. The component of claim 1, wherein: The photonic integrated circuit includes a modulator, and The electronic integrated circuit includes an amplifier connected to the modulator via a conduction path having a length of less than 500 micrometers.

15. The component of claim 14, wherein the length of the conductive path is less than 200 micrometers.

16. The component of claim 14, wherein the length of the conductive path is less than 100 micrometers.

17. The component of claim 1, wherein: The photonic integrated circuit includes a modulator, and The electronic integrated circuit includes an amplifier connected to the modulator; and The signal path from the input of an electrical signal to the amplifier to the output of the modulator carrying light with amplitude modulation corresponding to the electrical signal has a bandwidth of at least 3 dB of 10 GHz.

18. The component of claim 17, wherein the signal path has a 3dB bandwidth of at least 40 GHz.

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