A light emitting diode chip and a method of manufacturing the same

Abstract

The application provides a preparation method of a light emitting diode chip, which comprises the following steps: providing a sapphire substrate, depositing an N-type semiconductor layer, an active light emitting layer and a P-type semiconductor layer on the sapphire substrate as epitaxial layers in sequence; preparing an N-type semiconductor layer conductive step on the P-type semiconductor layer; preparing a current spreading layer on the P-type semiconductor layer; preparing a current blocking layer on the current spreading layer, and then preparing a current blocking layer through hole on the current blocking layer; preparing a first semiconductor layer on the current blocking layer; thinning the sapphire substrate, and then laser peeling the thinned sapphire substrate to expose a PSS on the bottom of the N-type semiconductor layer; preparing an isolation groove on the PSS on the bottom of the N-type semiconductor layer; preparing a second insulating layer on the PSS on the bottom of the N-type semiconductor layer; preparing a second insulating layer through hole on the second insulating layer, and then preparing a P-type pad on the second insulating layer through hole.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a light-emitting diode chip and its fabrication method. Background Technology

[0002] Light-emitting diode (LED) chips are widely used in lighting and display fields due to their energy efficiency and high performance. Many of these applications involve extremely high power, such as outdoor lighting and automotive lighting. These high-power applications require the use of vertically structured LED chips.

[0003] In existing technologies, the fabrication of vertical LED chips requires the use of inductively coupled plasma etching (ICP-C) to etch the epitaxial layer and create isolation trenches. However, during the fabrication of these isolation trenches, after laser stripping, the depth difference between the PSS peaks and valleys creates pits. Existing etching methods replicate these pits onto the current blocking layer. Excessive depth difference between the PSS peaks and valleys can lead to over-etching of the current blocking layer. This can cause the etching ions to react with the metal layer beneath the current blocking layer, resulting in LED chip failure. Current solutions to this problem involve increasing the thickness of the current blocking layer, but this reduces the LED chip's luminous brightness. Summary of the Invention

[0004] Therefore, the purpose of this invention is to provide a light-emitting diode chip and its fabrication method, which can effectively solve the shortcomings of the prior art.

[0005] A method for fabricating a light-emitting diode chip, the method comprising:

[0006] S1, a sapphire substrate is provided, and an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially deposited on the sapphire substrate as an epitaxial layer;

[0007] S2, an N-type semiconductor layer conductive step is prepared on the P-type semiconductor layer;

[0008] S3, a current spreading layer is prepared on the P-type semiconductor layer;

[0009] S4, a current blocking layer is formed on the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer, and the N-type semiconductor layer conductive steps not covered by the current spreading layer, and then a current blocking layer via is formed on the current blocking layer.

[0010] S5, a first semiconductor layer is formed on the current blocking layer and the via of the current blocking layer;

[0011] S6, the sapphire substrate is thinned, and then the thinned sapphire substrate is laser-lifted to expose the PSS on the bottom of the N-type semiconductor layer;

[0012] S7, photoresist is coated on the PSS at the bottom of the N-type semiconductor layer, and then exposed and developed to remove part of the photoresist, exposing the PSS with the photoresist removed. Then, the exposed PSS and the epitaxial layer below the PSS are removed by the first inductively coupled plasma etching process to form an isolation trench.

[0013] The first inductively coupled plasma etching process includes a first etching step, a second etching step, a third etching step, a fourth etching step, and a fifth etching step to increase the material etching selectivity. The etching up power (SRF) and etching down power (BRF) of the first etching step are both greater than those of the second etching step. The ratio of the etching up power (SRF) to the etching down power (BRF) of the first etching step is less than that of the second etching step. The etching up power (SRF) and etching down power (BRF) of the third etching step are both greater than those of the second etching step. In the fourth etching step, the ratio of the etching power SRF to the etching power BRF in the third etching step is less than the ratio of the etching power SRF to the etching power BRF in the fourth etching step. The difference between the ratio of the etching power SRF to the etching power BRF in the first etching step and the ratio of the etching power SRF to the etching power BRF in the second etching step is less than the difference between the ratio of the etching power SRF to the etching power BRF in the third etching step and the ratio of the etching power SRF to the etching power BRF in the fourth etching step.

[0014] S8, a second insulating layer is prepared on the PSS at the bottom of the N-type semiconductor layer, the current blocking layer and the isolation trench;

[0015] S9, a second insulating layer through-hole is prepared on the second insulating layer, and then a P-type pad is prepared on the second insulating layer through-hole;

[0016] Furthermore, in the first etching step, the etching power SRF of the first etching step is 1000W-1200W, the etching power BRF of the first etching step is 800W-1000W, the ratio S / B of the etching power SRF of the first etching step to the etching power BRF of the first etching step is 1-1.5, and the etching time of the first etching step is 100S-150S.

[0017] Furthermore, in the second etching step, the etching power SRF of the second etching step is 400W-600W, the etching power BRF of the second etching step is 100W-150W, the ratio S / B of the etching power SRF of the second etching step to the etching power BRF of the second etching step is 4-6, the etching time of the second etching step is determined by the etching depth, and the total etching depth of the first etching step and the second etching step is 20%-30% of the depth of the entire isolation trench.

[0018] Furthermore, the difference between the ratio of etching power SRF to etching power BRF in the first etching step and the ratio of etching power SRF to etching power BRF in the second etching step is greater than or equal to 3.

[0019] Furthermore, in the third etching step, the etching power SRF of the third etching step is 1000W-1200W, the etching power BRF of the third etching step is 800W-1000W, the ratio S / B of the etching power SRF and the etching power BRF of the third etching step is 1-1.5, and the etching time of the third etching step is 100S-150S.

[0020] Furthermore, in the fourth etching step, the etching power SRF of the fourth etching step is 200W-400W, the etching power BRF of the fourth etching step is 30W-50W, the ratio S / B of the etching power SRF to the etching power BRF of the fourth etching step is 6-8, the etching time of the fourth etching step is determined by the etching depth, and the total etching depth of the third etching step and the fourth etching step is 60%-65% of the depth of the entire isolation trench.

[0021] Furthermore, the difference between the ratio of etching power SRF to etching power BRF in the third etching step and the ratio of etching power SRF to etching power BRF in the fourth etching step is greater than or equal to 5.

[0022] Furthermore, in the fifth etching step, the etching power SRF of the fifth etching step is 100W-300W, the etching power BRF of the fifth etching step is 30W-100W, the ratio S / B of the etching power of the fifth etching step and the etching power of the fifth etching step is 3-4, and the etching depth of the fifth etching step is 5%-20% of the depth of the entire isolation trench.

[0023] Furthermore, the first semiconductor layer includes a P-type reflective metal layer, a P-type conductive metal layer, a first insulating layer, a first insulating layer via, an N-type conductive metal layer, a first bonding layer, a second bonding layer, and a conductive silicon wafer, which are sequentially disposed on the current blocking layer.

[0024] The present invention also provides a light-emitting diode chip, which is prepared by the light-emitting diode chip preparation method described above.

[0025] Compared with the prior art, the beneficial effects of the present invention are:

[0026] In the first etching step, the etching up power SRF and etching down power BRF of the first etching step are set to be greater than those of the second etching step. The ratio of etching up power SRF to etching down power BRF of the first etching step is set to be less than that of etching up power SRF to etching down power BRF of the second etching step. The larger etching power and the smaller ratio of etching up power to etching down power make the etching have a good bombardment effect. At this time, the bombardment effect on the PSS peak position is much greater than that on the PSS trough position, reducing the depth difference between the PSS peak and PSS trough.

[0027] In the second etching step, the etching power SRF and etching power BRF of the second etching step are both set to be less than those of the first etching step. The ratio of etching power SRF to etching power BRF of the second etching step is set to be greater than that of the first etching step. The reduction in etching power and the increase in the ratio of etching power SRF to etching power BRF result in the etching rate of the PSS peak being greater than that of the PSS trough, thereby further reducing the depth difference between the PSS peak and the PSS trough.

[0028] In the third etching step, the etching up power SRF and etching down power BRF of the third etching step are both set to be greater than those of the fourth etching step. The ratio of the etching up power SRF to the etching down power BRF of the third etching step is set to be less than that of the etching up power SRF to the etching down power BRF of the fourth etching step. This setting makes the third etching step achieve the same effect as the first etching step.

[0029] In the fourth etching step, the etching up power SRF and etching down power BRF of the fourth etching step are both set to be less than those of the third etching step. The ratio of the etching up power SRF to the etching down power BRF of the fourth etching step is set to be greater than that of the third etching step. This setting makes the fourth etching step achieve the same effect as the second etching step.

[0030] The difference between the ratio of etching up power SRF to etching down power BRF in the first etching step and the ratio of etching up power SRF to etching down power BRF in the second etching step is smaller than the difference between the ratio of etching up power SRF to etching down power BRF in the third etching step and the ratio of etching up power SRF to etching down power BRF in the fourth etching step, thus achieving better results.

[0031] After the first, second, third and fourth etching steps are completed, the PSS peak is completely eliminated and the PSS peak and PSS valley are located on the same horizontal plane. This can avoid the reaction between the etching ions and the metal layer under the current blocking layer caused by the large depth difference between the PSS peak and PSS valley, which would cause the light-emitting diode chip to fail.

[0032] The fifth etching step increases the etching selectivity ratio of SiO2 and GaN materials, meaning that the etching parameters for SiO2 are much higher than those for GaN. This further reduces the over-etching of the current blocking layer caused by the preparation of the isolation trench, thus eliminating the need to thicken the current blocking layer and avoiding a decrease in the luminous brightness of the LED chip. Attached Figure Description

[0033] Figure 1 This is a flowchart of the fabrication method of the light-emitting diode chip in Embodiment 1 of the present invention;

[0034] Figure 2 This is a cross-sectional schematic diagram of the light-emitting diode chip in Embodiment 1 of the present invention;

[0035] Figure 3 This is a cross-sectional schematic diagram of the semi-finished product after completing step S2 in Embodiment 1 of the present invention;

[0036] Explanation of key component symbols:

[0037]

[0038] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0039] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0040] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0042] Example 1

[0043] Please see Figures 1-3 This invention discloses a method for fabricating a light-emitting diode chip, the method comprising:

[0044] S1, a sapphire substrate 10 is provided, and an N-type semiconductor layer 111, an active light-emitting layer 112 and a P-type semiconductor layer 113 are sequentially deposited on the sapphire substrate 10 as an epitaxial layer 11;

[0045] S2, an N-type semiconductor conductive step 114 is prepared on the P-type semiconductor layer 113;

[0046] Specifically, in this embodiment, the specific steps for preparing the N-type semiconductor layer conductive step 114 include:

[0047] Photoresist is coated on the surface of the P-type semiconductor layer 113. Then, a portion of the photoresist is removed using an exposure and development process to expose a portion of the P-type semiconductor layer. Then, a second inductively coupled plasma etching process is used to remove the exposed P-type semiconductor layer and the active light-emitting layer below this portion of the P-type semiconductor layer until the N-type semiconductor layer is exposed, forming the conductive step 114 of the N-type semiconductor layer. Finally, excess photoresist is removed.

[0048] S3, a current spreading layer 12 is prepared on the P-type semiconductor layer 113;

[0049] Specifically, in this embodiment, the specific steps for fabricating the current spreading layer 12 include:

[0050] Indium tin oxide (ITO) is deposited on the surface of the P-type semiconductor layer 113 using a magnetron sputtering process. Then, photoresist is coated on the ITO surface. After exposure and development, some of the photoresist is removed, exposing some of the ITO. The exposed ITO is then removed using an ITO etching solution. Finally, excess photoresist is removed to form the current spreading layer 12.

[0051] S4, a current blocking layer 13 is prepared on the current spreading layer 12, the P-type semiconductor layer not covered by the current spreading layer 12, and the N-type semiconductor layer conductive steps not covered by the current spreading layer 12, and then a current blocking layer via 131 is prepared on the current blocking layer 13.

[0052] Specifically, in this embodiment, the specific steps for preparing the current blocking layer 13 and the current blocking layer via 131 include:

[0053] SiO2 is deposited as the current blocking layer 13 on the current spreading layer 12, the P-type semiconductor layer not covered by the current spreading layer 12, and the N-type semiconductor layer not covered by the current spreading layer 12 using a PECVD process. Then, photoresist is coated on the surface of the current blocking layer 13. Then, exposure and development are used to remove part of the photoresist, exposing the current blocking layer under the photoresist. Then, BOE etching solution is used to remove the exposed current blocking layer, forming the current blocking layer via 131. Then, the photoresist is removed.

[0054] S5, a first semiconductor layer is formed on the current blocking layer 13 and the current blocking layer via 131;

[0055] Furthermore, the first semiconductor layer includes a P-type reflective metal layer 14, a P-type conductive metal layer 15, a first insulating layer 16, a first insulating layer via 161, an N-type conductive metal layer 17, a first bonding layer 181, a second bonding layer 182, and a conductive silicon wafer 19, which are sequentially disposed on the current blocking layer 13.

[0056] Specifically, in this embodiment, the specific steps for preparing the P-type reflective metal layer 14 include:

[0057] A negative photoresist is coated on the surface of the current blocking layer via 131 and the current blocking layer 13. Then, a portion of the photoresist is removed by exposure and development. Then, Ag metal with a thickness of 1500Å-2000Å, Ni metal with a thickness of 300Å-500Å, and Ti metal with a thickness of 300Å-500Å are deposited sequentially by electron beam evaporation. Then, the metal on the photoresist is removed by lift-off process, and then the photoresist is removed to form the P-type reflective metal layer 14.

[0058] Specifically, in this embodiment, the steps for preparing the P-type conductive metal layer 15 include:

[0059] A negative photoresist is coated on the surface of the P-type reflective metal layer 14 and the current blocking layer not covered by the P-type reflective metal layer 14. Then, a portion of the photoresist is removed by exposure and development. Then, Ti metal with a thickness of 200 Å-300 Å, Pt metal with a thickness of 1500 Å-2000 Å, Au metal with a thickness of 4000 Å-8000 Å, and Cr metal with a thickness of 200 Å-500 Å are deposited sequentially by electron beam evaporation. Then, the metal on the photoresist is removed by lift-off process. Finally, the photoresist is removed to form the P-type conductive metal layer 15.

[0060] Specifically, in this embodiment, the steps for preparing the first insulating layer 16 include:

[0061] An Al2O3 film with a thickness of 600Å-1200Å is first deposited on the surface of the P-type conductive metal layer 15 and the current blocking layer not covered by the P-type conductive metal layer 15 using an atomic layer deposition process. Then, a SiO2 film with a thickness of 6000Å-8000Å is deposited on the Al2O3 film using a PECVD process. The two films together constitute the first insulating layer 16.

[0062] Specifically, in this embodiment, the steps for preparing the first insulating layer via 161 include:

[0063] Photoresist is coated on the surface of the first insulating layer 16. Then, a portion of the photoresist is removed using an exposure and development process to expose the first insulating layer beneath the photoresist. The exposed portion of the first insulating layer and the current blocking layer beneath it are then removed using an ICP etching process to form a via 161 in the first insulating layer. The via 161 in the first insulating layer is located above the conductive step 114 of the N-type semiconductor layer.

[0064] Specifically, in this embodiment, the steps for preparing the N-type conductive metal layer 17 include:

[0065] Using an electron beam evaporation process, Cr metal with a thickness of 20 Å-50 Å, Al metal with a thickness of 2000 Å-5000 Å, Ti metal with a thickness of 1500 Å-2000 Å, and Pt metal with a thickness of 1500 Å-2000 Å are sequentially deposited on the first insulating layer 16 and the through-hole 161 of the first insulating layer. The above four metal layers together constitute the N-type conductive metal layer 17.

[0066] Specifically, in this embodiment, the steps for preparing the first bonding layer 181 include:

[0067] Using an electron beam evaporation process, a metal Ti layer with a thickness of 3000Å-4000Å and 2-5 sets of Sn and Ni metal stacks are sequentially deposited on the N-type conductive metal layer 17 as the first bonding layer 181. In each stack, the Sn metal thickness is 5000Å-10000Å and the Ni metal thickness is 2000Å-4000Å.

[0068] Specifically, in this embodiment, the steps for preparing the second bonding layer 182 include:

[0069] A conductive silicon wafer 19 is provided. Then, an electron beam evaporation process is used to sequentially deposit a metal Ti with a thickness of 3000Å-4000Å and 2-5 sets of Sn and Ni metal stacks as the second bonding layer 182 on the conductive silicon wafer 19. In each stack, the Sn metal thickness is 5000Å-10000Å and the Ni metal thickness is 2000Å-4000Å. Then, the conductive silicon wafer 19 is hot-pressed onto the first bonding layer 181 through the second bonding layer 182 using a hot-press bonding process.

[0070] S6, the sapphire substrate 10 is thinned, and then the thinned sapphire substrate is laser-lifted to expose the PSS on the bottom of the N-type semiconductor layer 111;

[0071] Specifically, in this embodiment, step S6 includes the following steps:

[0072] The sapphire substrate 10 is thinned using a grinding process, leaving a thickness of 200µm-350µm. Then, a laser lift-off process is used to remove the thinned sapphire substrate. This process employs a 266nm ultraviolet laser to irradiate the sapphire surface, using the laser energy to decompose GaN at the interface between the sapphire substrate and the N-type semiconductor layer 111, generating metallic gallium and nitrogen gas. This process removes the thinned sapphire substrate, exposing the PSS at the bottom of the N-type semiconductor layer 111. The laser spot radius in the laser lift-off process is between 12µm and 16µm, the laser spot movement speed is between 2500mm / s and 3000mm / s, and the laser power is between 80W and 100W.

[0073] S7, photoresist is coated on the PSS at the bottom of the N-type semiconductor layer 111, and then exposed and developed to remove part of the photoresist, exposing the PSS with the photoresist removed. Then, the first inductively coupled plasma etching process is used to remove the exposed PSS and the epitaxial layer below the PSS to form an isolation trench 20.

[0074] The first inductively coupled plasma etching process includes a first etching step, a second etching step, a third etching step, a fourth etching step, and a fifth etching step to increase the material etching selectivity. The etching up power (SRF) and etching down power (BRF) of the first etching step are both greater than those of the second etching step. The ratio of the etching up power (SRF) to the etching down power (BRF) of the first etching step is less than that of the second etching step. The etching up power (SRF) and etching down power (BRF) of the third etching step are both greater than those of the second etching step. In the fourth etching step, the ratio of the etching power SRF to the etching power BRF in the third etching step is less than the ratio of the etching power SRF to the etching power BRF in the fourth etching step. The difference between the ratio of the etching power SRF to the etching power BRF in the first etching step and the ratio of the etching power SRF to the etching power BRF in the second etching step is less than the difference between the ratio of the etching power SRF to the etching power BRF in the third etching step and the ratio of the etching power SRF to the etching power BRF in the fourth etching step.

[0075] Furthermore, in the first etching step, the etching power SRF of the first etching step is 1000W-1200W, the etching power BRF of the first etching step is 800W-1000W, the ratio S / B of the etching power SRF of the first etching step to the etching power BRF of the first etching step is 1-1.5, and the etching time of the first etching step is 100S-150S.

[0076] Specifically, in this embodiment, the etching power SRF of the first etching step is 1000W, the etching power BRF of the first etching step is 1000W, and the ratio S / B of the etching power SRF and the etching power BRF of the first etching step is 1.

[0077] Furthermore, in the second etching step, the etching power SRF of the second etching step is 400W-600W, the etching power BRF of the second etching step is 100W-150W, the ratio S / B of the etching power SRF of the second etching step to the etching power BRF of the second etching step is 4-6, the etching time of the second etching step is determined by the etching depth, and the total etching depth of the first etching step and the second etching step is 20%-30% of the depth of the entire isolation trench.

[0078] Specifically, in this embodiment, the etching power SRF of the second etching step is 400W, the etching power BRF of the second etching step is 100W, and the ratio S / B of the etching power SRF and the etching power BRF of the second etching step is 4.

[0079] Furthermore, the difference between the ratio of etching power SRF to etching power BRF in the first etching step and the ratio of etching power SRF to etching power BRF in the second etching step is greater than or equal to 3.

[0080] Specifically, in this embodiment, the difference between the ratio of etching power SRF to etching power BRF in the first etching step and the ratio of etching power SRF to etching power BRF in the second etching step is 3.

[0081] Furthermore, in the third etching step, the etching power SRF of the third etching step is 1000W-1200W, the etching power BRF of the third etching step is 800W-1000W, the ratio S / B of the etching power SRF and the etching power BRF of the third etching step is 1-1.5, and the etching time of the third etching step is 100S-150S.

[0082] Specifically, in this embodiment, the etching power SRF of the third etching step is 1000W, the etching power BRF of the third etching step is 1000W, and the ratio S / B of the etching power SRF and the etching power BRF of the third etching step is 1.

[0083] Furthermore, in the fourth etching step, the etching power SRF of the fourth etching step is 200W-400W, the etching power BRF of the fourth etching step is 30W-50W, the ratio S / B of the etching power SRF to the etching power BRF of the fourth etching step is 6-8, the etching time of the fourth etching step is determined by the etching depth, and the total etching depth of the third etching step and the fourth etching step is 60%-65% of the depth of the entire isolation trench.

[0084] Specifically, in this embodiment, the etching power SRF of the fourth etching step is 200W, the etching power BRF of the fourth etching step is 30W, and the ratio S / B of the etching power SRF to the etching power BRF of the fourth etching step is 20 / 3.

[0085] Furthermore, the difference between the ratio of etching power SRF to etching power BRF in the third etching step and the ratio of etching power SRF to etching power BRF in the fourth etching step is greater than or equal to 5.

[0086] Specifically, in this embodiment, the difference between the ratio of etching power SRF to etching power BRF in the third etching step and the ratio of etching power SRF to etching power BRF in the fourth etching step is 17 / 3.

[0087] Furthermore, in the fifth etching step, the etching power SRF of the fifth etching step is 100W-300W, the etching power BRF of the fifth etching step is 30W-100W, the ratio S / B of the etching power of the fifth etching step and the etching power of the fifth etching step is 3-4, and the etching depth of the fifth etching step is 5%-20% of the depth of the entire isolation trench.

[0088] Specifically, in this embodiment, the etching power SRF of the fifth etching step is 100W, the etching power BRF of the fifth etching step is 30W, and the ratio S / B of the etching power of the fifth etching step to the etching power of the fifth etching step is 10 / 3.

[0089] It should be noted that in this embodiment, the first etching step, the second etching step, the third etching step, and the fourth etching step all etch away the depth of the maximum value, while the fifth etching step can only etch away the depth of the minimum value; the first etching step, the second etching step, the third etching step, and the fourth etching step all etch away the depth of the minimum value, while the fifth etching step can only etch away the depth of the maximum value.

[0090] In the first etching step, the etching up power SRF and etching down power BRF of the first etching step are set to be greater than those of the second etching step. The ratio of etching up power SRF to etching down power BRF of the first etching step is set to be less than that of etching up power SRF to etching down power BRF of the second etching step. The larger etching power and the smaller ratio of etching up power to etching down power make the etching have a good bombardment effect. At this time, the bombardment effect on the PSS peak position is much greater than that on the PSS trough position, reducing the depth difference between the PSS peak and PSS trough.

[0091] In the second etching step, the etching power SRF and etching power BRF of the second etching step are both set to be less than those of the first etching step. The ratio of etching power SRF to etching power BRF of the second etching step is set to be greater than that of the first etching step. The reduction in etching power and the increase in the ratio of etching power SRF to etching power BRF result in the etching rate of the PSS peak being greater than that of the PSS trough, thereby further reducing the depth difference between the PSS peak and the PSS trough.

[0092] In the third etching step, the etching up power SRF and etching down power BRF of the third etching step are both set to be greater than those of the fourth etching step. The ratio of the etching up power SRF to the etching down power BRF of the third etching step is set to be less than that of the etching up power SRF to the etching down power BRF of the fourth etching step. This setting makes the third etching step achieve the same effect as the first etching step.

[0093] In the fourth etching step, the etching up power SRF and etching down power BRF of the fourth etching step are both set to be less than those of the third etching step. The ratio of the etching up power SRF to the etching down power BRF of the fourth etching step is set to be greater than that of the third etching step. This setting makes the fourth etching step achieve the same effect as the second etching step.

[0094] The difference between the ratio of etching up power SRF to etching down power BRF in the first etching step and the ratio of etching up power SRF to etching down power BRF in the second etching step is smaller than the difference between the ratio of etching up power SRF to etching down power BRF in the third etching step and the ratio of etching up power SRF to etching down power BRF in the fourth etching step, thus achieving better results.

[0095] After the first, second, third and fourth etching steps are completed, the PSS peak is completely eliminated and the PSS peak and PSS valley are located on the same horizontal plane. This can avoid the reaction between the etching ions and the metal layer under the current blocking layer caused by the large depth difference between the PSS peak and PSS valley, which would cause the light-emitting diode chip to fail.

[0096] The fifth etching step increases the etching selectivity ratio of SiO2 and GaN materials, meaning that the etching parameters have a much higher etching rate for SiO2 than for GaN. This further reduces the over-etching of the current blocking layer caused by the preparation of the isolation trench, thus eliminating the need to thicken the current blocking layer and avoiding a decrease in the luminous brightness of the LED chip.

[0097] S8, a second insulating layer 21 is prepared on the PSS at the bottom of the N-type semiconductor layer 111, the current blocking layer 13 and the isolation trench 20;

[0098] Specifically, in this embodiment, the steps for preparing the second insulating layer 21 include:

[0099] Al2O3 is deposited as the second insulating layer 21 on the PSS at the bottom of the N-type semiconductor layer 111, the current blocking layer 13, and the isolation trench 20.

[0100] S9, a second insulating layer through-hole 211 is prepared on the second insulating layer 21, and then a P-type pad 22 is prepared on the second insulating layer through-hole 211;

[0101] Specifically, in this embodiment, the steps for preparing the second insulating layer via 211 and the P-type pad 22 include:

[0102] A negative photoresist is coated on the surface of the second insulating layer 21. Then, exposure and development are performed to remove part of the photoresist, exposing part of the second insulating layer. Then, BOE etching solution is used to etch away the exposed part of the second insulating layer and the current blocking layer below it until the P-type conductive metal layer is formed, forming the second insulating layer via 211. Then, electron beam evaporation is used to sequentially deposit Ti metal with a thickness of 500 Å, Pt metal with a thickness of 1000 Å, Au metal with a thickness of 5000 Å, Ni metal with a thickness of 2000 Å, and Au metal with a thickness of 10000 Å. Then, the metal on the photoresist is removed using a lift-off process, and then the photoresist is removed to form the P-type pad layer.

[0103] Please see Figure 2 The figure shown is a cross-sectional schematic diagram of a light-emitting diode chip prepared by the method for preparing a light-emitting diode chip according to an embodiment of the present invention.

[0104] Example 2

[0105] A light-emitting diode chip, which differs from the light-emitting diode chip prepared in Example 1 in that:

[0106] The etching power SRF of the first etching step is 1200W, the etching power BRF of the first etching step is 1000W, and the ratio S / B of the etching power SRF and the etching power BRF of the first etching step is 1.2.

[0107] The etching power SRF of the second etching step is 600W, the etching power BRF of the second etching step is 125W, and the ratio S / B of the etching power SRF and the etching power BRF of the second etching step is 4.8.

[0108] The difference between the ratio of etching power SRF to etching power BRF in the first etching step and the ratio of etching power SRF to etching power BRF in the second etching step is 3.6.

[0109] The etching power SRF of the third etching step is 1200W, the etching power BRF of the third etching step is 1000W, and the ratio S / B of the etching power SRF to the etching power BRF of the third etching step is 1.2.

[0110] The etching power SRF of the fourth etching step is 300W, the etching power BRF of the fourth etching step is 40W, and the ratio S / B of the etching power SRF to the etching power BRF of the fourth etching step is 7.5.

[0111] The difference between the ratio of etching power SRF to etching power BRF in the third etching step and the ratio of etching power SRF to etching power BRF in the fourth etching step is 6.3.

[0112] The etching power SRF of the fifth etching step is 175W, and the etching power BRF of the fifth etching step is 50W. The ratio of the etching power SRF to the etching power BRF of the fifth etching step is 3.5.

[0113] Example 3

[0114] A light-emitting diode chip, which differs from the light-emitting diode chip prepared in Example 1 in that:

[0115] The etching power SRF of the first etching step is 1200W, the etching power BRF of the first etching step is 800W, and the ratio S / B of the etching power SRF and the etching power BRF of the first etching step is 1.5.

[0116] The etching power SRF of the second etching step is 600W, the etching power BRF of the second etching step is 100W, and the ratio S / B of the etching power SRF and the etching power BRF of the second etching step is 6.

[0117] The difference between the ratio of etching power SRF to etching power BRF in the first etching step and the ratio of etching power SRF to etching power BRF in the second etching step is 4.5.

[0118] The etching power SRF of the third etching step is 1200W, the etching power BRF of the third etching step is 800W, and the ratio S / B of the etching power SRF to the etching power BRF of the third etching step is 1.5.

[0119] The etching power SRF of the fourth etching step is 400W, the etching power BRF of the fourth etching step is 50W, and the ratio S / B of the etching power SRF to the etching power BRF of the fourth etching step is 8.

[0120] The difference between the ratio of etching power SRF to etching power BRF in the third etching step and the ratio of etching power SRF to etching power BRF in the fourth etching step is 6.5.

[0121] The etching power SRF of the fifth etching step is 300W, and the etching power BRF of the fifth etching step is 75W. The ratio of the etching power SRF to the etching power BRF of the fifth etching step is 4.

[0122] Comparative Example 1

[0123] A light-emitting diode chip, which differs from the light-emitting diode chip prepared in Example 1 in that:

[0124] In step S7, the first inductively coupled plasma etching process includes only the sixth etching step, wherein the etching up power SRF of the sixth etching step is 1100W and the etching down power BRF of the sixth etching step is 550W.

[0125] Based on the LED chips of Embodiments 1, 2, and 3 above, and the LED chip in Comparative Example 1, the LED chips prepared in Embodiments 1, 2, and 3, and the LED chip in Comparative Example 1, were subjected to the same test current for comparison of current blocking layer thickness, chip brightness, and chip voltage. The corresponding test results are shown in the table below:

[0126]

[0127] It should be noted that, in order to ensure the reliability of the verification results, when comparing the current blocking layer thickness, chip brightness and chip voltage of the LED chips prepared in the above embodiments 1, 2 and 3 of the present invention and the LED chips in Comparative Example 1, the other processes and parameters should be kept consistent except for the above parameters.

[0128] In summary, the method for fabricating a light-emitting diode chip in the above embodiments of the present invention, in the first etching step, sets both the etching up power (SRF) and etching down power (BRF) of the first etching step to be greater than those of the second etching step, and sets the ratio of the etching up power (SRF) to the etching down power (BRF) of the first etching step to be less than that of the second etching step. This higher etching power and lower ratio of etching up power to etching down power result in a better bombardment effect during etching. In this case, the bombardment effect at the PSS peak position is much greater than that at the PSS trough position. The bombardment effect reduces the depth difference between PSS peaks and troughs. In the second etching step, the etching up power (SRF) and etching down power (BRF) are set to be lower than those of the first etching step. Furthermore, the ratio of the etching up power (SRF) to the etching down power (BRF) in the second etching step is set to be greater than that in the first etching step. This reduction in etching power and increase in the ratio of the etching up power to the etching down power results in a higher etching rate for the PSS peaks compared to the PSS troughs, thus reducing the depth difference between the PSS peaks and troughs. The etching power difference is further reduced; in the third etching step, the etching up power SRF and etching down power BRF of the third etching step are both set to be greater than those of the fourth etching step, and the ratio of the etching up power SRF to the etching down power BRF of the third etching step is set to be less than that of the fourth etching step. This setting makes the third etching step achieve the same effect as the first etching step; in the fourth etching step, the etching up power SRF and etching down power BRF of the fourth etching step are both set to be less than those of the third etching step. The etching power BRF setting is optimized by setting the ratio of the etching up power SRF to the etching down power BRF in the fourth etching step to be greater than that in the third etching step. This setting ensures that the fourth etching step achieves the same effect as the second etching step. The difference between the ratio of the etching up power SRF to the etching down power BRF in the first etching step and the ratio of the etching up power SRF to the etching down power BRF in the second etching step is smaller than the difference between the ratio of the etching up power SRF to the etching down power BRF in the third etching step and the ratio of the etching up power SRF to the etching down power BRF in the fourth etching step, resulting in better performance.After the first, second, third, and fourth etching steps are completed, the PSS peak is completely eliminated, and the PSS peak and trough are located on the same horizontal plane. This avoids the reaction between the etching ions and the metal layer below the current blocking layer caused by an excessive depth difference between the PSS peak and trough, which could lead to LED chip failure. The fifth etching step increases the etching selectivity ratio of SiO2 and GaN materials, meaning the etching parameters for SiO2 have a much higher etching rate than for GaN. This further reduces the over-etching of the current blocking layer caused by the fabrication of the isolation trench, thus eliminating the need to increase the thickness of the current blocking layer and preventing a decrease in the LED chip's brightness.

[0129] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0130] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these modifications and improvements all fall within the scope of protection of the present invention. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a light-emitting diode chip, characterized in that, The preparation method includes the following steps: S1, a sapphire substrate is provided, and an N-type semiconductor layer, an active light-emitting layer and a P-type semiconductor layer are sequentially deposited on the sapphire substrate as an epitaxial layer; S2, an N-type semiconductor layer conductive step is prepared on the P-type semiconductor layer; S3, a current spreading layer is prepared on the P-type semiconductor layer; S4, a current blocking layer is formed on the current spreading layer, the P-type semiconductor layer not covered by the current spreading layer, and the N-type semiconductor layer conductive steps not covered by the current spreading layer, and then a current blocking layer via is formed on the current blocking layer. S5, a first semiconductor layer is formed on the current blocking layer and the via of the current blocking layer; S6, the sapphire substrate is thinned, and then the thinned sapphire substrate is laser-lifted to expose the PSS on the bottom of the N-type semiconductor layer; S7, photoresist is coated on the PSS at the bottom of the N-type semiconductor layer, and then exposed and developed to remove part of the photoresist, exposing the PSS with the photoresist removed. Then, the exposed PSS and the epitaxial layer below the PSS are removed by the first inductively coupled plasma etching process to form an isolation trench. The first inductively coupled plasma etching process includes a first etching step, a second etching step, a third etching step, a fourth etching step, and a fifth etching step to increase the material etching selectivity. The etching up power (SRF) and etching down power (BRF) of the first etching step are both greater than those of the second etching step. The ratio of the etching up power (SRF) to the etching down power (BRF) of the first etching step is less than that of the second etching step. The etching up power (SRF) and etching down power (BRF) of the third etching step are both greater than those of the second etching step. In the fourth etching step, the ratio of the etching power SRF to the etching power BRF in the third etching step is less than the ratio of the etching power SRF to the etching power BRF in the fourth etching step. The difference between the ratio of the etching power SRF to the etching power BRF in the first etching step and the ratio of the etching power SRF to the etching power BRF in the second etching step is less than the difference between the ratio of the etching power SRF to the etching power BRF in the third etching step and the ratio of the etching power SRF to the etching power BRF in the fourth etching step. S8, a second insulating layer is prepared on the PSS at the bottom of the N-type semiconductor layer, the current blocking layer and the isolation trench; S9, a second insulating layer via is prepared on the second insulating layer, and then a P-type pad is prepared on the second insulating layer via.

2. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, In the first etching step, the etching up power SRF of the first etching step is 1000W-1200W, the etching down power BRF of the first etching step is 800W-1000W, the ratio S / B of the etching up power SRF and the etching down power BRF of the first etching step is 1-1.5, and the etching time of the first etching step is 100S-150S.

3. The method for fabricating a light-emitting diode chip according to claim 2, characterized in that, In the second etching step, the etching power SRF of the second etching step is 400W-600W, the etching power BRF of the second etching step is 100W-150W, the ratio S / B of the etching power SRF of the second etching step to the etching power BRF of the second etching step is 4-6, the etching time of the second etching step is determined by the etching depth, and the total etching depth of the first etching step and the second etching step is 20%-30% of the depth of the entire isolation trench.

4. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, The difference between the ratio of etching power SRF to etching power BRF in the first etching step and the ratio of etching power SRF to etching power BRF in the second etching step is greater than or equal to 3.

5. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, In the third etching step, the etching power SRF of the third etching step is 1000W-1200W, the etching power BRF of the third etching step is 800W-1000W, the ratio S / B of the etching power SRF of the third etching step to the etching power BRF of the third etching step is 1-1.5, and the etching time of the third etching step is 100S-150S.

6. The method for fabricating a light-emitting diode chip according to claim 5, characterized in that, In the fourth etching step, the etching power SRF is 200W-400W, the etching power BRF is 30W-50W, the ratio S / B of the etching power SRF to the etching power BRF is 6-8, the etching time of the fourth etching step is determined by the etching depth, and the total etching depth of the third and fourth etching steps is 60%-65% of the depth of the entire isolation trench.

7. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, The difference between the ratio of etching up power SRF to etching down power BRF in the third etching step and the ratio of etching up power SRF to etching down power BRF in the fourth etching step is greater than or equal to 5.

8. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, In the fifth etching step, the etching power SRF of the fifth etching step is 100W-300W, the etching power BRF of the fifth etching step is 30W-100W, the ratio S / B of the etching power of the fifth etching step and the etching power of the fifth etching step is 3-4, and the etching depth of the fifth etching step is 5%-20% of the depth of the entire isolation trench.

9. The method for fabricating a light-emitting diode chip according to claim 1, characterized in that, The first semiconductor layer includes a P-type reflective metal layer, a P-type conductive metal layer, a first insulating layer, a first insulating layer via, an N-type conductive metal layer, a first bonding layer, a second bonding layer, and a conductive silicon wafer, which are sequentially disposed on the current blocking layer.

10. A light-emitting diode chip, manufactured by the method for manufacturing a light-emitting diode chip according to any one of claims 1-9, characterized in that, include: The epitaxial layer, N-type semiconductor layer conductive steps, current spreading layer, current blocking layer, current blocking layer via, and first semiconductor layer are arranged sequentially from top to bottom. The epitaxial layer includes an N-type semiconductor layer, an active light-emitting layer, and a P-type semiconductor layer arranged sequentially from top to bottom. An isolation trench is provided on the outside of the epitaxial layer. A second insulating layer is provided on top of the epitaxial layer, the isolation trench, and the current blocking layer not covered by the epitaxial layer. A second insulating layer via is provided on the second insulating layer, and a P-type pad is provided in the second insulating layer via. A laser-lifted sapphire substrate-based PSS is disposed between the side of the N-type semiconductor layer away from the active light-emitting layer and the second insulating layer. The thickness of the epitaxial layer plus the current blocking layer is greater than the thickness of the isolation trench plus the depth of the PSS.

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