Display mother board, detection method thereof and display panel

Abstract

The embodiment of the invention provides a display mother board, a detection method thereof and a display panel. The display mother board comprises a carrier board; the display area comprises a plurality of sub-pixels, the non-display area comprises a plurality of detection bonding pads, and the detection bonding pads are connected with the sub-pixels; the plurality of display substrates comprise a plurality of first display substrates; the plurality of signal lines comprise a first signal line, the first signal line comprises at least one first signal input end and a plurality of first signal output ends, and one first signal output end is connected with the detection bonding pad of one first display substrate; the plurality of first signal output ends comprise a first sub-signal output end and a second sub-signal output end, the resistor of the first signal line between the first sub-signal output end and the first signal input end is a first resistor, and the resistor of the first signal line between the second sub-signal output end and the first signal input end is a second resistor; the absolute value of the difference between the first resistor and the second resistor is less than or equal to 5%.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of display, in particular to a display mother board, a detection method thereof and a display panel. BACKGROUND

[0002] Organic Light Emitting Diode (OLED) display technology is considered as the most potential new display technology in the next generation. Compared with liquid crystal display technology, OLED display technology has the advantages of low energy consumption, low cost, self-luminous, wide viewing angle and fast response speed.

[0003] In the preparation process of a traditional OLED display panel, a fine metal mask (FMM) is usually used to realize the patterning of a light-emitting pixel. FMM technology is mature and has rich mass production experience. However, FMM technology also has the problems of limited precision and high cost. The fine metal mask-free technology eliminates the limitations of the traditional OLED process on the size, resolution and other performance of the display screen, and has the advantages of high performance, full-size and agile delivery. The patents CN118251982A, CN115666161A, CN116648095A, CN117062489A, CN118678742A, CN118785761A, CN115224220A, CN118678729A, CN118660529A and CN118660589A disclose the related content of the fine metal mask-free technology, which are referred to.

[0004] However, it is not easy to realize the detection of the display panel in the preparation process of the display panel using the fine metal mask-free technology, so that the yield of the display panel cannot be effectively guaranteed. SUMMARY

[0005] In order to overcome the technical problems mentioned in the above technical background, the present application provides a display mother board, a detection method thereof and a display panel.

[0006] The first aspect of the present application provides a display mother board, comprising:

[0007] a carrier plate;

[0008] a plurality of display substrates located on one side of the carrier plate, the display substrate comprising a display area and a non-display area, the non-display area surrounding at least part of the display area, the display area comprising a plurality of sub-pixels, the non-display area comprising a plurality of detection pads, the detection pads being connected with the sub-pixels; the plurality of display substrates comprising a plurality of first display substrates;

[0009] Multiple signal lines are located on the same side of the carrier plate as the display substrate. The multiple signal lines include a first signal line, which includes at least one first signal input terminal and multiple first signal output terminals. One first signal output terminal is connected to a detection pad of a first display substrate. The multiple first signal output terminals include a first sub-signal output terminal and a second sub-signal output terminal. The resistance of the first signal line between the first sub-signal output terminal and the first signal input terminal is a first resistance, and the resistance of the first signal line between the second sub-signal output terminal and the first signal input terminal is a second resistance. The absolute value of the difference between the first resistance and the second resistance is less than or equal to 5%.

[0010] In one embodiment, the number of first display substrates is N, where N is an integer greater than or equal to 2, and the first to Nth first display substrates are arranged sequentially along the signal transmission direction in the first signal line.

[0011] The first signal line includes a first segment, a second segment, a third segment, and a fourth segment. The first end of the first segment is connected to the second end of the second segment, the first end of the first segment is connected to the fourth end of the third segment, and the fifth end of the third segment is connected to the sixth end of the fourth segment. The fourth and fifth ends are positioned opposite each other. The third end of the second segment is connected to the detection pad of the i-th first display substrate, and the seventh end of the fourth segment is connected to the detection pad of the (i+1)-th first display substrate. The second and third ends are positioned opposite each other, and the sixth and seventh ends are positioned opposite each other. The third end is the first signal output terminal, and the seventh end is the first signal output terminal. i takes integer values ​​from 1 to N-1.

[0012] Among them, the absolute value of the difference between the resistance of the second segment and the sum of the resistances of the third and fourth segments is less than or equal to 5%.

[0013] Preferably, the difference between the resistance of the second segment and the sum of the resistances of the third and fourth segments is equal.

[0014] Preferably, a plurality of first display substrates are arranged along a first direction;

[0015] Preferably, the first and third segments extend along a first direction, and the second and fourth segments extend along a second direction, with the first and second directions intersecting.

[0016] In one embodiment, the first, second, third, and fourth segments have the same thickness along a direction perpendicular to the plane of the carrier plate.

[0017] The length of the second segment is L1, and the width of the second segment is W1; the length of the third segment is L2, and the width of the third segment is W2; the length of the fourth segment is L3, and the width of the fourth segment is W3.

[0018] Where L1 / W1 = L2 / W2 + L3 / W3;

[0019] Preferably, the first segment, the second segment, the third segment and the fourth segment each independently extend along a straight line.

[0020] In one embodiment, the first segment, the second segment, the third segment and the fourth segment have the same width along a direction parallel to the plane on which the carrier plate lies.

[0021] The second segment has a length L1 and a thickness H1; the third segment has a length L2 and a thickness H2; and the fourth segment has a length L3 and a thickness H3.

[0022] L1 / H1=L2 / H2+L3 / H3.

[0023] Preferably, the first segment, the second segment, the third segment and the fourth segment each independently extend along a straight line.

[0024] In one embodiment, the first segment, the second segment, the third segment and the fourth segment have the same thickness.

[0025] The first segment and the third segment have the same width, and the fourth segment has a width greater than that of the second segment; or the second segment and the fourth segment have the same width, and the third segment has a width greater than that of the first segment.

[0026] In one embodiment, the first segment, the second segment, the third segment and the fourth segment have the same width.

[0027] The first segment and the third segment have the same thickness, and the fourth segment has a thickness greater than that of the second segment; or the second segment and the fourth segment have the same thickness, and the third segment has a thickness greater than that of the first segment.

[0028] In one embodiment, the signals connected by the signal lines include at least one of a data signal and a scan signal.

[0029] Preferably, among the signal lines connected to the same first display substrate, the number of signal lines connected to the data signal is the same as the number of color types of the sub-pixels; and the number of signal lines connected to the scan signal is at least one.

[0030] In one embodiment, the first display substrate further comprises a plurality of lead lines, the detection pads are connected to the first signal output end through the lead lines, and the absolute value of the resistance difference between any two lead lines is less than or equal to 5%.

[0031] In one embodiment, in each first display substrate, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel and a third sub-pixel, and the plurality of detection pads include a first detection pad, a second detection pad and a third detection pad, the first detection pad is connected to the first sub-pixel, the second detection pad is connected to the second sub-pixel, and the third detection pad is connected to the third sub-pixel.

[0032] The signal lines connected with the data signals include a first signal line, a second signal line and a third signal line, the second signal line includes at least one second signal input end and a plurality of second signal output ends, and the third signal line includes at least one third signal input end and a plurality of third signal output ends;

[0033] One first signal output end of the first signal line is connected with a first detection pad of one first display substrate, one second signal output end of the second signal line is connected with a second detection pad of one first display substrate, and one third signal output end of the third signal line is connected with a third detection pad of one first display substrate.

[0034] Preferably, the plurality of second signal output ends include a third sub signal output end and a fourth sub signal output end, the resistance of the second signal line between the third sub signal output end and the second signal input end is a third resistance, the resistance of the second signal line between the fourth sub signal output end and the second signal input end is a fourth resistance, and the absolute value of the difference between the third resistance and the fourth resistance is less than or equal to 5%.

[0035] Preferably, the plurality of third signal output ends include a fifth sub signal output end and a sixth sub signal output end, the resistance of the third signal line between the fifth sub signal output end and the third signal input end is a fifth resistance, the resistance of the third signal line between the sixth sub signal output end and the third signal input end is a sixth resistance, and the absolute value of the difference between the fifth resistance and the sixth resistance is less than or equal to 5%.

[0036] Preferably, in each first display substrate, the plurality of detection pads include a fourth detection pad, the signal lines connected with the scanning signals include a fourth signal line, the fourth signal line includes at least one fourth signal input end and a plurality of fourth signal output ends, and one fourth signal output end of the fourth signal line is connected with the fourth detection pad of one first display substrate.

[0037] Preferably, the plurality of fourth signal output ends include a seventh sub signal output end and an eighth sub signal output end, the resistance of the fourth signal line between the seventh sub signal output end and the fourth signal input end is a seventh resistance, the resistance of the fourth signal line between the eighth sub signal output end and the fourth signal input end is an eighth resistance, and the absolute value of the difference between the seventh resistance and the eighth resistance is less than or equal to 5%.

[0038] In one embodiment, the plurality of first display substrates arranged along the first direction constitute a display substrate group, and the plurality of display substrate groups are arranged at intervals along a second direction, and the first direction intersects the second direction.

[0039] Preferably, the number of the first signal lines is plural, and the first signal output end of one first signal line is connected with the detection pad of the first display substrate in one display substrate group.

[0040] In one embodiment, further comprising:

[0041] The pin is connected with the signal input end of the first signal line, and the pin is configured to enable the external detection device to provide a detection signal to each first display substrate through the pin to simultaneously perform light-on detection on each first display substrate.

[0042] Preferably, the display substrate further comprises a detection circuit located in the non-display area, and the sub-pixel and the detection pad are connected through the detection circuit.

[0043] In one embodiment, the display substrate comprises:

[0044] The array substrate is located on one side of the carrier substrate, and the array substrate comprises a pixel driving circuit.

[0045] The isolation structure is located on the side of the array substrate away from the carrier substrate, and the isolation structure surrounds a plurality of isolated openings.

[0046] A plurality of light emitting devices, the orthogonal projection of the light emitting device on the carrier substrate overlaps with the orthogonal projection of the isolated opening on the carrier substrate; the light emitting device and the pixel driving circuit constitute a plurality of sub-pixels.

[0047] Preferably, in the direction away from the array substrate, the isolation structure comprises a stacked isolation portion and a blocking portion, and the orthogonal projection of the isolation portion on the array substrate is located within the range of the orthogonal projection of the blocking portion on the array substrate.

[0048] Preferably, the isolation structure further comprises a base portion, and the base portion is located on the side of the isolation portion close to the array substrate, and the orthogonal projection of the isolation portion on the array substrate is located within the range of the orthogonal projection of the base portion on the array substrate.

[0049] The second aspect of the present application provides a display mother substrate, comprising:

[0050] The carrier substrate;

[0051] A plurality of display substrates are located on one side of the carrier substrate, and the display substrate comprises a display area and a non-display area, the non-display area surrounds at least part of the display area, the display area comprises a plurality of sub-pixels, the non-display area comprises a plurality of detection pads, the detection pad is connected with the sub-pixel; the plurality of display substrates comprise a plurality of first display substrates;

[0052] A plurality of signal lines are located on the same side of the display substrate on the carrier substrate, and the plurality of signal lines comprise a first signal line; the first signal line comprises at least one first signal input end and a plurality of first signal output ends, one first signal output end is connected with the detection pad of one first display substrate, and the first signal line is configured to enable the external detection device to provide a detection signal to each first display substrate through the first signal line to simultaneously perform light-on detection on each first display substrate.

[0053] The first signal input end to the first sub-signal output end has a first voltage drop, and the first signal input end to the second sub-signal output end has a second voltage drop. The absolute value of the difference between the first voltage drop and the second voltage drop is less than or equal to 5%.

[0054] The third aspect of the present application provides a display mother board detection method, comprising:

[0055] The external detection device is connected to the first signal line in the display mother board as described above, and provides a light-on detection signal to the sub-pixels of the plurality of first display substrates through the first signal line.

[0056] The actual value of the predetermined parameter of the sub-pixel is measured.

[0057] The actual value is compared with the target value of the predetermined parameter. If the difference between the actual value and the target value is within a predetermined range, the sub-pixel is qualified.

[0058] The fourth aspect of the present application provides a display panel, which is cut from the display mother board as described above.

[0059] According to the display mother board provided by the embodiments of the present application, the resistance of the first signal line between the first sub-signal output end and the first signal input end and the resistance of the first signal line between the second sub-signal output end and the first signal input end are less different, and the voltage drops between the first signal input end and the first sub-signal output end and the second sub-signal output end are less different. When the display mother board is tested by light-on, the detection accuracy of the first display substrate connected to the first sub-signal output end and the second sub-signal output end is improved. At the same time, the display mother board of the embodiments of the present application is beneficial to online or real-time detection of the display substrate, and is beneficial to improving the yield of the substrate. BRIEF DESCRIPTION OF DRAWINGS

[0060] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor.

[0061] Figure 1 It is a top view structure schematic diagram of a display mother board in the related art.

[0062] Figure 2 It is a top view structure schematic diagram of a display mother board in an embodiment of the present application.

[0063] Figure 3 It is a display mother board in an embodiment of the present application in a light-on test.Figure 2 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0064] Figure 4 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. Figure 3 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0065] Figure 5 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0066] Figure 6 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. Figure 3 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0067] Figure 7 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0068] Figure 8 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. Figure 7 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0069] Figure 9 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. Figure 2 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0070] Figure 10 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. Figure 2 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0071] Figure 11 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. Figure 2 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0072] Figure 12 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0073] Figure 13 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0074] A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. Figure 14 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. Figure 3 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6.

[0075] Figure 15 A local enlarged structure diagram of the display mother board in the embodiment of the present application along the direction of A-A' in FIG. 6. DETAILED DESCRIPTION

[0076] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will be combined with the accompanying drawings for clear and complete description of the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the accompanying drawings can be arranged and designed in various different configurations.

[0077] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0078] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. It should be noted that, in the case of no conflict, different features in the embodiments of the present application can be combined with each other.

[0079] For easy understanding, the X-axis, Y-axis and Z-axis which are orthogonal to each other are recorded in the drawings. The direction along the X-axis is referred to as the X direction, the direction along the Y-axis is referred to as the Y direction, and the direction along the Z-axis is referred to as the Z direction. The Z direction is the normal direction with respect to the plane containing the X direction and the Y direction. In addition, the case of observing various elements in parallel with the plane containing the X direction and the Y direction is referred to as a top view. Or the plane of the X direction and the Y direction is a plane parallel to the display surface of the display panel, and the Z direction is a direction parallel to the thickness direction of the display panel.

[0080] For some elements, the terms of "upper" or "above" are used when describing the position of the element in the Z direction, and the terms of "lower" or "below" are used when describing the position of the element in the opposite direction. In addition, when the terms of "upper", "above", "lower", "below", "relative" and the like are used to define the positional relationship between two elements, it not only includes the state that the above two elements are directly connected, but also includes the state that the above two elements are separated by a gap, other elements. In addition, the terms "first", "second", "third" and the like are only used for differentiation, and cannot be understood as indicating or implying relative importance.

[0081] Currently, in the process of preparing a display substrate by using a non-fine metal mask technology, different color sub-pixels are sequentially subjected to deposition of a light-emitting functional layer, a cathode layer and an encapsulation layer of a light-emitting device, and after the deposition of the film layers of each color sub-pixel is completed, etching is performed to remove the excess film layers. If the display substrate is detected after the deposition of all color sub-pixels is completed, the process is relatively long, and the deposition process of the sub-pixels cannot be adjusted according to the detection structure. Figure 1 As shown in a top view structural schematic diagram of a display mother board, the present inventor finds that the signal line 200 can be connected with each display substrate 100 in the display mother board, specifically, the plurality of display substrates 100 are arranged along a first direction X and a second direction Y respectively, the plurality of display substrates 100 arranged along the first direction X and located in the same row are connected with the same signal line 200, each signal line 200 includes one signal input end a and a plurality of signal output ends b, and one signal output end b is connected to one display substrate 100; the plurality of display substrates 100 in the same row can be connected with a plurality of signal lines 200, and the plurality of signal lines 200 are connected with different signals (for example, can include but are not limited to data signals and scanning signals, etc.) to realize detection of the display substrate 100. If the width of each signal line is consistent, due to the relatively long length of the signal line, there is a voltage drop in the process of signal transmission, resulting in inconsistent voltage drops from the signal input end a to each signal output end b, the voltage drop between the signal output end b farther away from the signal input end a and the signal input end a is larger, resulting in the risk of inaccurate detection results of the display substrate 100.

[0082] Therefore, the present application provides a display mother board in the first aspect, referring to Figure 2 As shown in a top view structural schematic diagram of a display mother board, the display mother board includes a carrier plate 300, a plurality of display substrates 100 and a plurality of signal lines 200.

[0083] Optionally, as shown in Figure 3 The plurality of display substrates 100 are located on one side of the carrier plate 300, the display substrate 100 includes a display area AA and a non-display area NA, the non-display area NA surrounds at least part of the display area AA, the display area AA includes a plurality of sub-pixels 110, and the non-display area NA includes a plurality of detection pads 120, the detection pad 120 is connected with the sub-pixel 110; the plurality of display substrates 100 include a plurality of first display substrates 101.

[0084] Optionally, the first display substrate 101 can be an organic light-emitting diode display panel (Organic Light Emitting Diode, abbreviated as OLED) or a quantum dot electroluminescent display panel (Quantum Dot Light Emitting Diodes, abbreviated as QLED).

[0085] For example, the display area AA of the display substrate 100 can have a rectangular shape, or can have a square shape, a circular shape, an elliptical shape, or other shapes.

[0086] The plurality of sub-pixels 110 of different colors constitute a pixel PX, and the display area AA includes the pixels PX arranged in the first direction X and the second direction Y. In some embodiments, the pixel PX includes a first sub-pixel 111, a second sub-pixel 112, and a third sub-pixel 113. For example, the first sub-pixel 111 is a blue sub-pixel, the second sub-pixel 112 is a green sub-pixel, and the third sub-pixel 113 is a red sub-pixel. In some embodiments, the pixel PX further includes a sub-pixel that emits white light or light of other colors in addition to the first sub-pixel 111, the second sub-pixel 112, and the third sub-pixel 113.

[0087] The sub-pixel 110 includes a pixel circuit and a light emitting device driven by the pixel circuit to emit light of a corresponding color. The first sub-pixel 111 includes a first light emitting device, the second sub-pixel 112 includes a second light emitting device, and the third sub-pixel 113 includes a third light emitting device. One pixel circuit drives at least one light emitting device to emit light. For example, the display area AA includes a normal display area and a light-transmitting display area. The light-transmitting display area is a display area corresponding to a sensor and having a light-transmitting property. The normal display area is a display area that is not arranged corresponding to the sensor. In the normal display area, one pixel circuit drives one light emitting device to emit light. In the light-transmitting display area, one pixel circuit drives one or more light emitting devices to emit light.

[0088] In an embodiment, Figure 4 A partial film layer cross-sectional structure diagram of a local area of the display substrate 100 in the A-A’ direction is shown. Figure 3 Referring to Figure 4 , the display substrate 100 includes an array substrate 11, an isolation structure 12, and a plurality of light emitting devices 13.

[0089] Referring to Figure 4 and Figure 5The isolation structure 12 is located on one side of the array substrate 11 and encloses to form a plurality of isolation openings 12a, which include a plurality of first isolation openings 12a1, a plurality of second isolation openings 12a2 and a plurality of third isolation openings 12a3. The plurality of light emitting devices 13 are located on the side of the array substrate 11 away from the carrier plate 300, and the orthographic projection of the light emitting devices 13 on the carrier plate 300 overlaps with the orthographic projection of the isolation openings 12a on the carrier plate 300. The plurality of light emitting devices 13 include a plurality of first light emitting devices 13a, a plurality of second light emitting devices 13b and a plurality of third light emitting devices 13c, the first light emitting devices 13a are arranged corresponding to the first isolation openings 12a1, the second light emitting devices 13b are arranged corresponding to the second isolation openings 12a2, and the third light emitting devices 13c are arranged corresponding to the third isolation openings 12a3. In an embodiment, one light emitting device 13 is arranged corresponding to one isolation opening 12a, for example, the first light emitting devices 13a are arranged one-to-one corresponding to the first isolation openings 12a1, the second light emitting devices 13b are arranged one-to-one corresponding to the second isolation openings 12a2, and the third light emitting devices 13c are arranged one-to-one corresponding to the third isolation openings 12a3. At least part of the first light emitting devices 13a is arranged in the corresponding first isolation openings 12a1, at least part of the second light emitting devices 13b is arranged in the corresponding second isolation openings 12a2, and at least part of the third light emitting devices 13c is arranged in the corresponding third isolation openings 12a3. In another embodiment, a plurality of light emitting devices 13 are arranged corresponding to one isolation opening 12a, for example, a plurality of light emitting devices with the same color are arranged corresponding to one isolation opening 12a. The plurality of light emitting devices 13 and the pixel driving circuit constitute a plurality of sub-pixels 110.

[0090] In one example, the isolation structure 12 includes an isolation portion 122 and a barrier portion 121 which are stacked in a direction away from the array substrate 11 (i.e. the Z direction), the orthogonal projection of the isolation portion 122 on the array substrate 11 is within the orthogonal projection range of the barrier portion 121 on the array substrate 11, and the width of the barrier portion 121 is greater than the width of the isolation portion 122. Thus, the two end portions of the barrier portion 121 are arranged to protrude compared to the side surface of the isolation portion 122, and the shape of this isolation structure 12 is also referred to as overhanging. The isolation portion 122 and the barrier portion 121 are made of different materials, and the etching rate of the barrier portion 121 is less than the etching rate of the isolation portion 122. The material of the isolation portion 122 includes a conductive material, and specifically can include at least one of aluminum (Al) and an aluminum alloy, and the aluminum alloy can include at least one of an aluminum-neodymium alloy (AlNd), an aluminum-yttrium alloy (AlY), or an aluminum-silicon alloy (AlSi). The barrier portion 121 can be a single-layer structure or a multi-layer structure, and in the case of a single-layer structure, the material of the barrier portion 121 can include at least one of titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy. In the case of a multi-layer structure, one layer of the barrier portion 121 includes at least one of titanium, titanium nitride, molybdenum, tungsten, a molybdenum-tungsten alloy, or a molybdenum-niobium alloy, and another layer of the barrier portion 121 can include a conductive oxide or an inorganic insulating material, and the conductive oxide is, for example, indium tin oxide (ITO) or indium zinc oxide (IZO).

[0091] In some embodiments, with reference to Figure 6 , the isolation structure 12 can further include a base portion 123 located on the side of the isolation portion 122 close to the array substrate 11, the base portion 123 is arranged to protrude in the direction towards the isolation opening 12a relative to the isolation portion 122, and the orthogonal projection of the isolation portion 122 on the array substrate 11 is within the orthogonal projection of the base portion 123 on the array substrate 11. The material of the base portion 123 can include at least one of molybdenum (Mo), titanium (Ti), titanium nitride (TiN), a molybdenum-tungsten alloy (MoW), or a molybdenum-niobium alloy (MoNb).

[0092] In an embodiment, the display substrate 100 can further include a pixel defining layer 17, and the isolation structure 12 is disposed on the pixel defining layer 17. The pixel defining layer 17 is provided with pixel openings in communication with the isolation openings 12a. Specifically, the pixel defining layer 17 is provided with a first pixel opening in communication with the first isolation opening 12a1, a second pixel opening in communication with the second isolation opening 12a2, and a third pixel opening in communication with the third isolation opening 12a3. The first pixel opening, the second pixel opening, and the third pixel opening have the same or different areas of orthographic projections on the array substrate 11. The shapes of orthographic projections of the pixel openings and the corresponding isolation openings 12a on the array substrate 11 can be the same or different. Generally, the area of the orthographic projection of the isolation opening 12a on the array substrate 11 is greater than the area of the orthographic projection of the pixel opening in communication with the isolation opening 12a on the array substrate 11. The orthographic projection of the pixel opening of the light emitting device 13 on the array substrate 11 overlaps the orthographic projection of the isolation opening 12a on the array substrate 11. The pixel defining layer 17 is made of an inorganic material, for example, the pixel defining layer 17 is formed of an inorganic insulating material such as at least one of silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON).

[0093] For example, the first light emitting device 13a, the second light emitting device 13b, and the third light emitting device 13c emit different colors of light, respectively; the first light emitting device 13a, the second light emitting device 13b, and the third light emitting device 13c each include a first electrode 131, a light emitting structure 132, and a second electrode 133 stacked. The first electrode 131 is disposed on the array substrate 11, the pixel defining layer 17 covers the end portion of the first electrode 131, and the pixel defining layer 17 is provided with a pixel opening through which the first electrode 131 is exposed. The light emitting structure 132 of each of the first light emitting device 13a, the second light emitting device 13b, and the third light emitting device 13c covers the sidewall of the pixel opening of the pixel defining layer 17 and the side of the pixel defining layer 17 facing away from the array substrate 11. Each light emitting structure 132 is located in the pixel opening and contacts the first electrode 131.

[0094] For example, the second electrode 133 of each of the first light emitting device 13a, the second light emitting device 13b, and the third light emitting device 13c covers the corresponding light emitting structure 132. The second electrode 133 is electrically connected to the isolation structure 12. For example, the second electrode 133 is connected to the isolation portion 122 of the isolation structure 12, and / or the second electrode 133 is connected to the base portion 123 of the isolation structure 12.

[0095] For example, the first electrode 131 can be an anode, and the second electrode 133 can be a cathode. The first electrode 131 of each light emitting device 13 can be connected to the pixel circuit through a via hole, so that the pixel circuit drives the light emitting device 13 to emit light.

[0096] The first electrode 131 may include a multilayer structure, such as a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed, for example, using silver, a metallic material with excellent light reflectivity. Each conductive oxide layer can be formed, for example, from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide). The second electrode 133 is formed, for example, from a metallic material such as an alloy of magnesium and silver (MgAg).

[0097] For example, refer to Figure 7 The diagram shows a cross-sectional view of the light-emitting structure 132. The light-emitting structure 132 of at least one of the first light-emitting device 13a, the second light-emitting device 13b, and the third light-emitting device 13c includes a hole injection layer HIL, a hole transport layer HTL, an electron blocking layer EBL, a light-emitting material layer EML, a hole blocking layer HBL, an electron transport layer ETL, and an electron injection layer EIL stacked along a direction away from the array substrate 11 (i.e., the Z direction). The light-emitting structure 132 may include one light-emitting material layer EML, or a stacked light-emitting structure including multiple light-emitting material layers EML.

[0098] To enable the light-emitting structure 132 to emit light, a pixel voltage is provided to the first electrode 131 and a common voltage is provided to the second electrode 133, respectively. A potential difference is formed between the first electrode 131 and the second electrode 133, causing the light-emitting structure 132 disposed between the first electrode 131 and the second electrode 133 to emit light. In one embodiment, if a potential difference is formed between the first electrode 131 and the second electrode 133 of the first light-emitting device 13a, the light-emitting material layer EML of the light-emitting structure 132 emits blue light; if a potential difference is formed between the first electrode 131 and the second electrode 133 of the second light-emitting device 13b, the light-emitting material layer EML of the light-emitting structure 132 emits green light; and if a potential difference is formed between the first electrode 131 and the second electrode 133 of the third light-emitting device 13c, the light-emitting material layer EML of the light-emitting structure 132 emits red light.

[0099] The pixel voltage of the first electrode 131 is determined by the pixel circuit (see details). Figure 8 The common voltage of the second electrode 133 is provided by the isolation structure 12. Specifically, the second electrode 133 is electrically connected to the isolation structure 12, and the common voltage is supplied to the second electrode 133 by providing the isolation structure 12. That is, the isolation structure 12 has the function of supplying a common voltage to the second electrode 133.

[0100] like Figure 4As shown, the display panel 10 further comprises a first encapsulation layer, the first encapsulation layer comprises a plurality of encapsulation portions 14, the encapsulation portions 14 are located on the side of the second electrode 133 away from the array substrate 11 and extend to the side of the isolation structure 12 away from the array substrate 11 through the side wall of the isolation structure 12. The plurality of encapsulation portions 14 comprises a plurality of first encapsulation portions 14a corresponding to the plurality of first light emitting devices 13a, a plurality of second encapsulation portions 14b corresponding to the plurality of second light emitting devices 13b, and a plurality of third encapsulation portions 14c corresponding to the plurality of third light emitting devices 13c. The first encapsulation portion 14a is arranged on the side of the corresponding first light emitting device 13a away from the array substrate 11, the second encapsulation portion 14b is arranged on the side of the corresponding second light emitting device 13b away from the array substrate 11, and the third encapsulation portion 14c is arranged on the side of the corresponding third light emitting device 13c away from the array substrate 11.

[0101] The manufacturing method of the display substrate 100 of the embodiment of the present application will be described below. The manufacturing method of the display substrate 100 comprises: a step S11 of providing an array substrate 11. A step S12 of forming an isolation structure 12 on one side of the array substrate 11, the isolation structure 12 is provided with a plurality of isolation openings 12a, the plurality of isolation openings 12a comprises a plurality of first isolation openings 12a1, a plurality of second isolation openings 12a2 and a plurality of third isolation openings 12a3. A step S13 of manufacturing a film layer of the first light emitting device 13a, the film layer of the first light emitting device 13a comprises a light emitting structure layer and a second electrode layer of the first light emitting device 13a. A step S14 of manufacturing a first encapsulation layer of the first light emitting device 13a. Since the film layer and the first encapsulation layer of the first light emitting device 13a are prepared as a whole, the positions of the plurality of first isolation openings 12a1, the plurality of second isolation openings 12a2 and the plurality of third isolation openings 12a3 are all provided with the film layer and the first encapsulation layer of the first light emitting device 13a. A step S15 of etching to remove the film layer and the first encapsulation layer of the first light emitting device 13a at the positions of the plurality of second isolation openings 12a2 and the plurality of third isolation openings 12a3, so as to form only the light emitting structure 132 and the second electrode 133 of the first light emitting device 13a and the first encapsulation portion 14a of the first light emitting device 13a at the positions of the plurality of first isolation openings 12a1. Based on the above steps S13 to S15, the light emitting structure 132 and the second electrode 133 of the second light emitting device 13b and the first encapsulation portion 14b of the second light emitting device 13b are arranged at the positions of the plurality of second isolation openings 12a2, and the light emitting structure 132 and the second electrode 133 of the third light emitting device 13c and the first encapsulation portion 14c of the third light emitting device 13c are arranged at the positions of the plurality of third isolation openings 12a3.

[0102] It can be understood that, in the process of preparing the first light emitting device 13a, the second light emitting device 13b and the third light emitting device 13c, the first light emitting device 13a, the second light emitting device 13b and the third light emitting device 13c need to be tested to control the quality of the display substrate 100. As described in the previous preparation process of the first light emitting device 13a, the second light emitting device 13b and the third light emitting device 13c, the first light emitting device 13a, the second light emitting device 13b and the third light emitting device 13c are prepared in turn, so after the first light emitting device 13a is prepared, the first light emitting device 13a can be tested first. If the first light emitting device 13a meets the requirements, the preparation process conditions of the second light emitting device 13b and the third light emitting device 13c are continued; if the first light emitting device 13a does not meet the requirements, the preparation process conditions of the second light emitting device 13b and the third light emitting device 13c need to be adjusted to compensate for or reduce the defects of the first light emitting device 13a. Since the process of preparing the display substrate 101 in the display mother board is a continuous process, i.e. the first light emitting device 13a of the display substrate 101 in the plurality of display mother boards is prepared continuously, when the first light emitting device 13a of the previous batch does not meet the requirements, the preparation process conditions of the first light emitting device 13a of the subsequent batch can be adjusted to improve the yield of the subsequent display substrate 100. By analogy, after the second light emitting device 13b and the third light emitting device 13c are prepared, the second light emitting device 13b and the third light emitting device 13c can be tested to adjust the preparation process conditions and improve the yield of the display substrate 100.

[0103] The light test refers to applying a specific electrical signal and power to the display substrate 100 in the production process of the display substrate 100 to make it enter the working state, and then observing through professional equipment and naked eyes to detect whether the display effect, pixel lighting, brightness, color, contrast and other parameters of the display substrate 100 are normal. The light test can screen defects that may occur in the manufacturing process of the display substrate 100, such as dead pixels, bright spots, dark spots, Mura (display unevenness), line short circuit / disconnection, etc., and verify whether the photoelectric performance indicators (such as brightness uniformity, color saturation, response time, etc.) of the display substrate 100 meet the standards.

[0104] It can be understood that, in the display substrate 100 of the embodiment of the present application, one of the first light emitting device 13a, the second light emitting device 13b and the third light emitting device 13c can be included, any two of the first light emitting device 13a, the second light emitting device 13b and the third light emitting device 13c can be included, or the first light emitting device 13a, the second light emitting device 13b and the third light emitting device 13c can be included at the same time.

[0105] Optionally, the plurality of first display substrates 101 are arranged along a first direction X. For example, the spacing between adjacent first display substrates 101 along the first direction X can be the same or different.

[0106] In one embodiment, as shown in FIG. 1, the plurality of first display substrates 101 arranged along the first direction X constitute a display substrate group G, and a plurality of display substrate groups G are arranged at intervals along a second direction Y, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other, and the plurality of first display substrates 101 are arranged in an array. Figure 2

[0107] For example, the first direction X and the second direction Y are parallel to the plane on which the carrier board 300 is located.

[0108] For example, the plurality of first display substrates 101 in the display substrate group G are located in the same row, and the plurality of display substrate groups G are a plurality of rows of first display substrates 101.

[0109] Optionally, the plurality of signal lines 200 are located on the same side of the carrier board 300 as the display substrate 100; the plurality of signal lines 200 include a first signal line 210, the first signal line 210 includes at least one first signal input end 211 and a plurality of first signal output ends 212, one first signal output end 212 is connected to the detection pad 120 of one first display substrate 101; the plurality of first signal output ends 212 include a first sub-signal output end 2121 and a second sub-signal output end 2122, the resistance of the first signal line 210 between the first sub-signal output end 2121 and the first signal input end 211 is a first resistance, the resistance of the first signal line 210 between the second sub-signal output end 2122 and the first signal input end 211 is a second resistance, and the absolute value of the difference between the first resistance and the second resistance is less than or equal to 5%, for example, the absolute value of the difference between the first resistance and the second resistance can be 5%, 4.5%, 4%, 3.5%, 3%, 2.5%, 2%, 1.5%, 1%, 0.5%, or 0.

[0110] According to the display mother board provided in the embodiments of the present application, the resistance of the first signal line 210 between the first sub-signal output end 2121 and the first signal input end 211 and the resistance of the first signal line 210 between the second sub-signal output end 2122 and the first signal input end 211 are relatively small, and the voltage drop difference between the first sub-signal output end 2121 and the second sub-signal output end 2122 from the first signal input end 211 is also relatively small. When the display mother board is tested, the detection accuracy of the first display substrate 101 connected to the first sub-signal output end 2121 and the second sub-signal output end 2122 is improved.

[0111] Optionally, as shown in FIG. 1, the plurality of first display substrates 101 arranged along the first direction X constitute a display substrate group G, and a plurality of display substrate groups G are arranged at intervals along a second direction Y, and the first direction X intersects the second direction Y. For example, the first direction X and the second direction Y are perpendicular to each other, and the plurality of first display substrates 101 are arranged in an array. Figure 2 ​As shown, the first signal line 210 is in plurality, and the first signal output end 212 of one first signal line 210 is connected with the detection pad 120 of the first display substrate 101 in one display substrate group G. For example, all the display substrates in the display motherboard are the first display substrate 101, which can improve the detection accuracy of each display substrate 100 in the display motherboard, and is beneficial to improve the yield of the display substrate.

[0112] Exemplarily, the first signal line 210 is connected with the data signal or the scanning signal.

[0113] In one embodiment, the number of the first display substrate 101 is N, N is an integer greater than or equal to 2, and the first display substrate 101 and the Nth first display substrate 101 are arranged in sequence along the transmission direction of the signal in the first signal line 210.

[0114] Exemplarily, with reference to Figure 9 As shown in the partial enlarged structure schematic diagram, the first signal line 210 includes a first segment 201, a second segment 202, a third segment 203 and a fourth segment 204, the first end 201a of the first segment 201 is connected with the second end 202a of the second segment 202, the first end 201a of the first segment 201 is connected with the fourth end 203a of the third segment 203, the fifth end 203b of the third segment 203 is connected with the sixth end 204a of the fourth segment 204, and the fourth end 203a and the fifth end 203b are oppositely arranged; the third end 203b of the second segment 202 is connected with the detection pad 120 of the ith first display substrate 101, the seventh end 204b of the fourth segment 204 is connected with the detection pad 120 of the (i+1)th first display substrate 101, the second end 202a and the third end 202b are oppositely arranged, the sixth end 204a and the seventh end 204b are oppositely arranged, the third end 202b is the first signal output end, and the seventh end 204b is the first signal output end; i is an integer between 1 and N-1.

[0115] Exemplarily, when i is 1, the end of the first segment 201 opposite to the first end 201a is the first signal input end 211.

[0116] The absolute value of the difference between the resistance of the second segment 202 and the sum of the resistance of the third segment 203 and the resistance of the fourth segment 204 is less than or equal to 5%, for example, it can be 5%, 4.5%, 4%, 3.5%, 3%, 2.5%, 2%, 1.5%, 1%, 0.5% or 0. Thus, the voltage drop between the first signal input end 211 and each first signal output end 212 can be small, which is beneficial to improve the detection accuracy of the display substrate 100.

[0117] In one specific embodiment, the difference between the resistance of the second segment 202 and the sum of the resistances of the third segment 203 and the fourth segment 204 is equal. This ensures that the voltage drop between the first signal input terminal 211 and each first signal output terminal 212 is almost equal, which helps improve the detection accuracy of the display substrate 100.

[0118] Optionally, the first segment 201 and the third segment 203 extend along the first direction X, and the second segment 202 and the fourth segment 204 extend along the second direction Y, with the first direction X intersecting the second direction Y. This facilitates the connection of multiple first display substrates 100 via a single first signal line 210, simplifying wiring, saving space on the display motherboard, and enabling simultaneous detection of multiple first display substrates 100.

[0119] It should be noted that the transmission direction of the signal in the first signal line 210 refers to the transmission direction of the signal in the first segment 201 and the third segment 203.

[0120] For example, the cross-section of the signal line includes a rectangle. The resistance R of the signal line satisfies the following relationship with the length L of the signal line and the cross-sectional area S of the signal line: R = ρ * L / S (where ρ is the resistivity of the signal line), and the cross-sectional area S = H * W, where H is the thickness of the signal line and W is the width of the signal line. During the fabrication of the signal line, depending on the different spacing between the display substrate 100 and the pin 400, the resistance of the signal line between the pin 400 and each of the first display substrates 101 can be made the same by changing the width and / or thickness of the signal line.

[0121] In one embodiment, such as Figure 9 As shown, along the direction perpendicular to the plane of the carrier plate 300, the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 have the same thickness. For example, the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 are made of the same material. Specifically, the length of the second segment 202 is L1, and the width of the second segment 202 is W1; the length of the third segment 203 is L2, and the width of the third segment 203 is W2; the length of the fourth segment 204 is L3, and the width of the fourth segment 204 is W3. The lengths and widths of the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 satisfy the following relationship: L1 / W1 = L2 / W2 + L3 / W3. Therefore, the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 have the same thickness. By controlling the length and width of the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204, the voltage drop between the first signal input terminal 211 and each first signal output terminal 212 is almost the same. Moreover, the length and width of the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 are relatively easy to control, which helps to simplify the manufacturing process.

[0122] Optionally, as shown in Figure 2 The display motherboard further comprises: a pin 400 connected to the signal input end of the first signal line 210, the pin 400 being configured to enable an external detection device to provide a detection signal to each first display substrate 101 through the pin 400, and to simultaneously perform light-on detection on each first display substrate 101.

[0123] For example, each signal line 200 has a signal input end, and the pin 400 is connected to the signal input end. At least one pin 400 is provided for each signal input end.

[0124] Exemplarily, the pin 400 is of a crimping type. During detection, the pin 400 is crimped with an external detection device.

[0125] Optionally, the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 can extend along a straight line or a curved line or a broken line, as long as the resistance of the signal line between the pin 400 and each first display substrate 101 is the same, and a person skilled in the art can make a flexible selection according to actual conditions. In one specific embodiment, the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 each independently extend along a straight line. In this way, the manufacturing of the signal line 200 is facilitated.

[0126] In one embodiment, the widths of the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 are the same in a direction parallel to the plane on which the carrier plate 300 lies; the length of the second segment 202 is L1, and the thickness of the second segment 202 is H1; the length of the third segment 203 is L2, and the thickness of the third segment 203 is H2; the length of the fourth segment 204 is L3, and the thickness of the fourth segment 204 is H3; the length and the thickness of the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 satisfy the following relationship: L1 / H1=L2 / H2+L3 / H3.

[0127] The inventors have found through research that changing the widths of the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 makes it easier to control the resistance of the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204.

[0128] In one embodiment, as shown in Figure 9As shown, the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 have the same thickness; the width of the first segment 201 is the same as the width of the third segment 203, and the width of the fourth segment 204 is greater than the width of the second segment 202. When the width of the fourth segment 204 is greater than the width of the second segment 202, the resistance of the fourth segment 204 can be made less than the resistance of the second segment 202. By adjusting the widths of the fourth segment 204 and the second segment 202, the resistance of the second segment 202 can be made equal to the sum of the resistances of the third segment 203 and the fourth segment 204.

[0129] In another embodiment, such as Figure 10 As shown, the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 have the same thickness; the width of the second segment 202 and the width of the fourth segment 204 are the same, and the width of the third segment 203 is greater than the width of the first segment 201. When the width of the third segment 203 is greater than the width of the first segment 201, the resistance of the third segment 203 can be made less than the resistance of the first segment 201. By adjusting the widths of the fourth segment 204 and the second segment 202, and simultaneously ensuring that the length of the second segment 202 is greater than the length of the fourth segment 204, the resistance of the second segment 202 is made equal to the sum of the resistances of the third segment 203 and the fourth segment 204. The inventors of this application discovered through research that controlling the width of the first segment 201 to be the same as the width of the third segment 203, and changing the width of the second segment 202 and the fourth segment 204, is more conducive to controlling the resistance accuracy of the signal lines, so that the resistance difference of the first signal lines 210 between the first signal input terminal 211 and each first signal output terminal 212 is smaller, which can further improve the detection accuracy of the display substrate 100 in the display motherboard.

[0130] Optionally, the first segment 201 and the third segment 203 have the same length, and the second segment 202 and the fourth segment 204 have the same length.

[0131] In another embodiment, such as Figure 11 As shown, the first segment 201, the second segment 202, the third segment 203, and the fourth segment 204 have the same thickness; the width of the second segment 202 is less than the width of the fourth segment 204, while the width of the third segment 203 is greater than the width of the first segment 201. By simultaneously adjusting the widths of the third segment 203 and the fourth segment 204, the resistance of the second segment 202 can be made equal to the sum of the resistances of the third segment 203 and the fourth segment 204. Although it is possible to achieve the same resistance for the second segment 202, the precision is not very high when simultaneously adjusting the widths of the third segment 203 and the fourth segment 204.

[0132] In one embodiment, the first segment 201, the second segment 202, the third segment 203 and the fourth segment 204 have the same width; the first segment 201 has the same thickness as the third segment 203, and the fourth segment 204 has a thickness greater than the second segment 202. When the fourth segment 204 has a thickness greater than the second segment 202, the resistance of the fourth segment 204 can be made smaller than the resistance of the second segment 202. By adjusting the thickness of the fourth segment 204 and the second segment 202, the resistance of the second segment 202 can be made equal to the sum of the resistance of the third segment 203 and the resistance of the fourth segment 204.

[0133] In another embodiment, the first segment 201, the second segment 202, the third segment 203 and the fourth segment 204 have the same width; the second segment 202 has the same thickness as the fourth segment 204, and the third segment 203 has a thickness greater than the first segment 201. When the third segment 203 has a thickness greater than the first segment 201, the resistance of the third segment 203 can be made smaller than the resistance of the first segment 201. By adjusting the thickness of the fourth segment 204 and the second segment 202, and by adjusting the length of the second segment 202 and the length of the fourth segment 204, the resistance of the second segment 202 can be made equal to the sum of the resistance of the third segment 203 and the resistance of the fourth segment 204. The inventor of the present application has found that, compared with adjusting the thickness of the signal line, adjusting the width of the signal line can better ensure the accuracy of the resistance value of the signal line.

[0134] The inventor of the present application has found that, compared with adjusting the thickness of the signal line, adjusting the width of the signal line can better ensure the accuracy of the resistance value of the signal line.

[0135] In another embodiment, the first segment 201, the second segment 202, the third segment 203 and the fourth segment 204 have the same width; the second segment 202 has a thickness smaller than the fourth segment 204, and the third segment 203 has a thickness greater than the first segment 201. By adjusting the thickness of the third segment 203 and the fourth segment 204, the resistance of the second segment 202 can be made equal to the sum of the resistance of the third segment 203 and the resistance of the fourth segment 204. Although the resistance of the second segment 202 can be made equal to the sum of the resistance of the third segment 203 and the resistance of the fourth segment 204, the accuracy of the thickness of the third segment 203 and the fourth segment 204 is not high.

[0136] In one embodiment, the signal connected by the signal line 200 includes at least one of a data signal and a scanning signal.

[0137] Optionally, as Figure 12As shown, the number of signal lines 200 connected to the data signals is the same as the number of color categories of the sub-pixels 110 in the signal lines 200 connected to the same first display substrate 101. For example, the colors of the sub-pixels 110 include three color categories of red, green and blue, and the number of signal lines 200 connected to the data signals is three.

[0138] Optionally, the number of signal lines 200 connected to the scanning signals is at least one. Thus, by using the at least one signal line 200 connected to the scanning signals and the same number of signal lines 200 connected to the data signals as the number of color categories of the sub-pixels 110 to drive the same first display substrate 101, detection of all the sub-pixels 110 in the first display substrate 101 can be achieved. Alternatively, during detection, the at least one signal line 200 connected to the scanning signals and the at least one signal line 200 connected to the data signals are used to drive the same first display substrate 101, so as to achieve detection of the sub-pixels 110 of at least one color category.

[0139] In one embodiment, referring to Figure 3 and Figure 12 In each first display substrate 101, the plurality of sub-pixels 110 include a first sub-pixel 111, a second sub-pixel 112 and a third sub-pixel 113, the plurality of detection pads 120 include a first detection pad 125, a second detection pad 126 and a third detection pad 127, the first detection pad 125 is connected to the first sub-pixel 111, the second detection pad 126 is connected to the second sub-pixel 112, and the third detection pad 127 is connected to the third sub-pixel 113; the signal lines 200 connected to the data signals include a first signal line 210, a second signal line 220 and a third signal line 230, the second signal line 220 includes at least one second signal input end 221 and a plurality of second signal output ends 222; and the third signal line 230 includes at least one third signal input end 231 and a plurality of third signal output ends 232.

[0140] It should be noted that Figure 12 only the general trends of the first signal line 210, the second signal line 220, the third signal line 230 and the fourth signal line 240 are shown, and the widths of the signal line segments in the first signal line 210, the second signal line 220, the third signal line 230 and the fourth signal line 240 are not shown, which should not be construed as a limitation of the present application.

[0141] It should be noted that the specific structure of the second signal line 220 and the third signal line 230 can refer to the first signal line 210.

[0142] Optionally, one first signal output end 212 of the first signal line 210 is connected with a first detection pad 125 of the first display substrate 101, one second signal output end 222 of the second signal line 220 is connected with a second detection pad 126 of the first display substrate 101, and one third signal output end 232 of the third signal line 230 is connected with a third detection pad 127 of the first display substrate 101. Thus, the connection of the first signal line 210, the second signal line 220 and the third signal line 230 with the first display substrate 101 can be realized respectively.

[0143] Optionally, the plurality of second signal output ends 222 comprises a third sub signal output end and a fourth sub signal output end, the resistance of the second signal line 220 between the third sub signal output end and the second signal input end 221 is a third resistance, the resistance of the second signal line 220 between the fourth sub signal output end and the second signal input end 221 is a fourth resistance, and the absolute value of the difference between the third resistance and the fourth resistance is less than or equal to 5%, for example, which can be 5%, 4.5%, 4%, 3.5%, 3%, 2.5%, 2%, 1.5%, 1%, 0.5% or 0, etc.

[0144] Optionally, the plurality of third signal output ends 232 comprises a fifth sub signal output end and a sixth sub signal output end, the resistance of the third signal line 230 between the fifth sub signal output end and the third signal input end 231 is a fifth resistance, the resistance of the third signal line 230 between the sixth sub signal output end and the third signal input end 231 is a sixth resistance, and the absolute value of the difference between the fifth resistance and the sixth resistance is less than or equal to 5%, for example, which can be 5%, 4.5%, 4%, 3.5%, 3%, 2.5%, 2%, 1.5%, 1%, 0.5% or 0, etc.

[0145] Optionally, in each first display substrate 101, the plurality of detection pads 120 comprises a fourth detection pad 124, the signal line 200 connected with the scanning signal comprises a fourth signal line 240, the fourth signal line 240 comprises at least one fourth signal input end 241 and a plurality of fourth signal output ends 242, and one fourth signal output end 242 of the fourth signal line 240 is connected with the fourth detection pad 124 of the first display substrate 101.

[0146] Optionally, the plurality of fourth signal output ends 242 comprises a seventh sub signal output end and an eighth sub signal output end, the resistance of the fourth signal line 240 between the seventh sub signal output end and the fourth signal input end 241 is a seventh resistance, the resistance of the fourth signal line 240 between the eighth sub signal output end and the fourth signal input end 241 is an eighth resistance, and the absolute value of the difference between the seventh resistance and the eighth resistance is less than or equal to 5%, for example, which can be 5%, 4.5%, 4%, 3.5%, 3%, 2.5%, 2%, 1.5%, 1%, 0.5% or 0, etc.

[0147] Optionally, the specific structure of the fourth signal line 240 can refer to the first signal line 210.

[0148] It can be understood that the first detection pad 125, the second detection pad 126, the third detection pad 127 and the fourth detection pad 124 are respectively connected to the pixel driving circuit, the first detection pad 125, the second detection pad 126 and the third detection pad 127 can be connected to the data signal line in the pixel driving circuit, and the fourth detection pad 124 can be connected to the scan signal line in the pixel driving circuit.

[0149] For example, the plurality of sub-pixels 110 include a first sub-pixel 111, a second sub-pixel 112 and a third sub-pixel 113. In the same display substrate 100, the pixel driving circuits of the first sub-pixels 111 are all connected to the first detection pad 125, the pixel driving circuits of the second sub-pixels 112 are all connected to the second detection pad 126, and the pixel driving circuits of the third sub-pixels 113 are all connected to the third detection pad 127.

[0150] Reference Figure 8 The array substrate 11 includes a pixel circuit layer and a planarization layer 19, the pixel circuit layer includes a pixel circuit for driving the light emitting device 13 to emit light, Figure 3 The transistor 18 in the pixel circuit is shown, and a via is provided in the planarization layer 19, and the first electrode 131 is electrically connected to the transistor 18 in the pixel circuit layer through the via. In addition, the pixel circuit layer further includes at least one insulating layer, which can include at least one of an inorganic layer and an organic layer. In addition, the array substrate 11 further includes a scan signal line for providing a scan signal Scan and a data signal line for providing a data signal Data.

[0151] Reference Figure 13 The pixel circuit includes a driving transistor T1 and a data transistor T2, the source of the data transistor T2 is connected to the data signal line for providing the data signal Data, the gate of the data transistor T2 is connected to the scan signal line for providing the scan signal Scan, the drain of the data transistor T2 is connected to the gate of the driving transistor T1, the two ends of the storage capacitor C1 are respectively connected to the gate and the source of the driving transistor T1, and the drain of the driving transistor T1 is connected to the light emitting device 13. Figure 4 is one embodiment of the pixel circuit, and the pixel circuit of the present application is not limited to Figure 4 The pixel circuit shown in FIG. 2T1C can also be other pixel circuits, such as 7T1C, 8T1C pixel circuits, etc.

[0152] In one embodiment, as Figure 12As shown, the first display substrate 101 further comprises a plurality of lead wires 500, the detection pad 120 is connected with the first signal output end 212, the second signal output end 222, the third signal output end 232 and the fourth signal output end 242 through the lead wire 500, and the absolute value of the resistance difference between any two lead wires 500 connected with the same signal line 200 is less than or equal to 5%, for example, can be 5%, 4.5%, 4%, 3.5%, 3%, 2.5%, 2%, 1.5%, 1%, 0.5% or 0, etc. It can be understood that in the process of preparing the display substrate 100, the light emitting structure 132 and the second electrode 133 of the light emitting device 13 can cover the detection pad 120, causing the signal line 200 to be unable to be directly connected with the detection pad 120, and the light emitting structure 132 and the second electrode 133 covering the detection pad 120 need to be etched and removed, which can increase the preparation process and cannot be timely online detected. Therefore, the lead wire 500 is used to lead out the detection pad 120, and the lead wire 500 is connected with the signal line 200, without increasing the etching process, and the online detection of the sub-pixel 110 can be timely realized, and the yield of the display substrate 100 is improved.

[0153] Exemplarily, the lead wire 500 leads out the signals in the detection pad 120, and the surface of the detection pad 120 can include a plurality of first pins, the lead wire 500 leads out the signals of the plurality of first pins in the detection pad 120, and the end of the lead wire 500 away from the detection pad 120 also correspondingly includes a plurality of second pins, the second pins correspond to the first pins one by one, and one first pin is connected with one second pin.

[0154] Optionally, the display substrate 100 further comprises a detection circuit located in the non-display area NA, and the sub-pixel 110 and the detection pad 120 are connected through the detection circuit 600. The detection circuit can transmit the signals transmitted in the detection circuit to each sub-pixel 110 through line switching.

[0155] For example, the sub-pixel 110 is connected with the detection circuit through a data signal line. Alternatively, the sub-pixel 110 is connected with the detection circuit through a scanning signal line.

[0156] It can be understood that driving a certain sub-pixel 110 needs to use a scanning signal line and a data signal line to drive at the same time, and in the light test, the signal line 240 connected with the data signal and the data signal line driving a certain sub-pixel 110 drive the sub-pixel 110 at the same time to realize the lighting of the sub-pixel 110.

[0157] For example, the sub-pixel 110 is connected with the detection circuit through a data signal line. Alternatively, the sub-pixel 110 is connected with the detection circuit through a scanning signal line. Figure 14As shown, the display substrate 100 further comprises a second encapsulation layer 15 and a third encapsulation layer 16, the second encapsulation layer 15 covers the isolation structure 12 and the encapsulation part 14, and the third encapsulation layer 16 covers the second encapsulation layer 15. The first encapsulation layer and the third encapsulation layer 16 are both inorganic materials, and the materials of the first encapsulation layer and the third encapsulation layer 16 include at least one of silicon nitride (SiN), silicon oxide (SiO), and silicon oxynitride (SiON). The second encapsulation layer 15 is an organic insulating material, such as an epoxy resin, an acrylic resin, or the like. The second encapsulation layer 15 and the third encapsulation layer 16 are continuously arranged at least on the display area AA as a whole, and a part thereof is also arranged in the frame area NA.

[0158] The second aspect of the present application provides a display mother board, referring to Figure 2 The display mother board comprises a carrier plate 300, a plurality of display substrates 100, and a plurality of signal lines 200.

[0159] Optionally, the plurality of display substrates 100 are located on one side of the carrier plate 300, the display substrate 100 comprises a display area AA and a non-display area NA, the non-display area NA surrounds at least part of the display area AA, the display area AA comprises a plurality of sub-pixels 110, and the non-display area NA comprises a plurality of detection pads 120, the detection pad 120 is connected with the sub-pixel 110; the plurality of display substrates 100 comprise a plurality of first display substrates 101.

[0160] Optionally, the plurality of signal lines 200 are located on the same side of the carrier plate 300 as the display substrate 100; the plurality of signal lines 200 comprise a first signal line 210, the first signal line 210 comprises at least one first signal input end 211 and a plurality of first signal output ends 212, one first signal output end 212 is connected with the detection pad 120 of one first display substrate 101; the first signal line 210 is configured to enable an external detection device to provide a detection signal to each first display substrate 101 through the first signal line 210, and simultaneously perform a lighting detection on each first display substrate 101; wherein the plurality of first signal output ends 212 comprise a first sub-signal output end 2121 and a second sub-signal output end 2122, during the lighting detection, the voltage drop between the first signal input end 211 and the first sub-signal output end 2121 is a first voltage drop, the voltage drop between the first signal input end 211 and the second sub-signal output end 2122 is a second voltage drop, and the absolute value of the difference between the first voltage drop and the second voltage drop is less than or equal to 5%, for example, it can be 5%, 4.5%, 4%, 3.5%, 3%, 2.5%, 2%, 1.5%, 1%, 0.5%, or 0.

[0161] It should be noted that the structure of the display mother board of the present embodiment can be combined with the structure of the display mother board described above as a whole or in part, and will not be described in detail here.

[0162] The third aspect of the present application provides a display mother board detection method, referring to the detection method flow diagram shown in the figure, the detection method comprises the following steps. Figure 15

[0163] S100: The external detection device is connected with the first signal line and the fourth signal line in the display mother board as described above, and a lighting detection signal is provided to the sub-pixels of the plurality of first display substrates through the first signal line and the fourth signal line.

[0164] It should be noted that the display mother board, the first display substrate, the first signal line and the fourth signal line are consistent with the previous description, and will not be described in detail here.

[0165] Exemplarily, the signal line includes the first signal line, the second signal line, the third signal line and the fourth signal line, the first signal line, the second signal line and the third signal line are connected with the data signal respectively, the fourth signal line is connected with the scanning signal, and at least one of the different color sub-pixels is driven through at least one of the first signal line, the second signal line, the third signal line and the fourth signal line.

[0166] For example, the first signal line is connected with the red sub-pixel, the second signal line is connected with the green sub-pixel, and the third signal line is connected with the blue sub-pixel, the lighting test of the red sub-pixel can be realized through the first signal line and the fourth signal line, the lighting test of the green sub-pixel can be realized through the second signal line and the fourth signal line, and the lighting test of the blue sub-pixel can be realized through the third signal line and the fourth signal line.

[0167] S200: Measure the actual value of the predetermined parameter of the sub-pixel.

[0168] For example, the predetermined parameter can include but is not limited to optical parameters such as color coordinates, brightness and efficiency, etc.

[0169] S300: Compare the actual value with the target value of the predetermined parameter, if the difference between the actual value and the target value is within a predetermined range, the sub-pixel is qualified.

[0170] Taking the color coordinates as an example, if the difference between the actual value and the target value of the color coordinates is within 2%, the sub-pixel is considered to be qualified, and there is no need to adjust the light emitting structure of the light emitting device and the preparation process conditions of the second electrode layer; if the difference between the actual value and the target value is greater than 2%, the light emitting structure of the subsequent light emitting device and the preparation process conditions of the second electrode layer need to be adjusted to compensate for the defects of the previous light emitting device and improve the yield of the display substrate.

[0171] The fourth aspect of the present application provides a display panel, which is cut from the display mother board as described above.

[0172] ​It should be noted that when the display mother board is cut, the cut structures include but are not limited to signal lines, pins, detection pads and the like.

[0173] In some possible implementation manners, the present application also provides a display device, and the display device includes the display panel in the present application. The display device can include a device with image processing capability, for example, a mobile phone, a desktop computer, a notebook computer, a tablet computer, a vehicle display, a wearable device, etc.

[0174] The technical features of the above embodiments can be combined in any manner. To make the description concise, all possible combinations of the technical features in the above embodiments are not described, but as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present application.

[0175] The above embodiments only express several embodiments of the present application, and the description is more specific and detailed, but it should not be understood as a limitation on the scope of the patent. It should be pointed out that for ordinary skilled in the art, without departing from the concept of the present application, a number of modifications and improvements can be made, which are within the scope of the present application. Therefore, the scope of the patent protection of the present application should be subject to the appended claims.

Claims

1. A display motherboard, characterized by, The application relates to a display device, comprising: a carrier plate; a plurality of display substrates located on one side of the carrier plate, the display substrate comprising a display area and a non-display area, the non-display area surrounding at least part of the display area, the display area comprising a plurality of sub-pixels, and the non-display area comprising a plurality of detection pads connected to the sub-pixels; the plurality of display substrates comprising a plurality of first display substrates; a plurality of signal lines located on the same side of the carrier plate as the display substrates; the plurality of signal lines comprising a first signal line, the first signal line comprising at least one first signal input end and a plurality of first signal output ends, one first signal output end being connected to a detection pad of one first display substrate; the plurality of first signal output ends comprising a first sub-signal output end and a second sub-signal output end, the resistance of the first signal line between the first sub-signal output end and the first signal input end being a first resistance, the resistance of the first signal line between the second sub-signal output end and the first signal input end being a second resistance, and the absolute value of the difference between the first resistance and the second resistance being less than or equal to 5%.

2. The display motherglass of claim 1, wherein, The number of first display substrates is N, N being an integer greater than or equal to 2, and the first display substrates are arranged in sequence along the transmission direction of signals in the first signal line; the first signal line comprising a first segment, a second segment, a third segment and a fourth segment, the first end of the first segment being connected to the second end of the second segment, the first end of the first segment being connected to the fourth end of the third segment, the fifth end of the third segment being connected to the sixth end of the fourth segment, and the fourth end being arranged opposite the fifth end; the third end of the second segment being connected to the detection pad of the ith first display substrate, the seventh end of the fourth segment being connected to the detection pad of the (i+1)th first display substrate, the second end being arranged opposite the third end, and the sixth end being arranged opposite the seventh end, the third end being the first signal output end, and the seventh end being the first signal output end; i being an integer between 1 and N-1; wherein the absolute value of the difference between the resistance of the second segment and the sum of the resistance of the third segment and the resistance of the fourth segment is less than or equal to 5%; Preferably, the difference between the resistance of the second segment and the sum of the resistance of the third segment and the resistance of the fourth segment is equal. Preferably, the plurality of first display substrates are arranged along a first direction. Preferably, the first segment and the third segment extend along the first direction, and the second segment and the fourth segment extend along a second direction, the first direction intersecting the second direction.

3. The display motherglass of claim 2, wherein, The thicknesses of the first segment, the second segment, the third segment and the fourth segment are the same in the direction perpendicular to the plane in which the carrier plate is located; the length of the second segment being L1, and the width of the second segment being W1; the length of the third segment being L2, and the width of the third segment being W2; the length of the fourth segment being L3, and the width of the fourth segment being W3; wherein L1 / W1=L2 / W2+L3 / W3. Preferably, the first segment, the second segment, the third segment and the fourth segment each independently extend along a straight line.

4. The display motherglass of claim 2, wherein, The first segment, the second segment, the third segment and the fourth segment have the same width in a direction parallel to the plane on which the carrier plate lies; The length of the second segment is L1, and the thickness of the second segment is H1; the length of the third segment is L2, and the thickness of the third segment is H2; the length of the fourth segment is L3, and the thickness of the fourth segment is H3; L1 / H1 = L2 / H2 + L3 / H3; Preferably, the first segment, the second segment, the third segment and the fourth segment each independently extend along a straight line.

5. The display motherglass of claim 2, wherein, The first segment, the second segment, the third segment and the fourth segment have the same thickness; The first segment and the third segment have the same width, and the fourth segment has a width greater than that of the second segment; or the second segment and the fourth segment have the same width, and the third segment has a width greater than that of the first segment. The first segment, the second segment, the third segment and the fourth segment have the same width; 6. The display motherglass of claim 2, wherein, The first segment and the third segment have the same thickness, and the fourth segment has a thickness greater than that of the second segment; or the second segment and the fourth segment have the same thickness, and the third segment has a thickness greater than that of the first segment. The signal connected by the signal line includes at least one of a data signal and a scanning signal; 7. The display motherglass of claim 1, wherein, Preferably, among the signal lines connected to the same first display substrate, the number of signal lines connected to the data signal is the same as the number of color categories of the sub-pixels; and the number of signal lines connected to the scanning signal is at least one. The first display substrate further comprises a plurality of lead lines, the detection pads and the first signal output end are connected through the lead lines, and the absolute value of the resistance difference between any two lead lines is less than or equal to 5%.

8. The display motherglass of claim 1, wherein, In each of the first display substrates, the plurality of sub-pixels include first sub-pixels, second sub-pixels and third sub-pixels, and the plurality of detection pads include first detection pads, second detection pads and third detection pads, the first detection pads are connected to the first sub-pixels, the second detection pads are connected to the second sub-pixels, and the third detection pads are connected to the third sub-pixels; 9. The display motherglass of claim 1, wherein, The signal line connected to the data signal includes the first signal line, the second signal line and the third signal line, the second signal line includes at least one second signal input end and a plurality of second signal output ends; and the third signal line includes at least one third signal input end and a plurality of third signal output ends; One of the first signal output ends of the first signal line is connected to the first detection pad of one of the first display substrates, one of the second signal output ends of the second signal line is connected to the second detection pad of one of the first display substrates; and one of the third signal output ends of the third signal line is connected to the third detection pad of one of the first display substrates; ​ Preferably, the plurality of second signal output terminals comprises a third sub signal output terminal and a fourth sub signal output terminal, the resistance of the second signal line between the third sub signal output terminal and the second signal input terminal is a third resistance, the resistance of the second signal line between the fourth sub signal output terminal and the second signal input terminal is a fourth resistance, and the absolute value of the difference between the third resistance and the fourth resistance is less than or equal to 5%. Preferably, the plurality of third signal output terminals comprises a fifth sub signal output terminal and a sixth sub signal output terminal, the resistance of the third signal line between the fifth sub signal output terminal and the third signal input terminal is a fifth resistance, the resistance of the third signal line between the sixth sub signal output terminal and the third signal input terminal is a sixth resistance, and the absolute value of the difference between the fifth resistance and the sixth resistance is less than or equal to 5%. Preferably, in each of the first display substrates, the plurality of detection pads comprises a fourth detection pad, the signal line connected to the scanning signal comprises a fourth signal line, the fourth signal line comprises at least one fourth signal input terminal and a plurality of fourth signal output terminals, and one fourth signal output terminal of the fourth signal line is connected to the fourth detection pad of one first display substrate. Preferably, the plurality of fourth signal output terminals comprises a seventh sub signal output terminal and an eighth sub signal output terminal, the resistance of the fourth signal line between the seventh sub signal output terminal and the fourth signal input terminal is a seventh resistance, the resistance of the fourth signal line between the eighth sub signal output terminal and the fourth signal input terminal is an eighth resistance, and the absolute value of the difference between the seventh resistance and the eighth resistance is less than or equal to 5%.

10. The display motherglass of claim 1, wherein, A plurality of first display substrates arranged along a first direction form a display substrate group, and a plurality of display substrate groups are arranged at intervals along a second direction, the first direction intersecting the second direction. Preferably, the number of first signal lines is multiple, and the first signal output terminal of one first signal line is connected to the detection pad of the first display substrate in one display substrate group.

11. The display motherglass of claim 1, wherein, Further comprising: a pin connected to the signal input terminal of the first signal line, the pin being configured to enable an external detection device to provide a detection signal to each first display substrate through the pin to simultaneously perform light-on detection on each first display substrate; Preferably, the display substrate further comprises a detection circuit located in the non-display area, and the sub-pixel and the detection pad are connected through the detection circuit.

12. The display motherglass of claim 1, wherein, The display substrate comprises: an array substrate located on one side of the carrier substrate, the array substrate comprising a pixel driving circuit; an isolation structure located on the side of the array substrate away from the carrier substrate, the isolation structure surrounding a plurality of isolated openings; a plurality of light emitting devices, the light emitting devices having a projection on the carrier substrate that overlaps with a projection of the isolated openings on the carrier substrate; the light emitting devices and the pixel driving circuit forming a plurality of sub-pixels. Preferably, the isolation structure comprises a blocking portion and a isolation portion stacked in a direction away from the array substrate, a footprint of the isolation portion on the array substrate is within a footprint of the blocking portion on the array substrate. Preferably, the isolation structure further comprises a base portion, the base portion is located on a side of the isolation portion close to the array substrate, a footprint of the isolation portion on the array substrate is within a footprint of the base portion on the array substrate.

13. A display motherboard, characterized by Comprising: a carrier plate; a plurality of display substrates located on one side of the carrier plate, the display substrate comprising a display area and a non-display area, the non-display area surrounding at least part of the display area, the display area comprising a plurality of sub-pixels, the non-display area comprising a plurality of detection pads, the detection pads being connected to the sub-pixels; the plurality of display substrates comprising a plurality of first display substrates; a plurality of signal lines located on the same side of the carrier plate as the display substrate, the plurality of signal lines comprising a first signal line; the first signal line comprising at least one first signal input end and a plurality of first signal output ends, one first signal output end being connected to a detection pad of one first display substrate, the first signal line being configured to enable an external detection device to provide a detection signal to each first display substrate through the first signal line, and simultaneously perform a light-on detection on each first display substrate. Wherein, the plurality of first signal output ends comprises a first sub-signal output end and a second sub-signal output end, during the light-on detection, the voltage drop between the first signal input end and the first sub-signal output end is a first voltage drop, the voltage drop between the first signal input end and the second sub-signal output end is a second voltage drop, and the absolute value of the difference between the first voltage drop and the second voltage drop is less than or equal to 5%.

14. A method of detecting a display motherboard, characterized by, Comprising: an external detection device connected to the first signal line in the display mother board according to any one of claims 1-13, to provide a light-on detection signal to the sub-pixels of the plurality of first display substrates through the first signal line; measuring an actual value of a predetermined parameter of the sub-pixel; comparing the actual value with a target value of the predetermined parameter, if the difference between the actual value and the target value is within a predetermined range, the sub-pixel is qualified.

15. A display panel, characterized by Cut from the display mother board according to any one of claims 1-12.

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