Replacement source / drain contact methods in complemental field effect transistor (CFET) devices

Abstract

A semiconductor structure forming a complementary field effect transistor (CFET) includes: a metal gate; a bottom field effect transistor (FET) module including a plurality of channel layers extending in a first direction through the metal gate, and a bottom source / drain (S / D) contact electrically connected to the plurality of channel layers via a bottom epitaxy (epi S / D) and a bottom interface; and a top FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, the top FET module including a plurality of channel layers extending through the metal gate in the first direction, and a top source / drain (S / D) contact electrically connected to the plurality of channel layers via a top epitaxy (epi S / D) and a top interface, wherein the bottom S / D contact and the top S / D contact each comprise cobalt (Co) or tungsten (W).

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to U.S. Provisional Application Serial No. 63 / 456,435, filed March 31, 2023, the entirety of which is incorporated by reference herein. TECHNICAL FIELD

[0003] Embodiments described herein generally relate to semiconductor device manufacturing, and more specifically, to methods for forming complementary field effect transistor (CFET) devices. BACKGROUND

[0004] To continue scaling beyond the physical limits of planar metal oxide semiconductor field effect transistors (MOSFETs), three-dimensional FinFETs, stacked nanosheet gate-all-around FETs (GAA FETs), and complementary FETs (CFETs) have been proposed. In a CFET architecture, n-type and p-type devices are stacked vertically on top of each other, eliminating the n-p spacing of the standard cell height. In the currently proposed process flow, the contact trench in the bottom device is filled with silicide and metal contact plugs before the top device is formed. As a result, the silicide and contact plugs formed from currently known materials, such as titanium silicide, cobalt, or tungsten, can not withstand the high temperature processes of forming the top device and degrade during the high temperature processes. Using materials that can withstand such high temperature processes can result in high resistance and cause complexity in the deposition and etch processes.

[0005] Thus, there is a need for improved methods for fabricating silicide and metal contact plugs in the bottom device of a CFET architecture. SUMMARY

[0006] Embodiments of the present disclosure provide a semiconductor structure for forming a complementary field effect transistor (CFET). The semiconductor structure includes: a metal gate; a bottom field effect transistor (FET) module including a plurality of channel layers extending in a first direction through the metal gate, and a bottom source / drain (S / D) contact electrically connected to the plurality of channel layers via a bottom epitaxial (epi) S / D and a bottom interface; and a top FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, the top FET module including a plurality of channel layers extending in the first direction through the metal gate, and a top source / drain (S / D) contact electrically connected to the plurality of channel layers via a top epitaxial (epi) S / D and a top interface, wherein the bottom S / D contact and the top S / D contact each include cobalt (Co) or tungsten (W).

[0007] Embodiments of the present disclosure provide a method for forming a complementary field effect transistor (CFET). The method includes: performing a top cap spacer formation process to deposit a top cap spacer covering exposed surfaces of top nanosheets and a spacer around the top nanosheets along a first plane orthogonal to a first direction, wherein the top nanosheets are stacked on bottom nanosheets in a second direction orthogonal to the first direction, and the top nanosheets and the bottom nanosheets each include a plurality of channel layers extending in the first direction through a dummy gate; performing a bottom epitaxial (epi) source / drain (S / D) formation process to form a bottom epi S / D on exposed surfaces of the bottom nanosheets along the first plane; performing a bottom contact patterning and sacrificial fill process to deposit a bottom inter-layer dielectric (ILD) on surfaces of the spacer around the bottom epi S / D, pattern the bottom ILD, form a dummy contact, and remove the top cap spacer; performing a top epi S / D formation process to form a top epi S / D on exposed surfaces of the top nanosheets along the first plane and form a top ILD around the top epi S / D; performing a replacement metal gate (RMG) process to replace the dummy gate with a metal gate; performing a top contact patterning and metal fill process to pattern the top ILD to form a top S / D contact; after the bottom epi S / D formation process, the top epi S / D formation process, and the RMG process, performing a dummy contact lift-off process to selectively etch the dummy contact; and performing a bottom replacement S / D contact formation process to form a bottom S / D contact in a portion etched in the dummy contact lift-off process.

[0008] Embodiments of the present disclosure provide a semiconductor structure forming a complementary field effect transistor (CFET). The semiconductor structure includes a metal gate; a bottom field effect transistor (FET) module including a plurality of channel layers extending in a first direction through the metal gate, and a dummy contact connected to the plurality of channel layers via a bottom epitaxial (epi) S / D and a bottom interface; and a top FET module stacked on the bottom FET module in a second direction orthogonal to the first direction, the top FET module including a plurality of channel layers extending in the first direction through the metal gate, and a top source / drain (S / D) contact electrically connected to the plurality of channel layers via a top epitaxial (epi) S / D and a top interface, wherein the dummy contact comprises silicon oxide (Si02), silicon nitride (Si3N4), silicon carbide (SiC), or a combination thereof, and the top S / D contact comprises cobalt (Co) or tungsten (W). BRIEF DESCRIPTION OF DRAWINGS

[0009] In order to provide a detailed understanding of the above-mentioned features of the present disclosure, a more particular description will be rendered by reference to specific embodiments, some of which are illustrated in the accompanying drawings. It is to be noted, however, that the appended drawings are provided by way of example only and are not intended to be limiting, as the present disclosure can allow for other equally effective embodiments.

[0010] Figure 1 is a schematic top view of a multi-chamber processing system according to one or more embodiments of the present disclosure.

[0011] Figure 2A is an isometric view of a portion of a semiconductor structure that can form a complementary field effect transistor (CFET) according to one or more embodiments of the present disclosure. Figure 2B shows a ZX plane along line 2B-2B of Figure 2A the semiconductor structure of Figure 2A is a cross-sectional view of the semiconductor structure of

[0012] Figure 3A and Figure 3B depicts a process flow diagram of a method of forming a unit transistor in a semiconductor structure according to one embodiment.

[0013] Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4J' , Figure 4K ,Figure 4L 、 Figure 4M 、 Figure 4N 、and Figure 4O are isometric views of a portion of a semiconductor structure corresponding to various states of a method. Figure 3A and Figure 3B .

[0014] To facilitate an understanding of this description, like reference characters are used throughout the disclosure to identify like elements. It will be readily understood that elements and features of one embodiment can be readily recombined with those of another without departing from the scope of the present disclosure. In the drawings and the following description, an orthogonal coordinate system including an X-axis, a Y-axis, and a Z-axis is used. For convenience, the direction indicated by the arrows in the figures is assumed to be the positive direction. It will be appreciated that elements disclosed in some embodiments can be advantageously employed in other implementations without specific recitation. DETAILED DESCRIPTION

[0015] Embodiments described herein provide methods for complementary FET (CFET) devices. In the methods described herein, dummy contacts are deposited in place of source / drain (S / D) contacts of a bottom device of a CFET prior to formation of a top device of the CFET. After top device formation, which includes high temperature processes, the dummy contacts are replaced with S / D contacts. Such replacement S / D contacts allow for the use of optimized materials for the S / D contacts of the bottom device without any thermal budget limitations.

[0016] Figure 1 is a schematic top view of a multi-chamber processing system 100 according to one or more embodiments of the present disclosure. The processing system 100 generally includes a factory interface 102, load lock chambers 104, 106, transfer chambers 108, 110 having respective transfer robots 112, 114, hold chambers 116, 118, and processing chambers 120, 122, 124, 126, 128, 130. As detailed herein, substrates in the processing system 100 can be processed in the various chambers and transferred between the various chambers without exposing the substrates to the ambient environment outside of the processing system 100 (e.g., an atmospheric ambient environment, such as can be present in a semiconductor foundry). For example, substrates can be processed in the various chambers that are maintained at a low pressure (e.g., less than or equal to about 300 Torr) or vacuum environment and transferred between the various chambers without breaking the low pressure or vacuum environment among the various processes performed on the substrates in the processing system 100. As such, the processing system 100 can provide an integrated solution for some processing of substrates.

[0017] Examples of processing systems that can be suitably modified in accordance with the teachings provided herein include Endura ® , Producer ® or Centura® Integrated processing systems or other suitable processing systems commercially available from Applied Materials, Inc. of Santa Clara, California. It is contemplated that other processing systems, including those from other manufacturers, can be suitable for benefiting from aspects described herein.

[0018] In Figure 1 In the illustrated example, the factory interface 102 includes docks 132 and factory interface robots 134 to facilitate transfer of substrates. The docks 132 are adapted to accept one or more front opening unified pods (FOUPs) 136. In some examples, each factory interface robot 134 generally includes a blade 138 disposed on an end of the respective factory interface robot 134, the blade being adapted to transfer substrates from the factory interface 102 to the load lock chambers 104, 106.

[0019] The load lock chambers 104, 106 have respective ports 140, 142 coupled to the factory interface 102 and respective ports 144, 146 coupled to the transfer chamber 108. The transfer chamber 108 further has respective ports 148, 150 coupled to the hold chambers 116, 118 and respective ports 152, 154 coupled to the processing chambers 120, 122. Similarly, the transfer chamber 110 has respective ports 156, 158 coupled to the hold chambers 116, 118 and respective ports 160, 162, 164, 166 coupled to the processing chambers 124, 126, 128, 130. The ports 144, 146, 148, 150, 152, 154, 156, 158, 160, 162, 164, 166 can be, for example, slit valve openings having slit valves for passing substrates therethrough by the transfer robots 112, 114 and for providing a seal between respective chambers to prevent passing gases between respective chambers. Generally, any port is opened for passing a substrate therethrough. Otherwise, the port is closed.

[0020] The load lock chambers 104, 106, the transfer chambers 108, 110, the holding chambers 116, 118, and the processing chambers 120, 122, 124, 126, 128, 130 can be fluidically coupled to a gas and pressure control system (not specifically shown). The gas and pressure control system can include one or more gas pumps (e.g., turbo pumps, cryo pumps, roughing pumps), gas sources, various valves, and piping fluidically coupled to the various chambers. In operation, the factory interface robot 134 transfers a substrate from the FOUP 136 through the port 140 or 142 to the load lock chamber 104 or 106. The gas and pressure control system then evacuates the load lock chamber 104 or 106. The gas and pressure control system further maintains the transfer chambers 108, 110 and the holding chambers 116, 118 to have an internal low pressure or vacuum environment (which can include an inert gas). Thus, evacuating the load lock chamber 104 or 106 facilitates transferring the substrate between, for example, the atmospheric environment of the factory interface 102 and the low pressure or vacuum environment of the transfer chamber 108.

[0021] With the substrate in the load lock chamber 104 or 106 that has been evacuated, the transfer robot 112 transfers the substrate from the load lock chamber 104 or 106 through the port 144 or 146 into the transfer chamber 108. The transfer robot 112 can then transfer the substrate through the respective ports 152, 154 to and / or between any of the processing chambers 120, 122 for processing, and through the respective ports 148, 150 to and / or between the holding chambers 116, 118 for holding to await further transfer. Similarly, the transfer robot 114 can access the substrate in the holding chamber 116 or 118 through the port 156 or 158, and can transfer the substrate through the respective ports 160, 162, 164, 166 to and / or between any of the processing chambers 124, 126, 128, 130 for processing, and through the respective ports 156, 158 to and / or between the holding chambers 116, 118 for holding to await further transfer. Transferring and holding the substrate within and among the various chambers can be in a low pressure or vacuum environment provided by the gas and pressure control system.

[0022] The processing chambers 120, 122, 124, 126, 128, 130 can be any suitable chamber for processing a substrate. In some examples, the processing chamber 120 can be capable of performing an etch process, the processing chamber 122 can be capable of performing a cleaning process, the processing chamber 124 can be capable of performing a selective removal process, the processing chamber 126 can be capable of performing a chemical vapor deposition (CVD) deposition process, and the processing chambers 128, 130 can be capable of performing respective epitaxial growth processes. The processing chamber 120 can be a Selectra TM Etch chamber. The processing chamber 122 can be a SiCoNi TM Pre-clean chamber. The processing chamber 126 can be a WxZ TM Chamber. The processing chamber 128 or 130 can be a Centura TM Epi chamber.

[0023] A system controller 168 is coupled to the processing system 100 for controlling the processing system 100 or components thereof. For example, the system controller 168 can control operation of the processing system 100 using direct control of the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130 of the processing system 100 or by controlling controllers associated with the chambers 104, 106, 108, 110, 116, 118, 120, 122, 124, 126, 128, 130. In operation, the system controller 168 implements data collection and feedback from the respective chambers to coordinate performance of the processing system 100.

[0024] The system controller 168 generally includes a central processing unit (CPU) 170, memory 172, and support circuits 174. The CPU 170 can be one of any form of general purpose processor that can be used in an industrial setting. The memory 172, or non-transitory computer readable medium, is accessible by the CPU 170 and can be one or more of a number of memory, such as random access memory (RAM), read only memory (ROM), a floppy disk, a hard disk, or any other form of digital storage (local or remote). The support circuits 174 are coupled to the CPU 170 and can include cache, clock circuits, input / output subsystems, power supplies, and the like. The various methods disclosed herein can be implemented by the CPU 170 executing computer instruction code stored in the memory 172 (or in the memory of a particular processing chamber), for example, as a software routine, under control of the CPU 170. When the computer instruction code is executed by the CPU 170, the CPU 170 controls the chamber to perform processes according to the various methods.

[0025] Other processing systems can be in other configurations. For example, more or fewer processing chambers can be coupled to the transfer apparatus. In the illustrated example, the transfer apparatus includes transfer chambers 108, 110 and hold chambers 116, 118. In other examples, more or fewer transfer chambers (e.g., one transfer chamber) and / or more or fewer hold chambers (e.g., no hold chambers) can be implemented as the transfer apparatus in a processing system.

[0026] Figure 2A is an isometric view of a portion of a semiconductor structure 200 that can form a complementary field effect transistor (CFET) in accordance with one or more embodiments of the present disclosure. Figure 2B shows a cross-sectional view of the semiconductor structure 200 along the ZX plane of the line 2B-2B. Figure 2A The semiconductor structure 200 includes a bottom field effect transistor (FET) module TR B and a top FET module TR B stacked in the Z direction on the bottom FET module TR T . The bottom FET module TR B and the top FET module TR T each include a channel layer 202 extending in the Y direction across a metal gate 204. The channel layer 202 can be encapsulated in a spacer 206. The surface of the metal gate 204 along the ZX plane is covered by a spacer 208. The bottom FET module TR BThe channel layer 202 in the bottom FET module TR T is electrically isolated from the channel layer 202 in the top FET module TR B is p-type and the top FET module TR T is n-type, where the bottom epi S / D 214 is p-type doped and the top epi S / D 222 is n-type doped. In some embodiments, the bottom FET module TR B is n-type and the top FET module TR T is p-type, where the bottom epi S / D 214 is n-type doped and the top epi S / D 222 is p-type doped. The top FET module TR T The channel layer 202 in the top FET module TR is electrically connected to the top S / D contacts 220 via the top epi S / D 222 and a top interface 224 embedded in a top ILD 226. The bottom S / D contacts 212, the top S / D contacts 220, and the metal gate 204 are connected to metal layers 228 formed within dielectric layers 230, 232, and 234 via contact plugs 236.

[0027] The channel layer 202 can be formed of silicon (Si), germanium (Ge), silicon germanium (SiGe), or indium gallium zinc oxide (IGZO). The metal gate 204, the bottom S / D contacts 212, the top S / D contacts 220, the metal layers 228, and the contact plugs 236 can be formed of cobalt (Co), tungsten (W), ruthenium (Ru), copper (Cu), molybdenum (Mo), titanium (Ti), nickel (Ni), silver (Ag), gold (Au), iridium (Ir), tantalum (Ta), platinum (Pt), a conductive oxide or nitride of the above, or any combination of the above. In the embodiments described herein, the bottom S / D contacts 212 are formed by a replacement S / D contact method, in which dummy contacts formed of materials that withstand high temperature processes, such as epitaxial deposition processes and replacement metal gate processes, are replaced with metal after the high temperature processes, as described in detail below. Thus, the bottom S / D contacts 212 can be made of metal materials listed above that can not be able to withstand such high temperature processes. The spacers 208 and the MDI 210 can be formed of dielectric materials, such as silicon oxide (SiO x C y). The spacer 206 can be formed of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), or tungsten (W). The bottom epi S / D 214 and the top epi S / D 222 can be formed of epitaxially grown silicon (Si) or silicon germanium (SiGe). The bottom interface 216 and the top interface 224 can be formed of a metal silicide, such as titanium silicide (TiSi2), molybdenum silicide (MoSi2), cobalt silicide (CoSi2), nickel silicide (Ni2Si), tantalum silicide (TaSi2), or any combination thereof. The dielectric layers 230, 232, and 234 can be formed of carbon-doped silicon oxide (SiO2), silicon nitride (Si3N4), aluminum oxide (Al2O3), or any combination thereof, such as silicon oxycarbide (SiOC), silicon oxycarbonitride (SiOCN), silicon carbonitride (SiCN). The bottom ILD 218 and the top ILD 226 can be formed of silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), or any combination thereof.

[0028] Figure 3A and Figure 3B A process flow diagram of a method 300 of forming a semiconductor structure 400, which can be the semiconductor structure 200 that is part of forming a complementary field effect transistor (CFET), is depicted in accordance with one or more embodiments of the present disclosure. Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4J' , Figure 4K , Figure 4L , Figure 4M , Figure 4N , and Figure 4O are isometric views of portions of the semiconductor structure 400 corresponding to various states of the method 300. It should be understood that Figure 4A , Figure 4B , Figure 4C , Figure 4D , Figure 4E , Figure 4F , Figure 4G , Figure 4H , Figure 4I , Figure 4J , Figure 4J' , Figure 4K , Figure 4L , Figure 4M , Figure 4N , and Figure 4OOnly portions of the semiconductor structure 400 are shown, and the semiconductor structure 400 can contain any number of transistor sections and additional material with aspects as shown in the figures. It should also be noted that although the methods shown in Figure 3A and Figure 3B other process sequences including one or more operations that have been omitted and / or added and / or have been rearranged in another desired order fall within the scope of the embodiments of the disclosure provided herein.

[0029] The method 300 begins at block 302, where a dual superlattice deposition process is performed to deposit a bottom superlattice 402 on a substrate 404, a superlattice inter-sacrificial layer 406 on the bottom superlattice 402, and a top superlattice 408 on the superlattice inter-sacrificial layer 406, as shown in Figure 4A The bottom superlattice 402 and the top superlattice 408 each include alternating channel layers 202 and sacrificial layers 410 stacked in a Z-direction. The channel layers 202 can be formed of a first material. The sacrificial layers 410 can be formed of a second material. The etch selectivity of the second material (i.e., the ratio of the etch rate of the second material to the etch rate of the first material) is between about 10: 1 to 500: 1. Examples of the first material include pure silicon (Si), germanium (Ge), and silicon germanium (SiGe). Examples of the second material include silicon germanium (SiGe) with a germanium (Ge) concentration between about 10% and about 30%. The superlattice inter-sacrificial layer 406 can be formed of a material having an etch selectivity with respect to the first material and the second material, for example, silicon germanium (SiGe) with a higher germanium (Ge) concentration between about 35% and about 60%. The bottom superlattice 402 and the top superlattice 408 each can include between about 2 pairs and about 10 pairs of channel layers 202 and sacrificial layers 410. The channel layers 202 each have a thickness between about 5 nm and about 40 nm. The sacrificial layers 410 each have a thickness between about 5 nm and about 40 nm. The superlattice inter-sacrificial layer 406 can have a thickness between about 20 nm and about 100 nm.

[0030] As used herein, the term "substrate" refers to a material layer that is used as a basis for subsequent processing operations and includes a surface to be cleaned. The substrate 404 can be a silicon-based material or any suitable insulating or conductive material, as desired. The substrate 404 can include materials such as crystalline silicon (e.g., Si<100> or Si<111>), silicon oxide, strained silicon, silicon germanium, doped or undoped poly silicon, doped or undoped silicon wafers and patterned or non-patterned wafers, silicon on insulator (SOI), carbon-doped silicon oxides, silicon nitrides, doped silicon, germanium, gallium arsenide, glass, or sapphire.

[0031] The dual superlattice deposition process in block 302 may be included in a processing chamber (such as...) Figure 1 Any suitable deposition process performed in the processing chambers 126, 128, or 130 shown, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxial deposition, etc.

[0032] Within box 304, a nanosheet patterning process is performed to form nanosheets 412 and shallow trench isolation (STI) 414, as shown. Figure 4B As shown. The nanosheet patterning process includes etching a top superlattice 408, an inter-superlattice sacrificial layer 406, and a bottom superlattice 402 into a substrate 404. A nanosheet 412 having a bottom nanosheet 416 etched from the bottom superlattice 402 and a top nanosheet 418 etched from the top superlattice 408 has a width in the X direction between about 5 nm and about 60 nm and an aspect ratio between about 1:10 and about 1:80. The etched portion of the substrate 404 is filled onto the top surface of the remaining substrate 404 using a dielectric material such as silicon oxide (SiO2) to form shallow trench isolation (STI) 414.

[0033] The nanosheet patterning process in box 304 may be included in a processing chamber (such as...) Figure 1 Any suitable lithography and etching processes (such as photolithography) performed in the processing chamber 120 shown, and in the processing chamber (such as...) Figure 1 Any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in the processing chambers 126, 128, or 130 shown.

[0034] In block 306, a gate and spacer formation process is performed to form a dummy gate 420 around the nanosheet 412, and spacers 208 are formed along the ZX plane on the surface of the dummy gate 420, as shown. Figure 4C As shown. A gate capping layer 422 may be formed on a dummy gate 420 between spacers 208. The dummy gate 420 may be formed of polysilicon. The spacers 208 may be formed of a dielectric material, such as silicon oxycarbide (SiO2). x C y The gate capping layer 422 may be formed of a dielectric material, such as silicon nitride (Si3N4).

[0035] The gate and spacer formation process in block 306 may include processing chambers (such as...) Figure 1any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxial deposition processes, etc., performed in a processing chamber (such as the processing chamber 126, 128, or 130) as shown.

[0036] In block 308, a middle dielectric isolation (MDI) formation process is performed to selectively etch the superlattice inter-sacrificial layers 406 in the nanosheets 412 and fill the etched portions with a dielectric material to form MDIs 210, as shown. Figure 4D The MDIs 210 can be formed from the same or similar dielectric material as the spacers 208.

[0037] The MDI formation process in block 308 can include any suitable etching process performed in a processing chamber (such as the processing chamber 120) as shown, and any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in a processing chamber (such as the processing chamber 126, 128, or 130) as shown. Figure 1 Figure 1 The MDI formation process in block 308 can include any suitable etching process performed in a processing chamber (such as the processing chamber 120) as shown, and any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in a processing chamber (such as the processing chamber 126, 128, or 130) as shown.

[0038] In block 310, an inner spacer formation process is performed to selectively etch the sacrificial layers 410 in the bottom nanosheets 416 and the top nanosheets 418 and fill the etched portions with a dielectric material to form inner spacers 424, as shown. Figure 4E The inner spacers 424 can be formed from the same or similar dielectric material as the spacers 208 having a composition of silicon (Si), oxygen (O), carbon (C), nitrogen (N), and boron (B).

[0039] The inner spacer formation process in block 310 can include any suitable etching process performed in a processing chamber (such as the processing chamber 120) as shown, and any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in a processing chamber (such as the processing chamber 126, 128, or 130) as shown. Figure 1 Figure 1 The inner spacer formation process in block 310 can include any suitable etching process performed in a processing chamber (such as the processing chamber 120) as shown, and any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in a processing chamber (such as the processing chamber 126, 128, or 130) as shown.

[0040] In block 312, a top cap spacer formation process is performed to deposit a top cap spacer 426 in a top portion of the semiconductor structure 400, as shown. Figure 4F The top cap spacer 426 can be deposited along the ZX plane on the exposed surfaces of the top nanosheets 418 and on the spacers 208 around the top nanosheets 418, thereby covering the exposed surfaces of the top nanosheets 418. The bottom nanosheets 416 and the spacers 208 around the bottom nanosheets 416 remain exposed along the ZX plane. The top cap spacer 426 can be formed from the same or similar dielectric material as the spacers 208.​​

[0041] The top cover spacer forming process in block 312 may include processing chambers (such as...) Figure 1 Any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in the processing chambers 126, 128, or 130 shown.

[0042] In block 314, a bottom epitaxial (epi) source / drain (S / D) formation process is performed to form the bottom epi S / D214, as shown. Figure 4G As shown, the bottom epi S / D 214 is epitaxially grown along the ZX plane on the exposed surface of the bottom nanosheet 416. The bottom epi S / D 214 is interfaced between the channel layer 202 in the bottom nanosheet 416 and the S / D contacts to be formed in the bottom portion of the semiconductor structure 400 to minimize parasitic resistance. The bottom epi S / D 214 may be formed of silicon (Si) or silicon germanium (SiGe).

[0043] The bottom epi S / D 214 can be doped with p-type dopant, such as boron (B) or gallium (Ga), at a concentration of approximately 10. 20 cm -3 With 5x10 21 cm -3 The value depends on the desired conductivity of the bottom epiS / D 214. In some embodiments, the bottom epiS / D 214 is doped with an n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), at a concentration of about 10. 20 cm -3 With 5x10 21 cm -3 The value depends on the desired conductivity of the bottom epi S / D 214.

[0044] The bottom epi S / D forming process in box 314 may be included in the processing chamber (such as...) Figure 1 An epitaxial deposition process is performed in the processing chamber 128 or 130 shown, wherein the semiconductor structure 400 is exposed to a deposition gas. In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor may include silane (SiH4), disilane (Si2H6), tetrasilane (Si4H6), etc. 10), or a combination thereof. The germanium-containing precursor can include germane (GeH4), germanium tetrachloride (GeCl4), and digermane (Ge2H6). The dopant source can include a precursor diborane (B2H6) or trimethyl gallium Ga(CH3)3, including a p-type dopant such as boron (B) or gallium (Ga). In embodiments where the bottom epi S / D 214 is n-type doped, the dopant source includes a precursor phosphine (PH3), phosphorus trichloride (PCl3), triisobutylphosphine ([(CH3)3C]3P), arsine (AsH3), arsenic trichloride (AsCl3), tert-butyl arsine (AsC4H 11 ), antimony trichloride (SbCl3), or Sb(C2H5)5, including an n-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb).

[0045] The epitaxial deposition process can be performed at a temperature between about 400 °C and about 800 °C. The dopant in the bottom epi S / D 214 can be activated by a subsequent anneal process performed at a temperature between 850 °C and about 1200 °C.

[0046] In block 316, a bottom contact patterning and sacrificial fill process is performed to deposit a bottom interlayer dielectric (ILD) 218 on the uncovered surface of the spacer 208 around the bottom epi S / D 214 in the bottom portion of the semiconductor structure 400, and to pattern the bottom ILD 218 to form dummy contacts 428, as shown. Figure 4H The bottom ILD 218 can be formed of a dielectric material such as silicon oxide (SiO2). The dummy contacts 428 can be formed of a dielectric material such as silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), or a combination thereof, which has an etch selectivity with respect to the bottom ILD 218 and withstands subsequent high-temperature processes. After the dummy contacts 428 are formed, the top cap spacers 426 are removed to expose the top nanosheets 418, as shown, as well as the surface of the spacer 208 around the top nanosheets 418 along the ZX plane. Figure 4E

[0047] The bottom contact patterning and sacrificial fill process in block 316 can include any appropriate lithography and etching processes such as photolithography performed in a process chamber such as the process chamber 120, as shown, as well as any appropriate deposition processes such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc. performed in a process chamber such as the process chambers 126, 128, or 130, as shown. Figure 1 Figure 1

[0048] ​​​In box 318, the top epi S / D forming process is performed to form top epi S / D 222, as follows. Figure 4I As shown. The top epi S / D 222 is epitaxially grown along the ZX plane on the exposed surface of the top nanosheet 418. The top epi S / D 222 interfaces between the channel layer 202 in the top nanosheet 418 and the S / D contacts to be formed in the top portion of the semiconductor structure 400 to minimize parasitic resistance. The top epi S / D 222 may be formed of silicon (Si) or silicon germanium (SiGe). After the formation of the top epi S / D 222, top ILD 226 is formed around the top epi S / D 222 on the exposed surface of the spacer 208 and between the spacers 208. The top ILD 226 may be formed of a dielectric material, such as silicon oxide (SiO2).

[0049] The top epi S / D 222 can be doped with n-type dopant, such as phosphorus (P), arsenic (As), or antimony (Sb), at a concentration of approximately 10. 20 cm -3 With 5x10 21 cm -3 The specific values ​​depend on the desired conductivity of the top epi S / D 222. In embodiments where the bottom epi S / D 214 is doped with a p-type dopant, the top epi S / D 222 is doped with a p-type dopant, such as boron (B) or gallium (Ga), at a concentration of approximately 10. 20 cm -3 With 5x10 21 cm -3 Between these values, it depends on the desired conductivity of the top epi S / D 222.

[0050] The top epi S / D forming process in box 318 may include processing chambers (such as...) Figure 1 An epitaxial deposition process is performed in the processing chamber 128 or 130 shown, wherein the semiconductor structure 400 is exposed to a deposition gas. In some embodiments, the deposition gas includes a silicon-containing precursor, a germanium-containing precursor, and a dopant source. The silicon-containing precursor may include silane (SiH4), disilane (Si2H6), tetrasilane (Si4H6), etc. 10 ( ), or a combination of the above. Germanium-containing precursors may include germanane (GeH4), germanium tetrachloride (GeCl4), and digerane (Ge2H6). Dopant sources may include precursors such as phosphine (PH3), phosphorus trichloride (PCl3), triisobutylphosphine ([(CH3)3C]3P), arsine (AsH3), arsenic trichloride (AsCl3), and tert-butylarsine (AsC4H). 11Antimony trichloride (SbCl3) or Sb(C2H5)5, including n-type dopants such as phosphorus (P), arsenic (As), or antimony (Sb). In embodiments where the top epi S / D 222 is p-type doped, the dopant source may include the precursor diborane (B2H6) or trimethylgallium Ga(CH3)3, including p-type dopants such as boron (B) or gallium (Ga).

[0051] The epitaxial deposition process can be performed at temperatures between approximately 400°C and approximately 800°C. The dopants in the top epi S / D 222 can be activated by a subsequent annealing process performed at temperatures between 850°C and approximately 1200°C.

[0052] In block 320, a replacement metal gate (RMG) process is performed to replace the dummy gate 420 with a metal gate 204, as follows: Figure 4J and Figure 4J' As shown. Figure 4J' It shows along including Figure 4J The diagram shows a cross-sectional view of the semiconductor structure 400 along the ZX plane of line J'-J'. The metal gate 204 may be formed of a metal-filled material, such as cobalt (Co) and tungsten (W). The metal gate 204 may be interfaced with the channel layer 202 and MDI 210 via a pad 206. The pad 206 may be formed of titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), or tungsten (W).

[0053] The RMG process in block 320 may be included in the processing chamber (such as...) Figure 1 Any suitable etching process performed in the processing chamber 120 shown, and in the processing chamber (such as...) Figure 1 Any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in the processing chambers 126, 128, or 130 shown.

[0054] The metal filling process can be performed at temperatures between approximately 150°C and approximately 400°C. Following the metal filling process can be various annealing steps, such as high-k annealing and reliability annealing, performed at temperatures between approximately 700°C and approximately 950°C.

[0055] In box 322, a top contact patterning and metal infill process is performed to pattern the top ILD 226 for forming the top S / D contact 220, as shown. Figure 4K As shown. Top interface 224 provides an ohmic contact between top epi S / D 222 and top S / D contact 220.

[0056] The top S / D contacts 220 can be formed of cobalt (Co) or tungsten (W) and can include a liner (not shown) formed of titanium nitride (TiN) or tungsten (W) around it. The top interface 224 can be formed of a metal silicide, such as titanium silicide (TiSi2), molybdenum silicide (MoSi2), cobalt silicide (CoSi2), nickel (Ni2Si), tantalum silicide (TaSi2), or any combination thereof. An optional contact epi (not shown) can be formed between the top epi S / D 222 and the top interface 224 by a low temperature epitaxy at a low temperature between about 400 °C and about 900 °C. The contact epi and the top interface 224 can be formed in a cluster tool without vacuum break.

[0057] The top contact patterning and metal fill process in block 322 can include any suitable photolithography and etching processes (such as photolithography) performed in a process chamber (such as the process chamber 120 shown), and any suitable deposition processes (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxy deposition processes, etc.) performed in a process chamber (such as the process chambers 126, 128, or 130 shown). Figure 1 The low temperature epitaxy deposition process in block 322 can be performed in a process chamber (such as the process chambers 126, 128, or 130 shown). The top contact patterning and metal fill process and the low temperature epitaxy deposition process in block 322 can be performed without breaking the vacuum in a cluster tool (such as the processing system 100). Figure 1 Figure 1 The low temperature epitaxy deposition process in block 322 can be performed in a process chamber (such as the process chambers 126, 128, or 130 shown). The top contact patterning and metal fill process and the low temperature epitaxy deposition process in block 322 can be performed without breaking the vacuum in a cluster tool (such as the processing system 100).

[0058] In block 324, a via contact (VCT) and via contact to gate (VCG) patterning process is performed to form a bottom VCT 430, a top VCT 432, and a VCG 434, as shown. Figure 4L The dielectric layers 232 and 234 are deposited over the semiconductor structure 400. The bottom VCT 430 is formed by etching through the dielectric layers 232 and 234, the top ILD 226, and the bottom ILD 218 to the dummy contact 428. The top VCT 432 is formed by etching through the dielectric layers 232 and 234 to the top S / D contact 220. The VCG 434 is formed by etching through the dielectric layers 232 and 234 to the metal gate 204.

[0059] The dielectric layers 232 and 234 can be formed of silicon oxide (SiO2), silicon nitride (Si3N4), or aluminum oxide (Al2O3). The dielectric layers 232 and 234 are formed of different materials.

[0060] The VCT and VCG patterning process in block 324 can include any suitable photolithography and etching processes (such as photolithography) performed in a process chamber (such as the process chamber 120 shown), and any suitable deposition processes (such as chemical vapor deposition (CVD), physical vapor deposition (PVD), epitaxy deposition processes, etc.) performed in a process chamber (such as the process chambers 126, 128, or 130 shown). Figure 1 ​Any suitable lithography and etching processes (such as photolithography) performed in the processing chamber 120 shown, and in the processing chamber (such as...) Figure 1 Any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in the processing chambers 126, 128, or 130 shown.

[0061] In block 326, a dummy contact stripping process is performed to selectively etch dummy contacts 428 and form etched portions 436, as shown. Figure 4M As shown.

[0062] The dummy contact stripping process in block 324 may be included in a processing chamber (such as...) Figure 1 Any suitable etching process, such as photolithography, performed in the processing chamber 120 shown.

[0063] In block 328, a bottom replacement S / D contact forming process is performed to form bottom S / D contact 212, as follows: Figure 4N As shown. The bottom S / D contact 212 is formed by filling the portion 436 etched in the dummy contact stripping process within the box 324 with a metallic filler material (such as cobalt (Co) and tungsten (W)). The bottom VCT 430 is filled to the top surface of the top ILD 226 with a metallic filler material to form a contact plug 438. The bottom S / D contact 212 may interface with the bottom epi S / D 214 via a bottom interface 216. The bottom S / D contact 212 may include a pad (not shown) formed of titanium nitride (TiN) or tungsten (W) around it. The bottom interface 216 may be formed of a metal silicide, such as titanium silicide (TiSi2), molybdenum silicide (MoSi2), cobalt silicide (CoSi2), nickel (Ni2Si), tantalum silicide (TaSi2), or any combination thereof. An optional contact epi (not shown) can be formed between the bottom epi S / D 214 and the bottom interface 216 by low-temperature epitaxial deposition at a low temperature between about 400°C and about 900°C. The contact epi and the bottom interface 216 can be formed in a cluster tool without vacuum destruction.

[0064] The bottom replacement S / D contact forming process in box 328 may include processing chambers (such as...) Figure 1 Any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., can be performed in the processing chambers 126, 128, or 130 shown. The low-temperature epitaxial deposition process in block 328 can be performed in the processing chamber (such as...) Figure 1The bottom replacement S / D contact formation process and the low temperature epitaxial deposition process in block 328 can be performed without breaking vacuum in a cluster tool, such as processing system 100. The cluster tool can be the same cluster tool used to perform the top contact patterning and metal fill process in block 322 with the low temperature epitaxial deposition process.

[0065] In block 330, a VCT and VCG fill process is performed to fill the bottom VCT 430, the top VCT 432, and the VCG 434 within the dielectric layers 232 and 234 with a metal fill material, such as cobalt (Co) and tungsten (W), to form the contact plug 236, as shown. Figure 4O

[0066] The VCT and VCG fill process in block 330 can include any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in a processing chamber, such as processing chamber 126, 128, or 130, as shown. Figure 1

[0067] In block 332, a metal layer formation process is performed to form a metal layer 228 on the dielectric layers 232 and 234 and embedded in the dielectric layer 230, as shown. The metal layer 228 can be formed of cobalt (Co) or tungsten (W). The dielectric layer 230 can be formed of silicon oxide (Si02), silicon nitride (Si3N4), or aluminum oxide (AI2O3). Figure 2A

[0068] The metal layer formation process in block 332 can include any suitable lithography and etching process, such as photolithography, performed in a processing chamber, such as processing chamber 120, as shown, and any suitable deposition process, such as chemical vapor deposition (CVD), physical vapor deposition (PVD), etc., performed in a processing chamber, such as processing chamber 126, 128, or 130, as shown. Figure 1 Figure 1

[0069] Embodiments described herein provide methods for complementary FET (CFET) devices. In the methods described herein, dummy contacts are deposited in place of bottom source / drain (S / D) contacts of a bottom FET module of a CFET prior to high temperature processes, such as epitaxial deposition processes and replacement metal gate processes, and subsequently replaced with bottom S / D contacts formed of metal. Such replacement S / D contacts allow for optimized materials to be used for bottom S / D contacts in the bottom FET module without any thermal budget limitations.

[0070] ​​​​​While the foregoing is directed to embodiments of the present disclosure, other and further embodiments of the disclosure can be devised without departing from the basic scope thereof, and the scope thereof is determined by the claims that follow.

Claims

1. A semiconductor structure for forming a complementary field-effect transistor (CFET), the semiconductor structure comprising: Metal gate; A bottom field-effect transistor (FET) module, the bottom FET module comprising: Multiple channel layers extend through the metal gate in a first direction; and Bottom source / drain (S / D) contacts are electrically connected to the plurality of channel layers via bottom epitaxial (epi) S / D and bottom interface; and A top FET module, stacked on top of the bottom FET module in a second direction orthogonal to the first direction, the top FET module comprising: Multiple channel layers extend through the metal gate in the first direction; and The top source / drain (S / D) contacts are electrically connected to the multiple channel layers via the top epitaxial (epi) S / D and the top interface. The bottom S / D contact and the top S / D contact each contain cobalt (Co) or tungsten (W).

2. The semiconductor structure of claim 1, wherein the metal gate comprises cobalt (Co) or tungsten (W).

3. The semiconductor structure of claim 1, wherein the plurality of channel layers in the top FET module and the plurality of channel layers in the bottom FET module each comprise silicon.

4. The semiconductor structure of claim 1, wherein the bottom epi S / D is p-type doped and the top epi S / D is n-type doped.

5. The semiconductor structure of claim 1, wherein the bottom epi S / D is n-type doped and the top epi S / D is p-type doped.

6. The semiconductor structure of claim 1, wherein the top interface and the bottom interface each comprise a metal silicide.

7. A method for forming a complementary field-effect transistor (CFET), the method comprising: A top cover spacer forming process is performed to deposit a top cover spacer covering the exposed surface of the top nanosheet and spacers around the top nanosheet along a first plane orthogonal to a first direction, wherein: The top nanosheets are stacked on the bottom nanosheets in a second direction orthogonal to the first direction, and The top nanosheet and the bottom nanosheet each contain a plurality of channel layers extending through the dummy gate in the first direction; Perform a bottom epitaxial (epi) source / drain (S / D) formation process to form a bottom epitaxial S / D along the first plane on the exposed surface of the bottom nanosheet; Perform bottom contact patterning and sacrificial fill processes to deposit a bottom interlayer dielectric (ILD) on the surface of the spacer around the bottom epi S / D, pattern the bottom ILD to form dummy contacts, and remove the top cover spacer; Perform a top epi S / D forming process to form a top epi S / D along the first plane on the exposed surface of the top nanosheet and form a top ILD around the top epi S / D; Perform a replacement metal gate (RMG) process to replace the dummy gate with a metal gate; Perform top contact patterning and metal infill processes to pattern the top ILD, thereby forming the top S / D contact; After the bottom epi S / D forming process, the top epi S / D forming process, and the RMG process, a dummy contact stripping process is performed to selectively etch the dummy contacts; and A bottom replacement S / D contact formation process is performed to form bottom S / D contacts in the portion etched in the dummy contact stripping process.

8. The method of claim 7, wherein the bottom S / D contact, the top S / D contact, and the metal gate each comprise cobalt (Co) or tungsten (W).

9. The method of claim 7, wherein the dummy contact comprises silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), or a combination thereof.

10. The method of claim 7, wherein the bottom ILD and the top ILD each comprise silicon oxide (SiO2).

11. The method of claim 7, wherein the bottom epi S / D is p-type doped and the top epi S / D is n-type doped.

12. The method of claim 11, further comprising: Prior to the dummy contact stripping process, an annealing process is performed to activate the dopants in the bottom epiS / D and the top epiS / D.

13. The method of claim 7, wherein the bottom epi S / D forming process and the top epi S / D forming process are performed at a temperature between 400°C and 1200°C.

14. The method of claim 7, wherein the RMG process is performed at a temperature between 150°C and 950°C.

15. A semiconductor structure for forming a complementary field-effect transistor (CFET), the semiconductor structure comprising: Metal gate; A bottom field-effect transistor (FET) module, the bottom FET module comprising: Multiple channel layers extend through the metal gate in a first direction; and Dummy contacts are connected to the plurality of channel layers via bottom epitaxial S / D and bottom interface; and A top FET module, stacked on top of the bottom FET module in a second direction orthogonal to the first direction, the top FET module comprising: Multiple channel layers extend through the metal gate in the first direction; and The top source / drain (S / D) contacts are electrically connected to the multiple channel layers via the top epitaxial (epi) S / D and the top interface. The dummy contact comprises silicon oxide (SiO2), silicon nitride (Si3N4), silicon carbide (SiC), or a combination thereof, and the top S / D contact comprises cobalt (Co) or tungsten (W).

16. The semiconductor structure of claim 15, wherein the metal gate comprises cobalt (Co) or tungsten (W).

17. The semiconductor structure of claim 15, wherein the plurality of channel layers in the top FET module and the plurality of channel layers in the bottom FET module each comprise silicon.

18. The semiconductor structure of claim 15, wherein the bottom epi S / D is p-type doped and the top epi S / D is n-type doped.

19. The semiconductor structure of claim 15, wherein the bottom epi S / D is n-type doped and the top epi S / D is p-type doped.

20. The semiconductor structure of claim 15, wherein the top interface and the bottom interface each comprise a metal silicide.

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