Memory bit cell with three-dimensional cross field effect transistor

Abstract

An apparatus and method for efficiently creating a layout of memory bit cells is described. In various implementations, a memory bit cell uses a transistor pair that is a vertically stacked gate-all-around (GAA) transistor having gate terminals that form a T-shape relative to each other and a single gate contact that overlaps only one of the two active layers of the pair. The transistors of such a field effect transistor (FET) pair are referred to as TFETs. The active layers of the TFETs use opposite doping polarities relative to each other and conduct current in orthogonal directions. The non-overlapping distance between the top and bottom active layers of the pair of TFETs is at least the width of the drain / source contact. The orthogonal current flow of the top and bottom active layers simplifies local connections, thereby reducing the resistance and capacitance of signal routing.

Description

BACKGROUND

[0001] Description of Related Art

[0002] As semiconductor manufacturing processes advance and die geometries decrease, semiconductor chips provide more functionality and performance while occupying less space. Despite the many advances, modern technology still presents design problems in the processing and integrated circuit design that limit the potential benefits. For example, capacitive coupling, electromigration, short channel effects such as at least sub-threshold current, and process yield are some of the problems that affect device placement and signal routing for the entire die of a semiconductor chip. These problems can delay completion of the design and impact time to market.

[0003] To shorten the design cycle of a semiconductor chip, manual full-custom design is replaced by automation where possible. In some cases, standard cell layouts are created manually. In other cases, the rules used by the layout routing tools are adjusted, thereby automating cell creation. However, the automated process sometimes does not satisfy every rule for performance, power consumption, signal integrity, process yield, both local and external signal routing (including internal cross-coupled connections), pin access, etc. Therefore, the designer manually creates these cells to achieve better results for multiple characteristics or rewrites the rules for the layout routing tools. However, many times, the layout tools and rules are set up for planar devices rather than for relatively newer non-planar devices. One example of these cells is a memory bit cell of a random access memory.

[0004] Generally, a variety of semiconductor chips include at least one processing unit coupled to a memory. The processing unit sends memory access requests to the memory for fetching instructions, fetching data, and storing computation results. Static random access memory (SRAM) is often used as the memory. The SRAM includes an array of many memory bit cells and surrounding circuitry for accessing values stored in the array. The die or package can include other cells or components in addition to the processing unit and the memory. The dimensions of the individual components have limitations so that all of the components are placed on the same die or the same package. For several types of memory, such as SRAM, the dimensions are large enough that they interfere with placement of other components. Therefore, the chip becomes inoperable or requires a larger and more expensive package without a significant redesign.

[0005] In view of the foregoing, methods and systems for efficiently creating a layout of a memory bit cell are desired. BRIEF DESCRIPTION OF DRAWINGS

[0006] Figure 1 is a generalized diagram of a cross-sectional view of a semiconductor device layout.

[0007] Figure 2 is a generalized block diagram of a top view of a standard cell layout.

[0008] Figure 3 is a generalized block diagram of a top view of a standard cell layout.

[0009] Figure 4 is a generalized diagram of a data storage circuit of a memory bit cell.

[0010] Figure 5 is a generalized block diagram of a top view of a standard cell layout.

[0011] Figure 6 is a generalized block diagram of a top view of a standard cell layout.

[0012] Figure 7 is a generalized block diagram of a top view of a standard cell layout.

[0013] Figure 8 is a generalized block diagram of a top view of a standard cell layout.

[0014] Figure 9 is a generalized block diagram of a top view of a standard cell layout.

[0015] Figure 10 is a generalized block diagram of a top view of a standard cell layout.

[0016] Figure 11 is a generalized block diagram of a top view of a standard cell layout.

[0017] Figure 12 is a generalized block diagram of a top view of a standard cell layout.

[0018] Figure 13 is a generalized diagram of a memory bank.

[0019] Figure 14 is a generalized block diagram of a top view of a standard cell layout.

[0020] Figure 15 is a generalized block diagram of a top view of a standard cell layout.

[0021] Figure 16 is a generalized block diagram of a top view of a standard cell layout.

[0022] Figure 17 is a generalized block diagram of a top view of a standard cell layout.

[0023] Figure 18 is a generalized block diagram of a top view of a standard cell layout.

[0024] Figure 19 is a generalized block diagram of a top view of a standard cell layout.

[0025] Figure 20 is a generalized block diagram of a top view of a standard cell layout.

[0026] Figure 21 is a generalized block diagram of a top view of a standard cell layout.

[0027] Figure 22 is a generalized block diagram of a top view of a standard cell layout.

[0028] Figure 23 is a generalized block diagram of a top view of a standard cell layout.

[0029] Figure 24 is a generalized diagram of a method for efficiently creating a layout of memory bit cells that utilize TFETs.

[0030] Figure 25 is a generalized diagram of a computing system having an integrated circuit that uses an array of memory bit cells that utilize TFETs.

[0031] While the application can be susceptible to various modifications and alternative forms, a specific embodiment has been shown by way of example in the drawings and will be described in detail herein. However, it should be understood that the application is not intended to be limited to the particular DETAILED DESCRIPTION

[0032] In the following description, numerous specific details are set forth to provide a thorough understanding of the application. However, it will be apparent to one skilled in the art that the application can be practiced without the specific details. In some instances, well-known circuits, structures and techniques have not been shown in detail in order not to obscure the application. Also, it is to be understood that the description and drawings are not intended to limit the scope of the present application, but merely to provide illustrative examples of the application. Moreover, the use of certain terms to describe the application is not intended to limit the scope of the present application to such terms. The description and drawings are to be regarded as illustrative in nature and their intent is not to limit the scope of the application.

[0033] Systems and methods for efficiently creating a layout of memory bit cells are contemplated. In various implementations, one or more standard cells include a transistor pair having gate terminals that form a T-shape relative to one another. As used herein, a "transistor" is also referred to as a "field effect transistor" (FET), a "semiconductor device," or a "device." In some implementations, the transistor pair is a vertically stacked all-around gate (GAA) transistor, such as a top vertical GAA transistor (or GAA transistor) formed vertically on top of a bottom GAA transistor with at least one layer of isolation oxide between the two GAA transistors.

[0034] Additionally, the top GAA transistor of the pair of transistors has one or more electrically conductive channels (or channels) that are positioned orthogonally to the one or more electrically conductive channels of the bottom GAA transistor. Thus, the top GAA transistor has a current flow direction through the one or more top channels that is orthogonal to a current flow direction of the one or more bottom channels of the bottom GAA transistor. In some implementations, the channels comprise electrically conductive lateral nanowires. In other implementations, the channels comprise electrically conductive nanosheets. In such implementations, the current of a particular transistor flows through one or more channels, or in other words, one or more nanosheets.

[0035] The pair of top and bottom GAA transistors (two vertically stacked transistors) also includes a single gate contact for connecting the same input signal to both gate terminals of the pair of vertically stacked transistors. This single gate contact overlaps only one of the two active layers (i.e., only one, not both) used to form the pair of vertically stacked transistors. For example, this single gate contact overlaps only one of the n-type active layer of the n-type transistor and the p-type active layer of the p-type transistor that is formed in a vertically stacked manner above or below the n-type transistor. As used herein, “active layer” refers to a region of a semiconductor wafer that forms doped silicon. For planar transistors (devices), the active layer defines a region of a silicon substrate that is doped with either p-type atoms (dopants) or n-type atoms (dopants). For non-planar transistors (devices), the active layer defines a region of a three-dimensional structure above a silicon substrate that contains doped silicon, such as where the channels are formed. The pair of vertically stacked transistors having gate terminals that form a T-shape with respect to each other and a single gate contact that overlaps only one of the two active layers used to form the pair of vertically stacked transistors is referred to as a “TFET.”

[0036] The top GAA transistor of the TFET has a top active layer with a doping polarity that is the opposite polarity of the bottom active layer of the bottom GAA transistor. In one implementation, the top GAA transistor includes a p-type active layer, while the bottom GAA transistor includes an n-type active layer. In another implementation, the p-type and n-type polarities between the active layers of the top GAA transistor and the bottom GAA transistor are reversed. With the orthogonal orientation between the top GAA transistor and the bottom GAA transistor, both the top GAA transistor and the bottom GAA transistor have maximum drive current of their respective carriers based on their orientation. It should be understood that silicon wafers, integrated circuits, and semiconductor packages using a silicon substrate layer can be rotated and flipped. Accordingly, the materials and layers described will be rotated and flipped, and the orientations and directions will have different implications. Accordingly, the terms “top,” “bottom,” “horizontal,” “vertical,” “above,” and “below” can change with a layout rotation or flip.

[0037] In various implementations, the top active layer of the top GAA transistor of the two vertically stacked transistors does not overlap the bottom active layer of the bottom GAA transistor of the two vertically stacked transistors. The non-overlapping distance between the first (top) active layer and the second (bottom) active layer includes at least the width of a source or drain contact. A single gate contact for connecting the same input signal to both gate terminals of the top GAA transistor and the bottom GAA transistor overlaps only one of the top active layer and the bottom active layer. In one implementation, the single gate contact overlaps at least a portion of the bottom active layer. The gate terminals of the top GAA transistor and the bottom GAA transistor form a T-shape with respect to the location of the single gate contact. Placing the single gate contact overlapping only one of the top active layer and the bottom active layer simplifies semiconductor fabrication and improves manufacturing yield when compared to placing the single gate contact overlapping both the top active layer and the bottom active layer.

[0038] The memory array (or array) utilizes memory bit cells arranged as a plurality of rows and a plurality of columns. These memory bit cells use TFETs. In various implementations, the orthogonal current flow of the top active layer and the bottom active layer simplifies local connections for cross-coupled inverters, reducing resistance and capacitance of signal routing, thus improving performance. A first memory bit cell includes a drain contact between a drain node of a p-type pull-up transistor and an n-type pull-down transistor, the drain contact contacting an area of a local interconnect layer of the p-type pull-up transistor. This area of the local interconnect layer is not physically adjacent to the p-type active layer of the p-type pull-up transistor. Additional details of arrays using TFETs are provided in the description of Figures 1 to 25

[0039] Turning now to​Figure 1 A generalized block diagram showing cross-sectional views of semiconductor device layouts 100 using TFETs is shown. The semiconductor material of a cross field effect transistor (FET) 102 is shown in the left drawing or box. The cross FET is also referred to as an "XFET." Thus, the cross FET 102 is also referred to as an XFET 102. The semiconductor material of a TFET 104 is shown in the right drawing or box. Three-dimensional (3-D) illustrations of the p-type and n-type cross FETs 102 and TFETs 104 are shown. Each of the XFETs 102 and TFETs 104 includes a p-type device vertically stacked on an n-type device. The n-type device includes an n-type gate 116 formed at least around an n-type channel 110. Similarly, a p-type gate 136 is formed around a p-type channel 130. Thus, the p-type channel 130 has a doping polarity that is opposite to that of the n-type channel 110 of the underlying n-type device.

[0040] While a single n-type channel 110 and a single p-type channel 130 of a cross FET 102 are shown, in other implementations, the semiconductor device includes another number of conductive channels (or channels). As an example, a TFET 104 includes an n-type channel 110 and an n-type channel 111. In some implementations, a channel includes one or more conductive lateral nanowires. In other implementations, a channel includes one or more conductive nanosheets. A nanosheet is a sheet of doped silicon, as opposed to a line of doped silicon. In other words, a nanosheet is a wider conductive line than a lateral nanowire. A nanosheet can also be thought of as a fin that is rotated and placed on its side vertically above a silicon substrate so that the nanosheet is not in physical contact with the silicon substrate. Instead, a metal gate is formed between the nanosheet and the silicon substrate. However, no actual fabrication steps for forming a nanosheet are described in this imagination.

[0041] The use of a gate-all-around (GAA) nanowire or nanosheet reduces threshold voltage, speeds up switching time, reduces leakage current, and further reduces short channel effects as compared to a finFET. Examples of short channel effects other than leakage current are latch-up, drain-induced barrier lowering (DIBL), punchthrough, temperature dependence of performance, impact ionization, and parasitic capacitance to the silicon substrate. As previously described, an "active layer" refers to a region of a semiconductor wafer that is formed of doped silicon. For a planar transistor (device), the active layer defines a region of the silicon substrate that is doped with either p-type atoms (dopants) or n-type atoms (dopants). For a non-planar transistor (device), the active layer defines a region of a three-dimensional structure above the silicon substrate that contains doped silicon, such as where a channel is formed.

[0042] In the illustrated implementation, the XFET 102 has an n-type active layer (not labeled) that includes a single n-type channel 110. In other implementations, the n-type active layer of the n-type device includes multiple n-type channels instead of the single n-type channel 110. The XFET 102 has a p-type active layer (not labeled) that includes a single p-type channel 130. In other implementations, the p-type active layer of the p-type device includes multiple p-type channels instead of the single p-type channel 130. In the illustrated implementation, the TFET 104 has an n-type active layer 180 that includes the n-type channel 110 and the n-type channel 111. In other implementations, the n-type active layer 180 of the n-type device includes another number of n-type channels. The TFET 104 has a p-type active layer 182 that includes the single p-type channel 130. In other implementations, the p-type active layer 182 of the p-type device includes multiple p-type channels instead of the single p-type channel 130.

[0043] With one or more channels, the p-type active layer 182 of the p-type device includes a three-dimensional region having dimensions, such as length, width, and height. These dimensions correspond to the dimensions of the one or more p-type channels (or p-type nanosheets). For example, the p-type active layer length 126 is the same as the length of the one or more p-type channels, such as the p-type channel 130. Similarly, the n-type active layer length 124 is the same as the length of the one or more n-type channels, such as the length of the n-type channel 110 or the same length of the n-type channel 111. The n-type active layer height 125 of the n-type active layer 180 is the same as the total height of the one or more n-type channels, such as the total height of the n-type channel 110 and the n-type channel 111. The p-type active layer width (not labeled) is the same as the width of the one or more p-type channels. Similarly, the n-type active layer width (not labeled) of the n-type active layer 180 is the same as the width of the n-type channel 110, which is the same as the width of the n-type channel 111.

[0044] The n-type channel 110 and the n-type gate 116 are oriented orthogonally to the p-type channel 130 and the p-type gate 136. In other words, the n-type channel 110 and the n-type gate 116 are oriented at a 90-degree angle to the direction of the p-type channel 130 and the p-type gate 136. Thus, the direction of current flow through the n-type channel 110 of the bottom n-type device is orthogonal to the direction of current flow of the p-type channel 130 of the top p-type device. With the orthogonal orientation between the top p-type device and the bottom n-type device, both devices have maximum mobility of their respective charge carriers based on their orientation. Additionally, the orthogonal orientation of the top p-type device and the bottom n-type device allows for connections between the vertically stacked devices to use a single via layer.

[0045] A complementary FET (CFET), not shown, includes a top GAA transistor vertically stacked on top of a bottom GAA transistor with at least one oxide layer in between for isolation. Thus, the CFET, XFET, and TFET use vertically stacked GAA transistors. Vertically stacking a top GAA transistor on top of a bottom GAA transistor further improves performance, reduces power consumption, and reduces the die area occupied by the GAA transistors. However, the CFET uses a top GAA transistor with one or more channels of the top GAA transistor aligned in the same direction as one or more channels of the bottom GAA transistor. The CFET does not rotate the top GAA transistor and the bottom GAA transistor relative to each other. However, as shown here, the XFET 102 and the TFET 104 have an orthogonal orientation between one or more channels of the top GAA transistor and one or more channels of the bottom GAA transistor.

[0046] The XFET 102 and the TFET 104 have better drive current for each of the top GAA transistor and the bottom GAA transistor compared to the complementary FET, resulting in higher performance. The complementary FET typically uses at least two metal layers and three via layers to create connections between the top GAA transistor and the bottom GAA transistor. In contrast, the XFET 102 and the TFET 104 utilize a single metal layer and a single via layer to connect between the top GAA transistor and the bottom GAA transistor.

[0047] The insulating layer is between the top p-type device and the bottom n-type device with a gate contact 122 formed between the devices in the insulating layer when the gate terminals of the pair of devices (p-type device and n-type device) receive the same input signal. The gate contact 122 between the vertically stacked devices is directly connected to the p-type metal gate 136 and the n-type metal gate 116 without traversing any metal layers. One advantage of the orthogonal orientation of the XFET 102 and the TFET 104 is the use of a single via layer, which is shown later in a semiconductor layout of a memory bit cell. The use of a single via layer reduces the resistance and capacitance of the corresponding circuitry.

[0048] As shown, the gate contact 122 of the XFET 102 overlaps each of the n-type and p-type active layers of the two vertically stacked transistors. Since the illustrated implementation of the XFET 102 includes a single channel for each of the p-type and n-type devices, the active layers in the illustrated implementation include a single channel 110 and 130. The gate contact 122 overlaps each of the n-type channel 110 and the p-type channel 130. In contrast, the gate contact 122 of the TFET 104 overlaps only one of the p-type active layer 182 of the p-type device and the n-type active layer 180 of the n-type device, where the p-type and n-type devices form two vertically stacked devices. In the illustrated implementation, the gate contact 122 of the TFET 104 overlaps only the n-type active layer 180, which includes the n-type channel 110 and the n-type channel 111. Thus, the gate contact 122 of the TFET 104 overlaps only the n-type active layer 180. The gate contact 122 of the TFET 104 does not overlap the p-type active layer 182.

[0049] For the TFET 104, in various implementations, the p-type active layer 182 does not overlap the n-type active layer 180. The distance between the p-type active layer 182 and the n-type active layer 180 is shown as a width (or offset distance) 106. The width 106 includes at least the width of the source or drain contact. In some implementations, the width 106 also includes another minimum distance between the p-type channel 130 and the source or drain contact, which is determined by the design rules and checks of the particular semiconductor fabrication process used to manufacture the TFET 104. In one implementation, this minimum distance is 3 nanometers (nm), and the width of the source or drain contact is 18 nm. In such an implementation, the minimum width of the width 106 is 21 nm (3 nm + 18 nm is 21 nm).

[0050] The top view of the TFET 104 shows that the gate terminals (gates 116 and 136) of the top GAA transistor and the bottom GAA transistor form a T-shape. Placing a single gate contact 122 that overlaps only one of the n-type active layer 180 and the p-type active layer 182, such as the n-type active layer 180, simplifies semiconductor fabrication and improves manufacturing yield when compared to placing a single gate contact 122 that overlaps both the n-type and p-type active layers as shown in the XFET 102.

[0051] Reference Figure 2FIG. 1 shows a top view of a semiconductor device layout 100 using TFETs. The numbering of the contacts (or vias), semiconductor materials, and structures described previously are the same. The layout 100 is for an inverter using TFETs 104. The layout 100 is accompanied by a three-dimensional (3-D) illustration of the p-type TFET and the n-type TFET. The right side shows a top view of the semiconductor device layout 100 (or layout 100), and the left side shows a cross-sectional view of the TFET 104. For this inverter, the p-type device is vertically stacked on the n-type device. However, in other implementations, it is possible and contemplated that the n-type device will be vertically stacked on the p-type device. Each device of the inverter uses a gate-all-around (GAA) metal that wraps one or more nanosheets in the gate region in a 360-degree fashion. The bottom n-type device is fabricated on a first wafer. The top p-type device is fabricated on a separate second wafer, which is then oxide-to-oxide bonded to the first wafer. As shown, the gate contact 122 overlaps with only one of the n-type active layer and the p-type active layer. In addition to the current flow (I flow) direction of the two devices, the length dimension 124 and the length dimension 126 are shown. The width 106 includes the width of at least the source or drain contact 120. Here, the inverter uses the contact 120 as a drain contact.

[0052] The inverter uses a frontside power metal zero (or metal 0 or M0 or metal 0) layer 150 to provide a power reference level indicated as "VDD." The contact 140 connects the frontside M0 layer 150 to the p-type local interconnect 134 in order to route VDD to the source region of the p-type device. The frontside M0 layer 150 is also used to route the input signal "input" and the output signal "output." For the input signal "input," the contact 142 connects the frontside M0 layer 150 to the p-type gate 136. For the input signal "input," the contact 122 connects the p-type gate 136 to the n-type gate 116. The drain region of the n-type device uses the n-type local interconnect 114. The drain region of the p-type device uses the p-type local interconnect 134. The contact 120 connects the two drain regions together.

[0053] Contact 120 is located between the drain nodes of the p-type transistor and the n-type transistor and contacts an area of the p-type local interconnect 134 of the p-type transistor. This area of the local interconnect layer 134 is not physically adjacent to the p-type active layer of the p-type transistor. As a result of the placement of the contact 120, the contact 120 provides a lower resistance contact between the p-type local interconnect 134 and the n-type local interconnect 114. In addition, the placement of the contact 120 provides higher reliability (less process variation) and higher manufacturing yield than if the contact 120 were placed along an area of the p-type local interconnect 134 that is physically adjacent to the p-type active layer. The technique shown in the layout 200 is again used in the upcoming layouts 500 - layout 1200 and layout 1100 - layout 2300, providing a standard cell layout of a memory bit cell that includes the benefits of the TFET 104.

[0054] For the output signal "output", the contact 140 overlaps the area of the contact 120 and connects the p-type local interconnect 134 to the front side M0 layer 150. The inverter uses a back side power metal zero (or metal 0 or M0 or metal 0) layer that is located below the silicon substrate layer and any oxide layer (not shown) used for isolation. A micro silicon via (TSV) traverses the silicon substrate layer so as to be placed between the back side power M0 rail and the source region of the n-type device.

[0055] Reference Figure 3 is a generalized block diagram showing a cross-sectional view of a standard cell layout 300 that utilizes power connections routed in front side metal layers and back side metal layers. The numbering of the contacts (or vias), semiconductor materials, and structures described previously are the same. The standard cell layout 300 is used in any of various types of Boolean gates and composite gates that include transistors arranged in a particular way for providing data processing functions or providing data storage. The standard cell layout 300 (or layout 300) uses a TFET. The TFET includes an n-type device 340 and a p-type device 342. Although the cross-sectional view shows each of the two transistors (devices) 340 and 342 with metal gates oriented in the same direction, the actual placement of these transistors in a semiconductor layout includes an orthogonal placement with respect to each other. Both front side metal layers and back side metal layers are used to route power signals.

[0056] Here, the first transistor of the TFET, such as n-type device 340, has an n-type active layer 380 that provides current flow oriented in a first direction orthogonal to a second direction of current flow in p-type active layer 382. In one embodiment, n-type active layer 380 includes a plurality of n-type nanosheets. In the designation or illustration, the designation "n-type nanosheet 110" is used. However, it should be understood that n-type active layers, such as n-type active layer 380 (and Figure 1 The n-type active layer 180 may include multiple n-type nanosheets, as shown in the cross-sectional view provided in layout 300. The upcoming ( Figures 5 to 12 Layout 500 - Layout 1200 and ( Figures 14 to 23 Layouts 1400-2300 provide top views, not cross-sectional views, and therefore only show a single n-type nanosheet. However, it should be understood that, as ( Figure 1 As shown in layouts 300 and 100, one or more additional n-type nanosheets are formed below the topmost n-type nanosheet. The same applies to p-type nanosheet 130.

[0057] In various specific implementations, each of the n-type nanosheets 110 of the n-type active layer 380 is composed of a silicon semiconductor epitaxial growth layer doped with n-type atoms. Similarly, each of the p-type nanosheets 130 is composed of a silicon semiconductor epitaxial growth layer doped with p-type atoms. Each of the n-type nanosheets 110 and p-type nanosheets 130 terminates within the edges of their respective drain and source regions. The drain and source regions of the n-type device 340 utilize the previously shown n-type local interconnects 114. The drain and source regions of the p-type device 342 utilize the previously shown p-type local interconnects 134. Compared to a complementary FET, the n-type nanosheets 110 do not traverse the entire drain and source regions. Instead, the n-type nanosheets 110 utilize metal sidewall contacts at the ends of the nanosheets within the source and drain regions, thereby enabling the creation of more nanosheets in the n-type active layer. The p-type nanosheets 130 of the p-type active layer 382 are formed in a similar manner, and also utilize metal sidewall contacts at the ends of the nanosheets in their respective source and drain regions.

[0058] As previously described, the n-type active layer 380 refers to the region of the semiconductor wafer where silicon is formed. The n-type active layer 380 of the n-type device 340 is a three-dimensional region whose length is equal to the distance between the metal sidewall contacts at the ends of the nanosheets within the source and drain regions. The height of this n-type active layer 380 is equal to the distance from the bottom of the bottom n-type nanosheet 110 to the top of the top n-type nanosheet 110. Furthermore, the width of this n-type active layer 380 is equal to the distance the n-type nanosheet 110 traverses along the direction of entry into (or exit from) the page. The p-type active layer 382 of the p-type device 342 has dimensions defined in a similar manner.

[0059] The n-type device 340 is connected to a first voltage level reference provided by a backside metal layer. This backside power metal zero (or metal 0 or M0 or metal 0) layer 302 is below the silicon substrate layer and any oxide layers for isolation (not shown). A micro-silicon through via (TSV) 304 traverses the silicon substrate layer so as to be placed between the backside power M0 layer 302 and the source region of the n-type device 340. The TFET also uses a second transistor, such as the p-type device 342, that has a second channel oriented in a second direction that is orthogonal to the first direction and connected to a second voltage level reference provided by a frontside metal layer. This frontside power metal zero (or metal 0 or M0 or metal 0) layer 320 is above the silicon substrate layer and any oxide layers for isolation (not shown). The drain region and source region of the p-type device 342 use the p-type local interconnect 134 shown previously. In other implementations, the n-type transistor 340 and the p-type transistor 342 are switched along with the voltage reference level types connected to the backside power M0 layer 302 and the frontside power M0 layer 320.

[0060] The "micro-TSV" 304 is a silicon through via that traverses through the silicon substrate layer from the backside power M0 layer 302 to the source region 306 and terminates at a physical contact at each of the backside power M0 layer 302 to the source region 306. The distance between the backside power M0 layer 302 to the n-type local interconnect 114 used as the source region defines the height or length of the micro-TSV 304 that only traverses the silicon substrate layer and any oxide layers above the backside power M0 layer 302. The micro-TSV 304 does not physically extend into the multiple insulating layers of the semiconductor die that are used to route the multiple frontside metal layers. Similarly, the micro-TSV 304 does not physically extend into the multiple insulating layers of the semiconductor die that are used to route the multiple backside metal layers.

[0061] While the orientation of the standard cell layout 300 (or layout 300) is shown with each of the backside power M0 layer 302 and the frontside power M0 layer 320 routed in the horizontal direction, other orientations are possible and are contemplated. It should be understood that silicon wafers, integrated circuits, and semiconductor packages that use a silicon substrate layer can be rotated and flipped. Thus, the described materials and layers will be rotated and flipped and the orientation and direction will have different meanings. Accordingly, the terms "top," "bottom," "horizontal," "vertical," "above," and "below" can change as the layout 100 is rotated or flipped and the use of these terms in the following description corresponds to the orientation shown in the layout 300.

[0062] As used herein, a “terminal” of a transistor is also referred to as a “region” of the transistor. For example, a source region is also referred to as a source terminal, a drain region is also referred to as a drain terminal, and a gate region is also referred to as a gate terminal. Source and drain regions are typically formed in the same orientation (horizontal or vertical) as the corresponding gate metal of the same device. An example of a source and drain region is a trench silicide contact. In some implementations, the source and drain regions include cobalt silicide (CoSi2). In other implementations, the source and drain regions include titanium silicide (TiSi2) or ruthenium (Ru).

[0063] To pass current from an off-chip power supply to the p-type device 342, current flows from the off-chip power supply to the plurality of front-side metal layers to the front-side power M0 layer 320 to the p-type source contact 308 of the p-type device 342. To pass current from an off-chip ground reference to the n-type device 340, current flows from the off-chip ground reference to the one or more back-side metal layers to the back-side power M0 layer 302 to the n-type local interconnect 114 that serves as a source region of the n-type device 340. In some implementations, a single thick back-side metal layer is used instead of multiple thick back-side metal layers to pass the ground reference to reduce semiconductor manufacturing costs. The power connections shown in the layout 300 reduce die area, reduce semiconductor manufacturing complexity, thereby increasing wafer yield, and reduce voltage drop, thereby improving performance.

[0064] Turning to Figure 4 , a generalized block diagram of one implementation of data storage of a memory bit cell 400 is shown. In the implementation shown, data storage of a latching element is provided by device P1 402, device N1 406, device P2 412, and device N2 416. These devices use a back-to-back configuration of two inverters to provide data storage. A back-to-back configuration of two inverters is also referred to as cross-coupled inverters. As used herein, a Boolean logic high level is also referred to as a logic high level. Similarly, a Boolean logic low level is also referred to as a logic low level. In various implementations, a logic high level is equal to a power supply reference voltage level, and a logic low level is equal to a ground reference voltage level. As used herein, a circuit node or line is “asserted” when it stores a voltage level that enables a transistor that receives that voltage level or that voltage level indicates that an operation is enabled. For example, an n-type transistor is enabled when it receives a positive non-zero voltage level on its gate terminal that is at least a threshold voltage higher than the voltage level on its source terminal.

[0065] As used herein, a circuit node or line is “negated” when it stores a voltage level that disables a transistor that receives that voltage level. An n-type transistor is disabled when it receives a voltage level on its gate terminal that is within a threshold voltage of the voltage level on its source terminal. Similarly, a p-type transistor is enabled when it receives a voltage level on its gate terminal that is at least a threshold voltage below the voltage level on its source terminal. A p-type transistor is negated when it receives a voltage level on its gate terminal that is within a threshold voltage of the voltage level on its source terminal. Additionally, operations are enabled and disabled based on corresponding control signals being asserted or negated.

[0066] When a write operation occurs, external circuitry (not shown) asserts the write word line WL 430 with a logic high level. As a result, each of the n-type transistors N3 421 and N4 422 is enabled. The transistor N3 421, which is enabled through the gate, electrically connects the bit line BLT (bit line true) 440 to the node B 414. The transistor N4 422, which is enabled through the gate, electrically connects the bit line BLC (bit line complement) 442 to the node BB 404. In various implementations, during a write operation, the external circuitry ensures that the BLC 442 has a Boolean value that is opposite (complementary) to that of the BLT 440. As a result, the bit line BLT 440 drives a voltage level to be stored on the node D 414. One of the transistor P2 412 and the transistor N2 416 is enabled based on the voltage level of the node B 414. Similarly, one of the transistor P1 402 and the transistor N1 406 is enabled based on the node BB 404, which is an output node between the two transistors P2 412 and N2 416.

[0067] When a write operation does not occur, external circuitry (not shown) negates the write word line WL 430 with a logic low level. As a result, each of the n-type transistors N3 421 and N4 422 is disabled. The data storage of the memory bit cell 400 is one implementation of a static RAM (SRAM). In other implementations, another one of various types of RAM cells is used. This “memory bit cell” can also be referred to as a “memory bit cell,” a “SRAM bit cell,” and a “bit cell.” In various implementations, the memory bit cell 400 is replicated multiple times and arranged in rows and columns of a memory array, as shown later in the memory bank 1300 of FIG. 13. In various implementations, the memory bit cell 400 includes the cell layout 500-1200 and the cell layout 600-1200 of the upcoming description. Figure 13 Figures 5 to 12 Figures 14 to 23 ​​The TFET and layout techniques for cell layouts 1400-2300. These layout techniques are used to form six-transistor (6T) random access data storage for memory bit cells.

[0068] Now go to Figure 5 This shows a schematic block diagram of a top view of a standard cell layout 500. The numbering of the previously described contacts (or vias), semiconductor materials, and structures is the same. The standard cell layout 500 (or layout 500) is used for (… Figure 1 The memory bit cell of the TFET 104. Layout 500 includes a symmetrical layout 502 (or layout 502) and an asymmetrical layout 504 (or layout 504). Each of layouts 502 and 504 is used for the corresponding memory bit cell using the TFET. Layout 502 uses symmetrical placement of materials, electrical nodes, and signals, which provides a higher semiconductor manufacturing yield. Layout 504 uses asymmetrical placement of materials, electrical nodes, and signals, which provides a smaller standard cell. Therefore, the trade-off between using layout 502 and layout 504 is to choose either higher yield or a smaller memory bit cell. Similarly, ( Figures 6 to 12 The layouts 602-1202 utilize materials and symmetrical placement of electrical nodes and signals, which provides higher semiconductor manufacturing yields. Figures 6 to 12 The layouts 604-1204 utilize materials and asymmetrical placement of electrical nodes and signals, which provides smaller standard cells.

[0069] Here, in both layouts 502 and 504, the n-type nanosheet 110 is created by stacking alternating layers (such as silicon-germanium semiconductor epitaxial growth layers alternating with silicon semiconductor epitaxial growth layers). As previously described, ( Figures 5 to 12 Layout 500 - Layout 1200 and ( Figures 14 to 23 Layouts 1400-2300 provide top views, not cross-sectional views, and therefore only show a single n-type nanosheet. However, it should be understood that, as ( Figure 3 The layout of 300 and ( Figure 1 As shown in layout 100, one or more additional n-type nanosheets are formed below the topmost n-type nanosheet. For ( Figures 8 to 12 Layout 800-Layout 1200 and ( Figures 17 to 23 The same applies to the p-type nanosheet 130 shown in layouts 1700-2300.

[0070] For n-type nanosheet 110, a stack of alternating layers is etched to the size of n-type nanosheet 110 using one of sidewall image transfer (SIT) process, extreme ultraviolet (EUV) lithography, directed self-assembly (DSA) patterning via chemical epitaxy, or self-aligned custom. In other implementations, the alternating layers are grown on top of a silicon-on-insulator (SOI) oxide layer, followed by the etching step. The given conductive layers of alternating silicon germanium semiconductor epitaxial growth layers and silicon semiconductor epitaxial growth layers are selected to preserve for forming gate regions. Thereafter, any semiconductor layers other than the selected layers are removed. N-type TSV local interconnects 112 are formed in locations of later placed connections to micro-TSVs.

[0071] Turning now to Figures 6 to 12 , a generalized block diagram of a top view of a standard cell layout 600 - standard cell layout 1200 (or layout 600 - layout 1200) is shown. The numbering of the contacts (or vias), materials, and structures previously described are the same. In layout 600, n-type source and drain regions are formed. In one implementation, the n-type source and drain regions are phosphorus doped epitaxial grown silicon. Thereafter, n-type local interconnects 114 are formed. In some implementations, n-type local interconnects 114 include tungsten, cobalt, ruthenium, or molybdenum.

[0072] A gate metal material 116 is deposited, followed by a chemical mechanical planarization (CMP) step to polish n-type gate metal 116. In various implementations, titanium nitride (TiN) is used for gate metal 116. Gate metal 116 is disposed in a 360 degree manner fully encircling n-type nanosheet 110. An interlayer dielectric (ILD) oxide layer is deposited around the gate regions. The label "BLT" corresponds to the BLT 440 signal of memory bit cell 400 (of FIG. 4). Similarly, the label "BLC" corresponds to the BLC 442 signal of memory bit cell 400 (of FIG. 4). In addition, layout 604 includes n-type TSV local interconnects 112 along the length of the entire side of layout 604, while layout 602 includes n-type TSV local interconnects 112 in the corners of layout 602. Although not shown, n-type local interconnects 114 overlie n-type TSV local interconnects 112. Figure 4 Figure 4

[0073] ​​Layout 700 has contact 120 (n-type local interconnect connected with p-type local interconnect) formed and gate contact 122 formed. However, only two gate contacts 122 will be connected to p-type gate 136, such as for n-type gate of a pull-down device (transistor). Layout 800 has p-type channel 130 (or p-type nanosheet 130) formed, followed by p-type local interconnect 134. Etching of oxide layer and deposition of corresponding material is performed to form these p-type local interconnect 134 layers. Layout 900 has p-type gate 136 formed. For example, n-type gate metal material 136 is deposited, followed by a chemical mechanical planarization (CMP) step to polish the p-type gate metal 136. In various implementations, titanium nitride (TiN) is used for p-type gate metal 136. Layout 900 also has contact 140 formed. The label "PD" indicates a pull-down n-type device, such as N1 406 and N2 416 devices of memory bitcell 400 (FIG. 1). The label "PU" indicates a pull-up p-type device, such as P1 402 and P2 412 devices of memory bitcell 400 (FIG. 1). Figure 4 Figure 4

[0074] Layout 1000 has contact 142 formed. For symmetric layout 1002, the non-overlapping distance between p-type active layer and n-type active layer is shown as width (or offset distance) 106. This width 106 is between the p-type active layer of a p-type pull-up device and the n-type active layer of an n-type pass-gate device. Examples of these devices are p-type device P2 412 and n-type device N4 422 of memory bitcell 400 (FIG. 1). Figure 4 Figure 4

[0075] ​​​​Width 106 includes the width of at least a source contact or a drain contact, such as contact 120 used as a drain contact between a p-type pull-up device and an n-type pass-gate device. Although this node can also be a source region of an n-type pass-gate device when this node has a logical low value and signal BLC has a logical high value. In some implementations, width 106 also includes another minimum distance between p-type nanosheet 130 and drain contact 120, which is determined by design rules and checks of a particular semiconductor fabrication process used to manufacture TFET 104. Between the drain node of the p-type pull-up device and the n-type pass-gate device is drain contact 120 in contact with an area of p-type local interconnect 134 of the p-type pull-up device. This area of p-type local interconnect layer 134 is not physically adjacent to p-type nanosheet 130 (p-type active layer) of the p-type pull-up device. Because of this placement of drain contact 120, drain contact 120 provides a lower resistance contact between p-type local interconnect 134 and n-type local interconnect 114.

[0076] In asymmetric layout 1004, the placement of the p-type pull-up device is to the right of the n-type pull-down device. The n-type pass-gate device is at the far left of layout 1004. In asymmetric layout 1004, the p-type pull-up device is not adjacent to the n-type pass-gate device compared to symmetric layout 1002. Similar to symmetric layout 1002, drain contact 120 of asymmetric layout 1004 is in contact with an area of p-type local interconnect 134, and this area is not physically adjacent to p-type nanosheet 130 (p-type active layer) of the p-type pull-up device. Because of this placement of drain contact 120, drain contact 120 provides a lower resistance contact between p-type local interconnect 134 and n-type local interconnect 114.

[0077] The non-overlapping distance between p-type nanosheet 130 of the p-type pull-up device and n-type nanosheet 110 of the adjacent (although vertically below) n-type pull-down device is less than width (or offset distance) 106 compared to symmetric layout 1002. P-type local interconnect 134 providing the drain node of the p-type pull-up device is extended left past n-type nanosheet 110 of the n-type pull-down device to provide a location for drain contact 120. This drain contact 120 of asymmetric layout 1004 is not physically between p-type nanosheet 130 of the p-type pull-up device and n-type nanosheet of the n-type pull-down device compared to symmetric layout 1002. Similar to symmetric layout 1002, gate contact 122 used by p-type gate 136 of the p-type pull-up device and n-type gate 116 of the n-type pull-down device partially overlaps n-type nanosheet 110 of the n-type pull-down device, but does not overlap p-type nanosheet 130 of the p-type pull-up device.

[0078] In layout 1100, a front-side M0 layer 150 is formed to complete the signal connections for creating 6T random access data storage of memory bit cells. The marker "WL" corresponds to ( Figure 4 The WL 430 signal of memory bit cell 400. Continuing the signal connection, layout 1200 has a via 160, which is formed to connect the front M0 layer 150 to a metal layer (or metal 1 or metal 1 or M1) 170. Then, layer M1 170 is deposited to create even further connections for the bit cell.

[0079] Now go to Figure 13 This diagram illustrates a general block diagram of a specific embodiment of memory bank 1300. In various embodiments, the memory is organized into multiple memory banks, and the memory macroblock includes a left memory bank and a right memory bank. In some embodiments, memory bank 1300 is one of the left or right memory banks of a memory macroblock. Although "left" and "right" are used to describe memory banks, other notations such as "top memory bank" and "bottom memory bank" may be used. As shown, memory bank 1300 includes arrays 1312A-1312B, row decoders 1320A-1320B, sense amplifiers 1330A-1330B between arrays 1312A-1312B, read and write timing control logic 1340A-1340B, and read latches and write latches in block 1350. It should be noted that in some embodiments, multiple memory banks are accessed simultaneously in the same clock cycle or the same pipeline stage. Access includes either read access or write access. In this specific implementation, the memory address decoder selects the corresponding memory bank to be accessed.

[0080] In various embodiments, each of blocks 1312A-1312B, 1320A-1320B, 1330A-1330B, 1340A-1340B, and 1350 in memory bank 1300 is communicatively coupled to another block. For example, a direct connection is used, where routing occurs through another block. Alternatively, segmented signal transmission is performed in an intermediate block. In various embodiments, each of arrays 1312A-1312B includes a plurality of memory bit cells 1360 (or bit cells 1360) arranged in a tiled format. Here, rows are aligned with the tracks of the word lines used for the array, such as in the illustrated embodiment, in the vertical direction. Columns are aligned with the tracks of the bit lines used for the array, such as in the illustrated embodiment, in the horizontal direction. In other embodiments, rows and columns are rotated and have different orientations.

[0081] The row decoders and word line drivers in blocks 1312A-1312B receive address information corresponding to the access request. For example, each of blocks 1312A-1312B receives information provided by the access request address 1370. Each of blocks 1312A-1312B selects a specific row or entry from among multiple rows in one of the associated rows in arrays 1312A-1312B. In some implementations, blocks 1312A-1312B use the index portion of address 1370 to select a given row or entry in one of the associated rows in arrays 1312A-1312B. Each row or entry stores one or more memory lines.

[0082] In the illustrated embodiment, rows or entries in arrays 1312A-1312B are arranged in a vertical orientation. However, in other embodiments, a horizontal orientation is used to store memory lines. For write access requests, write latches are located in block 1350. Write data is driven into arrays 1312A-1312B. Timing control logic 1340A-1340B updates the write latches in block 1350 with new data and sets the write word line driver logic. Write data is written to the row of bit cells selected by one of the associated units in blocks 1312A-1312B. In some embodiments, a precharge circuit is included in block 1350.

[0083] For read access requests, block 1350 is used to precharge the read bit lines routed to arrays 1312A-1312B. Timing circuitry in blocks 1340A-1340B is used to precharge and set the sense amplifiers in blocks 1330A-1330B. Timing circuitry 1340A-1340B sets the read word line driver logic. One of the row decoders 1320A-1320B selects a row to read data, which will be provided on the read bit lines sensed by the sense amplifiers. A read latch captures the read data.

[0084] In various specific implementations, memory bit cell 1360 (or bit cell 1360) utilizes six transistors (6T) for random access data storage. For example, data storage uses a back-to-back configuration of two inverters (cross-coupled inverters). In various specific implementations, memory bit cell 1360 (or bit cell 1360) utilizes ( Figure 4 The data storage circuit configuration of the bit unit 400 and ( Figures 6 to 12 (Standard cell layout 600 - Standard cell layout 1200 and ( Figures 14 to 23 The layout technology of standard cell layout 1100-standard cell layout 2300.

[0085] Now go to Figures 14 to 23, showing a generalized block diagram of a top view of the standard cell layout 1100 - standard cell layout 2300 (or layout 1100 - layout 2300). The numbering of the previously described contacts (or vias), materials, and structures is the same. Additionally, the previously described labels use the same names. In layout 1400, the n-type nanosheet 110 is created, the n-type TSV local interconnect 112 is formed in the location of the micro TSV's connection later placed, and the n-type local interconnect 114 is formed. Although not shown, the n-type local interconnect 114 covers the n-type TSV local interconnect 112. In layout 1500, the n-type gate 116 is deposited, and the gate contact 120 is formed.

[0086] Layout 1600 has the gate contact 122 formed. However, only two gate contacts 122 will connect to the p-type gate 136, such as an n-type gate for a pull-down device (transistor). Layout 1700 has the p-type channel 130 (or p-type nanosheet 130) formed. Next, the p-type local interconnect 134 is formed in layout 1800. Layout 1800 also has the p-type gate 136 formed.

[0087] Layout 1900 has the contact 140 formed. Layout 2000 has the contact 142 formed. In layout 2100, the frontside M0 layer 150 is formed to complete the signal connections creating the 6T random access data storage of the memory bit cell. Continuing the signal connections, layout 2200 has the via 160 formed to connect the frontside M0 layer 150 to the metal one layer (or metal 1 or metal 1 or Ml) 170. In layout 2300, the Ml 170 layer is then deposited for creating even further connections for the bit cell. The Ml 170 layer provides connections for the word line (WL) signals and the power reference levels (VDD and VSS). In comparison to the symmetric layout 1202 and the asymmetric layout 1204, the layout 2300 does not use the Ml 170 layer for the bit line (BLT and BLC). As a result, the dimensions of the on-die area of the layout 2300 are different than either of the layout 1202 and the layout 1204. For example, a first height of the layout 1202 that contributes to the on-die area of this memory bit cell layout 1202 is less than a second height of the layout 2300 that contributes to the on-die area of this memory bit cell layout 2300. A first width of the layout 1202 that contributes to the on-die area of this memory bit cell layout 1202 is greater than a second width of the layout 2300 that contributes to the on-die area of this memory bit cell layout 2300. Similar height and width relationships exist between the layout 1204 and the layout 2300 as well.

[0088] Layouts 500 - Layout 1200 and Layouts 1400 - Layout 2300 provide standard cell layouts that include the benefits of TFETs 104. For example, n-channel 110 (n-nanoplate) and p-channel 130 (p-nanoplate) are displaced from each other. Semiconductor fabrication is simplified, resulting in higher yield. Less complex selective etch bias processes can be used, and less material is used compared to complementary FETs and XFETs 102. Width 106 shows this displacement. Gate terminals of p- and n- devices of the TFET form a T-shape, rather than an X-shape. P-channel local interconnect 134 extends beyond p-channel 130 (p-active layer) before contact 120 is placed for connection to n-channel local interconnect 114. Figure 2 Placement of contact 120 on p-channel local interconnect 134 in Layout 200 illustrates one example of this placement of drain contacts. When both p-gate 136 and n-gate 116 overlap, the contact for connecting p-channel local interconnect 134 to n-gate 116 has been eliminated and replaced by contact 120. TFETs 104 have lower resistance and capacitance compared to complementary FETs and XFETs 102. The displacement of n-channel 110 and p-channel 130 that creates width 106 also increases heat dissipation.

[0089] Referring now to Figure 24 , a generalized block diagram of a method 2400 for efficiently creating a layout of a memory bitcell is shown. The steps in the implementation are shown in sequential order for purposes of discussion. However, in other implementations, some steps occur in a different order than shown, some steps are performed concurrently, some steps are combined with other steps, and some steps are not present.

[0090] A semiconductor fabrication process forms transistors with orthogonal orientation in a vertical stack (block 2402). The process forms a cross-coupled transistor in a bitcell with a single gate contact that overlaps only one of the two active layers of the cross-coupled inverter (block 2404). Figure 2 Placement of contact 122 in Layout 200 illustrates one example of this placement of gate contacts. The process forms a drain contact between the drain nodes of two transistors that contacts a region of a local interconnect layer of a particular transistor of the two transistors. This region of the local interconnect layer is not physically adjacent to the active layer of the particular transistor (block 2406). Figure 2 Placement of contact 120 on p-channel local interconnect 134 in Layout 200 illustrates one example of this placement of drain contacts. The process forms a memory bitcell using a cross-coupled inverter (block 2408).

[0091] The memory bitcells of an array are arranged as a plurality of rows and a plurality of columns, storing data (block 2410). In various implementations, the value of the stored data is held by a data storage circuit within the memory bitcell. Further, the value of the stored data is updated by a write operation. If the array does not receive a read operation (the "No" branch of conditional block 2412), each of the bitcells maintains the stored binary value (block 2414). For example, each of the bitcells includes a latch element to store the binary value until the binary value is modified by a write access operation. If the array receives a read operation (the "Yes" branch of conditional block 2412), the bitcells in the row targeted by the read operation transfer the data stored in the bitcells to corresponding read bitlines (2416).

[0092] Referring to Figure 25 , a generalized block diagram of a computing system 2500 is shown. The computing system 2500 includes a processor 2510 and a memory 2530. Interfaces such as memory controllers, buses or communication fabric, one or more phase-locked loops (PLLs) and other clock generation circuitry, power management units, and the like are not shown for ease of illustration. It will be appreciated that, in other implementations, the computing system 2500 includes one or more of other processors of the same type or different types as the processor 2510, one or more peripheral devices, network interfaces, one or more other memory devices, and the like. In some implementations, the functionality of the computing system 2500 is incorporated on a system on a chip (SoC). In other implementations, the functionality of the computing system 2500 is incorporated on a peripheral card that plugs into a motherboard. The computing system 2500 is used in any of a variety of computing devices such as a desktop computer, a tablet computer, a laptop computer, a smart phone, a smart watch, a game console, a personal assistant device, and the like.

[0093] The processor 2510 includes hardware such as circuitry. For example, the processor 2510 includes at least one integrated circuit 2520 that implements memory bitcells 2522 instantiated in one or more memory arrays using TFETs. In some implementations, the bitcells 2522 use the circuitry of the bitcell 400 of FIG. 4 and the layouts 500-Layout 1200 of FIGS. 5-12 and the layouts 1300-Layout 1400 of FIGS. 13-14. Figure 4 Figures 5 to 12 Figures 14 to 23 ​​one or more of layouts 1400-2300. In various implementations, processor 2510 includes one or more processing units. In some implementations, each of the processing units includes one or more processor cores capable of general purpose data processing and an associated cache subsystem. In such implementations, processor 2510 is a central processing unit (CPU). In another implementation, the processing cores are compute units, each having a highly parallel data micro-architecture with multiple parallel execution lanes and associated data storage buffers. In such implementations, processor 2510 is a graphics processing unit (GPU), a digital signal processor (DSP), or the like.

[0094] In some implementations, memory 2530 includes one or more of a hard disk drive, a solid state disk, other types of flash memory, a portable solid state drive, a tape drive, or the like. Memory 2530 stores an operating system (OS) 2532, one or more application programs represented by code 2534, and at least source data 2536. Memory 2530 can also store intermediate and final result data generated by processor 2510 in executing a particular application of code 2534. Although a single instance of operating system 2532 and code 2534 and source data 2536 are shown, another number of these software components are stored in memory 2530 in other implementations. Operating system 2532 includes instructions for initiating startup of processor 2510, assigning tasks to hardware circuits, managing resources of computing system 2500, and hosting one or more virtual environments.

[0095] Each of processor 2510 and memory 2530 includes an interface unit for communicating with each other and any other hardware components included in computing system 2500. The interface units include queues for servicing memory requests and memory responses and control circuitry for communicating with each other based on a particular communication protocol. The communication protocol determines various parameters, such as power supply voltage levels, power performance states that determine operating power supply voltages and operating clock frequencies, data rates, one or more burst modes, and the like.

[0096] It should be noted that one or more of the above-described implementations include software. In such an implementation, the program instructions implementing the methods and / or mechanisms are conveyed or stored on a computer readable medium in a machine-readable format. Numerous types of media which are configured to store program instructions include hard- disk, floppy disk, magnetic tape, CD-ROM, DVD, flash memory, programmable ROM (PROM), random access memory (RAM), and various other forms of volatile or non-volatile storage. Generally speaking, a computer accessible storage medium includes any medium that can be accessed by a computer during use to provide instructions and / or data to the computer. For example, a computer accessible storage medium includes storage media such as magnetic or optical media, e.g., disk (fixed or removable), cassette tape, CD-ROM, or DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-ray, and any other medium which can be used to store program instructions. Storage media also include volatile and non-volatile storage media, such as RAM (e.g., synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2, DDR3, etc.) SDRAM, low power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM (RDRAM), static RAM (SRAM), etc.), ROM, flash memory, non-volatile memory (e.g., flash memory), and the like. Storage media include microelectromechanical systems (MEMS), and storage media that can be accessed via a communication medium (e.g., a network and / or a wireless link).

[0097] Additionally, in various implementations, the program instructions include a behavioral-level description or register-transfer level (RTL) description of the hardware functionality in a high-level programming language such as C or a hardware description language (HDL) such as Verilog, VHDL, or database format such as GDS II stream format (GDSII). In some cases, the description is read by a synthesis tool, which synthesizes the description to produce a netlist comprising a list of gates from a synthesis library. The netlist includes a gate-level description of hardware logic of the functional units of a system. The netlist is then placed and routed to produce a data set describing geometric shapes to be applied to masks. The masks are then used in various semiconductor fabrication steps to produce a semiconductor circuit or circuits that correspond to the system. Alternatively, the instructions on the computer-accessible storage medium are the netlist (with or without the synthesis library) or the data set, as desired. and Mentor such vendors for the purpose of emulation.

[0098] While the above implementations have been described in considerable detail, many variations and modifications will become apparent to those skilled in the art once they read the above disclosure. It is therefore intended that the following claims be construed as including all such variations and modifications as fall within the scope of the above disclosure.

Claims

1. An integrated circuit, the integrated circuit comprising: The memory bit cells of the first array are arranged in multiple rows and multiple columns. The first memory bit cell of the first array includes a gate contact between the first gate of the first transistor and the second gate of the second transistor, wherein the gate contact overlaps with only one of the first active layer of the first transistor and the second active layer of the second transistor.

2. The integrated circuit according to claim 1, wherein: Each of the first transistor and the second transistor is a vertical gate all-around (GAA) device that utilizes multiple nanosheets as channels; and wherein, in response to receiving an indication of receiving a first read operation targeting a row of the multiple rows that includes the first memory bit cell, the first array is configured to transfer data stored in the first memory bit cell.

3. The integrated circuit according to claim 2, wherein: The second active layer includes a channel configured to conduct current in a direction orthogonal to the current flow direction in the channel of the first active layer; The first active layer and the second active layer do not overlap; and The distance between the first active layer and the second active layer is at least the width of the source or drain contact.

4. The integrated circuit according to claim 3, wherein: The first memory bit cell includes a drain contact that contacts a region of the partial interconnect layer of the second transistor between the drain nodes of the first and second transistors; and The region of the local interconnect layer is not physically adjacent to the second active layer of the second transistor.

5. The integrated circuit of claim 3, wherein the first memory bit cell comprises an asymmetrical layout with respect to the placement of transistors and signal nodes within the first memory bit cell.

6. The integrated circuit of claim 3, further comprising memory bit cells of a second array, the memory bit cells of the second array comprising a plurality of rows and a plurality of columns, wherein the highest metal layer for signal routing in the second memory bit cells of the second array is a metal zero layer.

7. The integrated circuit according to claim 6, wherein: The height of the first memory bit cell is less than the height of the second memory bit cell; and The width of the first memory bit cell is greater than the width of the second memory bit cell.

8. A method, the method comprising: A first memory bit cell forming a memory bit cell of a first array, wherein the first memory bit cell includes a gate contact between a first gate of a first transistor and a second gate of a second transistor, the gate contact overlapping only one of the first active layer of the first transistor and the second active layer of the second transistor; And the memory bit cells of the first array, which will be arranged in multiple rows and multiple columns, are placed in the integrated circuit.

9. The method of claim 8, the method further comprising forming the first memory bit cell such that: Each of the first transistor and the second transistor is a vertical gate all-around (GAA) device that utilizes multiple nanosheets as channels; and in response to receiving an instruction for a first read operation targeting a row of the multiple rows that includes the first memory bit cell, data stored in the first memory bit is transferred by the memory bit cells of the first array.

10. The method of claim 9, the method further comprising forming the first memory bit cell such that: The second active layer includes a channel configured to conduct current in a direction orthogonal to the current flow direction in the channel of the first active layer; The first active layer and the second active layer do not overlap; and The distance between the first active layer and the second active layer is at least the width of the source or drain contact.

11. The method of claim 10, the method further comprising forming the first memory bit cell such that: The first memory bit cell includes a drain contact that contacts a region of the partial interconnect layer of the second transistor between the drain nodes of the first and second transistors; and The region of the local interconnect layer is not physically adjacent to the second active layer of the second transistor.

12. The method of claim 10, the method further comprising forming the first memory bit cell such that the first memory bit cell includes an asymmetric layout with respect to the placement of transistors and signals within the first memory bit cell.

13. The method of claim 10, the method further comprising forming memory bit cells of a second array, the memory bit cells of the second array comprising a plurality of rows and a plurality of columns, wherein the highest metal layer for signal routing in the second memory bit cells of the second array is a metal zero layer.

14. The method of claim 13, the method further comprising forming the second memory bit cell such that: The height of the first memory bit cell is less than the height of the second memory bit cell; and The width of the first memory bit cell is greater than the width of the second memory bit cell.

15. A computing system, the computing system comprising: An integrated circuit, configured to execute instructions using source data, wherein the integrated circuit includes: The memory bit cells of the first array are arranged in multiple rows and multiple columns. The first memory bit cell of the first array includes a gate contact between the first gate of the first transistor and the second gate of the second transistor, wherein the gate contact overlaps with only one of the first active layer of the first transistor and the second active layer of the second transistor.

16. The computing system according to claim 15, wherein: Each of the first transistor and the second transistor is a vertical gate all-around (GAA) device that utilizes multiple nanosheets as channels; and wherein, in response to receiving an indication of receiving a first read operation targeting a row of the multiple rows that includes the first memory bit cell, the first array is configured to transfer data stored in the first memory bit cell.

17. The computing system according to claim 16, wherein: The second active layer includes a channel configured to conduct current in a direction orthogonal to the current flow direction in the channel of the first active layer; The first active layer and the second active layer do not overlap; and The distance between the first active layer and the second active layer is at least the width of the source or drain contact.

18. The computing system according to claim 17, wherein: The first memory bit cell includes a drain contact between the drain nodes of the first transistor and the second transistor, the drain contact contacting a region of a local interconnect layer of the second transistor; and The region of the local interconnect layer is not physically adjacent to the second active layer of the second transistor.

19. The computing system of claim 17, wherein the first memory bit cell includes an asymmetric layout with respect to the placement of transistors and signals within the first memory bit cell.

20. The computing system of claim 17, further comprising memory bit cells of a second array, the memory bit cells of the second array comprising a plurality of rows and a plurality of columns, wherein the highest metal layer for signal routing in the second memory bit cells of the second array is a metal zero layer.

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