High-frequency ultrasonic echo protection circuit based on MOSFET (Metal Oxide Semiconductor Field Effect Transistor) architecture

Abstract

The invention provides a high-frequency ultrasonic echo protection circuit based on an MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) framework. The high-frequency ultrasonic echo protection circuit comprises an MOSFET cascade protection network, a high-speed bidirectional amplitude limiting module and a transient overvoltage cooperative protection module. The T / R switch based on the MOSFET architecture can effectively clamp a high-frequency high-voltage excitation pulse signal to a low level, and an echo receiving circuit is prevented from being damaged. The T / R switch based on the MOSFET architecture does not need an additional power supply circuit, the circuit design and use are simpler and more convenient, and the complexity of a circuit system is reduced. A new circuit protection mode is provided for the high-frequency ultrasonic imaging circuit system, and the high-frequency ultrasonic imaging circuit system has good economic value and practicability.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of high-frequency ultrasonic echo protection circuit system, and particularly relates to a high-frequency ultrasonic echo protection circuit based on a MOSFET architecture. BACKGROUND

[0002] As a non-invasive and real-time diagnostic tool, ultrasonic imaging technology has been widely used in medical imaging, industrial detection and other fields. When imaging with ultrasonic waves, the higher the frequency of the ultrasonic waves, the higher the imaging resolution, and more image details can be obtained. However, the higher the frequency of the ultrasonic waves, the more serious the attenuation of the ultrasonic waves when propagating in an object, resulting in a shallower penetration depth. High-frequency ultrasonic imaging (>50MHz) can bring very excellent image resolution due to its extremely high frequency, and thus plays an important role in industrial non-destructive testing and biomedical fields.

[0003] In the field of industrial non-destructive testing, ultrahigh-frequency ultrasonic waves are mainly used for observing the microstructure of the surface and subsurface layer and the interior of new materials and for detecting surface cracks and internal defects of microelectronic devices, ceramics, aerospace devices, artificial hearts and other devices. For example, ultrasonic microscopy (UM) as an important detection device for microelectronic devices and key materials usually uses ultrasonic frequencies above 100MHz, which can achieve imaging with a resolution of microns or even nanometers. In the medical field, ultrahigh-frequency ultrasonic waves are mainly used for imaging of superficial regions, including oral cavity, skin, eye and blood vessels. For example, intravascular ultrasound (IVUS) usually uses frequencies of 40-80MHz, which can provide a resolution of about 100 microns.

[0004] With the increase of ultrasonic frequency, the design of ultrasonic hardware system faces higher technical requirements. In high-frequency and ultrahigh-frequency ultrasonic imaging systems, the higher the frequency of ultrasonic waves, the more serious the attenuation of the ultrasonic waves when propagating in an object. Therefore, it is very important to reduce the attenuation of echoes when passing through an echo protection circuit.

[0005] In an ultrasonic imaging device, since a transducer is shared for transmission and reception, a high-power ultrasonic transmission circuit is usually connected to a high-sensitivity reception circuit. In order to avoid damage to the reception circuit by high-voltage transmission pulses, an isolation protection circuit (i.e., a transmission / reception switch, referred to as a T / R switch) is provided at the front end of an ultrasonic preamplifier. The T / R switch needs to meet two key requirements:

[0006] (1) Large amplitude power pulse signals cannot pass through.

[0007] (2) Small amplitude ultrasonic echo signals are allowed to pass through with the lowest attenuation.

[0008] At present, the common T / R switch implementation mainly includes: (1) Bridge diode switch mode, which uses diode conduction / cutoff to realize isolation, without special control, such as integrated chip TX810. (2) MOSFET / CMOS two-terminal voltage-sensitive fast switch mode, which is often used in low-voltage or integrated ultrasonic systems, has fast response speed and simple control, such as integrated chip MD0101. The MD0101 switch is normally closed, but when the voltage across the device exceeds ±1V, the switch will be disconnected within about 20ns. When open, the switch can withstand a voltage of up to ±100V. In the open state, about 200μA current passes through the switch to detect whether the high voltage still exists. Once the transmitter output no longer applies high voltage, the switch will return to the closed state. The above two modes both face the problem of large attenuation of high-frequency ultrasonic echo, and the absolute signal amplitude of high-frequency echo signal is lower, and the T / R switch with large attenuation will further reduce the signal-to-noise ratio of the echo signal, thereby reducing the ultrasonic image quality and imaging depth. In addition, the above two modes also face the problem of difficulty in clamping high-frequency ultrasonic excitation signal. For high-frequency ultrasonic excitation pulse signal, the pulse duration is very short, which causes the high-voltage signal to easily pass through the T / R switch, affecting the receiving circuit. (3) Use mechanical relay, which can obtain lower insertion loss and smaller echo attenuation, but has slow response speed up to ms level, which is difficult to meet the requirements of high pulse repetition frequency of ultrasonic.

[0009] Therefore, for the T / R switch module in the high-frequency ultrasonic echo circuit, it is necessary to design a T / R switch implementation with low attenuation, good clamping effect and fast response speed. SUMMARY

[0010] In order to achieve the above-mentioned purposes and other advantages of the present application, the purpose of the present application is to provide a high-frequency ultrasonic echo protection circuit based on MOSFET architecture, which comprises a MOSFET cascade protection network, a high-speed bidirectional limiting module and a transient overvoltage cooperative protection module.

[0011] After the bipolar high-frequency high-voltage pulse excitation signal reaches the signal input end of the MOSFET cascade protection network, the positive and negative polarity pulses are transmitted through the MOSFET cascade protection network and are clamped by the high-speed bidirectional limiting module and the transient overvoltage cooperative protection module.

[0012] The high-frequency echo small signal passes through the signal input end of the MOSFET cascade protection network to its signal output end.

[0013] Further, the topology of the MOSFET cascade protection network is a mirror-symmetry three-stage cascade structure composed of N-channel enhancement-mode MOSFETs, which is composed of six separate N-channel enhancement-mode MOSFETs; wherein the three-stage cascade structure is used to limit the passage of positive high-voltage pulses, and the mirror-symmetry three-stage cascade structure is used to limit the passage of negative high-voltage pulses.

[0014] In the three-stage cascade structure, the first stage is the interconnection of the gate and drain of the first NMOS tube as the signal input end, the second stage is the interconnection of the gate and drain of the second NMOS tube connected to the source of the first NMOS tube, the third stage is the interconnection of the gate and drain of the third NMOS tube connected to the source of the second NMOS tube, and the source of the third NMOS tube is as the signal output end.

[0015] In the mirror-symmetry three-stage cascade structure, the first stage is the source of the fourth NMOS tube connected to the signal input end, the gate and drain of the fourth NMOS tube are interconnected and connected to the source of the fifth NMOS tube, the second stage is the gate and drain of the fifth NMOS tube interconnected and connected to the source of the sixth NMOS tube, and the third stage is the gate and drain of the sixth NMOS tube interconnected and connected to the signal output end.

[0016] Further, the N-channel enhancement-mode MOSFET uses IRF5802TRPBF silicon-based MOSFET.

[0017] Further, the MOSFET cascade protection network adopts a two-stage symmetrical cascade structure composed of N-channel depletion-mode MOSFETs, which is composed of two N-channel depletion-mode MOSFETs.

[0018] The first stage structure has the drain of the seventh NMOS tube as the signal input end, the second stage structure has the gate and source of the eighth NMOS tube interconnected and connected to the gate and source of the seventh NMOS tube, and the drain of the eighth NMOS tube as the signal output end.

[0019] Further, the N-channel depletion-mode MOSFET uses BSS169H6327 N-channel MOSFET.

[0020] Further, the high-speed bidirectional limiting module is composed of two high-speed switching diodes in reverse parallel connection, the anode of the first high-speed switching diode and the cathode of the second high-speed switching diode are commonly connected to the signal output end, and the cathode of the first high-speed switching diode and the anode of the second high-speed switching diode are commonly connected to the system ground.

[0021] Further, the high-speed bidirectional limiting module uses BAV99 high-speed switching diode pair.

[0022] Further, the transient overvoltage cooperative protection module is composed of a bidirectional transient voltage suppressor, and the bidirectional transient voltage suppressor is connected in parallel with the high-speed bidirectional limiting module, and the two cooperate to clamp the high-frequency high-voltage pulse excitation signal.

[0023] Further, the bidirectional transient voltage suppressor adopts SP0115-01 ETG bidirectional TVS.

[0024] Further, when the topology of the MOSFET cascade protection network is a mirror-symmetrical three-stage cascade structure composed of N-channel enhancement-mode MOSFETs, after a bipolar high-frequency high-voltage pulse excitation signal reaches the signal input end, in the positive half cycle, the positive polarity pulse is transmitted through the first NMOS tube, the second NMOS tube and the third NMOS tube in the structure, and is clamped by the first high-speed switching diode and the bidirectional transient voltage suppressor; similarly, in the negative half cycle, the negative polarity pulse is transmitted through the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube in the structure, and is clamped by the second high-speed switching diode and the bidirectional transient voltage suppressor.

[0025] After a high-frequency echo small signal reaches the signal input end, the equivalent circuit model of the mirror-symmetrical three-stage cascade structure composed of N-channel enhancement-mode MOSFETs is close to a high-pass filter, and the high-frequency echo small signal can reach the signal output end.

[0026] Further, when the MOSFET cascade protection network adopts a two-stage symmetrical cascade structure composed of N-channel depletion-mode MOSFETs, after a bipolar high-frequency high-voltage pulse excitation signal reaches the signal input end, in the positive half cycle, the positive polarity pulse is transmitted through the drain-source low-impedance channel of the seventh NMOS tube and the parasitic diode of the eighth NMOS tube in the structure, and is clamped by the first high-speed switching diode and the bidirectional transient voltage suppressor; similarly, in the negative half cycle, the negative polarity pulse is transmitted through the parasitic diode of the seventh NMOS tube and the drain-source low-impedance channel of the eighth NMOS tube in the structure, and is clamped by the second high-speed switching diode and the bidirectional transient voltage suppressor.

[0027] After a high-frequency echo small signal reaches the signal input end, the gate-source voltage of the two-stage symmetrical cascade structure composed of N-channel depletion-mode MOSFETs is equal to 0, the drain-source is turned on, and the amplitude of the high-frequency echo small signal also does not turn on the body diode of the seventh NMOS tube and the eighth NMOS tube, and the high-frequency echo small signal can reach the signal output end.

[0028] Compared with the prior art, the beneficial effects of the present application are:

[0029] The T / R switch based on the MOSFET architecture designed by the application can effectively reduce the insertion loss of high-frequency echo small signals, and effectively improve the signal-to-noise ratio in high-frequency ultrasonic imaging.

[0030] The T / R switch based on the MOSFET architecture designed by the application can effectively clamp the high-frequency high-voltage excitation pulse signal to a lower level, preventing damage to the echo receiving circuit.

[0031] The T / R switch based on the MOSFET architecture designed by the application does not require an additional power supply circuit, and the circuit design and use are more convenient, and the circuit system complexity is reduced.

[0032] The application provides a new protection circuit method for high-frequency ultrasonic imaging circuit systems, and has good economic value and practicability.

[0033] The above description is only a summary of the technical solutions of the application, in order to more clearly understand the technical means of the application, and can be implemented according to the content of the specification, the following is a preferred embodiment of the application and the accompanying drawings are described in detail. The specific embodiments of the application are given in detail by the following examples and their accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0034] The drawings described herein are used to provide further understanding of the application, and form a part of the application, the schematic embodiments of the application and their description are used to explain the application, and do not constitute improper limitation on the application. In the drawings:

[0035] Figure 1 It is a high-frequency ultrasonic echo protection circuit principle diagram based on MOSFET architecture;

[0036] Figure 2 It is a topology structure diagram of MOSFET cascade protection network;

[0037] Figure 3 It is another topology structure diagram of MOSFET cascade protection network;

[0038] Figure 4 It is a T / R switch insertion loss comparison diagram. DETAILED DESCRIPTION

[0039] Next, the application will be further described in combination with the drawings and specific embodiments. Obviously, the described embodiments are part of the embodiments of the application, rather than all the embodiments. It should be noted that the following described embodiments or technical features can be combined to form new embodiments without conflict.

[0040] All other embodiments obtained by a person of ordinary skill in the art without creative labor based on the embodiments of the present application fall within the scope of protection of the present application.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present application belongs. The terminology used in the description of the present application herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application.

[0042] The present application designs a T / R switch which can realize low attenuation of high-frequency echo and good clamping effect of high-voltage excitation signal. The specific scheme is as follows:

[0043] Embodiment 1

[0044] A high-frequency ultrasonic echo protection circuit based on MOSFET architecture, as shown in Figures 1-3 , includes a MOSFET cascade protection network, a high-speed bidirectional limiting module, and a transient overvoltage cooperative protection module.

[0045] After the bipolar high-frequency high-voltage pulse excitation signal reaches the signal input end of the MOSFET cascade protection network, the positive and negative polarity pulses are transmitted through the MOSFET cascade protection network and are clamped by the high-speed bidirectional limiting module and the transient overvoltage cooperative protection module.

[0046] High-frequency echo small signals pass through the signal input end of the MOSFET cascade protection network to its signal output end.

[0047] In some embodiments, as shown in Figure 2 , the topology of the MOSFET cascade protection network is a mirror-symmetric three-stage cascade structure composed of N-channel enhancement-mode MOFFETs, which is composed of six discrete N-channel enhancement-mode MOFFETs (NMOS1-NMOS6); wherein the three-stage cascade structure is used to limit the passage of positive high-voltage pulses, and the mirror-symmetric three-stage cascade structure is used to limit the passage of negative high-voltage pulses.

[0048] In the three-stage cascade structure, the first stage is the interconnection of the gate and drain of the first NMOS tube (NMOS1) as the signal input end (TX_IN1), the second stage is the interconnection of the gate and drain of the second NMOS tube (NMOS2) connected to the source of the first NMOS tube, and the third stage is the interconnection of the gate and drain of the third NMOS tube (NMOS3) connected to the source of the second NMOS tube, and the source of the third NMOS tube is as the signal output end (RX_OUT1).

[0049] In the mirror-symmetric three-stage cascaded structure, the first stage is where the source of the fourth NMOS transistor (NMOS4) is connected to the signal input terminal (TX_IN1), and the gate and drain of the fourth NMOS transistor are interconnected and then connected to the source of the fifth NMOS transistor (NMOS5). The second stage is where the gate and drain of the fifth NMOS transistor are interconnected and then connected to the source of the sixth NMOS transistor (NMOS6). The third stage is where the gate and drain of the sixth NMOS transistor are interconnected and then connected to the signal output terminal (RX_OUT1).

[0050] The advantage of this topology is that it can clamp high-voltage pulse excitation signals with higher voltage amplitudes by using a multi-stage structure.

[0051] Furthermore, the N-channel enhancement-mode MOFFET employs an IRF5802TRPBF (Infineon, Germany) silicon-based MOSFET, capable of withstanding high gate-source voltages and limiting high ultrasonic transducer excitation voltages. The IRF5802TRPBF has a gate-source voltage range of ±30V, and combined with a mirror-symmetric three-stage cascaded structure, it can clamp high-voltage excitation pulse signals with peak-to-peak values ​​of 180V. Its parasitic capacitance is as low as tens of pF, effectively reducing the attenuation of high-frequency echo signals.

[0052] In some other embodiments, such as Figure 3 As shown, the MOSFET cascade protection network adopts a two-stage symmetrical cascade structure composed of N-channel depletion-type MOSFETs, consisting of two N-channel depletion-type MOSFETs (NMOS7 and NMOS8);

[0053] The first-stage structure uses the drain of the seventh NMOS transistor (NMOS7) as the signal input terminal (TX_IN2). The second-stage structure uses the gate and source of the eighth NMOS transistor (NMOS8) interconnected and connected to the gate and source of the seventh NMOS transistor. The drain of the eighth NMOS transistor serves as the signal output terminal (RX_OUT2).

[0054] The advantage of this topology is that the number of components is reduced, and the attenuation of high-frequency echo signals is relatively smaller. However, the amplitude of the high-voltage pulse depends on the breakdown voltage amplitude between the drain and source of a single NOMS transistor, and it cannot be superimposed as in the previous embodiment to improve the withstand voltage.

[0055] Further, the N-channel depletion mode MOSFET uses BSS169H6327 (Infineon, Germany) N-channel MOSFET. Compared with N-channel enhancement mode MOSFET, N-channel depletion mode MOSFET can conduct when the gate-source voltage is equal to zero, which is beneficial to reduce the degree of high-frequency echo attenuation, and its drain-source on-resistance RDS(on) is usually larger, typically 12 Ω, and the drain current is smaller, which is beneficial to clamp the high-voltage pulse excitation signal. The drain-source breakdown voltage of BSS169H6327 is 100 V, which can clamp the high-voltage pulse excitation signal with a peak-to-peak value of less than 200 V in combination with a two-stage symmetric cascade structure, and the parasitic capacitance is as low as tens of pF, which can effectively reduce the attenuation of high-frequency echo signals.

[0056] Further, the high-speed bidirectional limiting module is composed of two anti-parallel high-speed switching diodes (D1, D2), the anode of the first high-speed switching diode (D1) and the cathode of the second high-speed switching diode (D2) are commonly connected to the signal output end (RX_OUT), and the cathode of the first high-speed switching diode and the anode of the second high-speed switching diode are commonly connected to the system ground (GND). When the bipolar high-voltage excitation signal reaches the RX_OUT end, D1 and D2 can be broken down to clamp the high-voltage excitation signal. Since the high-voltage excitation signal has a high frequency, it requires that the high-speed switching diode has a very low on-time and reverse recovery time, and a small junction capacitance.

[0057] Further, the high-speed bidirectional limiting module uses BAV99 high-speed switching diode pair (Nexperia, Netherlands), the reverse recovery time of BAV99 is less than or equal to 4 ns, the junction capacitance is less than 1.5 pF, and it can withstand a reverse voltage of up to 100 V, while having a low reverse breakdown voltage, which can effectively clamp the high-voltage excitation signal while having little effect on the high-frequency echo signal.

[0058] Further, as shown in Figures 2-3 The transient overvoltage cooperative protection module is composed of a bidirectional transient voltage suppressor (TVS). When an abnormal overvoltage occurs in the circuit and reaches the breakdown voltage of the TVS, the TVS quickly changes from a high resistance state to a low resistance state, discharges the abnormal overvoltage to the ground while clamping the abnormal overvoltage at a lower level, thereby protecting the subsequent circuit from damage caused by the abnormal overvoltage. When the abnormal overvoltage disappears, the resistance of the TVS returns to a high resistance state. The bidirectional transient voltage suppressor (D3) is connected in parallel with the high-speed bidirectional limiting module, and the two cooperate to clamp the high-frequency high-voltage pulse excitation signal.

[0059] Further, the bidirectional transient voltage suppressor adopts SP0115-01 ETG bidirectional TVS (Littefuse, USA), the junction capacitance of SP0115-01 ETG is 0.85 pF; the minimum breakdown voltage is typically as low as 1.6 V; the maximum rated reverse off voltage is 1 V; the maximum peak pulse current is typically as high as 12 A; and the maximum clamping voltage is as low as several V levels. The transient overvoltage cooperative protection module composed of SP0115-01 ETG and the high-speed bidirectional limiting module composed of BAV99 jointly limit the high-frequency high-voltage pulse excitation signal to a lower level to prevent damage to the subsequent circuit.

[0060] In some embodiments, when the topology of the MOSFET cascade protection network is a mirror-symmetrical three-stage cascade structure composed of N-channel enhancement-mode MOSFET, after the arrival of the bipolar high-frequency high-voltage pulse excitation signal at the signal input end (TX_IN1), in the positive half cycle, the positive polarity pulse is transmitted through the first NMOS tube, the second NMOS tube, and the third NMOS tube (NMOS1-NMOS3) in the structure, and is clamped by the first high-speed switching diode (D1) and the bidirectional transient voltage suppressor (D3); similarly, in the negative half cycle, the negative polarity pulse is transmitted through the fourth NMOS tube, the fifth NMOS tube, and the sixth NMOS tube (NMOS4-NMOS6) in the structure, and is clamped by the second high-speed switching diode (D2) and the bidirectional transient voltage suppressor (D3).

[0061] After the arrival of the high-frequency echo small signal at the signal input end (TX_IN1), the equivalent circuit model of the mirror-symmetrical three-stage cascade structure composed of N-channel enhancement-mode MOSFET is close to a high-pass filter, and the high-frequency echo small signal can reach the signal output end.

[0062] In yet some embodiments, when the MOSFET cascade protection network adopts a two-stage symmetrical cascade structure composed of N-channel depletion-mode MOSFET, after the arrival of the bipolar high-frequency high-voltage pulse excitation signal at the signal input end (TX_IN2), in the positive half cycle, the positive polarity pulse is transmitted through the low-impedance channel of the drain and the source of the seventh NMOS tube (NMOS7) and the parasitic diode of the eighth NMOS tube (NMOS8) in the structure, and is clamped by the first high-speed switching diode (D1) and the bidirectional transient voltage suppressor (D3); similarly, in the negative half cycle, the negative polarity pulse is transmitted through the parasitic diode of the seventh NMOS tube (NMOS7) and the low-impedance channel of the drain and the source of the eighth NMOS tube (NMOS8) in the structure, and is clamped by the second high-speed switching diode (D2) and the bidirectional transient voltage suppressor (D3).

[0063] After the high-frequency echo small signal arrives at the signal input terminal (TX_IN2), the drain and source of the two-stage symmetrical cascaded structure composed of N-channel depletion-type MOSFETs are turned on because the gate-source voltage is equal to 0. Moreover, the amplitude of the high-frequency echo small signal will not turn on the body diodes of the seventh and eighth NMOS transistors (NMOS7 and NMOS8), so the high-frequency echo small signal can reach the signal output terminal (RX_OUT2).

[0064] The signal insertion loss of the T / R switch designed in this invention was compared with that of a commercial T / R switch in the test. Figure 4 As shown, the results demonstrate that the T / R switch topology designed in this invention ( Figure 2 and Figure 3 The structure shown has lower attenuation loss and better signal transmission capability for signals with frequencies greater than 30MHz.

[0065] Furthermore, the T / R switch topology of this invention ( Figure 2 and Figure 3 The structure shown can not only effectively block bipolar pulses and output echo signals with low attenuation, but also has the same blocking and protection effect for unipolar pulse excitation.

[0066] The number of devices and processing scale described herein are for the purpose of simplifying the description of the invention. Applications, modifications, and variations of the invention will be readily apparent to those skilled in the art.

[0067] Although embodiments of the present invention have been disclosed above, they are not limited to the applications listed in the specification and embodiments. They can be applied to various fields suitable for the present invention. For those skilled in the art, other modifications can be easily made. Therefore, without departing from the general concept defined by the claims and their equivalents, the present invention is not limited to the specific details and illustrations shown and described herein.

[0068] It should also be noted that the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0069] Each of the embodiments in the specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, the system embodiments are described simply because they are basically similar to the method embodiments, and the relevant parts can be referred to the part of the method embodiments.

[0070] The above only describes the embodiments of the specification, and is not used to limit one or more embodiments of the specification. One or more embodiments of the specification can have various changes and variations for those skilled in the art. Any modification, equivalent replacement, improvement, etc. within the spirit and principle of one or more embodiments of the specification should be included in the claim range of one or more embodiments of the specification.

Claims

1. A high frequency ultrasonic echo protection circuit based on MOSFET architecture, characterized by: The MOSFET cascade protection network, the high-speed bidirectional limiting module, and the transient overvoltage cooperative protection module are included. After the bipolar high-frequency high-voltage pulse excitation signal reaches the signal input end of the MOSFET cascade protection network, the positive and negative polarity pulses are transmitted through the MOSFET cascade protection network and clamped by the high-speed bidirectional limiting module and the transient overvoltage cooperative protection module. The high-frequency echo small signal reaches the signal output end of the MOSFET cascade protection network through the signal input end of the MOSFET cascade protection network.

2. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 1 characterized by: The MOSFET cascade protection network adopts a mirror-symmetrical three-stage cascade structure composed of six discrete N-channel enhancement-mode MOSFETs. In the three-stage cascade structure, the gate and the drain of the first NMOS are interconnected as the signal input end, the gate and the drain of the second NMOS are interconnected and then connected to the source of the first NMOS, the gate and the drain of the third NMOS are interconnected and then connected to the source of the second NMOS, and the source of the third NMOS is the signal output end. In the mirror-symmetrical three-stage cascade structure, the source of the fourth NMOS is connected to the signal input end, the gate and the drain of the fourth NMOS are interconnected and then connected to the source of the fifth NMOS, the gate and the drain of the fifth NMOS are interconnected and then connected to the source of the sixth NMOS, and the gate and the drain of the sixth NMOS are interconnected and then connected to the signal output end.

3. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 2, wherein: The N-channel enhancement-mode MOSFET adopts IRF5802TRPBF silicon-based MOSFET.

4. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 1 characterized by: The MOSFET cascade protection network adopts a two-stage symmetrical cascade structure composed of two N-channel depletion-mode MOSFETs. The drain of the seventh NMOS is the signal input end, the gate and the source of the eighth NMOS are interconnected and then connected to the gate and the source of the seventh NMOS, and the drain of the eighth NMOS is the signal output end.

5. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 4, wherein: The N-channel depletion-mode MOSFET adopts BSS169H6327 N-channel MOSFET.

6. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 2 or 4 wherein: The high-speed bidirectional limiting module is composed of two high-speed switching diodes connected in reverse parallel, the anode of the first high-speed switching diode and the cathode of the second high-speed switching diode are connected to the signal output end, and the cathode of the first high-speed switching diode and the anode of the second high-speed switching diode are connected to the system ground.

7. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 6 characterized by: The high-speed bidirectional limiting module uses a pair of BAV99 high-speed switching diodes.

8. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 6, wherein: The transient overvoltage cooperative protection module is composed of a bidirectional transient voltage suppressor connected in parallel with the high-speed bidirectional limiting module, and the two modules cooperate to clamp the high-frequency high-voltage pulse excitation signal.

9. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 8, wherein: The bidirectional transient voltage suppressor adopts SP0115-01 ETG bidirectional TVS.

10. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 8, wherein: When the topology of the MOSFET cascade protection network is a mirror-symmetry three-stage cascade structure composed of N-channel enhancement-mode MOSFETs, after the bipolar high-frequency high-voltage pulse excitation signal reaches the signal input end, in the positive half cycle, the positive polarity pulse is transmitted through the first NMOS tube, the second NMOS tube and the third NMOS tube in the structure, and is clamped by the joint action of the first high-speed switching diode and the bidirectional transient voltage suppressor; similarly, in the negative half cycle, the negative polarity pulse is transmitted through the fourth NMOS tube, the fifth NMOS tube and the sixth NMOS tube in the structure, and is clamped by the joint action of the second high-speed switching diode and the bidirectional transient voltage suppressor. After the high-frequency echo small signal reaches the signal input end, the equivalent circuit model of the mirror-symmetry three-stage cascade structure composed of N-channel enhancement-mode MOSFETs is close to a high-pass filter, and the high-frequency echo small signal can reach the signal output end.

11. A high frequency ultrasonic echo protection circuit based on MOSFET architecture as claimed in claim 8, wherein: When the MOSFET cascade protection network adopts a two-stage symmetric cascade structure composed of N-channel depletion-mode MOSFETs, after the bipolar high-frequency high-voltage pulse excitation signal reaches the signal input end, in the positive half cycle, the positive polarity pulse is transmitted through the drain-source low-impedance channel of the seventh NMOS tube and the parasitic diode of the eighth NMOS tube in the structure, and is clamped by the joint action of the first high-speed switching diode and the bidirectional transient voltage suppressor; similarly, in the negative half cycle, the negative polarity pulse is transmitted through the parasitic diode of the seventh NMOS tube and the drain-source low-impedance channel of the eighth NMOS tube in the structure, and is clamped by the joint action of the second high-speed switching diode and the bidirectional transient voltage suppressor. After the high-frequency echo small signal reaches the signal input end, the gate-source voltage of the two-stage symmetric cascade structure composed of N-channel depletion-mode MOSFETs is equal to 0, the drain-source is turned on, and the amplitude of the high-frequency echo small signal also does not make the body diode of the seventh NMOS tube and the eighth NMOS tube conduct, and the high-frequency echo small signal can reach the signal output end.

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