Intelligent testing method and system based on field effect transistor and medium

Abstract

The invention provides an intelligent test method and system based on a field effect transistor and a medium, and relates to the technical field of field effect transistor test.The method comprises the steps that a pluggable FET interface is integrated in target equipment, and a multi-mode sensing array is arranged on the periphery of the pluggable FET interface; outputting real-time test time sequence data by randomly disturbing the dynamic working boundary; in the process of operating the target equipment based on the real-time test time sequence data, performing electrothermal coupling data acquisition, and outputting multi-source synchronous time sequence data; performing defect judgment, and outputting alternative defect features; and performing dynamic screening and iterative testing on the field effect transistors according to the alternative defect characteristics until an updated field effect transistor with a test defect being a null set is obtained, and taking the updated field effect transistor as an adapter of the target equipment. The technical problem that in the prior art, static testing or single performance testing is generally adopted, the working stability of the field effect transistor cannot be comprehensively evaluated, and therefore the reliability of the whole machine is reduced is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of field effect transistor testing, in particular to an intelligent testing method and system based on field effect transistors and a medium. BACKGROUND

[0002] As a core component widely used in power electronics and semiconductor devices, field effect transistors (FETs) are not only limited to switching control, but also involve high-speed signal processing, current amplification, and power regulation, etc. Therefore, it is particularly important to accurately screen and test the performance of field effect transistors. However, the existing technology usually adopts static testing and single performance testing, which cannot comprehensively evaluate the working stability of field effect transistors, resulting in insufficient test data to cover the performance of the device in the real working environment. Specifically, static testing is usually carried out under constant voltage, current and temperature conditions, and the results obtained can only reflect the parameter performance of the device in the ideal stable state, while ignoring the frequent dynamic changes and transient impacts in actual applications. Potential hidden dangers that cannot be found in the testing stage may be triggered in actual operation, which not only affects the service life of the field effect transistor itself, but also may cause system-level functional failure or damage, thereby reducing the reliability and safety of the whole machine. SUMMARY

[0003] The present application provides an intelligent testing method and system based on field effect transistors and a medium, aiming to solve the technical problem that the existing technology usually adopts static testing or single performance testing, which cannot comprehensively evaluate the working stability of field effect transistors, thereby reducing the reliability of the whole machine.

[0004] The first aspect of the present application provides an intelligent testing method based on field effect transistors, which comprises: integrating a pluggable FET interface in a target device, wherein the pluggable FET interface supports rapid replacement of field effect transistors, and a multi-modal sensor array is arranged peripherally around the pluggable FET interface; outputting real-time test timing data by randomly disturbing the dynamic working boundary of the target device; inserting and installing a candidate field effect transistor into the pluggable FET interface, and activating the multi-modal sensor array to collect electric-thermal coupling data of the candidate field effect transistor based on the real-time test timing data during the running of the target device, and outputting multi-source synchronous timing data; performing defect judgment based on the multi-source synchronous timing data, and outputting candidate defect features; taking the candidate field effect transistor as the iteration starting point, and performing dynamic screening and iterative testing of field effect transistors according to the candidate defect features until an updated field effect transistor with empty test defect set is obtained as the adaptive device of the target device.

[0005] In a second aspect, the application discloses a field effect transistor-based intelligent testing system, which is used for the field effect transistor-based intelligent testing method and comprises an interface integrated module, a random disturbance module, a data acquisition module, a defect determination module and an iterative testing module.

[0006] In a third aspect, the application discloses a storage medium, which stores a computer program. When the computer program is executed by a processor, the steps of the field effect transistor-based intelligent testing method in the first aspect are implemented.

[0007] The one or more technical solutions provided in the application have at least the following beneficial effects: By integrating the pluggable FET interface in the target device, the target device can be flexibly adapted to different types of field effect tubes and equipped with a multi-modal sensing array, realizing the rapid replacement and real-time monitoring of field effect tubes, providing rich input for subsequent defect detection; by randomly disturbing the dynamic working boundary of the target device, real-time test timing data is generated, this process simulates various working conditions that the target device may encounter in the real working environment, and through disturbance of the response mode of the detection device, the performance data of the target device under extreme conditions is obtained, providing a solid foundation for defect judgment and screening; by plugging the alternative field effect tube into the pluggable FET interface, real measurement is carried out based on real-time test timing data, and the multi-modal sensing array is activated to collect electro-thermal coupling data, realizing real-time monitoring of the alternative field effect tube, this step can accurately capture electrical and thermal abnormalities of the target device during operation, through the collection of multi-source synchronous timing data, the working performance of the field effect tube is comprehensively evaluated, and necessary information is provided for subsequent defect judgment; based on the multi-source synchronous timing data, the defect judgment is carried out, and the alternative defect characteristics are output, which provides accurate targets for subsequent screening and optimization; by taking the alternative field effect tube as the iteration starting point, dynamic screening and iteration testing are carried out according to the alternative defect characteristics, until the test defect set is empty, so as to find the adaptive device, this process ensures that the screened field effect tube meets the requirements of the target device, and is continuously optimized in multiple rounds of testing until there is no defect, through this iterative optimization method, the most suitable field effect tube can be efficiently found, and the reliability and stability of the target device in long-term operation are improved.

[0008] The above description is only a summary of the technical solutions of the present application, in order to more clearly understand the technical means of the present application, the specific embodiments of the present application can be implemented according to the content of the description, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following specific embodiments of the present application are described. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 The intelligent test method flowchart based on field effect tube provided by the embodiment of the present application.

[0010] Figure 2 The intelligent test system structure diagram based on field effect tube provided by the embodiment of the present application.

[0011] Explanation of reference numerals: interface integration module 10, random disturbance module 20, data acquisition module 30, defect judgment module 40, iteration test module 50. DETAILED DESCRIPTION

[0012] This application provides a method, system, and medium for intelligent testing based on field-effect transistors (FETs), which solves the technical problem that existing technologies typically use static testing or single performance testing, which cannot comprehensively evaluate the working stability of FETs, thereby reducing the reliability of the entire system.

[0013] After introducing the basic principles of this application, various non-limiting embodiments of this application will be described in detail below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit this application.

[0014] Example 1, as Figure 1 As shown in the figure, this application provides an intelligent testing method based on a field-effect transistor, the method comprising: A pluggable FET interface is integrated into the target device, wherein the pluggable FET interface supports quick replacement of the field-effect transistor, and a multi-mode sensor array is arranged around the pluggable FET interface.

[0015] A pluggable FET interface is integrated into the target device. This pluggable FET interface supports the insertion and removal of different types of field-effect transistors (FETs), allowing users to quickly replace different types of FET devices. A multi-mode sensor array is deployed around the pluggable FET interface. This array consists of a high-voltage differential probe, a Rogowski coil, an active voltage probe, an infrared thermal imager, and thermocouples. The high-voltage differential probe acquires the drain-source voltage variation of the FET, the Rogowski coil detects the timing data of the drain current, the active voltage probe monitors the gate-source voltage, the infrared thermal imager measures the junction temperature variation of the FET to provide thermal imaging data, and the thermocouples detect the FET's case temperature.

[0016] By randomly perturbing the dynamic operating boundary of the target device, real-time test timing data is output.

[0017] Real-time test timing data is generated by randomly perturbing the dynamic operating boundaries of the target device. The perturbation is divided into two parts: the rated operating boundary and the transient operating boundary. The rated operating boundary represents the stable state of the device under normal operating conditions, while the transient operating boundary reflects the performance and behavior of the device under extreme conditions. These perturbations are alternately performed under controlled conditions. By aligning the timestamps, the test data segments of the two types of perturbations are alternately spliced ​​to generate real-time test timing data, providing actual working data for subsequent testing processes.

[0018] The candidate MOSFET is plugged into the pluggable FET interface. During the operation of the target device based on the real-time test timing data, the multi-modal sensor array is activated to acquire the electrothermal coupling data of the candidate MOSFET and output multi-source synchronous timing data.

[0019] The alternative field effect tube is plugged into the pluggable FET interface, and the target device is run based on real-time test timing data. During the running process, the electro-thermal coupling data related to the alternative field effect tube is collected in real time through various sensors in the multi-modal sensor array, including drain-source voltage, drain current, gate-source voltage, junction temperature, and shell temperature. All sensors are time-aligned through synchronous trigger pulses when collecting data to ensure that the time markers of different data sources are consistent. These synchronized data are output as multi-source synchronized timing data, providing the necessary basis for subsequent defect analysis.

[0020] Based on the multi-source synchronized timing data, the defect is determined, and the alternative defect feature is output.

[0021] Based on the preset feature extraction rule, the key device performance parameters are extracted from the multi-source synchronized timing data and spliced in a fixed order to form a multi-dimensional vector as the comprehensive performance index of the alternative field effect tube under specific working conditions. A multi-source specification threshold is preset to reflect the allowable range of qualified devices. The difference between the test vector and the threshold, i.e., the mismatch degree, directly reflects the performance gap between the alternative field effect tube and the ideal device. The mismatch degree is mapped to the electro-thermal coupling rule library, which records the mapping relationship between historical defect patterns and corresponding parameter distributions. According to the matching result, the alternative defect feature is output, including defect location, time, and type.

[0022] Taking the alternative field effect tube as the iteration starting point, the dynamic screening and iterative testing of the field effect tube are performed according to the alternative defect feature until an updated field effect tube with an empty test defect set is obtained as the adapter device of the target device.

[0023] After obtaining the alternative defect feature, it is used as the starting point for subsequent field effect tube optimization. The optimal adapter device is found through database matching and iterative measurement. When the test defect set is empty, the corresponding field effect tube is used as the final adapter device, which can run stably in the target device for a long time. This process ensures that the selected device not only meets the requirements in a single working condition but also passes the verification of multiple disturbances and working conditions.

[0024] Further, the dynamic working boundary of the target device is disturbed by random disturbance, and real-time test timing data is output. The method comprises: decomposing the dynamic operating boundary to obtain a rated operating boundary and a transient operating boundary; generating a random perturbation instruction set using a linear congruential generator; executing the random perturbation instruction set with the rated operating boundary as an amplitude constraint to obtain a rated test data segment set; executing the random perturbation instruction set with the rated operating boundary as a perturbation taboo and the transient operating boundary as an amplitude constraint to obtain a transient test data segment set; and integrating the rated test data segment set and the transient test data segment set through time stamp aligned alternating splicing to generate the real-time test timing data.

[0025] The rated operating boundary is a stable state of the target device under normal operating conditions, which defines the operating range of the target device under any abnormal conditions and is the standard operating interval of the target device. The rated operating boundary is generally set according to the rated parameters (such as voltage, current, frequency, etc.) of the device and the standards of the manufacturer; the transient operating boundary refers to the change range of the operating parameters of the target device under external perturbation or extreme conditions, for example, sudden temperature changes, sharp load changes, etc. will cause instantaneous changes in the operating state of the device, and the transient operating boundary defines the operating capability of the device under extreme conditions.

[0026] The linear congruential generator is a commonly used pseudo-random number generator that generates seemingly random numerical values through specific mathematical formulas. These random numerical values are used to control the dynamic perturbation of the target device, thereby testing the performance and stability of the device under non-ideal operating conditions. The random perturbation instruction set is generated by the linear congruential generator, which contains the change values of parameters such as voltage, current, and temperature, and can simulate various changes that the device may face in the real environment.

[0027] Based on the rated operating boundary, the generated random perturbation instruction set is applied to the target device for testing. In this stage, the amplitude of the random perturbation instruction set is set as the constraint condition of the rated operating boundary to ensure that the perturbation does not exceed the normal operating range of the device. After executing the random perturbation instruction set, the response data of the target device under perturbation is recorded, which constitutes the rated test data segment set. These data reflect how the target device responds to different perturbations under rated operating conditions and can provide basic data for subsequent performance analysis.

[0028] Taking the rated operating boundary as a perturbation taboo means that this perturbation needs to avoid the rated operating boundary, and the amplitude is set as the constraint condition of the transient operating boundary to ensure that the test data can reflect the behavior of the target device under transient change conditions. By executing the random perturbation instruction set, the response data of the target device under the transient operating boundary is recorded, which constitutes the transient test data segment set. These data capture the dynamic response of the target device under sudden changes or extreme conditions and reflect the adaptability of the target device.

[0029] The nominal test data segment set and the transient test data segment set are aligned according to the time stamp, ensuring the timing synchronization of different data sources, and the two types of data are alternately combined into a continuous real-time test timing data in an alternating splicing manner. Through this way, the response data of the target device under normal working conditions and extreme conditions can be contained at the same time, which is used for subsequent defect analysis and performance evaluation.

[0030] Further, the alternative field effect tube is plugged and installed to the pluggable FET interface, and during the operation of the target device based on the real-time test timing data, the multi-modal sensing array is activated to collect the electro-thermal coupling data of the alternative field effect tube, and multi-source synchronous timing data is output. The method comprises: The drain-source voltage timing data is collected through the high-voltage differential probe connected in parallel between the drain and source pins of the alternative field effect tube; the drain current timing data is collected through the Rogowski coil connected in series to the source lead of the alternative field effect tube; the gate-source voltage timing data is collected through the active voltage probe connected between the gate and source pins of the alternative field effect tube; the junction temperature timing data is collected through the infrared thermal imager arranged opposite to the surface of the package of the alternative field effect tube at a preset safe distance; and the shell temperature timing data is collected through the thermocouple attached to the metal shell of the alternative field effect tube. The high-voltage differential probe, the Rogowski coil, the active voltage probe, the infrared thermal imager and the thermocouple constitute the multi-modal sensing array, and the drain-source voltage timing data, the drain current timing data, the gate-source voltage timing data, the junction temperature timing data and the shell temperature timing data are aligned based on the synchronous trigger pulse, thereby constituting the multi-source synchronous timing data.

[0031] After the alternative field effect tube is plugged and installed to the pluggable FET interface, the high-voltage differential probe is connected in parallel between the drain and source pins of the alternative field effect tube. The high-voltage differential probe can accurately capture the transient voltage change between the drain and source without affecting the normal operation of the device, including the peak voltage, oscillation waveform and steady-state voltage level in the switching process. The drain-source voltage timing data collected by the high-voltage differential probe can reflect the voltage response characteristics of the device in different working stages, thereby providing basic data for switching loss analysis and overvoltage problem diagnosis.

[0032] The Rogowski coil is connected in series to the source lead of the alternative field effect tube. The Rogowski coil is a coreless current sensor with a wide frequency response range, and is particularly suitable for capturing rapidly changing pulse current and transient waveform. Through the series installation, high-precision current detection can be realized without significantly increasing the line impedance. The drain current timing data collected by the Rogowski coil can be used to analyze the current rise rate, conduction current waveform and possible overcurrent or peak current phenomenon at the switching moment.

[0033] An active voltage probe is connected between the gate and the source pin of the alternative field effect tube, and has higher input impedance and lower capacitive load than a passive probe, so as to reduce the influence on the measured signal in high-frequency measurement. The active voltage probe is used to collect the gate-source voltage time series data, so as to analyze the charging and discharging characteristics of the device in the driving process and the stability of the gate voltage.

[0034] The infrared thermal imager is arranged opposite to the packaging surface of the alternative field effect tube at a preset safe distance, and is used to collect the change data of the junction temperature with time in a non-contact manner. The preset safe distance takes into account the resolution of thermal imaging and the electrical safety of the equipment, so as to avoid the risk of electric shock or interference caused by the high-voltage area. The infrared thermal imager can quickly capture the temperature distribution of the packaging surface of the alternative field effect tube. By positioning and temperature calibration of the hot spot area of the packaging surface, the dynamic change curve of the internal chip junction temperature can be calculated. The collected junction temperature time series data is a reference index for measuring the thermal stability, transient thermal response speed and effectiveness of the heat dissipation path of the device.

[0035] The thermocouple is directly attached to the surface of the metal shell of the alternative field effect tube, and is used to collect the dynamic change of the shell temperature in a contact manner. The thermocouple has fast response speed and high measurement accuracy, and is suitable for long-term stable monitoring of the shell temperature. Unlike the non-contact measurement of the infrared thermal imager, the thermocouple can provide accurate single-point temperature values, which helps to establish the thermal resistance relationship between the junction temperature and the shell temperature. The collected shell temperature time series data can be used to judge the heat conduction ability of the packaging material, the working efficiency of the heat dissipation device, and the thermal accumulation effect under long-time operation.

[0036] The above high-voltage differential probe, Rogowski coil, active voltage probe, infrared thermal imager and thermocouple constitute a multi-modal sensing array. The multi-modal sensing array can simultaneously cover two categories of data, namely electrical parameters and thermal parameters, and realize all-around monitoring of the running state of the field effect tube. In the collection process, all sensors are controlled by a synchronous trigger pulse to ensure that the timestamps of different types of data are completely aligned. The five types of time series data after alignment together constitute multi-source synchronous time series data, which provides a unified and accurate data basis for subsequent feature extraction, defect judgment and thermal-electric coupling analysis.

[0037] Further, based on the multi-source synchronous time series data, defect judgment is performed, and alternative defect features are output. The method comprises: The on-resistance parameter, the switching delay parameter, the threshold voltage drift, the reverse recovery charge and the thermal resistance parameter are extracted from the multi-source synchronous time series data based on a preset feature extraction rule; the multi-source specification vector is constructed by splicing the on-resistance parameter, the switching delay parameter, the threshold voltage drift, the reverse recovery charge and the thermal resistance parameter; the multi-source specification threshold is predefined, and the multi-source defect scale vector is output by calculating the mismatch degree of the multi-source specification vector and the multi-source specification threshold; the multi-source defect scale vector is subjected to thermal-electric coupling correlation analysis, and the candidate defect feature is output.

[0038] The on-resistance parameter is calculated from the steady-state values of drain-source voltage (V DS ) and drain current (I D ) in the on state, and when the junction temperature (T j ) is greater than or equal to 125℃, and the gate-source voltage (V GS ) is greater than the gate-source threshold voltage (V th ), the average value of V DS / I D is taken; the switching delay parameter includes the turn-on delay time and the turn-off delay time, which is extracted from the interaction relationship of the gate-source voltage (V GS ) and the drain current (I D ) waveform at the switching moment; the threshold voltage drift is the difference of V D corresponding to I GS =250μA at 25℃ and 125℃; the reverse recovery charge is the integral of the absolute value of the reverse current at the turn-off moment, reflecting the diode reverse recovery performance of the device; the thermal resistance parameter is calculated according to the junction temperature (T j ), the shell temperature (T c ) and the power consumption, reflecting the conduction ability of heat from the chip to the external environment.

[0039] The above five types of feature parameters are spliced in a fixed order to form a multi-source specification vector, which integrates electrical and thermal characteristics together in the form of multi-dimensional performance coordinates, constituting a digital description of the comprehensive state of the candidate field effect tube.

[0040] The multi-source specification threshold is predefined, and the multi-source specification threshold corresponds to the allowable range of qualified field effect tubes on each feature parameter. By comparing the multi-source specification vector with the multi-source specification threshold item by item, the mismatch degree of each parameter, i.e. the deviation degree between the actual value and the standard value, is calculated, and the mismatch degrees of each parameter are combined to obtain the multi-source defect scale vector. Each element of the vector not only represents the existence of the defect, but also reflects the severity of the defect in different dimensions.

[0041] The current multi-source defect scale vector is compared with the historical defect mode in the electro-thermal coupling rule library to determine the closest defect type, such as thermal runaway type, switch loss abnormal type, and packaging heat dissipation degradation type, and finally obtain the candidate defect characteristics with the defect type, impact parameter and correlation, providing accurate decision basis for subsequent field effect tube screening and iterative optimization.

[0042] Further, the multi-source defect scale vector is subjected to electro-thermal coupling correlation analysis, and the candidate defect characteristics are output, and the method comprises: An electro-thermal coupling rule library is configured, wherein the electro-thermal coupling rule library accumulates and records the mapping relationship between historical defect modes and historical defect vectors; the mismatch degree combination of the multi-source defect scale vector is used to traverse the electro-thermal coupling rule library for defect mode matching to obtain a real-time defect mode; based on the real-time defect mode, spatio-temporal correlation analysis is performed on the multi-source synchronous time sequence data to output the candidate defect characteristics.

[0043] An electro-thermal coupling rule library is established, and the core function of the electro-thermal coupling rule library is to accumulate and record the mapping relationship between historical defect modes and historical defect vectors, wherein the historical defect mode refers to the defect characteristics found for different types of field effect tubes in the past test process, and these historical defect modes include but are not limited to thermal runaway, excessive switch loss, threshold voltage drift, etc.; the historical defect vector is multi-dimensional feature data extracted according to the historical defect mode, and these vectors contain the changes of various electrical and thermal parameters related to defects.

[0044] The mismatch degree combination of the multi-source defect scale vector can quantify the deviation degree between the current test data and the ideal standard, thereby providing a basis for matching the historical defect mode, and the defect scale vector generated in real time is compared with the historical defect mode by traversing the electro-thermal coupling rule library, and the closest historical defect mode is found as the real-time defect mode through the similarity matching algorithm.

[0045] According to the real-time defect mode, the scale of the analysis window is determined, and the corresponding electrical and thermal time sequence data are intercepted for analysis, for example, the time domain signals of the drain current and the junction temperature are selected, and the fluctuation characteristics thereof at the time of defect occurrence are calculated, and on the basis of time analysis, the source of thermal anomaly is further analyzed through spatial distribution characteristic analysis, for example, the distribution of the junction temperature waveform is checked, and whether there is a local hot spot and its relationship with the chip design are analyzed, and after the spatio-temporal correlation analysis, the candidate defect characteristics are extracted, including the defect type, the defect position, the spatio-temporal characteristics, etc., providing key information for subsequent device screening and performance optimization.

[0046] Further, based on the real-time defect mode, the multi-source synchronous time sequence data is subjected to spatio-temporal correlation analysis, and the candidate defect characteristics are output, and the method comprises: According to the real-time defect mode, template matching loading is performed to obtain a time domain analysis window scale and a spatial domain space mask; in the multi-source synchronous time sequence data, a correlation time stamp of the real-time defect mode is located; based on the correlation time stamp as a starting point, the drain current time sequence data and the junction temperature time sequence data are intercepted based on the time domain analysis window scale, and a sliding window cross-correlation coefficient is calculated; based on the correlation time stamp as a starting point, the spatial distribution of the junction temperature time sequence data is extracted based on the spatial domain space mask, so as to detect the Euclidean distance between the hotspot coordinates and the center of the chip design, and output a spatial domain offset; the sliding window cross-correlation coefficient and the spatial domain offset are fused, and the candidate defect feature with a space-time coordinate is output.

[0047] The real-time defect mode predefines a time domain analysis window scale and a spatial domain space mask matched with the real-time defect mode, wherein the time domain analysis window scale is used to determine the range of data that should be intercepted on the time axis, for example, a certain length of signal data before and after the occurrence of the defect, so as to analyze the evolution process of the defect; the spatial domain space mask is used to define the area that needs to be focused on in the thermal image data or the temperature distribution data, for example, the area where the hotspot on the chip surface may appear or the specific packaging part. Through template matching loading, it can be ensured that the subsequent time domain and spatial domain analysis are processed in a targeted manner according to the current defect type, thereby improving the efficiency and accuracy of the analysis.

[0048] In the multi-source synchronous time sequence data, according to the characteristics of the real-time defect mode, a correlation time stamp of the defect occurrence is determined, which corresponds to the moment of abnormal change of the electrical or thermal parameter, for example, drain current mutation, rapid rise of junction temperature, etc. The positioning process combines the real-time defect mode characteristics and the actual collected waveform for matching, so as to accurately find the starting time of the defect. The correlation time stamp is used as a reference point for subsequent data interception and analysis, so as to ensure that the analysis process is completely consistent with the time sequence of the defect event.

[0049] Based on the correlation time stamp as a starting point, the corresponding time sequence fragments of the drain current time sequence data and the junction temperature time sequence data are intercepted from the multi-source synchronous time sequence data according to the loaded time domain analysis window scale. In the intercepted time range, the cross-correlation coefficient between the drain current curve and the junction temperature change curve is calculated step by step by using the sliding window method. The cross-correlation coefficient can reflect the correlation between the two at different time delays, thereby revealing the coupling relationship between the electrical change and the thermal response. If the cross-correlation coefficient significantly increases or a specific pattern appears at the time of the defect, it indicates that the defect may be closely related to the electro-thermal coupling effect, which provides a quantitative basis for the subsequent spatial domain analysis and defect positioning.

[0050] With the correlation timestamp as the starting point, the spatial distribution in the junction temperature time series data is extracted according to the loaded airspace spatial mask, and the airspace spatial mask gives the area that should be paid attention to, and only the search is carried out in the airspace spatial mask to avoid the interference of irrelevant heat dissipation structures. In the process of searching in the airspace spatial mask, when there is a single prominent peak, the peak pixel coordinates are taken as the detected hotspot coordinates, and when the hotspot is in a sheet-shaped distribution, the intensity weighted centroid is used as the detected hotspot coordinates to reflect the center position of the heat concentration area.

[0051] The detected hotspot coordinates are mapped to the chip design coordinate system through the camera chip geometric calibration model established in advance, so as to ensure that the detected hotspot coordinates and the chip design center are in the same coordinate system and can be compared. In the chip design coordinate system, the Euclidean distance between the detected hotspot coordinates and the chip design center is calculated to obtain the airspace offset.

[0052] The obtained sliding window cross-correlation coefficient and airspace offset are fused to form an alternative defect feature with time and space double labeling.

[0053] Further, taking the alternative field effect tube as the iteration starting point, performing dynamic screening and iterative testing of the field effect tube according to the alternative defect feature until an updated field effect tube with a null test defect is obtained as the adaptive device of the target device, and the method comprises: The alternative defect feature is used as a device parameter screening constraint to match a first candidate device from a field effect tube database. The first candidate device is installed to the pluggable FET interface for actual measurement. If the output first updated defect feature is not empty, the intersection of the first updated defect feature and the alternative defect feature is used as a first updated screening constraint. Based on the first updated screening constraint, a second candidate device is matched from the field effect tube database. The second candidate device is installed to the pluggable FET interface for actual measurement. If the output second updated defect feature is not empty, the intersection of the first updated defect feature, the second updated defect feature and the alternative defect feature is used as a second updated screening constraint. Iterative updating of the updated screening constraint and candidate device screening calling are carried out by analogy until an updated field effect tube with a null test defect is obtained as the adaptive device of the target device.

[0054] The alternative defect feature is used as a device parameter screening constraint to search in the field effect tube database to match a first candidate device.

[0055] The first candidate device is installed to the pluggable field effect transistor interface, and comprehensive measurement is performed under a given disturbance and synchronous acquisition process. The dynamic disturbance, synchronous acquisition, feature extraction, and rule matching processes described above are reused to output first updated defect features. If the first updated defect features are not empty, it indicates that there are still common problems or new problems are introduced. In this case, the intersection of the first updated defect features and the alternative defect features is calculated to obtain first updated screening constraints. The intersection represents common defects that occur on different devices, which may be key short boards triggered by system and device coupling or boundary conditions.

[0056] The first updated screening constraints are used as new screening conditions to match in the field effect transistor database again to obtain second candidate devices. This process focuses on setting more stringent target intervals for key parameters corresponding to the intersection defects. For example, if the intersection indicates packaging or heat path related problems, devices with different packaging forms or lower thermal resistance paths are preferred; if it indicates switching transient related problems, devices with smaller gate charge, faster but controllable switching characteristics are preferred.

[0057] The second candidate device is installed to the pluggable field effect transistor interface, and comprehensive measurement is performed under the same disturbance conditions and multi-modal synchronous acquisition process as before. The dynamic disturbance, synchronous acquisition, feature extraction, and rule matching processes described above are reused to output second updated defect features. If the second updated defect features are not empty, they are intersected with the first updated defect features and the initial alternative defect features. The intersection represents common defects that persist in multiple rounds of testing. Based on the intersection result, second updated screening constraints are obtained and applied to the matching of candidate devices in the next round to ensure that each iteration converges towards defect minimization.

[0058] New candidate devices are matched in the field effect transistor database using the latest updated screening constraints. The installation, disturbance testing, feature extraction, and defect determination are repeated for each newly selected candidate device in each round. After each round of measurement, the defect feature intersection is updated based on the results, and the screening constraints are adjusted accordingly. When the test results of a certain round show that the defect feature set is empty, i.e., the device does not have performance or thermal abnormalities under all disturbance conditions and detection dimensions, it is determined to be the final updated field effect transistor. This device can be used as the target device's adapter and put into use.

[0059] Further, the random disturbance instruction includes voltage step values, current step values, temperature cycle intervals, step intervals, and step durations.

[0060] The voltage step value refers to the change amplitude of the voltage applied to the target device in a short time, for example, instantaneously increasing or decreasing to a target value from the rated working voltage; the current step value refers to the change amplitude of the load current applied to the device in an extremely short time, for example, rapidly switching from light load to heavy load or no load; the temperature cycle interval refers to the range of cyclically changing the environmental temperature or heat dissipation condition of the device during the test process, for example, repeatedly switching between low temperature and high temperature; the step interval refers to the time interval between two consecutive disturbances; and the step duration refers to the length of time that each disturbance is maintained at a set value. The combination of the five parameters can flexibly construct various dynamic disturbance modes, so that the test process covers not only the normal working conditions within the rated range, but also the severe working conditions close to or temporarily exceeding the transient limit, thereby providing multi-dimensional data support for performance evaluation and defect judgment of the field effect transistor.

[0061] In summary, the intelligent test method based on the field effect transistor provided in the embodiments of the present application has the following technical effects: By integrating the pluggable FET interface in the target device, the target device can flexibly adapt to field effect transistors of different models, and is equipped with a multi-modal sensing array, thereby realizing rapid replacement and real-time monitoring of the field effect transistor and providing rich inputs for subsequent defect detection; by randomly disturbing the dynamic working boundary of the target device, real-time test timing data is generated, this process simulates various working conditions that the target device may encounter in the real working environment, and the performance data of the target device under the limit condition is obtained by disturbing the response mode of the device, thereby providing a solid foundation for defect judgment and screening; by plugging the alternative field effect transistor into the pluggable FET interface, real measurement is performed based on the real-time test timing data, and the multi-modal sensing array is activated to collect electro-thermal coupling data, thereby realizing real-time monitoring of the alternative field effect transistor, which can accurately capture electrical and thermal abnormalities of the target device during operation, and through the collection of multi-source synchronous timing data, the working performance of the field effect transistor is comprehensively evaluated, and necessary information is provided for subsequent defect judgment; based on the multi-source synchronous timing data, defect judgment is performed, and alternative defect features are output, thereby providing accurate targets for subsequent screening and optimization; by taking the alternative field effect transistor as the iteration starting point, dynamic screening and iteration test are performed according to the alternative defect features, until the test defect set is empty, thereby finding the adaptive device, which ensures that the screened field effect transistor meets the requirements of the target device, and is continuously optimized in multiple rounds of tests until there is no defect, and through this iterative optimization method, the most suitable field effect transistor can be efficiently found, thereby improving the reliability and stability of the target device in long-term operation.

[0062] Embodiment two, based on the same inventive concept as the intelligent test method based on the field effect transistor in the foregoing embodiments, as shown in Figure 2 The embodiments of the present application provide an intelligent test system based on a field effect transistor, which comprises: The interface integration module 10 is used for integrating a pluggable FET interface in a target device, wherein the pluggable FET interface supports quick replacement of field effect tubes, and a multi-modal sensing array is arranged peripherally to the pluggable FET interface; the random disturbance module 20 is used for outputting real-time test timing data by randomly disturbing a dynamic working boundary of the target device; the data acquisition module 30 is used for inserting and installing a candidate field effect tube into the pluggable FET interface, and activating the multi-modal sensing array to acquire electric-thermal coupling data of the candidate field effect tube based on the real-time test timing data during running of the target device, and outputting multi-source synchronous timing data; the defect judgment module 40 is used for performing defect judgment based on the multi-source synchronous timing data, and outputting candidate defect features; and the iterative test module 50 is used for taking the candidate field effect tube as an iterative starting point, and performing dynamic screening and iterative test of field effect tubes according to the candidate defect features until an updated field effect tube with an empty set of test defects is obtained as an adaptive device of the target device.

[0063] Further, the random disturbance module 20 is used for performing the following operation steps: decomposing the dynamic working boundary to obtain a rated working boundary and a transient working boundary; generating a random disturbance instruction set using a linear congruential generator; executing the random disturbance instruction set with the rated working boundary as an amplitude constraint to obtain a rated test data segment set; executing the random disturbance instruction set with the rated working boundary as a disturbance taboo and the transient working boundary as an amplitude constraint to obtain a transient test data segment set; and integrating the rated test data segment set and the transient test data segment set through time stamp aligned alternating splicing to generate the real-time test timing data.

[0064] Further, the data acquisition module 30 is used for performing the following operation steps: acquiring drain-source voltage timing data through a high-voltage differential probe connected in parallel between drain and source pins of the candidate field effect tube; acquiring drain current timing data through a Rogowski coil connected in series to a source lead of the candidate field effect tube; acquiring gate-source voltage timing data through an active voltage probe connected between a gate and a source pin of the candidate field effect tube; acquiring junction temperature timing data through an infrared thermal imager arranged at a preset safe distance opposite to a packaging surface of the candidate field effect tube; and acquiring shell temperature timing data through a thermocouple attached to a metal shell of the candidate field effect tube; wherein the high-voltage differential probe, the Rogowski coil, the active voltage probe, the infrared thermal imager, and the thermocouple constitute the multi-modal sensing array, and the drain-source voltage timing data, the drain current timing data, the gate-source voltage timing data, the junction temperature timing data, and the shell temperature timing data based on synchronous trigger pulse aligned time stamps constitute the multi-source synchronous timing data.

[0065] Further, the defect determination module 40 is configured to perform the following steps: Based on a preset feature extraction rule, a turn-on resistance parameter, a switching delay parameter, a threshold voltage drift, a reverse recovery charge and a thermal resistance parameter are extracted from the multi-source synchronous time sequence data; a multi-source specification vector is constructed by splicing the turn-on resistance parameter, the switching delay parameter, the threshold voltage drift, the reverse recovery charge and the thermal resistance parameter; a multi-source specification threshold is predefined, and a multi-source defect scale vector is output by calculating the mismatch degree of the multi-source specification vector and the multi-source specification threshold; the multi-source defect scale vector is subjected to a thermoelectric coupling correlation analysis, and the candidate defect feature is output.

[0066] Further, the defect determination module 40 is configured to perform the following steps: A thermoelectric coupling rule library is configured, wherein the thermoelectric coupling rule library accumulates a mapping relationship between a historical defect mode and a historical defect vector; a real-time defect mode is obtained by traversing the thermoelectric coupling rule library for defect mode matching using a mismatch degree combination of the multi-source defect scale vector; based on the real-time defect mode, a spatiotemporal correlation analysis is performed on the multi-source synchronous time sequence data, and the candidate defect feature is output.

[0067] Further, the defect determination module 40 is configured to perform the following steps: A template matching load is performed according to the real-time defect mode, and a time domain analysis window scale and a spatial domain space mask are obtained; in the multi-source synchronous time sequence data, an associated time stamp of the real-time defect mode is located; based on the time domain analysis window scale, the drain current time sequence data and the junction temperature time sequence data are intercepted from the associated time stamp as a starting point, and a sliding window cross-correlation coefficient is calculated; based on the spatial domain space mask, a spatial distribution of the junction temperature time sequence data is extracted from the associated time stamp as a starting point, a Euclidean distance of a hot spot coordinate and a chip design center is detected, and a spatial domain offset is output; the sliding window cross-correlation coefficient and the spatial domain offset are fused, and the candidate defect feature with a spatiotemporal coordinate is output.

[0068] Further, the iterative test module 50 is configured to perform the following steps: The alternative defect feature is taken as a device parameter screening constraint, a first candidate device is matched from a field effect transistor database, the first candidate device is installed to the pluggable FET interface for actual measurement, if the output first updated defect feature is not empty, the intersection of the first updated defect feature and the alternative defect feature is taken as a first updated screening constraint, a second candidate device is matched from the field effect transistor database based on the first updated screening constraint, the second candidate device is installed to the pluggable FET interface for actual measurement, if the output second updated defect feature is not empty, the intersection of the first updated defect feature, the second updated defect feature and the alternative defect feature is taken as a second updated screening constraint, iterative updating of the updated screening constraint and candidate device screening calling are carried out by analogy until an updated field effect transistor with a test defect empty set is obtained as the adaptive device of the target device.

[0069] Further, the random perturbation instruction includes a voltage step value, a current step value, a temperature cycle interval, a step interval and a step duration.

[0070] Through the foregoing detailed description of the field effect transistor-based intelligent testing method, those skilled in the art can clearly understand the field effect transistor-based intelligent testing system in the embodiments. Since the field effect transistor-based intelligent testing system corresponds to the method disclosed in the embodiments, the description is relatively simple, and the relevant part can be referred to the method part description.

[0071] Embodiment three provides a storage medium having a computer program stored thereon, the computer program is executed by a processor to implement any step of the embodiment one.

[0072] The technical features of the above embodiments can be combined in any manner. To make the description concise, not all possible combinations of the technical features in the above embodiments are described, however, as long as the combinations of the technical features do not exist contradictions, they should be considered as the scope of the present disclosure.

[0073] The above description of disclosed embodiments enables a person skilled in the art to implement or use the present application. Various modifications to the embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method of smart testing based on field effect transistors, characterized in that, The method comprises: integrating a pluggable FET interface in a target device, wherein the pluggable FET interface supports quick replacement of field effect tubes, and the pluggable FET interface is peripherally arranged with a multi-modal sensing array; outputting real-time test timing data by randomly perturbing a dynamic working boundary of the target device; inserting a candidate field effect tube into the pluggable FET interface, and activating the multi-modal sensing array to collect electro-thermal coupling data of the candidate field effect tube based on the real-time test timing data during operation of the target device, and outputting multi-source synchronous timing data; performing defect determination based on the multi-source synchronous timing data, and outputting candidate defect features; taking the candidate field effect tube as an iteration starting point, and performing dynamic screening and iteration testing of field effect tubes according to the candidate defect features until an updated field effect tube with an empty set of test defects is obtained as an adaptive device of the target device.

2. The field effect transistor based smart test method of claim 1, wherein, The method comprises: decomposing the dynamic working boundary to obtain a rated working boundary and a transient working boundary; generating a random perturbation instruction set using a linear congruential generator; using the rated working boundary as an amplitude constraint to execute the random perturbation instruction set to obtain a rated test data segment set; using the rated working boundary as a perturbation taboo and the transient working boundary as an amplitude constraint to execute the random perturbation instruction set to obtain a transient test data segment set; integrating the rated test data segment set and the transient test data segment set in an alternating splicing manner through timestamp alignment to generate the real-time test timing data.

3. The field effect transistor based smart test method of claim 1, wherein, The method comprises: collecting drain-source voltage timing data through a high-voltage differential probe connected in parallel between a drain and a source pin of the candidate field effect tube; collecting drain current timing data through a Rogowski coil connected in series to a source lead of the candidate field effect tube; collecting gate-source voltage timing data through an active voltage probe connected between a gate and a source pin of the candidate field effect tube; collecting junction temperature timing data through an infrared thermal imager arranged at a preset safe distance opposite a packaging surface of the candidate field effect tube; collecting shell temperature timing data through a thermocouple attached to a metal shell of the candidate field effect tube; wherein the high-voltage differential probe, the Rogowski coil, the active voltage probe, the infrared thermal imager, and the thermocouple constitute the multi-modal sensing array, and the drain-source voltage timing data, the drain current timing data, the gate-source voltage timing data, the junction temperature timing data, and the shell temperature timing data are aligned in time based on a synchronous trigger pulse, and constitute the multi-source synchronous timing data.

4. The field effect transistor based smart test method of claim 3, wherein, The method comprises: performing defect determination based on the multi-source synchronous timing data, and outputting candidate defect features; extracting a turn-on resistance parameter, a switching delay parameter, a threshold voltage drift, a reverse recovery charge and a thermal resistance parameter from the multi-source synchronous time series data based on a preset feature extraction rule; constructing a multi-source specification vector by splicing the turn-on resistance parameter, the switching delay parameter, the threshold voltage drift, the reverse recovery charge and the thermal resistance parameter; predefining a multi-source specification threshold, and outputting a multi-source defect scale vector by calculating a mismatch degree of the multi-source specification vector and the multi-source specification threshold; performing a thermoelectric coupling correlation analysis on the multi-source defect scale vector to output the candidate defect feature.

5. The field effect transistor based smart test method of claim 4, wherein, performing a thermoelectric coupling correlation analysis on the multi-source defect scale vector to output the candidate defect feature, the method comprising: configuring an electric-thermal coupling rule library, wherein the electric-thermal coupling rule library accumulates a mapping relationship between historical defect modes and historical defect vectors; adopting a mismatch degree combination of the multi-source defect scale vector to perform defect mode matching by traversing the electric-thermal coupling rule library, to obtain a real-time defect mode; based on the real-time defect mode, performing a space-time correlation analysis on the multi-source synchronous time series data to output the candidate defect feature.

6. The field effect transistor based smart test method of claim 5, wherein, based on the real-time defect mode, performing a space-time correlation analysis on the multi-source synchronous time series data to output the candidate defect feature, the method comprising: performing template matching loading according to the real-time defect mode to obtain a time domain analysis window scale and a spatial domain space mask; locating an associated time stamp of the real-time defect mode in the multi-source synchronous time series data; based on the time domain analysis window scale, intercepting the drain current time series data and the junction temperature time series data from the associated time stamp as a starting point, and calculating a sliding window cross-correlation coefficient; based on the spatial domain space mask, extracting a spatial distribution of the junction temperature time series data from the associated time stamp as a starting point, to detect a Euclidean distance between a hotspot coordinate and a chip design center, and output a spatial domain offset; fusing the sliding window cross-correlation coefficient and the spatial domain offset to output the candidate defect feature with a space-time coordinate.

7. The field effect transistor based smart test method of claim 1, wherein, taking the candidate field effect tube as an iteration starting point, performing dynamic screening and iterative testing of the field effect tube according to the candidate defect feature until an updated field effect tube with a test defect empty set is obtained as an adaptive device of the target device, the method comprising: taking the candidate defect feature as a device parameter screening constraint to match a first candidate device from a field effect tube database; installing the first candidate device to the pluggable FET interface for real measurement, and if a first updated defect feature is not empty, taking an intersection of the first updated defect feature and the candidate defect feature as a first updated screening constraint; based on the first updated screening constraint, matching a second candidate device from the field effect tube database; installing the second candidate device to the pluggable FET interface for real measurement, and if a second updated defect feature is not empty, taking an intersection of the first updated defect feature, the second updated defect feature and the candidate defect feature as a second updated screening constraint; iteratively updating the updated screening constraint and calling the candidate device screening until an updated field effect tube with a test defect empty set is obtained as an adaptive device of the target device.

8. The field effect transistor based smart test method of claim 2, wherein, The random perturbation instructions include voltage step values, current step values, temperature cycle intervals, step intervals, and step durations.

9. An intelligent test system based on field effect transistors, characterized in that A system for implementing the field effect transistor-based intelligent testing method of any one of claims 1-8, the system comprising: an interface integration module configured to integrate a pluggable FET interface in a target device, wherein the pluggable FET interface supports quick replacement of field effect transistors, and the pluggable FET interface is externally provided with a multi-modal sensing array; a random perturbation module configured to output real-time testing timing data by randomly perturbing a dynamic working boundary of the target device; a data acquisition module configured to plug and install a candidate field effect transistor into the pluggable FET interface, activate the multi-modal sensing array to perform electrical-thermal coupling data acquisition of the candidate field effect transistor based on the real-time testing timing data during running of the target device, and output multi-source synchronous timing data; a defect determination module configured to perform defect determination based on the multi-source synchronous timing data and output candidate defect features; an iterative testing module configured to take the candidate field effect transistor as an iteration starting point, perform dynamic screening and iterative testing of field effect transistors according to the candidate defect features, and obtain an updated field effect transistor with an empty set of testing defects as an adapted device of the target device.

10. A storage medium having stored thereon a computer program, characterized in that The computer program, when executed by a processor, implements the steps of the field effect transistor-based intelligent testing method of any one of claims 1-8.

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