Electrochemical impedance spectroscopy phase and amplitude detection of excited systems

Abstract

Embodiments of the present disclosure relate to electrochemical impedance spectroscopy phase and amplitude detection of an excited system. Systems, devices, and methods for electrochemical impedance spectroscopy (EIS) for use with batteries are provided, including systems, devices, and methods for EIS phase and amplitude detection of excited systems. A battery management system including an EIS circuit arrangement is electrically coupled to the battery. The EIS circuitry provides an excitation signal to the battery to generate a response signal from the battery. A current signal and a voltage signal are generated by the EIS circuitry based on a response signal from the battery. The EIS circuitry generates at least one output signal based on the current signal and the voltage signal, and generates an impedance based on the at least one output signal.

Description

TECHNICAL FIELD

[0001] Example embodiments of the present disclosure relate generally to systems, apparatuses, and methods for electrochemical impedance spectroscopy (EIS) for use with a battery, and in particular to systems, apparatuses, and methods for EIS phase and amplitude detection for an energized system. BACKGROUND

[0002] Batteries are increasingly used for a variety of applications. Electrochemical impedance spectroscopy (EIS) can be used to generate information that determines a state of health of a battery. The state of health of a battery can indicate whether a battery is healthy or aged, which can be used to prevent damage to a battery or to determine when a battery should no longer be used.

[0003] The inventors have identified a number of areas for improvement in the prior art and processes, which are the subject of the embodiments described herein. Through the efforts, ingenuity, and innovation applied by developing the solutions included in the embodiments of the present disclosure, a number of deficiencies, challenges, and problems have been addressed, some examples of which are described in detail herein. SUMMARY

[0004] Various embodiments described herein relate to systems, apparatuses, and methods for electrochemical impedance spectroscopy (EIS) for use with a battery, and in particular to systems, apparatuses, and methods for EIS phase and amplitude detection for an energized system.

[0005] According to some embodiments of the present disclosure, an example system is provided. The system can include: a battery; a battery management system including an EIS circuit apparatus, wherein the battery management system is electrically coupled to the battery; wherein the EIS circuit apparatus includes an excitation circuit apparatus configured to generate an excitation signal; wherein the EIS circuit apparatus is configured to provide the excitation signal to the battery and receive a response signal from the battery based on the excitation signal; wherein the EIS circuit apparatus further includes a current sense circuit apparatus configured to generate a current signal based on the response signal; wherein the EIS circuit apparatus further includes a voltage sense circuit apparatus configured to generate a voltage signal based on the excitation signal and the response signal; wherein the EIS circuit apparatus further includes a phase circuit apparatus configured to generate a phase signal based on the current signal and the voltage signal; wherein the EIS circuit apparatus further includes a current amplitude circuit apparatus configured to generate a current amplitude signal based on the current signal; wherein the EIS circuit apparatus further includes a voltage amplitude circuit apparatus configured to generate a voltage amplitude signal based on the current signal; wherein an EIS processor is configured to generate at least one output signal based on the phase signal, the current amplitude signal, and the voltage amplitude signal; and wherein the battery management system is configured to generate a first impedance based on an EIS model and the at least one output signal.

[0006] In some embodiments, the voltage magnitude circuit means comprises a voltage peak detector, and the current magnitude circuit means comprises a current peak detector.

[0007] In some embodiments, the phase circuit means comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

[0008] In some embodiments, the voltage magnitude circuit means comprises a voltage lock-in amplifier, and the current magnitude circuit means comprises a current lock-in amplifier.

[0009] In some embodiments, the phase circuit means comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

[0010] In some embodiments, the at least one output signal comprises a first output signal of an output phase and a second output signal of an output magnitude.

[0011] In some embodiments, to generate the first impedance based on the EIS model and the at least one output signal, the battery management system is configured to determine the first impedance from a lookup table.

[0012] According to some embodiments of the present disclosure, an example battery management integrated circuit is provided. The battery management integrated circuit can comprise: a battery management processor; an EIS circuit means comprising an excitation circuit means configured to generate an excitation signal; wherein the EIS circuit means is configured to provide the excitation signal to a battery, and receive a response signal from the battery based on the excitation signal; wherein the EIS circuit means further comprises a current sensing circuit means configured to generate a current signal based on the response signal; wherein the EIS circuit means further comprises a voltage sensing circuit means configured to generate a voltage signal based on the excitation signal and the response signal; wherein the EIS circuit means further comprises a phase circuit means configured to generate a phase signal based on the current signal and the voltage signal; wherein the EIS circuit means further comprises a current magnitude circuit means configured to generate a current magnitude signal based on the current signal; wherein the EIS circuit means further comprises a voltage magnitude circuit means configured to generate a voltage magnitude signal based on the current signal; wherein the EIS processor is configured to generate at least one output signal based on the phase signal, the current magnitude signal, and the voltage magnitude signal; and wherein the battery management processor is configured to generate a first impedance based on an EIS model and the at least one output signal.

[0013] In some embodiments, the voltage magnitude circuit means comprises a voltage peak detector, and the current magnitude circuit means comprises a current peak detector.

[0014] In some embodiments, the phase circuit means comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

[0015] In some embodiments, the voltage amplitude circuit means comprises a voltage lock-in amplifier, and the current amplitude circuit means comprises a current lock-in amplifier.

[0016] In some embodiments, the phase circuit means comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

[0017] In some embodiments, the at least one output signal comprises a first output signal of an output phase and a second output signal of an output amplitude.

[0018] In some embodiments, to generate the first impedance based on the EIS model and the at least one output signal, the battery management processor is configured to determine the first impedance from a lookup table.

[0019] According to some embodiments of the present disclosure, an example method is provided. The method can include generating, with excitation circuit means, an excitation signal; sending the excitation signal to a battery to generate a response signal; receiving, at EIS circuit means, the response signal; generating, with the EIS circuit means, a current signal based on the response signal; generating, with the EIS circuit means, a voltage signal based on the response signal and the excitation signal; generating, with phase circuit means, a phase signal based on the current signal and the voltage signal; generating, with current amplitude circuit means, a current amplitude signal; generating, with voltage amplitude circuit means, a voltage amplitude signal; generating at least one output signal based on the phase signal, the current amplitude signal, and the voltage amplitude signal; and determining a first impedance based on an EIS model and the at least one output signal.

[0020] In some embodiments, the voltage amplitude circuit means comprises a voltage peak detector, and the current amplitude circuit means comprises a current peak detector.

[0021] In some embodiments, the phase circuit means comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

[0022] In some embodiments, the voltage amplitude circuit means comprises a voltage lock-in amplifier, and the current amplitude circuit means comprises a current lock-in amplifier.

[0023] In some embodiments, the phase circuit means comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

[0024] In some embodiments, the at least one output signal comprises a first output signal of an output phase and a second output signal of an output amplitude.

[0025] The foregoing summary, being illustrative only, provided for the purpose of summarizing some example embodiments merely to provide a basic understanding of aspects of the disclosure. Accordingly, it will be appreciated that the above-described embodiments are merely examples and should not be construed as limiting the scope or spirit of the disclosure in any way. It will further be appreciated that the scope of the disclosure encompasses many potential embodiments beyond those here summarized, some of which will be further described below. BRIEF DESCRIPTION OF DRAWINGS

[0026] Having thus described certain example embodiments of the disclosure in general terms, reference will now be made to the accompanying drawings, which are not necessarily drawn to scale, and wherein:

[0027] Figure 1 illustrates an example battery and equivalent impedance measurement circuit in accordance with one or more embodiments of the disclosure;

[0028] Figure 2 illustrates an example EIS circuit arrangement in accordance with one or more embodiments of the disclosure;

[0029] Figure 3 illustrates an example battery impedance equivalent circuit arrangement and associated impedance measurement, also known as a Nyquist plot, in accordance with one or more embodiments of the disclosure;

[0030] Figure 4 illustrates example plots of impedance measurements in accordance with one or more embodiments of the disclosure;

[0031] Figure 5 illustrates a first example block diagram for generating EIS measurements in accordance with one or more embodiments of the disclosure;

[0032] Figure 6 illustrates a first example embodiment of a phase and amplitude detector circuit arrangement in accordance with one or more embodiments of the disclosure;

[0033] Figure 7 illustrates a second example embodiment of a phase and amplitude detector circuit arrangement in accordance with one or more embodiments of the disclosure;

[0034] Figure 8 illustrates a third example embodiment of a phase and amplitude detector circuit arrangement in accordance with one or more embodiments of the disclosure;

[0035] Figure 9 illustrates a fourth example embodiment of a phase and amplitude detector circuit arrangement in accordance with one or more embodiments of the disclosure;

[0036] Figure 10 illustrates a fifth example embodiment of a phase and amplitude detector circuit arrangement in accordance with one or more embodiments of the disclosure;

[0037] Figure 11 FIGURE illustrates an exemplary lock-in amplifier circuit arrangement in accordance with one or more embodiments of the disclosure;

[0038] Figure 12 FIGURE illustrates a second exemplary block diagram for generating an EIS measurement in accordance with one or more embodiments of the disclosure;

[0039] Figure 13 FIGURE illustrates an exemplary plot of a filtered output signal in accordance with one or more embodiments of the disclosure;

[0040] Figure 14 FIGURE illustrates an exemplary flowchart of a first set of operations for determining impedance in accordance with one or more embodiments of the disclosure;

[0041] Figure 15 FIGURE illustrates an exemplary flowchart of a second set of operations for determining impedance in accordance with one or more embodiments of the disclosure;

[0042] Figure 16 FIGURE illustrates an exemplary device in accordance with one or more embodiments of the disclosure;

[0043] Figure 17 FIGURE illustrates an exemplary phase-sensitive detector circuit arrangement in accordance with one or more embodiments of the disclosure;

[0044] Figure 18 FIGURE illustrates an exemplary peak detector circuit arrangement in accordance with one or more embodiments of the disclosure;

[0045] Figure 19 FIGURE illustrates an exemplary phase detector circuit arrangement in accordance with one or more embodiments of the disclosure. DETAILED DESCRIPTION

[0046] Some embodiments of the disclosure will now be described more fully hereinafter with reference to the accompanying drawings, in which some, but not all, embodiments of the disclosure are shown. Indeed, the disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will satisfy applicable legal requirements. Like reference numerals refer to like elements throughout.

[0047] As used herein, the term “comprising” means including, but not limited to, and should be interpreted in the manner it is typically used in the patent context; that is, in the sense of “including, but not limited to” rather than in the sense of “consisting only of.” The use of the more broad term “comprising” is not a limitation of the disclosed embodiments. The use of the more narrow term “consisting of” is not a limitation of the disclosed embodiments. The use of the term “consisting essentially of’ reserves the right to include additional elements incidental to the practice of the disclosure, but excludes elements that materially affect the basic and novel characteristics of the composition or method.

[0048] The phrases “in various embodiments,” “in one embodiment,” “according to one embodiment,” “in some embodiments,” and the like generally mean that the particular feature, structure, or characteristic following the phrase can be included in at least one embodiment of the present disclosure, and can be included in more than one embodiment of the present disclosure (importantly, such phrases are not necessarily referring to the same embodiment). In the following description, numerous specific details are discussed to provide a thorough and enabling description for embodiments of the present disclosure. One skilled in the relevant art will recognize that the aspects of the present disclosure can be practiced without resorting to these specific details.

[0049] The use of the word “example” or “exemplary” is intended to present what is considered, for purposes of explanation, to be an example or instance; the include things that are not to be considered as necessarily the best, advantageous, or important example or instance.

[0050] If the specification states a component, or feature “may,” “can,” “could,” “should,” “would,” “preferably,” “possibly,” “typically,” “optionally,” “for example,” “often,” or “probably” (or other similar language) be included or have a particular feature, an specific component or feature need not be included or have that feature. Such components or features can be optionally included in some embodiments or can be excluded.

[0051] The term “circuitry” as used herein with respect to components of a system or device should be understood to include the specific hardware configured to perform the functions associated with the particular circuitry described herein. The term “circuitry” should be interpreted broadly to encompass both a purely hardware circuit implementation as well as a combination of hardware circuitry and software that work together to perform the functions described for a given circuitry. For example, in some embodiments, “circuitry” can include processing circuitry, communication circuitry, input / output circuitry, and the like. In some embodiments, other elements can provide or supplement the functionality of a particular circuitry.

[0052] SUMMARY

[0053] Various embodiments of the present disclosure relate to improved systems, devices, and methods for electrochemical impedance spectroscopy (EIS) for use with a battery, and in particular, to improved systems, devices, and methods for EIS phase and amplitude detection of an excited system. In various embodiments, the excited system can be a battery that is excited with an excitation signal that is generated for use in detecting the phase and amplitude of impedance using EIS.

[0054] Batteries are included in a variety of applications. Exemplary applications include, but are not limited to, power tools, automobiles, and consumer electronics. Batteries in these applications can refer to individual battery cells or battery packs that include multiple battery cells. Embodiments of the present disclosure can use the phrase battery to refer to an individual battery cell or multiple battery cells.

[0055] Management of the battery can be performed with a battery management system. In various applications, the battery management system can be referred to as a battery management subsystem. Further, the battery management system can determine a state of health of the battery. The state of health of the battery deteriorates with use and aging through repeated charge / discharge cycles. Determining the state of health of the battery can indicate whether the battery is healthy, aging, or how much time the battery has before needing replacement. Such indications help prevent damage, explosion of the battery, and / or suggest when to replace a new battery.

[0056] For example, an electric vehicle can use multiple battery packs. Each battery pack can include multiple battery cells. The battery cells collectively provide power storage for the electric vehicle. A battery management system of the electric vehicle can be used to monitor the health of the battery using EIS such as described herein.

[0057] One way to determine the state of health of the battery is with electrochemical impedance spectroscopy (EIS). EIS evaluates the battery chemistry of the battery, focusing on an equivalent circuit model. In this equivalent circuit model, the battery can be modeled as a voltage source and an impedance.

[0058] The impedance is made up of a real component and an imaginary component. As the battery ages or is damaged, the impedance changes. These changes can be demonstrated by a plot of how the real component and imaginary component of the impedance change over time. The impedance can vary with frequency, which can also be plotted. An EIS system can determine the impedance at various frequencies, such as with a frequency sweep or by utilizing excitation signals at various frequencies.

[0059] EIS applies an excitation signal to the battery and measures a voltage and current associated with the response of the battery to the excitation signal, which is described as a response signal. An EIS circuit device can include or be used with a voltage sensor, a current sensor, and / or a phase sensor. By detecting the voltage, current, and phase, embodiments of the present disclosure can generate a state of health of the battery.

[0060] In addition to the state of health, EIS of the response signal can be utilized to estimate a state of charge of the battery as well as an internal temperature, which can be used to prevent events such as thermal runaway. EIS can measure temperature indirectly, including without or in addition to a temperature sensor. Additionally, in various embodiments, a temperature sensor can be located externally to the battery cell and measure the temperature at its location, while in addition, EIS is used to determine the temperature of the battery based on the battery chemistry inside the battery.

[0061] In various embodiments, a system or device can include a battery management system. The EIS circuitry can be included in the battery management system, or can be provided along with the battery management system. The battery management system can receive impedance values from the EIS circuitry, which can be provided as individual values or as magnitude and phase values. Each of these values can be provided as a signal generated by the EIS system that is associated with the value, such as a related voltage value or current value associated with one value (e.g., a 3 volt signal can be associated with the maximum voltage of the battery). The battery management system can receive these signals, and generate one or more alert signals or status signals based on the signals. One or more additional portions of the system or device can receive these signals sent from the battery management system, and perform one or more operations based on the signals, such as displaying an alert, sending an alert, stopping battery operation, etc.

[0062] Batteries, especially in higher power applications, utilize battery management systems to analyze and evaluate the battery. This can include determining the state of health of the battery. Conventional systems can utilize digital processing of sampled data, such as fast Fourier transforms, machine learning, artificial intelligence, etc. Additionally, conventional systems implementing EIS take a greater amount of time to process, respectively, due at least in part to the frequency of the conventional excitation signals. Such conventional excitation signals can range from mHz to kHz, thus, signals with longer time periods take longer to sample and digitally process. Such conventional systems require a large amount of memory and computational resources to process such sampled data. Embodiments of the present disclosure provide numerous improvements over such conventional systems. Embodiments of the present disclosure include a method for determining phase and magnitude used in EIS that allows for lower memory requirements and lower computational resources. One example of lower computational requirements is the use of embodiments configured with analog circuitry to reduce operations that might otherwise be performed with digital computation. Various embodiments of the present disclosure synchronously acquire voltage and current associated with a response signal of a battery with analog circuitry, which improves the speed of EIS analysis. Further, such analog circuitry can reduce the physical space or footprint required to implement embodiments, which can also reduce costs. Additionally or alternatively, embodiments of the present disclosure include improvements that measure reduced harmonic content of the signal.

[0063] Exemplary systems, devices, and methods

[0064] Figure 1 An example battery and equivalent circuit are illustrated in accordance with one or more embodiments of the present disclosure. The battery 100 has battery chemistry associated with an equivalent circuit including a voltage source 110, a current 120, and an impedance 130. The impedance 130 can be measured based on the voltage of the voltage source 110 and the current.

[0065] EIS measurements can be performed during battery charging and discharging. Voltage measurements can be V(t) of the equivalent voltage source 110, which is illustrated as open circuit voltage V OCV . Current measurements can be I(t) of the equivalent current through impedance 130 Z(jco). The measurements of voltage V(t) and current I(t) can be used to evaluate impedance 130 Z(jco) of battery 100.

[0066] While battery 100 is illustrated as a single battery, battery 100 can include multiple battery cells. Impedance 130 can be measured at each battery cell, all battery cells together, or as one or more groupings of multiple battery cells.

[0067] Figure 2 An exemplary EIS circuit arrangement is illustrated in accordance with one or more embodiments of the present disclosure. Further, the EIS circuit arrangement can include an excitation circuit arrangement 210, a current sense circuit arrangement 220, a voltage sense circuit arrangement 230, and a sense resistor 240. The EIS circuit arrangement can be electrically connected to at least one battery 100.

[0068] The EIS circuit arrangement includes multiple analog circuit arrangements and / or circuit components to minimize the required digital computation. In various embodiments, the EIS circuit arrangement includes an EIS processor in addition to analog circuits. The EIS processor (e.g., MCU) can interface with a battery management system (BMS).

[0069] The EIS circuit arrangement measures the current and voltage of the battery’s response to an excitation signal. The excitation signal is generated by the excitation circuit arrangement 210.

[0070] The excitation circuit arrangement 210 generates an excitation signal and provides it to the battery 100, and measures the current and voltage response signals. Voltage and current measurements can be taken synchronously for generating one or more signals to generate impedance 130. The sense resistor 240, which is illustrated as RSENSE 240, is measured across. The current is measured with the current sense circuit arrangement 220 to generate a current signal. The voltage is measured based on the excitation signal and the response signal. The voltage is measured with the voltage sense circuit arrangement 230 to generate a voltage signal. These voltage and current measurements are used to determine impedance. Alternatively or additionally, various embodiments can use a Hall sensor and / or a transformer to measure current.

[0071] Figure 3 An exemplary equivalent circuit arrangement and associated impedance measurements are illustrated in accordance with one or more embodiments of the present disclosure. Different parts of a battery (e.g., chemical and / or physical parts or aspects) can have different electronic component equivalents. It should be appreciated that, Figure 3is illustrative, and various portions of the impedance can not conform to size and / or impedance and can be associated with other models that include one or more electrical components. These different electrical component equivalents are associated with impedance measurements. The exemplary equivalent circuit 310 associated with the impedance 130 of the battery 100 varies with frequency. For example, from frequencies with longer time periods (e.g., kHz) to frequencies with shorter time periods (e.g., pHz), the equivalent circuit device of the impedance can be an inductor (L), a first resistor (R o ), a second resistor (R1) in parallel with a first capacitor (C1), a third resistor (R2) in parallel with a second capacitor (C2), which is referred to in Figure 3 with reference number 312, and a resistor (R W ). For EIS measurements, the impedance of the third resistor (R2) in parallel with the second capacitor (C2) can be used, referred to as 322, as these values change as the battery ages or is damaged.

[0072] Figure 3 The top portion of the graph 320 is a plot of the positive real part of the impedance on the x-axis and the negative imaginary part of the impedance on the y-axis. The y-axis using the negative imaginary part of the impedance 322 is due to the capacitor in the equivalent model, as capacitors have a negative imaginary impedance. Changes in the impedance 322 over time can be plotted, which can demonstrate how the impedance 322 changes as it ages and / or is damaged.

[0073] Figure 4 An example graph of impedance measurements is illustrated in accordance with one or more embodiments of the disclosure. The graph 400 includes impedance measurements of the battery 100 over time after different cycle counts, including the impedance 322.

[0074] The graph 400 is a Nyquist plot that includes 10 impedances measured for the battery 100 after 10 cycles of 100 cycles.

[0075] The first impedance 410A is after 100 cycles.

[0076] The second impedance 410B is after 200 cycles.

[0077] The third impedance 410C is after 300 cycles.

[0078] The fourth impedance 410D is after 400 cycles.

[0079] The fifth impedance 410E is after 500 cycles.

[0080] The sixth impedance 410F is after 600 cycles.

[0081] The seventh impedance 410G is after 700 cycles.

[0082] The eighth impedance, 410H, is achieved after 800 cycles.

[0083] The ninth impedance, 410I, is achieved after 900 cycles.

[0084] The tenth impedance, 410J, is achieved after 1000 cycles.

[0085] like Figure 4 As illustrated, the impedance 322 of battery 100 increases from 100 cycles (e.g., 410 A) to 1000 cycles (e.g., 410 J) through cyclic aging. Specifically, the arc of impedance 322, which is the second arc, widens with aging. As illustrated, impedance is measured at multiple frequencies, such as using frequency scanning. In various embodiments, frequency scanning can be performed by changing the frequency of the excitation signal supplied to battery 100. By determining the impedance measurement, the health status of the battery can be determined.

[0086] Figure 5 A first exemplary block diagram for generating EIS measurements according to one or more embodiments of the present disclosure is illustrated. Figure 5 The system includes a battery 10 and an EIS circuitry 510, which may include an excitation circuitry 210 and a phase and amplitude detector circuitry 520. The EIS circuitry 510 generates an excitation signal and analyzes a response signal 514 and the excitation signal 512 to generate one or more output signals 522. The excitation circuitry 210 can generate the excitation signal 512 (also referred to as the excitation signal), which can be provided to the battery 100 and the phase and amplitude detector circuitry 520. The excitation signal 512 can cause the battery 100 to generate a response signal 514, which is provided to and received by the EIS circuitry 510. The response signal 514 can be provided to the phase and amplitude detector circuitry 520. The phase and amplitude detector circuitry 520 can generate at least one output signal 522. In various embodiments, the output signals 522(one or more) can be provided to an external system, device, apparatus, or application 540, such as a battery management system.

[0087] In various embodiments, the output signal(s) 522 may be a single signal or multiple signals. For example, the output signal(s) 522 may be a phase output signal associated with the impedance of the battery and generated by the phase and amplitude detector circuitry 520. The output signal(s) 522 may be a phase output signal associated with the impedance of the battery and an amplitude output signal associated with the impedance of the battery, each of which is generated by the phase and amplitude detector circuitry 520. The output phase signal may be the phase of the response signal relative to the excitation signal. The output amplitude signal may be the amplitude of the response signal.

[0088] In various embodiments, the EIS circuitry 510 can be part of a battery management system. The battery management system can provide one or more input signals to the field circuitry 210 for generating the excitation signal 512. The generated excitation signal 512 can be a sinusoidal wave, a square wave, a triangular wave, etc. The frequency of the excitation signal 512 can vary over time, and / or multiple excitation signals 512 can be generated to vary the frequency.

[0089] In various embodiments, the EIS circuitry and / or the phase and amplitude detector circuitry 520 can include the current sense circuitry 220, the voltage sense circuitry 230, a phase circuitry, a current amplitude circuitry, a voltage amplitude circuitry, and / or an EIS processor. Alternatively or additionally, the EIS circuitry can include a square wave generator circuitry, a PSD circuitry, a filter circuitry, and / or an EIS processor. In various embodiments, the phase circuitry can be a PSD circuitry (e.g., 622), a phase detector circuitry (e.g., 722), or a phase lock amplifier circuitry (e.g., 822). In various embodiments, the current amplitude circuitry can be a current peak detector circuitry (e.g., 624) or a current lock amplifier circuitry (e.g., 824). In various embodiments, the voltage amplitude circuitry can be a voltage peak detector circuitry (e.g., 626) or a voltage lock amplifier circuitry (e.g., 826). The EIS processor (e.g., 630, 730, 830, 930, 1030, 1250) can be in the phase and amplitude detector circuitry 520. Alternatively or additionally, the EIS processor can be elsewhere in the EIS circuitry 510 or outside the EIS circuitry 510. For example, in various embodiments, the EIS processor can be a battery management system processor and / or a processor of another application or system. In various embodiments, the EIS circuitry and / or the phase and amplitude detector circuitry 520 can also include one or more multipliers and / or filters. Although Figures 6-10 and Figure 12 Various embodiments of the phase and amplitude detector circuitry of the EIS circuitry are illustrated, but it should be understood that there are additional embodiments not illustrated that are consistent with the description herein.

[0090] Figure 6 A first exemplary embodiment of a phase and amplitude detector circuitry in accordance with one or more embodiments of the present disclosure is illustrated.

[0091] The first exemplary embodiment of the phase and amplitude detector circuit arrangement 510 can receive the excitation signal 512 and the response signal 514. The current sense circuit arrangement 220 can generate and output a current signal based on the measured current across the sense resistor 240. The voltage sense circuit arrangement 230 can generate and output a voltage signal based on the measured voltage between the excitation signal 512 and the response signal 514. The current signal generated by the current sense circuit arrangement 220 can be output and provided to a phase sensitive detector (PSD) circuit arrangement 622 and a current peak detector circuit arrangement 624. The voltage signal generated by the voltage sense circuit arrangement 230 can be output and provided to the PSD circuit arrangement 622 and a voltage peak detector circuit arrangement 626. In various embodiments, the current sense circuit arrangement 220 can be a current sensor that generates an output signal, the current signal, which can be a voltage and / or a current that varies with and / or is proportional to the measured current. In various embodiments, the voltage sense circuit arrangement 230 can be a voltage sensor that generates an output signal, the voltage signal, which can be a voltage and / or a current that varies with and / or is proportional to the measured voltage.

[0092] In various embodiments, the PSD circuit arrangement 622 includes analog circuitry of a phase detector circuit, including multiple resistors, operational amplifiers, switches, and capacitors. The operational amplifiers can use positive feedback, and the switches can control the grounding of the reference signal m. The PSD circuit arrangement 622 can generate an output y based on a first input signal x (e.g., the current signal) and a second input signal m (e.g., the voltage signal). The output y can be mathematically represented as where X is the amplitude of the input signal x, M is the amplitude of the reference signal m, and ΔΦ is the phase difference between the phase of the input signal x and the phase of the reference signal m. As Figure 6 illustrated, the outputs of the current sense circuit arrangement 220 and the voltage sense circuit arrangement 230 are input into the PSD circuit arrangement 622 to measure the phase shift between the current signal and the voltage signal. In Figure 17 an exemplary embodiment of the PSD circuit arrangement 622 is illustrated. In various embodiments, offset removal filter(s) can precede the PSD circuit arrangement 622.

[0093] The current peak detector circuit arrangement 624 can include analog circuitry that can detect the peak of the current signal. The peak of the current signal can be the amplitude of the current signal. The output y of the current peak detector circuit arrangement 624 can be mathematically represented as y(t) = I. In various embodiments, this can be referred to as a current amplitude signal. In Figure 18 an exemplary embodiment of a peak detector circuit arrangement, such as the current peak detector circuit arrangement 624, is illustrated.

[0094] The voltage peak detector circuit device 626 can include an analog circuit device that can detect a peak value of the voltage signal. The peak value of the voltage signal can be the amplitude of the voltage signal. The output y of the current peak detector circuit device 624 can be mathematically represented as y(t) = V. In various embodiments, this can be referred to as a voltage amplitude signal.

[0095] The EIS processor 630 can receive the output of the PSD circuit device 622, the output of the current peak detector circuit device 624, and the output of the voltage peak detector circuit device 626. Based on these inputs, the EIS processor can determine an output of the phase of cos AΦ by using a division operation. Thus, the EIS processor can be configured to perform at least a division operation. Such an operation to determine a phase measurement of the impedance is an improvement due to a reduction in computational resources and time required.

[0096] Figure 7 A second exemplary embodiment of a phase and amplitude detector circuit device is illustrated in accordance with one or more embodiments of the present disclosure. The second exemplary embodiment of the phase and amplitude detector circuit device 520 is similar to the illustrated embodiment, but this embodiment includes a phase detector circuit device 722 and an EIS processor 730. Figure 6

[0097] The phase detector circuit device 722 can receive the current signal from the current sense circuit device 220 and the voltage signal from the voltage sense circuit device 230. In various embodiments, the phase detector circuit device 722 can include a plurality of operational amplifiers and XOR gates. The output y of the phase detector circuit device can be mathematically represented as y(t) = At. In various embodiments, the phase detector circuit device 722 can be configured to perform at least a subtraction operation. Figure 19 An exemplary embodiment of the phase detector circuit device 722 is illustrated in

[0098] The EIS processor 730 can receive the output of the phase detector circuit device 722, the output of the current peak detector circuit device 624, and the output of the voltage peak detector circuit device 626. Based on these inputs, the EIS processor 730 can determine an output of the amplitude value and the phase angle by using a division operation. For example, the EIS processor 730 can generate output signals yl and y2, where and where Twave is the known frequency of the excitation signal 512. Thus, the EIS processor 730 can be configured to perform at least a division operation.

[0099] Figure 8 A third exemplary embodiment of a phase and amplitude detector circuit device is illustrated in accordance with one or more embodiments of the present disclosure. The third exemplary embodiment of the phase and amplitude detector circuit device 520 is similar to the illustrated embodiment, Figure 6 ​and Figure 7 The illustrated embodiment, however, includes a phase lock amplifier circuit device 822, a current lock amplifier circuit device 824, a voltage lock amplifier circuit device 824, and an EIS processor 830.

[0100] The phase lock amplifier circuit device 822, the current lock amplifier circuit device 824, and the voltage lock amplifier circuit device 824 each use a lock amplifier. In Figure 12 An exemplary embodiment of a lock amplifier is illustrated in

[0101] The phase lock amplifier circuit device 822 inputs a current signal as a first input and a voltage signal as a second input. The output y of the phase lock amplifier circuit device can be mathematically represented as:

[0102] The current lock amplifier circuit device 824 inputs a current signal to both inputs of the lock amplifier. The output y of the current lock amplifier circuit device is the square of the magnitude of the input, which can be mathematically represented as: y(t) = I 2 .

[0103] The voltage lock amplifier circuit device 826 inputs a voltage signal to both inputs of the lock amplifier. The output y of the voltage lock amplifier circuit device is the square of the magnitude of the input, which can be mathematically represented as: y(t) = V 2 .

[0104] The EIS processor 830 can receive the output of the phase lock amplifier circuit device 822, the output of the current lock amplifier circuit device 824, and the output of the voltage lock amplifier circuit device 826. Based on these inputs, the EIS processor 830 can determine the output of the phase of cos A by using a division operation. Thus, the output of the respective lock amplifier circuit device is different than the output of other embodiments, but allows for a similar determination of cos A as is made in various other embodiments.

[0105] Various embodiments can include lock amplifier circuit devices and peak detector circuit devices.

[0106] Figure 9 A fourth exemplary embodiment of a phase and amplitude detector circuit device is illustrated in accordance with one or more embodiments of the present disclosure. The fourth exemplary embodiment of the phase and amplitude detector circuit device 520 is similar to the other illustrated embodiments, but this fourth exemplary embodiment includes a phase lock amplifier circuit device 822, a current peak detector circuit device 624, a voltage peak detector circuit device 626, and an EIS processor 930.

[0107] As described herein, the phase-locked amplifier circuit device 822 generates an output that can be mathematically represented as

[0108] As described herein, the current peak detector circuit device 624 generates an output that can be mathematically represented as y(t) = I.

[0109] As described herein, the voltage peak detector circuit device 626 generates an output that can be mathematically represented as y(t) = V.

[0110] The EIS processor 930 can receive the outputs of the phase-locked amplifier circuit device 822, the current peak detector circuit device 624, the voltage peak detector circuit device 626. Based on these inputs, the EIS processor 930 can determine the phase output of cos ΔΦ by using multiplication and division operations.

[0111] Figure 10 A fifth exemplary embodiment of a phase and amplitude detector circuit device is illustrated in accordance with one or more embodiments of the present disclosure. In the fifth exemplary embodiment of the phase and amplitude detector circuit device 520, portions of the circuit device are implemented digitally. The current signal and the voltage signal can be provided as inputs to the EIS processor 1030. The EIS processor can be configured to perform one or more operations for multiplication and filtering (e.g., a Butterworth filter) to generate output signals of voltage, current, and phase.

[0112] Figure 11 An exemplary lock-in amplifier circuit device is illustrated in accordance with one or more embodiments of the present disclosure. The lock-in amplifier circuit device 1200 includes an analog multiplier 1220 and a low pass filter circuit device 1230. The analog multiplier is a multiplier circuit device that multiplies an input signal 1202 with a reference signal 1204. Further, the product of this multiplication will contain higher frequency components that are twice the frequency of the excitation signal 1212 and the response signal 1214. The product signal is provided to the low pass filter circuit device 1230, which allows low frequencies to pass through while higher frequencies are filtered out. In various embodiments, the low pass filter circuit device 1230 includes a resistor and a capacitor. With an input signal A and a reference signal B, the lock-in amplifier circuit device 1200 generates an output that can be mathematically represented as

[0113] Figure 12 A second exemplary block diagram for generating an EIS measurement is illustrated in accordance with one or more embodiments of the present disclosure. Figure 12A battery 100 and EIS circuitry 1210 configured to generate impedance measurements is illustrated. The EIS circuitry 1210 includes excitation circuitry 210 that generates an excitation signal 1212. The excitation signal 1212 is sent to the battery 100, and a response signal is received from the battery 100 based on the excitation signal 100.

[0114] The excitation signal 1212 is also sent to square wave generator circuitry 1220. The square wave generator circuitry 1220 generates a square wave signal based on the excitation signal of a plurality of square waves. In various embodiments, the square wave generator circuitry 1220 generates three square waves: a first square wave with a 0 degree offset, a second square wave with a 90 degree offset, and a third square wave with a 180 degree offset. The square wave signal is sent to PSD circuitry 1230. In various embodiments, the excitation circuitry 210 and the square wave generator circuitry 1220 can be driven or controlled by one or more unillustrated processors, such as by a battery management system processor, which in addition can provide clock signals and / or instructions, etc. to start and / or end one or more operations.

[0115] The PSD circuitry 1230 receives the excitation signal 1212, the response signal 1214, and / or the square wave signal. The PSD circuitry 1230 compares two or more of these signals to generate one or more output signals.

[0116] In various embodiments, the PSD circuitry 1230 can determine the amplitudes of the voltage and current, which can depend on the input signal being evaluated. The impedance magnitude and phase can be determined as the ratio of the voltage to the current (i.e., V / I) and The output of the PSD circuitry 1230 can be similar to the output described herein for the PSD circuitry 622.

[0117] In various embodiments, the excitation signal 1212 can be sinusoidal, such as a cosine. The PSD circuitry 1230 can generate three output signals based on the response signal 214 and the three square waves in the square wave signal, each output signal to be proportional to the amplitude and phase cosine of the response signal 214 plus a 0 degree, 90 degree, or 180 degree offset. These output signals, which can also be referred to as comparison signal(s), contain the offset due to the initial offset of the battery response. The three output signals can be mathematically characterized as:

[0118]

[0119]

[0120]

[0121] The offset can be determined by an addition operation:

[0122]

[0123] The offset can be removed with filter circuitry 1240, which can include one or more filters. The filtered output signals can be mathematically represented as:

[0124]

[0125]

[0126] The three filtered output signals are provided to EIS processor 1250, which can perform one or more simple additions, divisions, or arctangent functions to determine the phase and magnitude of the impedance. The phase can be determined by dividing the first filtered output wave y(0°) by the second filtered output wave y(90°). For example, such a division removes the magnitude from the signal, and the arctangent function allows the phase angle to be determined. This can be mathematically represented as:

[0127]

[0128] Determining the magnitude can be done with a division operation by dividing the y(0°) signal by the angle cosine.

[0129] Thus, the phase and magnitude of the impedance from the response signal 214 can be determined. While Figure 12 Filter circuitry 1240 is illustrated, which can be analog circuitry, but in various embodiments, the filtering can be performed digitally by EIS processor 1250.

[0130] Various embodiments of EIS processors (e.g., 1250) allow for simple processing of signals using simple division operations, multiplication operations, addition operations, low pass filter operations, etc., allowing for faster processing with lower computational resources.

[0131] Figure 13 An exemplary graph of the filtered output signals is illustrated in accordance with one or more embodiments of the present disclosure. Graph 1300 is the filtered offset signal, and is after the offset of each of the three filtered offset signals has been removed. This allows only lower frequency signals to pass. As illustrated in the graph, the filtered offset signal reaches a steady state value. In various embodiments, this steady state value can be reached within, for example, 6 cycles. In various embodiments, such a fast steady state can reduce the computational requirements of any associated analog-to-digital converter associated with the EIS measurement.

[0132] Figure 14An exemplary flowchart of a first set of operations for generating an impedance in accordance with one or more embodiments of the present disclosure is illustrated. In various embodiments, Figure 14 The operations can be associated with generating an impedance using an embodiment of an EIS circuit arrangement 510 such as at least Figure 5 illustrated in FIG. 6.

[0133] At operation 1402, an excitation signal is generated. As described herein, the excitation signal can be generated by an excitation circuit arrangement 210.

[0134] At operation 1404, the excitation signal is sent to the battery. The excitation circuit arrangement 210 of an EIS circuit arrangement (e.g., 510) can send the excitation signal to the battery 100. In various embodiments, the excitation signal can also be sent to a phase and amplitude detector circuit arrangement 520.

[0135] At operation 1406, a response signal is received from the battery. The EIS circuit arrangement (e.g., 510) receives a response signal 214 from the battery 100. The response signal 514 is responsive to the excitation signal 512 provided to the battery 100.

[0136] At operation 1408, a current signal is acquired based on the response signal. The current sensing circuit arrangement 220 of the EIS circuit arrangement 510 can acquire a current signal based on the response signal 214. The current signal is based on the current of the response signal 214 measured across the sense resistor 240, which can acquire a current signal proportional to the measured current.

[0137] At operation 1410, a voltage signal is acquired based on the response signal and the excitation signal. The voltage sensing circuit arrangement 230 of the EIS circuit arrangement 510 can acquire a voltage signal based on the response signal 514 and the excitation signal 514. The voltage signal is based on the voltage measured between these two signals, which can acquire a voltage signal proportional to the measured voltage.

[0138] At operation 1412, a phase signal is generated. A phase circuit arrangement can generate a phase signal based on the current signal and the voltage signal. In various embodiments, the phase circuit arrangement can be a PSD circuit arrangement (e.g., 622), a phase detector circuit arrangement (e.g., 722), or a phase lock amplifier circuit arrangement (e.g., 822).

[0139] At operation 1414, a current amplitude signal is generated. A current amplitude circuit arrangement can generate a current amplitude signal based on the current signal. In various embodiments, the current amplitude circuit arrangement can be a current peak detector circuit arrangement (e.g., 624) or a current lock amplifier circuit arrangement (e.g., 824).

[0140] At operation 1416, a voltage magnitude signal is generated. The voltage magnitude circuitry can generate the voltage magnitude signal based on the voltage signal. In various embodiments, the voltage magnitude circuitry can be a voltage peak detector circuitry (e.g., 626) or a voltage lock-in amplifier circuitry (e.g., 826).

[0141] At operation 1418, at least one output signal is generated. The phase signal, the current magnitude signal, and the voltage signal are provided to an EIS processor. The EIS processor can generate the at least one output signal based on the phase signal, the current magnitude signal, and the voltage signal. The EIS processor can be configured to perform one or more operations, such as a division operation, a multiplication operation, an addition operation, a low-pass filtering operation, and the like, to generate the one or more output signals. In various embodiments, such output signals can be signals proportional to the phase, the magnitude, and / or the magnitude and phase of the impedance.

[0142] At operation 1420, an impedance is determined based on the at least one output signal. The at least one output signal can be provided to a battery management system, which can determine the impedance based on the at least one output signal. In various embodiments, the at least one output signal is proportional to the phase, the magnitude, and / or the magnitude and phase of the impedance. The battery management system can use a lookup table to determine an impedance value associated with the at least one output signal. In various embodiments, a plurality of output signals is generated via a plurality of excitation signals, including excitation signals from different frequencies. For example, one or more excitation signals can perform a frequency sweep on the excited battery 100. These multiple impedances can be used to determine how the battery ages, as Figure 4 explained.

[0143] Figure 15 FIG. illustrates an example flow diagram of a second set of operations for generating an impedance, in accordance with one or more embodiments of the present disclosure. In various embodiments, Figure 15 operations can be associated with generating an impedance using embodiments of EIS circuitry 1210 such as at least Figure 12 illustrated in FIG. 13.

[0144] At operation 1502, an excitation signal is generated. This operation is similar to operation 1402 described herein.

[0145] At operation 1504, the excitation signal is sent to a battery. This operation is similar to operation 1404 described herein.

[0146] At operation 1506, a response signal is received from the battery. The EIS circuitry (e.g., 1210) receives a response signal 214 from the battery 100. The response signal 214 is in response to the excitation signal 1212 provided to the battery 100.

[0147] At operation 1508, square wave signal(s) are acquired based on the excitation signal. Square wave signals comprising a plurality of square waves are generated by square wave generator circuitry 1220. The square wave signals can be based on the excitation signal 1212 having three sets of square waves each at a different phase. The different phases can be 0 degrees, 90 degrees, and 180 degrees.

[0148] At operation 1510, the response signal is compared to the square wave signal. PSD circuitry 1230 can compare the response signal 214 to the square wave signal to generate a compared signal. The compared signal can include an offset as described herein.

[0149] At operation 1512, the compared signal(s) are filtered. Filtering circuitry 1240 can filter the compared signal(s), such as with a low pass filter. Filtering the compared signal can remove the offset. The filtered signal can be provided to the EIS processor.

[0150] At operation 1514, at least one output signal is generated. The EIS processor can generate at least one output signal as described herein.

[0151] At operation 1516, an impedance is determined based on the at least one output signal. This operation is similar to operation 1420 described herein.

[0152] Figure 16 An exemplary device is illustrated in accordance with one or more embodiments of the present disclosure. Device 1600 can be a device for an application and / or system. For example, device 1600 can be a power tool, an electric vehicle, a consumer electronic product, etc. The illustrated device 1600 can be a system and / or apparatus that includes a processor 1602, a memory 1604, communication circuitry 1606, input / output circuitry 1608, a battery 1612, a battery management system 1614, EIS circuitry 1616, and all of these can be connected by one or more buses 1610. While such connections are illustrated as buses 1610, it should be readily understood that there can be numerous other connections.

[0153] Although processor 1602 is illustrated as a single block, it can include a plurality of components and / or processor circuitry. Processor 1602 can be implemented as, for example, various components including one or more microprocessors having accompanying digital signal processors; one or more processors without accompanying digital signal processors; one or more coprocessors; one or more multi-core processors; processing circuitry; and various other processing elements. The processor can include integrated circuitry. In various embodiments, processor 1602 can be configured to execute instructions stored in processor 1602, memory 1604, or an application, instructions, and / or program accessible to processor 1602. When executed by processor 1602, these instructions can enable the performance of one or more operations and / or functions described herein. Whether configured by hardware or by a combination of hardware and software methods, processor 1602 can include entities that, when configured, enable the performance of operations and / or functions according to embodiments of the present disclosure.

[0154] Memory 1604 can include, for example, volatile memory, non-volatile memory, or a specific combination thereof. Although illustrated as a single block, memory 1604 can include a plurality of memory components. In various embodiments, memory 1604 can include, for example, random access memory, cache memory, flash memory, hard disk, circuitry configured to store information, or a combination thereof. Memory 1604 can be configured to write or store data, information, application programs, instructions, etc., such that processor 1604 can perform various operations and / or functions according to embodiments of the present disclosure. For example, in at least some embodiments, memory 1604 can be configured to buffer or cache data processed by processor 1602. Additionally or alternatively, in at least some embodiments, memory 1604 can be configured to store program instructions executed by processor 1602. Memory 1604 can store information in the form of static and / or dynamic information. The stored information can be stored and / or used by processor 1602 when performing operations and / or functions.

[0155] The communication circuitry 1606 can be implemented as circuitry, hardware, a computer program product, or a combination thereof configured to receive data from and / or transmit data to another component or device. The computer program product can include computer-readable program instructions stored on a computer-readable medium (e.g., the memory 1604) and implemented by the processor 1602. In various embodiments, the communication circuitry 1606 (as with the other components discussed herein) can be implemented at least in part as a portion of the processor 1602, otherwise controlled by the processor 1602. The communication circuitry 1606 can be in communication with the processor 1602, for example, through the bus 1610. Such a bus 1610 can be connected to the processor 1602, and it can also be connected to one or more other components of the processor 1602. The communication circuitry 1606 can include, for example, a transmitter, a receiver, a transceiver, a network interface card, and / or supporting hardware and / or firmware / software, and can be used to establish communications with another component, device, and / or system. The communication circuitry 1606 can be configured to receive and / or transmit data that can be stored by, for example, the memory 1604, using one or more protocols that can be used for communication between components, devices, and / or systems.

[0156] The input / output circuitry 1608 can be in communication with the processor 1602 to receive instructions and / or to provide auditory, visual, mechanical, or other output to an operator. The input / output circuitry 1608 can include supporting devices, such as a keyboard, a mouse, a user interface, a display, a touch screen display, lights (e.g., warning lights), indicators, a speaker, and / or other input / output mechanisms. The input / output circuitry 1608 can include one or more interfaces to which the supporting devices can connect. In various embodiments, aspects of the input / output circuitry 1608 can be implemented on devices used by an operator to communicate with the processor 1602. The input / output circuitry 1608 can be in communication with the memory 1604, the communication circuitry 1606, and / or any other components, for example, through the bus 1610.

[0157] The battery 1612 can provide power to the device 1600. In various embodiments, the battery 1612 can be a single battery cell, or can be a plurality of battery cells forming one or more battery packs.

[0158] The battery management system 1614 can include the EIS circuitry 1616, one or more dedicated processors, one or more dedicated memories, and / or additional electronic components. In various embodiments, the EIS circuitry 1616 can be configured as described herein and configured to perform one or more operations as described herein. The EIS circuitry can generate one or more output signals that can be provided to the battery management system 1614 to determine and / or generate an impedance of the battery 1612. In various embodiments, the impedance of the battery 1612 can be determined via a lookup table based on the output signal(s) of the EIS circuitry 1616. Further, the battery management system 1614 can use the impedance of the battery 1612 to determine a state of health of the battery. The device 1600 can generate or perform one or more operations based on the state of health of the battery 1612, such as stopping battery operation, shutting down the device 1600, generating, displaying, and / or sending an alert message, etc.

[0159] Figure 17 An exemplary phase sensitive detector circuit is illustrated in accordance with one or more embodiments of the present disclosure. In various embodiments, a phase sensitive detector (PSD) circuit 1710 can include analog circuitry of a phase detector circuit, including a plurality of resistors, operational amplifiers, switches, and capacitors. The PSD circuit can receive a first signal X 1712 and a second signal M 1714 as inputs and generate an output signal Y 1716, such as described herein.

[0160] Figure 18 An exemplary peak detector circuit is illustrated in accordance with one or more embodiments of the present disclosure. In various embodiments, a peak detector circuit 1810 can include analog circuitry of an operational amplifier, diode(s), capacitor(s), and resistor(s). The peak detector circuit 1810 can receive a first signal X as an input and generate an output signal Y, such as described herein.

[0161] Figure 19is an exemplary phase detector circuit arrangement according to one or more embodiments of the present disclosure. In various embodiments, the phase detector circuit arrangement 1910 can include two flip-flops and an XOR gate. A first signal X 1912 and a second signal M 1914 can be input into the phase detector circuit arrangement 1910, which can generate an output signal Y 1916. This output can be mathematically represented as y(t) = At, such as described herein. At represents a time period proportional to the phase difference between the two input signals. In various embodiments, the phase detector circuit arrangement 1910 can be a zero-crossing detector that indicates when an At measurement is made using flip-flops and an XOR gate. The phase detector circuit arrangement 1910 can determine when a signal crosses zero and generate an output of At.

[0162] It should be readily understood that the embodiments of the systems, devices, and methods described herein can be configured in various additional and alternative ways than those explicitly described herein.

[0163] CONCLUSION

[0164] Operations and / or functions of the present disclosure have been described herein, such as in flowcharts. As should be appreciated, computer program instructions can be loaded onto a computer or other programmable apparatus (e.g., hardware) to produce a machine, such that the resulting computer or other programmable apparatus implements the operations and / or functions described in the flowchart blocks herein. These computer program instructions can also be stored in a computer-readable memory that can direct a computer, processor, or other programmable apparatus to operate in a particular manner and / or to produce a machine, such that the instructions stored in the computer-readable memory produce an article of manufacture that implements the operations and / or functions described in the flowchart blocks. The computer program instructions can also be loaded onto a computer, processor, or other programmable apparatus to cause a series of operations to be performed on the computer, processor, or other programmable apparatus, to produce a computer-implemented process such that the instructions that are executed on the computer, processor, or other programmable apparatus provide operations for implementing the functions and / or operations specified in the flowchart blocks. The flowchart blocks support combinations of operations for performing the specified operations and / or functions, combinations of the operations and / or functions for performing the specified operations and / or functions, and combinations of the apparatuses for performing the specified operations and / or functions. It should be understood that one or more blocks of the flowcharts, and combinations of blocks in the flowcharts, can be implemented by special purpose hardware-based computer systems that perform the specified operations and / or functions, or combinations of special purpose hardware and computer instructions.

[0165] While this specification includes many specifics, these should not be construed as limitations on the scope of any disclosures or of what can be claimed, but as descriptions of particular embodiments of specific disclosures. Certain features that are described in the context of separate embodiments can also be implemented in combination with each other. Conversely, various features that are described in the context of a single embodiment can also be implemented on a sub-combination basis. Moreover, although features can be described above as acting in certain combinations and even initially claimed as such, one or more features from a claimed combination can in some cases be excised from the combination and the claimed combination can be directed to a sub-combination or a variation of a sub-combination.

[0166] While operations and / or functions are illustrated in the drawings in a particular order, this should not be understood as requiring such order, nor limiting it to the order illustrated, for the operations and / or functions can be performed in any order or concurrently. In some cases, operations and / or functions can even be omitted entirely. In other cases, additional operations and / or functions can be added. It is not intended that the scope of the claims be limited by the order in which the operations and / or functions are illustrated in the drawings.

[0167] While this detailed description has set forth various embodiments of the application at a particular level of detail, this is not intended to limit the scope of the application but merely to provide a detailed description of certain specific embodiments of the application. Further, the detailed description includes specific details for the purpose of providing a thorough understanding of various embodiments of the application.

[0168] Within the scope of the appended claims, unless otherwise indicated, no single term is intended to be used in the sense of 35 U.S.C. 112, paragraph 6.

Claims

1. A system comprising: a battery; a battery management system including an EIS circuitry, wherein the battery management system is electrically coupled to the battery; wherein the EIS circuitry includes excitation circuitry configured to generate an excitation signal; wherein the EIS circuitry is configured to provide the excitation signal to the battery and receive a response signal from the battery based on the excitation signal; wherein the EIS circuitry further includes current sense circuitry configured to generate a current signal based on the response signal; wherein the EIS circuitry further includes voltage sense circuitry configured to generate a voltage signal based on the excitation signal and the response signal; wherein the EIS circuitry further includes phase circuitry configured to generate a phase signal based on the current signal and the voltage signal; wherein the EIS circuitry further includes current magnitude circuitry configured to generate a current magnitude signal based on the current signal; wherein the EIS circuitry further includes voltage magnitude circuitry configured to generate a voltage magnitude signal based on the current signal; wherein an EIS processor is configured to generate at least one output signal based on the phase signal, the current magnitude signal, and the voltage magnitude signal; and wherein the battery management system is configured to generate a first impedance based on an EIS model and the at least one output signal.

2. The system of claim 1, wherein the voltage magnitude circuitry includes a voltage peak detector and the current magnitude circuitry includes a current peak detector.

3. The system of claim 2, wherein the phase circuitry includes one of a phase shift detector, a phase detector, or a lock-in amplifier.

4. The system of claim 1, wherein the voltage magnitude circuitry includes a voltage lock-in amplifier and the current magnitude circuitry includes a current lock-in amplifier.

5. The system of claim 4, wherein the phase circuitry includes one of a phase shift detector, a phase detector, or a lock-in amplifier.

6. The system of claim 1, wherein the at least one output signal includes a first output signal of an output phase and a second output signal of an output magnitude.

7. The system of claim 1, wherein to generate a first impedance based on an EIS model and the at least one output signal, the battery management system is configured to determine the first impedance from a lookup table.

8. A battery management integrated circuit comprising: a battery management processor; EIS circuitry including excitation circuitry configured to generate an excitation signal; wherein the EIS circuitry is configured to provide the excitation signal to a battery and receive a response signal from the battery based on the excitation signal; wherein the EIS circuitry further includes current sense circuitry configured to generate a current signal based on the response signal; wherein the EIS circuitry further comprises voltage sensing circuitry configured to generate a voltage signal based on the excitation signal and the response signal; wherein the EIS circuitry further comprises phase circuitry configured to generate a phase signal based on the current signal and the voltage signal; wherein the EIS circuitry further comprises current amplitude circuitry configured to generate a current amplitude signal based on the current signal; wherein the EIS circuitry further comprises voltage amplitude circuitry configured to generate a voltage amplitude signal based on the current signal; wherein the EIS processor is configured to generate at least one output signal based on the phase signal, the current amplitude signal, and the voltage amplitude signal; and wherein the battery management processor is configured to generate a first impedance based on an EIS model and the at least one output signal.

9. The battery management integrated circuit of claim 8, wherein the voltage amplitude circuitry comprises a voltage peak detector and the current amplitude circuitry comprises a current peak detector.

10. The battery management integrated circuit of claim 9, wherein the phase circuitry comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

11. The battery management integrated circuit of claim 8, wherein the voltage amplitude circuitry comprises a voltage lock-in amplifier and the current amplitude circuitry comprises a current lock-in amplifier.

12. The battery management integrated circuit of claim 11, wherein the phase circuitry comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

13. The battery management integrated circuit of claim 8, wherein the at least one output signal comprises a first output signal of an output phase and a second output signal of an output amplitude.

14. The battery management integrated circuit of claim 8, wherein to generate a first impedance based on an EIS model and the at least one output signal, the battery management processor is configured to determine the first impedance from a lookup table.

15. A method comprising: generating an excitation signal with excitation circuitry; sending the excitation signal to a battery to generate a response signal; receiving the response signal at EIS circuitry; generating a current signal with the EIS circuitry based on the response signal; generating a voltage signal with the EIS circuitry based on the response signal and the excitation signal; generating a phase signal with phase circuitry based on the current signal and the voltage signal; generating a current amplitude signal with current amplitude circuitry; generating a voltage amplitude signal with voltage amplitude circuitry; generating at least one output signal based on the phase signal, the current amplitude signal, and the voltage amplitude signal; and determining a first impedance based on an EIS model and the at least one output signal.

16. The method of claim 15, wherein the voltage magnitude circuit means comprises a voltage peak detector and the current magnitude circuit means comprises a current peak detector.

17. The method of claim 16, wherein the phase circuit means comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

18. The method of claim 15, wherein the voltage magnitude circuit means comprises a voltage lock-in amplifier and the current magnitude circuit means comprises a current lock-in amplifier.

19. The method of claim 18, wherein the phase circuit means comprises one of a phase shift detector, a phase detector, or a lock-in amplifier.

20. The method of claim 15, wherein the at least one output signal comprises a first output signal of an output phase and a second output signal of an output magnitude.

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