Instruction segmentation prediction rate matching method for distributed controller-driver

Abstract

The invention discloses a distributed controller-driver instruction segmentation prediction rate matching method, and relates to the technical field of distributed control, and the method comprises the steps: carrying out the instruction frequency detection through a clock source of a driver, and obtaining a frequency error value of a controller instruction; based on the frequency error value of the controller instruction, adopting an interpolation algorithm to carry out interpolation caching processing on the controller instruction, and obtaining a controller instruction sequence of interpolation caching; and performing dynamic interpolation frequency adjustment according to the frequency error value of the controller instruction and the controller instruction sequence of the interpolation cache, and obtaining an instruction segmentation prediction rate matching result. Through a dynamic interpolation frequency adjustment mechanism, an instruction segmentation strategy can be automatically optimized according to a real-time frequency error, high-precision interpolation is still kept when the instruction frequency of the controller fluctuates, accumulative errors caused by fixed interpolation are avoided, and the execution precision of the control instruction is remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of distributed control, and particularly relates to a distributed controller-driver instruction segmentation prediction rate matching method. BACKGROUND

[0002] In a distributed control system, the issuing period of controller instructions and the execution period of drivers often have a non-integer multiple relationship, resulting in "window period" or "accumulation phenomenon" of instructions at the driver end. The traditional solution expands the instructions by a fixed interpolation multiple, but when the frequency of controller instructions fluctuates, the fixed interpolation strategy introduces cumulative errors and reduces control accuracy. For example, in the field of precision mechanical control, non-uniform interpolation of instructions may cause distortion of the motion trajectory; and in a high-frequency response system, a fixed segmentation number is difficult to match the dynamically changing instruction frequency, which easily causes waste of computing power or response delay at the execution end. In addition, the traditional method needs to pre-configure interpolation parameters, which has poor adaptability to different working conditions and increases the complexity of system debugging.

[0003] Therefore, there is an urgent need for a distributed controller-driver instruction segmentation prediction rate matching method to solve the problems in the prior art. SUMMARY

[0004] The purpose of the present application is to provide a distributed controller-driver instruction segmentation prediction rate matching method to solve the problems of poor execution continuity, low accuracy and waste of computing power caused by the non-integer multiple relationship between the issuing period of controller instructions and the execution period of drivers and the fluctuation of instruction frequency.

[0005] To achieve the above purpose, the present application provides a distributed controller-driver instruction segmentation prediction rate matching method, comprising the following steps: S1, using a clock source of a driver to detect the frequency of instructions and obtaining a frequency error value of controller instructions; S2, using an interpolation algorithm based on the frequency error value of the controller instructions to perform interpolation cache processing on the controller instructions and obtaining an interpolated controller instruction sequence; S3, adjusting the dynamic interpolation number based on the frequency error value of the controller instructions and the interpolated controller instruction sequence, and obtaining an instruction segmentation prediction rate matching result.

[0006] Optionally, S1, using a clock source of a driver to detect the frequency of instructions and obtaining a frequency error value of controller instructions, comprises: Initializing a double timer based on the clock source of the driver, the double timer comprising a first timer and a second timer; Using the first timer based on the clock source of the driver to obtain an actual control instruction period; A theoretical control instruction period is generated by the second timer; The actual control instruction period is compared with the theoretical control instruction period to obtain a frequency error value of the controller instruction.

[0007] Optionally, S2, based on the frequency error value of the controller instruction, an interpolation algorithm is used to perform interpolation cache processing on the controller instruction to obtain an interpolation cached controller instruction sequence, including: According to the frequency error value of the controller instruction, a reference interpolation multiple and a frequency error threshold value are set; The frequency error value of the controller instruction and the frequency error threshold value are used to determine the interpolation algorithm; Based on the frequency error value of the controller instruction, the reference interpolation multiple is dynamically adjusted by using the actual control instruction period and the theoretical control instruction period to determine an initial interpolation multiple; Based on the initial interpolation multiple, the interpolation algorithm is used to perform interpolation cache processing on the controller instruction to obtain an interpolation cached controller instruction sequence.

[0008] Optionally, according to the frequency error value of the controller instruction, a reference interpolation multiple and a frequency error threshold value are set, including: It is judged whether the frequency error value of the controller instruction is greater than the frequency error threshold value, if yes, a linear interpolation algorithm is obtained as the interpolation algorithm, otherwise, a first operation is performed; The first operation is to judge whether the frequency error value of the controller instruction meets the frequency error threshold value, if yes, a quadratic polynomial interpolation algorithm is obtained as the interpolation algorithm, otherwise, a spline interpolation algorithm is obtained as the interpolation algorithm.

[0009] Optionally, based on the frequency error value of the controller instruction, the reference interpolation multiple is dynamically adjusted by using the actual control instruction period and the theoretical control instruction period to determine an initial interpolation multiple, including: By using the actual control instruction period and the theoretical control instruction period, a deviation rate of the actual control instruction period and the theoretical control instruction period is obtained as a real-time deviation rate; According to the real-time deviation rate and the frequency error value of the controller instruction, a reference interpolation multiple adjustment amount is determined; Based on the interpolation number adjustment direction, the interpolation number is adjusted to obtain an instruction segmentation prediction rate matching result.

[0010] Optionally, based on the initial interpolation multiple, the interpolation algorithm is used to perform interpolation cache processing on the controller instruction to obtain an interpolation cached controller instruction sequence, including: determining a synchronization timestamp of an intermediate controller instruction according to the initial interpolation multiple based on the controller instruction; interpolating the controller instruction by using the interpolation algorithm based on the synchronization timestamp of the intermediate controller instruction, to obtain an intermediate controller instruction sequence; performing double buffering processing on the intermediate controller instruction sequence, to obtain an interpolation buffered controller instruction sequence.

[0011] Optionally, S3, dynamically adjusting an interpolation number according to the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence, to obtain an instruction segmentation prediction rate matching result, including: setting an interpolation number adjustment coefficient and a corresponding boundary parameter by using the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence; determining an interpolation number adjustment direction and an interpolation number adjustment amplitude according to the interpolation number adjustment coefficient and the corresponding boundary parameter in combination with the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence; adjusting the interpolation number based on the interpolation number adjustment direction, to obtain the instruction segmentation prediction rate matching result.

[0012] Optionally, setting an interpolation number adjustment coefficient and a corresponding boundary parameter by using the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence, including: obtaining a historical fluctuation range of the frequency error value by using the frequency error value of the controller instruction; dividing error intervals according to the historical fluctuation range of the frequency error value, the error intervals including a high error interval, a medium error interval and a low error interval; performing feature analysis on the interpolation buffered controller instruction sequence based on the error intervals, to obtain sequence feature parameters; obtaining an interpolation number adjustment coefficient based on the error intervals and the sequence feature parameters; obtaining a corresponding boundary parameter according to the interpolation number adjustment coefficient.

[0013] Optionally, determining an interpolation number adjustment direction and an interpolation number adjustment amplitude according to the interpolation number adjustment coefficient and the corresponding boundary parameter in combination with the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence, including: obtaining an actual interpolation fluctuation rate of the interpolation buffered sequence and an execution feedback deviation according to the interpolation buffered controller instruction sequence; determining whether the frequency error value of the controller instruction meets the high error interval, if yes, taking the frequency error value of the controller instruction as a high frequency error value, and performing a second operation, otherwise, performing a third operation; The second operation is: according to the actual interpolation fluctuation rate of the interpolation cache sequence and the execution feedback deviation, combining the high frequency error value, the sequence characteristic parameter, the interpolation frequency adjustment coefficient and the corresponding boundary parameter, obtaining the adjustment direction and adjustment amplitude of the interpolation frequency of the high error interval as the interpolation frequency adjustment direction and interpolation frequency adjustment amplitude respectively. The third operation is: determining whether the frequency error value of the controller instruction meets the medium error interval, if yes, taking the frequency error value of the controller instruction as a medium frequency error value, and performing a fourth operation, otherwise, taking the frequency error value of the controller instruction as a low frequency error value, and performing a fifth operation. The fourth operation is: according to the actual interpolation fluctuation rate of the interpolation cache sequence and the execution feedback deviation, combining the medium frequency error value, the sequence characteristic parameter, the interpolation frequency adjustment coefficient and the corresponding boundary parameter, obtaining the adjustment direction and adjustment amplitude of the interpolation frequency of the medium error interval as the interpolation frequency adjustment direction and interpolation frequency adjustment amplitude respectively. The fifth operation is: according to the actual interpolation fluctuation rate of the interpolation cache sequence and the execution feedback deviation, combining the low frequency error value, the sequence characteristic parameter, the interpolation frequency adjustment coefficient and the corresponding boundary parameter, obtaining the adjustment direction and adjustment amplitude of the interpolation frequency of the low error interval as the interpolation frequency adjustment direction and interpolation frequency adjustment amplitude respectively.

[0014] Optionally, adjusting the interpolation frequency based on the interpolation frequency adjustment direction to obtain an instruction segmentation prediction rate matching result, comprising: Using the initial interpolation multiple to obtain a corresponding initial interpolation frequency; Adjusting the interpolation frequency based on the initial interpolation frequency and the interpolation frequency adjustment direction to calculate a real-time interpolation frequency; According to the real-time interpolation frequency, using the interpolation algorithm to perform interpolation cache processing on the controller instruction to obtain a new interpolation cache controller instruction sequence; Based on the frequency error value of the controller instruction and the interpolation cache controller instruction sequence, respectively obtaining a frequency error trend and a cache sequence characteristic change; According to the new interpolation cache controller instruction sequence, combining the frequency error trend and the cache sequence characteristic change, obtaining an instruction stream synchronized with the driver execution cycle as an instruction segmentation prediction rate matching result.

[0015] Compared with the closest existing technology, the present invention has the following advantages: Unlike traditional synchronization mechanisms that rely on master-slave bidirectional communication, this invention innovatively integrates the clock compensation function entirely into the driver side for independent implementation. This completely eliminates the need for transmitting periodic frequency offset data in the uplink / downlink channels of the control loop. This not only avoids additional bandwidth consumption for real-time communication but also avoids the design burden of extending and customizing protocols for synchronization correction, thus fully preserving the standardized interface and compatibility of the existing controller-driver architecture. Specific effects are as follows: This invention introduces a dynamic interpolation frequency adjustment mechanism, which automatically optimizes the instruction segmentation strategy based on real-time detected frequency errors. This maintains interpolation accuracy even when the controller instruction frequency fluctuates, effectively avoiding the cumulative errors caused by fixed interpolation and significantly improving the execution accuracy of control instructions. Through instruction segmentation prediction, it achieves "pre-loading" of instructions, eliminating the "window period" of instructions at the driver end, enabling the execution end to respond to controller instructions continuously and smoothly. This is particularly suitable for scenarios with extremely high requirements for instruction continuity, such as precision trajectory control. The dynamic adjustment mechanism can adaptively allocate computing power according to the magnitude of the frequency error. When the error is small, it reduces the number of interpolations to reduce the computational load; when the error is large, it increases the number of interpolations to ensure accuracy, achieving optimal allocation of computing resources. Without the need for pre-configuration of interpolation parameters, the system can automatically adapt to the instruction frequency characteristics under different operating conditions, reducing debugging difficulty and improving the adaptability of the technical solution in complex industrial environments. Attached Figure Description

[0016] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0017] Figure 1 This is a flowchart illustrating a distributed controller-driver instruction segmentation prediction rate matching method according to an embodiment of the present invention. Detailed Implementation

[0018] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0019] The terms used in the embodiments of the present application are used only to explain specific embodiments of the present application, and are not intended to limit the present application.

[0020] As shown in Figure 1 The embodiment of the present application provides a distributed controller-driver instruction segmentation prediction rate matching method, which comprises the following steps: S1, using the clock source of the driver to detect the instruction frequency, obtaining the frequency error value of the controller instruction; The driver calculates the time interval of the controller instruction in real time through its own clock source, and compares it with the theoretical reference time interval, so as to detect the frequency error between the controller and the driver. This step can automatically identify a wide range of frequency deviation, avoiding the complexity of additional communication and protocol synchronization in the traditional scheme. This step realizes efficient and independent detection of the controller instruction frequency, providing basic data support for subsequent synchronous adjustment.

[0021] S2, based on the frequency error value of the controller instruction, using an interpolation algorithm to perform interpolation cache processing on the controller instruction, obtaining an interpolation cached controller instruction sequence; The driver expands the original instruction issued by the controller based on the detected frequency error value Δ f , using an interpolation algorithm (such as linear interpolation or spline interpolation) to generate an intermediate instruction sequence, and storing it in a ring buffer pool. This step effectively eliminates the "window period" problem caused by uneven instruction intervals through high-density instruction caching, providing a continuous and smooth instruction flow basis for subsequent dynamic segmentation. At the same time, through the design of the buffer pool, the preloading function of the instruction is realized, ensuring that the execution end always has pending instructions.

[0022] S3, dynamically adjusting the interpolation times according to the frequency error value of the controller instruction and the interpolation cached controller instruction sequence, obtaining the instruction segmentation prediction rate matching result; Combined with the real-time frequency error and the cache sequence, set the associated adjustment parameters and coefficients, determine the adjustment direction and amplitude of the interpolation times, update the interpolation times and optimize the cache sequence, and based on the error trend prediction, pre-adjust the number of times, finally output the instruction stream that completely matches the execution rate of the driver. Through the dynamic adjustment and prediction mechanism, this step makes the interpolation times accurately adapt to the frequency fluctuation, avoiding the loss of precision in high error, reducing the redundant computing power in low error, eliminating the execution "window period", and realizing the optimal balance of control precision and efficiency.

[0023] In summary, steps S1 to S3 achieve precise coordination between controller instructions and driver execution through three closely connected steps: first, detect the frequency error of the controller instructions based on the driver clock source to provide accurate frequency fluctuation data for subsequent processing; then, select an appropriate interpolation algorithm based on the error value to generate an interpolation cache instruction sequence that aligns with the driver execution period, preliminarily solving the problem of mismatch between instruction interval and execution rhythm; finally, dynamically adjust the interpolation times in combination with real-time frequency error and cache sequence characteristics, and optimize the instruction stream through a prediction mechanism to finally output an instruction sequence that completely matches the driver execution rate. The entire process forms a complete closed loop from error detection to instruction optimization, effectively improving the execution accuracy, continuity, and response efficiency of the control system in frequency fluctuation scenarios.

[0024] As a possible implementation, in the above embodiment, step S1 can specifically include the following steps: S1-1, initialize double timers based on the clock source of the driver; The driver uses its high-precision clock source to complete the initialization operation of the double timers (first timer and second timer), where the driver realizes controller instruction issuing frequency detection through the two timers, the first timer is used to measure the time interval (actual period) of the actual controller instruction issuing, and the second timer is based on a pre-set theoretical instruction period (such as a fixed time reference) to run, and the clock source uses a temperature-compensated crystal oscillator or a constant-temperature crystal oscillator. The two timers use a synchronous counter architecture, and the counting pulses are directly derived from a standard clock signal obtained by frequency division processing of the driver clock source, for example, dividing a 10MHz clock source to 1MHz, ensuring that the timing accuracy reaches 1 microsecond.

[0025] During the initialization process, the system synchronously calibrates the double timers, sends a reset signal through the internal bus, clears the initial count values of the two timers, and keeps the start time strictly synchronized, with a synchronization error ≤ 1 clock period. This step synchronously initializes the double timers by sharing the same high-stability clock source, ensuring that the timing references of the actual control instruction period and the theoretical control instruction period are completely consistent, thereby avoiding error accumulation caused by differences in timing references from the source, and providing a highly consistent time reference for subsequent frequency error calculation.

[0026] To avoid counting errors caused by timer overflow, the embodiment also sets a dynamic overflow warning mechanism: when the count value of the timer reaches 90% of the maximum range, an interrupt signal is triggered, and the controller automatically records the current count value and resets the counter in the interrupt response, ensuring the continuity of the timing process. In addition, the double timers are linked with the clock source calibration module of the driver, and the count reference is updated synchronously with the automatic calibration of the clock source every hour, eliminating the accumulated error in long-term operation.

[0027] S1-2, obtaining an actual control instruction period by the first timer according to a clock source of the driver; The first timer is configured in an event-triggered counting mode, and the time stamp of adjacent instructions is recorded in real time by triggering the timer through capturing the edge signal (such as rising edge / falling edge) of the instruction issued by the controller, and the actual control instruction period is calculated based on the clock source of the driver. Specifically as follows: When the signal conditioning circuit of the driver detects the edge signal of the control instruction, a start signal is immediately sent to the first timer, and the timer starts to accumulate the count; when the next edge of the same type is detected, a stop signal is sent, and the counter stops counting. The counting result of the first timer is transmitted in real time to the operation unit through a special data bus, and the operation unit divides the counting value by the frequency of the clock source of the driver (such as 1 MHz clock source corresponding to 1 microsecond per counting unit), and the time interval of the two adjacent instruction edges, i.e. the actual control instruction period, is obtained. In addition, in order to improve the detection accuracy, the measurement values of M (M≥5) actual control instruction periods are recorded continuously by using the multi-period average method, and the arithmetic mean value after removing the maximum value and the minimum value is taken as the final actual control instruction period.

[0028] This step can accurately capture the time interval of the instruction signal by using the real-time counting mode of edge triggering, and the multi-period average method can effectively suppress the measurement fluctuation caused by instantaneous noise interference, so that the measurement error of the actual control instruction period is reduced; the high-speed transmission of the special data bus ensures that the counting result is transmitted without delay, and provides high-fidelity raw data for subsequent error calculation.

[0029] S1-3, generating a theoretical control instruction period by the second timer; The second timer is configured in a fixed period output mode, and is used to generate a theoretical control instruction period. The timer runs independently and is not affected by the actual behavior of the controller, and always provides a stable theoretical period reference. The working principle is as follows: the comparison register value is configured according to the preset theoretical control instruction frequency (such as a nominal 100 Hz corresponding to a period of 10 ms), and an automatic reload mode is used to continuously fix the time interval (for example, the counting is triggered once every 1 ms). Specifically as follows: The theoretical control instruction frequency set by the user is received through the configuration interface F ref The operation unit converts it into a theoretical period T ref =1 / F ref , and the number of clock pulses corresponding to the period T refThe second timer writes the comparison register of the second timer with the frequency of the clock source. The second timer adopts an automatic reload mode, and when the count reaches the value of the comparison register, an interrupt is automatically triggered and the counter is reset to start counting the next period, and a synchronization pulse signal is output as a marker of the theoretical instruction period. For example, if the theoretical period is 1 ms and the clock source frequency is 1 MHz, the value of the comparison register is set to 1000 (1 ms = 1000 microseconds, corresponding to 1000 count units). The second timer generates a theoretical period completion signal every 1000 counts, which can be used for subsequent comparison with the actual instruction period. In addition, the system supports dynamic modification of the theoretical control instruction frequency, and the second timer can switch to a new theoretical period within 1 clock cycle by writing a new comparison register value, adapting to the control requirements under different working conditions.

[0030] The step of automatically reloading the counting mode ensures stable output of the theoretical control instruction period, and the accuracy is only determined by the stability of the driver clock source, avoiding the drift of the theoretical period caused by software calculation delay; the dynamic switching function improves the flexibility of the system, and the theoretical period parameters can be updated in real time according to the adjustment of the control strategy, providing a reliable reference for dynamic comparison of frequency errors.

[0031] S1-4, comparing the actual control instruction period with the theoretical control instruction period to obtain a frequency error value of the controller instruction; This step calculates the frequency error value of the controller instruction by comparing the actual control instruction period with the theoretical control instruction period, avoiding rounding errors in the frequency conversion process and making the error calculation more accurate.

[0032] In summary, steps S1-1 to S1-4 first start the clock source after the driver is started, enter the controller instruction issuing frequency detection phase, and calculate the actual control instruction period and the theoretical control instruction period through two timers, and then compare them in real time to obtain a frequency error value in a wide range. The clock source of the driver is used as a reference to detect the frequency of the controller instruction in real time, and the clock source of the driver has high stability and accuracy, which can provide a reliable reference standard for frequency detection. This process initializes the double timer by means of the high-precision clock source of the driver, effectively avoiding detection errors caused by unstable external reference sources, ensuring that the actual and theoretical control instruction period timing references are consistent, and ensuring the timing range and continuity; the first timer is used in combination with the multi-cycle average method to accurately obtain the actual period, and noise interference is suppressed; the second timer generates a stable theoretical period in an automatic reload mode and supports dynamic switching; the frequency error is obtained by comparing the periods, which facilitates improving the accuracy, system flexibility and maintainability of the control instruction rate matching, and provides a reliable basis for dynamic adjustment of the control period.

[0033] As a possible implementation, in the above embodiment, step S1-4 can specifically include the following steps: S1-4-1, using the actual control instruction period and the theoretical control instruction period, respectively calculating the actual controller instruction frequency and the theoretical controller instruction frequency; The actual control instruction period obtained by the first timer T 1, that is, the driver execution period, the actual controller instruction frequency is calculated through the inverse relationship between frequency and period, that is: Actual controller instruction frequency f 1=1 / T 1; At the same time, according to the system preset theoretical control instruction period T 0, that is, the theoretical instruction period of the controller, the theoretical controller instruction frequency is also calculated through the inverse relationship, that is: Theoretical controller instruction frequency f 0=1 / T 0; This step converts the period difference originally in time unit into frequency parameter which reflects the "fast / slow" characteristics of instruction sending more intuitively, and intuitively reflects the clock source bias of the controller and the driver, providing standardized input for subsequent relative frequency error calculation.

[0034] S1-4-2, error calculation is performed on the actual controller instruction frequency and the theoretical controller instruction frequency, and the relative frequency error of the actual controller instruction frequency and the theoretical controller instruction frequency is obtained as the relative frequency error of the controller instruction; By calculating the difference between the actual controller instruction frequency and the theoretical controller instruction frequency, and then dividing the difference by the theoretical controller instruction frequency and multiplying by 100%, the relative frequency error is obtained as the relative frequency error of the controller instruction, and the calculation formula is as follows: delta f =[( f 1- f 0) / f 0]×100% Wherein, delta f The relative frequency error of the controller instruction.

[0035] This process eliminates the influence of the absolute value of the frequency on error evaluation, and can more accurately reflect the deviation proportion of the actual frequency relative to the theoretical frequency, for example, the severity difference of the same absolute error under different theoretical frequencies. Through the relative error, a unified and objective evaluation is obtained, which provides a standardized quantitative index for subsequent threshold judgment.

[0036] S1-4-3, setting a reference time interval based on the relative frequency error of the controller instruction and the relative frequency error of the corresponding historical controller instruction; By analyzing the relative frequency error of the current controller instruction and the sequence of the relative frequency error of the corresponding historical controller instruction in the past period of time, the fluctuation law, change trend and stability of the error are observed, and then the reference time interval is dynamically set. For example, if the historical error fluctuates less in the past 50 ms, such as within ±0.5%, and the difference between the current error and the historical error is <1%, the reference time interval is set to 50 ms (reflecting the stable state of the error); if the error fluctuates more than ±5% in the past 20 ms, such as from -10% to +8%, the reference time interval is set to 20 ms (capturing high-frequency fluctuations). In this embodiment, the reference time interval is dynamically updated according to the stability of the error, wherein the interval is increased to reduce the amount of calculation when the error is stable, and the interval is reduced to improve the response speed when the error fluctuates.

[0037] This step extends the error analysis at a single time point to trend analysis in the time dimension by introducing the reference time interval, avoids misjudgment caused by instantaneous error, improves the robustness of error detection, and at the same time dynamically adjusts the interval size according to the error characteristics, ensuring the accuracy of error monitoring while taking into account the system calculation efficiency.

[0038] S1-4-4, obtaining the frequency error value of the controller instruction according to the reference time interval and the relative frequency error of the controller instruction; According to the set reference time interval, the change of the relative frequency error of the controller instruction in the time interval, for example, whether the error change is within the preset threshold, whether there is abnormal fluctuation, etc., the frequency error value of the controller instruction is determined. If the change amount of the relative frequency error in the reference time interval (such as 50 ms) is ≤ the preset threshold (such as ±1%), the average relative error in the time period is taken as the final frequency error value (such as -16.5%); if the change amount > the threshold (such as from -10% to -20% in 50 ms), the maximum deviation value (such as -20%) in the time period is taken and marked as “abnormal fluctuation”. In this embodiment, the final frequency error value can be described in combination with the error size and stability.

[0039] The error value output in this step not only contains the deviation size information, but also integrates the stability characteristics in the time dimension, making the error evaluation more comprehensive and being able to provide more practical guiding significance for the calibration of the controller, fault diagnosis and adjustment of the system control strategy.

[0040] In summary, steps S1-4-1 to S1-4-4 obtain a range of frequency error values with accuracy and practicality by quantitative analysis and time dimension trend judgment, which not only accurately reflects the deviation degree of the controller instruction, but also provides an operable basis for system optimization, such as triggering calibration, alarm or adjusting control strategy according to the error value.

[0041] As a possible implementation, in the above embodiment, step S2 can specifically include the following steps: S2-1, setting a reference interpolation multiple and a frequency error threshold according to the frequency error value of the controller instruction; This step determines the appropriate reference interpolation multiple f 0and the frequency error threshold Δ N f th The reference interpolation multiple N 0= floor ( T 0 / T 1) is the initial reference for subsequent interpolation calculation, and the frequency error threshold provides a clear boundary for the selection of different interpolation algorithms, wherein floor (∙) represents a floor function. This step lays the foundation for the entire interpolation process. By reasonably setting these two parameters, the subsequent interpolation algorithm selection and interpolation multiple adjustment can be more targeted, thereby ensuring the accuracy and stability of the interpolation process. In this embodiment, the reference interpolation multiple N ’=16, and the frequency error threshold is set to 3%≤∣Δ f th ∣<5%.

[0042] S2-2, determining an interpolation algorithm using the frequency error value of the controller instruction and the frequency error threshold; When determining the interpolation algorithm using the frequency error value of the controller instruction and the frequency error threshold, the actual frequency error value is compared with the preset threshold, and then the optimal interpolation algorithm is selected. This step realizes adaptive selection of the interpolation algorithm, which can flexibly adjust the algorithm according to the actual situation of the frequency error, thereby improving the accuracy of the interpolation while ensuring the processing efficiency.

[0043] S2-3, dynamically adjusting the reference interpolation multiple based on the frequency error value of the controller instruction using the actual control instruction period and the theoretical control instruction period to determine an initial interpolation multiple; ​The deviation rate of the actual control instruction period and the theoretical control instruction period is calculated, and the initial interpolation multiple is further corrected combined with the frequency error value of the controller instruction. This step ensures that the interpolation multiple is more suitable for the actual instruction period, avoids the interpolation deviation caused by the fixed interpolation multiple, and further improves the adaptability and accuracy of the interpolation processing.

[0044] S2-4, based on the initial interpolation multiple, using the interpolation algorithm to perform interpolation cache processing on the controller instruction to obtain an interpolation cached controller instruction sequence; According to the determined interpolation algorithm and interpolation multiple, the original controller instruction is interpolated to generate intermediate instructions strictly synchronized with the execution period of the driver, such as one instruction per 1 ms, and these instructions are stored in the double buffer area. Through the "preload" mechanism, the buffer area ensures that there is always an instruction input when the driver executes, avoiding the "window period", and finally forming an intermediate instruction sequence that meets the smoothness requirement and matches the execution rhythm, providing a continuous and accurate instruction source for subsequent rate matching.

[0045] In summary, steps S2-1 to S2-4 are based on the frequency error value of the controller instruction. First, the reference interpolation multiple range and the frequency error threshold are set, then the interpolation algorithm is determined according to the error value and the threshold, then the initial interpolation multiple is determined combined with the actual and theoretical control instruction period, and finally the controller instruction is interpolated using the algorithm and multiple to obtain an intermediate instruction sequence synchronized with the execution period of the driver. This process realizes the precise adaptation of the interpolation algorithm and multiple, improves the interpolation accuracy and adaptability, and ensures the continuous and accurate intermediate instruction sequence, providing reliable protection for subsequent rate matching. As a possible implementation, in the above embodiment, step S2-2 can specifically include the following steps: S2-2-1, determining whether the frequency error value of the controller instruction is greater than the frequency error threshold, if yes, obtaining a linear interpolation algorithm as the interpolation algorithm, otherwise, performing S2-2-2; S2-2-2, determining whether the frequency error value of the controller instruction meets the frequency error threshold, if yes, obtaining a quadratic polynomial interpolation algorithm as the interpolation algorithm, otherwise, obtaining a spline interpolation algorithm as the interpolation algorithm.

[0046] When the instruction frequency fluctuation is small, i.e. |Δ f |<3%, the linear interpolation algorithm with the smallest calculation amount and the fastest response is used to quickly process the small error under stable working conditions, reduce the driver algorithm power occupation, and ensure the basic control efficiency; when the instruction frequency exists moderate fluctuation, i.e. 3%≤|Δ f| < 5%, a quadratic polynomial interpolation is selected, by moderately increasing the calculation complexity, a better fitting effect than linear interpolation is obtained, when the error range is expanded but not to a severe degree, the smoothness and the calculation power consumption are balanced, the trajectory deviation under the medium fluctuation is avoided; when the instruction frequency fluctuates severely, i.e. | Δ f | ≥ 5%, a cubic spline interpolation is adopted, by the cost of higher calculation complexity, a multi-segment continuous smooth polynomial curve fitting is used, the instruction mutation caused by severe fluctuation is maximally reduced, the jitter is effectively inhibited in the precise control scene, the trajectory smoothness and the control precision under high-frequency fluctuation are ensured, and the stepwise adaptation of "efficiency-smoothness-precision" under different fluctuation degrees is realized.

[0047] As a possible implementation, in the above embodiment, step S2-3 can specifically include the following steps: S2-3-1, obtaining the deviation rate of the actual control instruction period and the theoretical control instruction period as a real-time deviation rate by using the actual control instruction period and the theoretical control instruction period; The driver calculates the actual control instruction period in real time through a local clock source T 1 and the deviation rate of the theoretical control instruction period T 0 delta | T 1- T 0| / T 0×100%, as the basic parameter of dynamic adjustment. This step directly quantifies the period deviation degree, provides a basic reference for the subsequent adjustment of the interpolation multiple, and ensures that the adjustment direction is consistent with the actual period change.

[0048] S2-3-2, determining a reference interpolation multiple adjustment amount according to the real-time deviation rate and the frequency error value of the controller instruction; Based on the real-time deviation rate delta and the frequency error value Δ f , the adjustment amount is calculated according to the formula Δ N = k × delta × sgn (Δ f ), wherein, k is a regulation coefficient, k = 0.05, sgn (Δ f ) is a direction factor, +1 indicates that the delay needs to be accelerated, and -1 indicates that the advance needs to be decelerated. This step realizes the linear / nonlinear mapping of the deviation rate and the adjustment amount, such as delta > 10% uses exponential adjustment, which avoids the under-adjustment or over-adjustment problem caused by fixed step length.

[0049] S2-3-3. Based on the reference interpolation factor, combined with the frequency error value of the controller command and the adjustment amount of the reference interpolation factor, obtain the initial interpolation factor; Based on the reference interpolation factor, an adjustment amount is added, and dynamic corrections are made according to the real-time changes in the frequency error value: when the absolute value of the error increases, an additional compensation coefficient is added to the adjustment amount, such as increasing the adjustment amount by 10% for every 1Hz increase in error; when the error decreases, the adjustment amount is appropriately reduced, such as decreasing the adjustment amount by 5% when the error drops below 0.5Hz, and finally rounded to obtain the initial interpolation factor. N This step achieves fine-grained calibration of the adjustment amount through error feedback, ensuring that the interpolation multiple is highly adapted to the real-time operating conditions. This avoids insufficient or redundant interpolation caused by period deviation, and can dynamically respond to frequency fluctuations, providing a quantitative basis for accurate interpolation.

[0050] In summary, steps S2-3-1 to S2-3-3 achieve accurate determination of the interpolation factor through three collaborative steps: First, the real-time deviation rate between the actual and theoretical control command cycles is calculated to quantify the degree of static deviation of the cycle; then, combined with the frequency error value of the controller command (reflecting dynamic fluctuations), a weighted fusion is performed to obtain the baseline interpolation factor adjustment amount, taking into account both static deviation and dynamic changes; finally, based on the initial interpolation factor, the adjustment amount is added and dynamically corrected in real time according to the frequency error, ultimately determining the initial interpolation factor adapted to the real-time operating conditions. This closed-loop logic avoids the limitations of a fixed factor and ensures that the interpolation factor can accurately match cycle changes and frequency fluctuations through dual-dimensional error considerations, providing key support for the accuracy and adaptability of subsequent interpolation processing.

[0051] In this process, the interpolation multiple is adjusted to a reference setting layer. By incorporating the dual quantization characteristics of frequency error and period deviation into the reference multiple calculation, the initial interpolation density can be adapted to the actual period deviation from the source. For example, when the actual period is extended due to the increase of frequency error, the reference multiple is increased synchronously to increase the number of intermediate instructions, ensuring that the time span of the original instructions is fully covered, avoiding insufficient or redundant initial interpolation due to a fixed reference multiple, and providing basic parameters that match the real-time period characteristics for subsequent interpolation processing.

[0052] As one possible implementation, in the above embodiments, step S2-4 may specifically include the following steps: S2-4-1. Based on the controller instructions and the initial interpolation multiple, determine the synchronization timestamp of the intermediate controller instructions; The timing of receiving two adjacent controller commands t k and t k+1 As the time boundary, based on the initial interpolation factor N , the time intervalt k+1 - t k uniformly divided into N +1 periods, each period strictly equal in length to the driver execution cycle T 1, thereby determining N the synchronized timestamps of the intermediate controller instructions t k + T 1, t k +2 T 1, …, t k+1 - T 1. This step ensures the time reference of the intermediate instructions is completely synchronized with the execution end by rigidly binding the timestamps with the driver execution cycle, avoiding execution delays or instruction accumulation caused by time misalignment.

[0053] S2-4-2, based on the synchronized timestamps of the intermediate controller instructions, using the interpolation algorithm to interpolate the controller instructions to obtain a sequence of intermediate controller instructions; According to the position of the synchronized timestamps, the matching interpolation algorithm is called to calculate based on the instruction values (such as position, speed parameters) of the original controller instructions: linear interpolation generates intermediate values by proportional distribution, quadratic polynomial interpolation optimizes the smoothness of moderate fluctuation scenarios through curve fitting, and cubic spline interpolation eliminates instruction mutations under severe fluctuations through high-order continuous curves, finally obtaining a sequence of intermediate instruction values corresponding to the synchronized timestamps one by one. This step ensures that the change rule of the intermediate instruction values is consistent with the original instruction trend based on time synchronization, not only maintaining control accuracy, but also reducing mechanical impact or trajectory distortion at the execution end through smooth transition.

[0054] S2-4-3, double-buffering the sequence of intermediate controller instructions to obtain an interpolated buffered sequence of controller instructions; The generated intermediate instruction sequence is stored in the double-buffering area in timestamp order, and the double-buffering area includes the current execution buffer and the preloading buffer. The current buffer outputs instructions to the driver in real time according to the timestamps, ensuring that the execution end responds without delay; the preloading buffer calculates and stores the intermediate sequence corresponding to the next group of original instructions in advance, and when the number of instructions remaining in the current buffer is below a threshold (such as N / 3), it automatically switches to the preloading buffer and starts interpolation calculation for the new sequence. This step uses the double-buffering mechanism of "real-time execution + preloading" to eliminate the "dead time" of the driver end, while avoiding the impact of algorithm power fluctuations on execution continuity, and the final output buffer sequence can maintain strict synchronization with the execution cycle and dynamically adapt to the frequency fluctuations of the controller instructions.

[0055] In summary, steps S2-4-1 to S2-4-3 achieve accurate matching of controller instructions and driver execution cycles through three steps: first, determine the synchronization timestamp of the intermediate instruction based on the interpolation multiple to ensure that the time reference is rigidly bound to the driver execution cycle; then, combine the synchronization timestamp to call the adaptive interpolation algorithm to generate the intermediate instruction sequence, ensuring time synchronization while ensuring instruction smoothness and accuracy through algorithm optimization; finally, through the double buffer mechanism, the intermediate sequence is output and preloaded in real time, which facilitates the elimination of the "window period" and balances the fluctuation of computing power. This process effectively solves the problems of low execution accuracy and poor continuity caused by non-integer multiples of controller and driver cycles and frequency fluctuations, significantly improving the adaptability and control effect of the distributed control system.

[0056] As a possible implementation, in the above embodiment, step S3 can specifically include the following steps: S3-1, using the frequency error value of the controller instruction and the controller instruction sequence of the interpolation buffer, setting an interpolation frequency adjustment coefficient and corresponding boundary parameters; By combining the frequency error value of the controller instruction and the controller instruction sequence of the interpolation buffer, the error interval and the corresponding sequence characteristic parameters, such as interpolation fluctuation rate and execution deviation threshold, are divided, and the adjustment coefficient and the upper and lower limits of the interpolation frequency of different intervals are matched. This step associates the frequency error with the buffer sequence characteristics to build a binding parameter system of "error level-sequence standard-adjustment intensity", providing a quantitative basis for subsequent adjustment, avoiding the blindness of parameter setting, and ensuring that the adjustment logic directly matches the actual working condition characteristics.

[0057] S3-2, according to the interpolation frequency adjustment coefficient and the corresponding boundary parameters, combining the frequency error value of the controller instruction and the controller instruction sequence of the interpolation buffer, determining the interpolation frequency adjustment direction and the interpolation frequency adjustment amplitude; This step compares the real-time frequency error, the actual interpolation fluctuation rate and the execution deviation of the buffer sequence according to the adjustment parameters and coefficients, converts the abstract error and sequence characteristics into specific adjustment direction (increase / decrease) and amplitude, ensures that the adjustment decision fits the current working condition and meets the preset quantitative standard, and avoids the adjustment error caused by single index judgment.

[0058] S3-3, adjust the interpolation frequency based on the interpolation frequency adjustment direction to obtain the instruction segmentation prediction rate matching result; The interpolation times are updated based on the adjustment direction and amplitude, a corresponding interpolation algorithm is called to generate an optimized intermediate instruction sequence, and the cache is updated, the pre-adjustment times are predicted in combination with the error trend, and finally an instruction stream matching the execution rate of the driver is output. Through dynamically updating the interpolation times and combining the prediction mechanism, the instruction sequence can not only adapt to the frequency fluctuation in real time, that is, when the error is large, the encryption is improved to improve the precision, and when the error is small, the precision is simplified to reduce the load, but also can eliminate the execution "window period" in advance, and finally the controller instruction and the execution rate of the driver are accurately matched, and the smoothness and response efficiency of the system control are significantly improved.

[0059] In summary, steps S3-1 to S3-3 achieve accurate matching of the controller instruction and the execution rate of the driver through three steps: first, combining the frequency error and the sequence characteristics of the cache, an association system including error intervals, sequence parameters, and adjustment coefficients is constructed to provide a quantitative standard for adjustment; then, according to the standard, the real-time error and sequence characteristics are converted into explicit adjustment direction and amplitude of interpolation times to ensure that the decision fits the current working condition; finally, the interpolation times are updated based on the adjustment result, an optimized intermediate instruction sequence is generated, and the pre-adjustment is combined with the prediction mechanism, and finally an instruction stream matching the execution rate of the driver is output. The process forms a closed loop of "standard setting-real-time decision-dynamic optimization", which effectively improves the smoothness and response efficiency of the system control.

[0060] As a possible implementation, in the above embodiment, step S3-1 can specifically include the following steps: S3-1-1, using the frequency error value of the controller instruction, obtaining the historical fluctuation range of the frequency error value; According to the frequency error value Δ f statistical analysis is performed to extract the historical fluctuation range of the error value, for example, 2000 groups of error data in the past are analyzed to obtain the maximum value of the frequency error as 4.5 Hz and the minimum value as -3.8 Hz, thereby determining the historical fluctuation range as [-3.8 Hz, 4.5 Hz], and recording the distribution probability of the error in different sub-intervals, such as 75% within ±2 Hz. This step provides a real error distribution basis for subsequent interval division, ensuring that subsequent operations are based on the actual frequency fluctuation characteristics of the system.

[0061] S3-1-2, dividing error intervals according to the historical fluctuation range of the frequency error value; Based on the obtained historical fluctuation range [-3.8 Hz, 4.5 Hz], and according to the influence degree of the error on the control performance, the error intervals are divided according to the "influence gradient": the interval with less influence on the control precision is defined as the low error interval, that is, |Δ f ≤1 Hz; the interval with medium influence is defined as the medium error interval, that is, 1 Hz<|Δ f|≤3Hz; significant impact is defined as high error interval, i.e. |Δ f |>3Hz. This division converts continuous error values into discrete levels, enabling subsequent analysis and adjustment to develop differentiated strategies for different volatility intensities.

[0062] S3-1-3, feature analysis of the controller instruction sequence of the interpolation cache based on the error interval, obtaining sequence feature parameters; For each error interval, extract the key features of the interpolation cache instruction sequence in the interval: calculate the interpolation volatility rate of adjacent intermediate instructions and the execution feedback deviation, and determine the feature threshold of each interval in combination with the control target, wherein the interpolation volatility rate of adjacent intermediate instructions reflects the smoothness of the sequence, and the execution feedback deviation reflects the execution accuracy. For example, high error interval requires higher smoothness, interpolation volatility rate threshold is set to ≤5%; medium error interval is set to ≤10%; low error interval is set to ≤15%; and the execution feedback deviation threshold is uniformly set to ≤±3% to ensure basic accuracy. This step establishes the correlation between error volatility and sequence quality, and sets clear standards for sequence performance in different scenarios.

[0063] S3-1-4, obtaining interpolation frequency adjustment coefficient based on the error interval and the sequence feature parameters; Based on the correlation between error interval and sequence feature parameters, match the interpolation frequency adjustment coefficient: high error interval corresponds to coefficient k h =0.3 to improve smoothness with fast encryption instructions, wherein the interpolation frequency adjustment amplitude is amplified by 30% for each 1Hz increase in error; medium error interval corresponds to coefficient k m =0.18 to balance accuracy and computing power, and low error interval corresponds to coefficient k l =0.09 for minor adjustments when error is low to avoid excessive interpolation.

[0064] S3-1-5, obtaining corresponding boundary parameters according to the interpolation frequency adjustment coefficient; Set the boundary parameters of interpolation frequency according to the interpolation frequency adjustment coefficient, N min =6, N max =35 to prevent adjustment from exceeding the system computing power carrying range.

[0065] In summary, steps S3-1-1 to S3-1-5 build a quantitative parameter system of "error level-sequence standard-adjustment intensity" by directly associating the dynamic characteristics of frequency error with the quality requirements of the interpolation cache sequence, so that the subsequent adjustment not only conforms to the objective law of frequency fluctuation, but also accurately matches the sequence smoothness and execution accuracy requirements, providing a scientific and reusable benchmark rule for dynamic adjustment.

[0066] As a possible implementation, in the above embodiment, step S3-2 can specifically include the following steps: S3-2-1, according to the controller instruction sequence of the interpolation cache, obtaining the actual interpolation fluctuation rate of the interpolation cache sequence and the execution feedback deviation; From the controller instruction sequence of the interpolation cache, the numerical difference of adjacent intermediate instructions is extracted, and the actual fluctuation rate is calculated by formula: V = (maximum interpolation of adjacent instructions / average instruction value of sequence) x 100%, quantifying sequence smoothness; at the same time, comparing the theoretical output value of the instructions in the sequence with the actual execution feedback value of the driver, calculating the absolute value of the deviation percentage of the theoretical value, i.e. execution feedback deviation D .

[0067] S3-2-2, judging whether the frequency error value of the controller instruction conforms to the high error interval, if yes, obtaining the frequency error value of the controller instruction as the high frequency error value, and executing S3-2-3, otherwise, executing S3-2-4; This step realizes the shunt of high error working condition and non-high error working condition through the first threshold judgment, ensures that the adjustment logic is started in priority under the condition of extreme frequency fluctuation, and clearly defines the execution path for subsequent operation.

[0068] S3-2-3, according to the actual interpolation fluctuation rate of the interpolation cache sequence and the execution feedback deviation, combining the high frequency error value, the sequence characteristic parameter, the interpolation times adjustment coefficient and the corresponding boundary parameter, obtaining the adjustment direction and adjustment amplitude of the interpolation times of the high error interval as the interpolation times adjustment direction and interpolation times adjustment amplitude respectively; The real-time frequency error value Δ f is compared with the threshold value Δ f th If |Δ f |> 3 Hz, i.e. conforming to the high error interval, the adjustment coefficient ( k h = 0.3) and boundary parameter ( V ≤ 5%、 D ≤ ± 3%) of the high error interval are called, and the obtained V and D determine the adjustment direction and amplitude according to the four combination cases of the high error interval, as follows: When V > 5% and D > 3%, the sequence smoothness and precision are both substandard, and the interpolation frequency needs to be increased, such as Δ f = 4 Hz, the interpolation frequency adjustment range Δ N h = 0.3 k h × |Δ f | = 0.3 x 4 = 1.2 → rounded up to 2 times, and the sequence quality is improved by encryption interpolation; When V > 5% and D ≤ 3%, the smoothness is substandard but the precision is qualified, and the interpolation frequency needs to be increased, such as Δ f = 3.2 Hz, the interpolation frequency adjustment range Δ N h = 0.3 k h × |Δ f | = 0.3 x 3.2 = 0.96 → rounded up to 1 time, and the sequence smoothness is improved preferentially; When V ≤ 5% and D > 3%, the smoothness is qualified but the precision is insufficient, and the interpolation frequency needs to be increased, such as Δ f = 3.8 Hz, the interpolation frequency adjustment range Δ N h = 0.3 k h × |Δ f | = 0.3 x 3.8 = 1.14 → rounded up to 2 times, and the tracking precision is improved by refining interpolation; When V ≤ 5% and D ≤ 3%, the smoothness and precision are both qualified, and the current interpolation frequency is maintained, that is, the interpolation frequency adjustment range Δ N h = 0, to avoid excessive interpolation and increase system load.

[0069] S3-2-4, determine whether the frequency error value of the controller instruction meets the medium error range, if yes, take the frequency error value of the controller instruction as the medium frequency error value, and execute S3-2-5, otherwise, take the frequency error value of the controller instruction as the low frequency error value, and execute S3-2-6; This step realizes accurate division of error ranges through secondary threshold judgment, so that the adjustment logic of medium and low error conditions is triggered in order, and the adjustment scheme is adapted to different fluctuation degrees combined with corresponding parameter output, to ensure that the adjustment decisions in the whole error range are matched with the working conditions.

[0070] S3-2-5. Based on the actual interpolation volatility and execution feedback deviation of the interpolation buffer sequence, combined with the mid-frequency error value, the sequence characteristic parameters, the interpolation number adjustment coefficient and the corresponding boundary parameters, the adjustment direction and adjustment magnitude of the interpolation number in the mid-error interval are obtained as the interpolation number adjustment direction and the interpolation number adjustment magnitude, respectively. The real-time frequency error value Δ f With this threshold Δ f th In comparison, if 1Hz < |Δ f |≤3Hz, which meets the standard error range, so the adjustment coefficient for the standard error range is applied. k m =0.18) and boundary parameters ( V ≤10%, D ≤±3%), obtained V and D The adjustment direction and magnitude are determined based on four combinations of the mean error range, as follows: when V >10% and D When the accuracy is greater than 3%, both smoothness and accuracy fail to meet the requirements, necessitating an increase in the number of interpolation iterations, such as Δ. f At 2.5Hz, the adjustment range Δ of the interpolation number in the mean error interval N m = k m ×|Δ f |=0.18×2.5=0.45→Round up to 1, simultaneously optimizing smoothness and accuracy; when V >10% and D When the accuracy is ≤3%, the smoothness is not up to standard but the accuracy is acceptable. The number of interpolations needs to be increased, such as Δ. f When the frequency is 1.8Hz, the adjustment range Δ of the interpolation number in the mean error interval is... N m = k m ×|Δ f |=0.18×1.8=0.324→Round up to 1, focusing on improving sequence smoothness; when V ≤10% and D When the accuracy is greater than 3%, the smoothness meets the standard but the accuracy is insufficient, requiring an increase in the number of interpolation iterations, such as Δ. f When the frequency is 2.2Hz, the adjustment range Δ of the interpolation number in the mean error interval is... N m = k m ×|Δ f=0.18×2.2=0.396→Rounded up to 1, specifically improving tracking accuracy; when V ≤10% and D When the error is ≤3%, both smoothness and accuracy meet the standards. The current interpolation count is maintained, meaning the interpolation count adjustment range Δ within the mean error interval is adjusted. N m =0, balancing control effectiveness and system resource consumption.

[0071] S3-2-6. Based on the actual interpolation volatility and execution feedback deviation of the interpolation buffer sequence, combined with the low-frequency error value, the sequence characteristic parameters, the interpolation number adjustment coefficient and the corresponding boundary parameters, the adjustment direction and adjustment magnitude of the interpolation number in the low error interval are obtained as the interpolation number adjustment direction and the interpolation number adjustment magnitude, respectively. The real-time frequency error value Δ f With this threshold Δ f th In comparison, if |Δ f |≤1Hz, which meets the low error range, so the adjustment coefficient for the low error range is applied. k l =0.09) and boundary parameters ( V ≤15%, D ≤±3%), obtained V and D The adjustment direction and magnitude are determined based on four combinations of low error ranges, as detailed below: when V >15% and D When the error rate is greater than 3%, both smoothness and accuracy fail to meet the standards. Reducing the number of interpolations is prohibited; the current number must be maintained, meaning the adjustment range Δ for the number of interpolations in the low error range is [not specified]. N l =0, to avoid performance degradation; when V >15% and D When the error is ≤3%, the smoothness is not up to standard but the accuracy is acceptable. Reducing the number of interpolations is prohibited; the current number should be maintained. That is, the adjustment range Δ for the number of interpolations in the low error range is... N l =0, adjust after smoothness improves; when V ≤15% and D When the error rate is >3%, the smoothness meets the standard but the accuracy is insufficient. Reducing the number of interpolations is prohibited; the current number of interpolations should be maintained. This means the adjustment range Δ for the number of interpolations in the low error range is not allowed. N l =0, prioritizing accuracy; when V ≤15% and D≤3%, both smoothness and accuracy meet the standard, and the interpolation frequency can be reduced, such as Δ f = 0.7 Hz, the interpolation frequency adjustment range of the low error interval Δ N l = k l × |Δ f | = -0.09 * 0.7 = -0.063 → rounded down to -1, reducing system load.

[0072] In summary, steps S3-2-1 to S3-2-6 convert abstract errors and sequence characteristics into specific adjustment directions and amplitudes through direct comparison of parameters and real-time data, ensuring that the adjustment decision not only fits the current working condition but also meets the preset quantitative standard, avoiding adjustment errors caused by single indicator judgment.

[0073] As a possible implementation, in the above embodiment, step S3-3 can specifically include the following steps: S3-3-1, obtaining the initial interpolation frequency corresponding to the initial interpolation frequency using the initial interpolation frequency; The frequency is directly used as the initial interpolation frequency, that is, the initial interpolation frequency = initial interpolation frequency. This step provides a reference starting point for subsequent dynamic adjustment through direct mapping of frequency and number, ensuring that there is an executable basic interpolation frequency at the start of the system, avoiding the disconnection of indicators caused by parameter missing in the initial stage.

[0074] S3-3-2, adjusting the interpolation frequency based on the initial interpolation frequency and the interpolation frequency adjustment direction, and calculating the real-time interpolation frequency; Taking the determined initial interpolation frequency (such as 10 times) as the starting point, combining the obtained adjustment direction and amplitude, the real-time interpolation frequency is calculated: when the adjustment direction is increased, the real-time frequency = initial frequency + adjustment amplitude N = 10 + 2 = 12 times; when the direction is reduced, the real-time frequency = initial frequency - adjustment amplitude. At the same time, it is necessary to check whether the result is within the preset boundary, if it exceeds the boundary, it is forced to be corrected to the nearest boundary value, to ensure that the interpolation frequency is within the system algorithm load range. This step realizes the transition from the initial reference to the real-time adaptation, so that the interpolation frequency can quickly respond to the change of frequency error.

[0075] S3-3-3, according to the real-time interpolation frequency, using the interpolation algorithm to perform interpolation cache processing on the controller instruction, and obtaining a new interpolation cache controller instruction sequence; Use the updated interpolation frequency to call the matching interpolation algorithm to re-interpolate the original controller instruction, for example, use 12 times of interpolation to generate 12 intermediate instructions in the high error scenario, and the timestamps are strictly aligned with the driver execution period (such as 2ms) t k+2ms, t k +4ms…), and synchronously update the newly generated sequence to the current execution area and the preloaded area of the interpolation cache area, the current execution area outputs instructions to the driver in real time according to the timestamp, and the preloaded area reserves the interpolation sequence of the next group of original instructions in advance.

[0076] S3-3-4, based on the frequency error value of the controller instruction and the controller instruction sequence of the interpolation cache, respectively, obtain the frequency error trend and the cache sequence characteristic change; The frequency error values of the last 3-5 control periods are continuously collected, and the frequency error trend is determined by calculating the error mean and the fluctuation slope. At the same time, the characteristic parameters of the interpolation cache sequence in the corresponding period are extracted, including the interpolation fluctuation rate of adjacent intermediate instructions, the mean of execution feedback deviation, etc., to form a cache sequence characteristic change curve. This step provides historical basis for subsequent prediction by accumulating multi-period data, avoiding the accidental influence of single-period data on judgment.

[0077] S3-3-5, according to the new interpolation cache controller instruction sequence, combining the frequency error trend and the cache sequence characteristic change, obtaining the instruction stream synchronized with the driver execution period as the instruction segmentation prediction rate matching result; Taking the new interpolation cache sequence as the basis, combining the obtained frequency error trend and cache sequence characteristic change, predicting the error interval of the next period, and adjusting the interpolation times of the preloaded area in advance. When the instructions of the current execution area are output to the remaining 1 / 3, trigger the cache switching, the sequence of the preloaded area seamlessly accesses the current execution area, ensuring that the output instruction stream is always synchronized with the driver execution period (such as 2ms). The finally formed continuous, smooth and adaptive real-time error trend instruction stream is the instruction segmentation prediction rate matching result, realizing the dynamic and accurate matching of controller instructions and driver execution.

[0078] In summary, steps S3-3-1 to S3-3-5 update the interpolation times in real time, so that the intermediate instruction sequence can dynamically adapt to frequency fluctuations, avoiding the precision deficiency or waste of computing power caused by fixed times; the boundary constraint ensures the stability of the system running; the prediction optimization and cache switching mechanism completely eliminates the "window period" of instruction output, and finally realizes the accurate matching of controller instructions and driver execution rate, significantly improving the continuity and response accuracy of the control process.

[0079] The interpolation frequency adjustment is a dynamic optimization layer, which is a dynamic optimization on the interpolation frequency corresponding to the initial interpolation multiple. The interpolation frequency adjustment combines the real-time frequency error fluctuation and the actual execution characteristics (such as smoothness and deviation) of the cache sequence to perform fine-grained fine-tuning, makes up for the limitation that the benchmark setting cannot cope with real-time working condition changes, and finally realizes the accurate matching of the interpolation density and the frequency fluctuation and the execution demand. The two form a progressive mechanism of “basic anchoring-dynamic calibration” together to jointly ensure the balance of the accuracy, continuity and computing power efficiency of the instruction sequence in the frequency fluctuation scene.

[0080] Those skilled in the art will appreciate that embodiments of the application can be provided as methods, systems, or computer program products. Accordingly, the application can be embodied in the form of complete hardware embodiments, complete software embodiments, or embodiments combining software and hardware aspects. Moreover, the application can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROMs, optical storage, etc.) having computer usable program code embodied thereon.

[0081] The application is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the application. It should be understood that each flow and / or block in the flowcharts and / or block diagrams, as well as combinations of flows and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing apparatus to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing apparatus produce an apparatus that implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1 The functions specified in one or more flows and / or blocks.

[0082] These computer program instructions can also be stored in a computer-readable memory that can direct the computer or other programmable data processing apparatus to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including instruction apparatus, which implements the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1 The functions specified in one or more flows and / or blocks.

[0083] These computer program instructions can also be loaded onto a computer or other programmable data processing apparatus, so that a series of operation steps are performed on the computer or other programmable data processing apparatus to produce a computer-implemented process, so that the instructions executed on the computer or other programmable data processing apparatus provide a process for implementing the functions specified in the flowcharts and / or block diagrams. Figure 1 The functions specified in one or more flows and / or blocks. Figure 1 The functions specified in one or more flows and / or blocks.

[0084] It should be pointed out finally that the above embodiments are only used to illustrate the technical solutions of the present application but not to limit it. Although the present application has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the specific embodiments of the present application can be modified or equivalently replaced without departing from the spirit and scope of the present application, and any modification or equivalent replacement should be covered in the protection scope of the claims of the present application.

Claims

1. A method for distributed controller-driver instruction partitioning rate matching, the method comprising: receiving a plurality of instructions from a controller; determining a plurality of driver instructions from the plurality of instructions; and sending the plurality of driver instructions to a plurality of drivers. The method comprises the steps of: S1, using the clock source of the driver to detect the instruction frequency, and obtaining the frequency error value of the controller instruction; S2, based on the frequency error value of the controller instruction, using an interpolation algorithm to perform interpolation cache processing on the controller instruction, and obtaining the interpolation cached controller instruction sequence; S3, according to the frequency error value of the controller instruction and the interpolation cached controller instruction sequence, dynamically adjusting the interpolation times, and obtaining the instruction segmentation prediction rate matching result.

2. The method of claim 1, wherein the method is performed by a distributed controller-driver. S1, using the clock source of the driver to detect the instruction frequency, and obtaining the frequency error value of the controller instruction, comprising: Initializing a double timer based on the clock source of the driver, the double timer comprising a first timer and a second timer; According to the clock source of the driver, using the first timer to obtain the actual control instruction period; Generating a theoretical control instruction period through the second timer; Comparing the actual control instruction period with the theoretical control instruction period to obtain the frequency error value of the controller instruction.

3. The method of claim 2, wherein the method is performed by a distributed controller-driver. S2, based on the frequency error value of the controller instruction, using an interpolation algorithm to perform interpolation cache processing on the controller instruction, and obtaining the interpolation cached controller instruction sequence, comprising: According to the frequency error value of the controller instruction, setting a reference interpolation multiple and a frequency error threshold; Using the frequency error value of the controller instruction and the frequency error threshold to determine the interpolation algorithm; Based on the frequency error value of the controller instruction, dynamically adjusting the reference interpolation multiple using the actual control instruction period and the theoretical control instruction period to determine the initial interpolation multiple; Based on the initial interpolation multiple, using the interpolation algorithm to perform interpolation cache processing on the controller instruction, and obtaining the interpolation cached controller instruction sequence.

4. The method of claim 3, wherein the method further comprises: According to the frequency error value of the controller instruction, setting a reference interpolation multiple and a frequency error threshold, comprising: Judging whether the frequency error value of the controller instruction is greater than the frequency error threshold, if yes, obtaining a linear interpolation algorithm as the interpolation algorithm, otherwise, performing a first operation; Wherein, the first operation is: judging whether the frequency error value of the controller instruction meets the frequency error threshold, if yes, obtaining a quadratic polynomial interpolation algorithm as the interpolation algorithm, otherwise, obtaining a spline interpolation algorithm as the interpolation algorithm.

5. The method of claim 3, wherein the method is a distributed controller- driver instruction partitioning and predictive rate matching method, and wherein the method further comprises: Based on the frequency error value of the controller instruction, dynamically adjusting the reference interpolation multiple using the actual control instruction period and the theoretical control instruction period to determine the initial interpolation multiple, comprising: Using the actual control instruction period and the theoretical control instruction period to obtain the deviation rate of the actual control instruction period and the theoretical control instruction period as the real-time deviation rate; According to the real-time deviation rate and the frequency error value of the controller instruction, determining the reference interpolation multiple adjustment amount; Based on the interpolation times adjustment direction, adjusting the interpolation times to obtain the instruction segmentation prediction rate matching result.

6. The method of claim 3, wherein the method is a distributed controller- driver instruction partitioning and predictive rate matching method, and wherein the method further comprises: Based on the initial interpolation multiple, using the interpolation algorithm to perform interpolation cache processing on the controller instruction, and obtaining the interpolation cached controller instruction sequence, comprising: determining a synchronization timestamp of an intermediate controller instruction according to the initial interpolation multiple based on the controller instruction; interpolating the controller instruction based on the synchronization timestamp of the intermediate controller instruction using the interpolation algorithm to obtain an intermediate controller instruction sequence; performing double buffering on the intermediate controller instruction sequence to obtain an interpolation buffered controller instruction sequence.

7. The method of claim 3, wherein the method is a distributed controller- driver instruction partitioning and predictive rate matching method. S3, dynamically adjusting an interpolation number based on the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence to obtain an instruction segmentation predicted rate matching result, comprising: setting an interpolation number adjustment coefficient and a corresponding boundary parameter using the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence; determining an interpolation number adjustment direction and an interpolation number adjustment amplitude based on the interpolation number adjustment coefficient and the corresponding boundary parameter in combination with the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence; adjusting the interpolation number based on the interpolation number adjustment direction to obtain an instruction segmentation predicted rate matching result.

8. The method of claim 7, wherein the method further comprises: setting an interpolation number adjustment coefficient and a corresponding boundary parameter using the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence, comprising: obtaining a historical fluctuation range of the frequency error value using the frequency error value of the controller instruction; dividing error intervals based on the historical fluctuation range of the frequency error value, the error intervals including a high error interval, a medium error interval, and a low error interval; performing feature analysis on the interpolation buffered controller instruction sequence based on the error intervals to obtain sequence feature parameters; obtaining an interpolation number adjustment coefficient based on the error intervals and the sequence feature parameters; obtaining a corresponding boundary parameter based on the interpolation number adjustment coefficient.

9. The method of claim 8, wherein the method further comprises: determining an interpolation number adjustment direction and an interpolation number adjustment amplitude based on the interpolation number adjustment coefficient and the corresponding boundary parameter in combination with the frequency error value of the controller instruction and the interpolation buffered controller instruction sequence, comprising: obtaining an actual interpolation fluctuation rate and an execution feedback deviation of the interpolation buffered sequence based on the interpolation buffered controller instruction sequence; determining whether the frequency error value of the controller instruction conforms to the high error interval, if yes, obtaining the frequency error value of the controller instruction as a high frequency error value and performing a second operation, otherwise, performing a third operation; wherein the second operation is: obtaining an adjustment direction and an adjustment amplitude of the interpolation number in the high error interval as the interpolation number adjustment direction and the interpolation number adjustment amplitude respectively based on the actual interpolation fluctuation rate and the execution feedback deviation of the interpolation buffered sequence in combination with the high frequency error value, the sequence feature parameters, the interpolation number adjustment coefficient, and the corresponding boundary parameter; the third operation is: determining whether the frequency error value of the controller instruction conforms to the medium error interval, if yes, obtaining the frequency error value of the controller instruction as a medium frequency error value and performing a fourth operation, otherwise, obtaining the frequency error value of the controller instruction as a low frequency error value and performing a fifth operation; The fourth operation is: according to the actual interpolation fluctuation rate of the interpolation cache sequence and the execution feedback deviation, combining the medium frequency error value, the sequence characteristic parameter, the interpolation frequency adjustment coefficient and the corresponding boundary parameter, the adjustment direction and the adjustment amplitude of the interpolation frequency of the medium error interval are obtained as the interpolation frequency adjustment direction and the interpolation frequency adjustment amplitude respectively. The fifth operation is: according to the actual interpolation fluctuation rate of the interpolation cache sequence and the execution feedback deviation, combining the low frequency error value, the sequence characteristic parameter, the interpolation frequency adjustment coefficient and the corresponding boundary parameter, the adjustment direction and the adjustment amplitude of the interpolation frequency of the low error interval are obtained as the interpolation frequency adjustment direction and the interpolation frequency adjustment amplitude respectively.

10. The method of claim 7, wherein the method is a distributed controller- driver instruction partitioning and predictive rate matching method. Based on the interpolation frequency adjustment direction, the interpolation frequency is adjusted to obtain the instruction segmentation prediction rate matching result, including: Using the initial interpolation multiple, the corresponding initial interpolation frequency is obtained; Based on the initial interpolation frequency, the interpolation frequency is adjusted based on the interpolation frequency adjustment direction to calculate the real-time interpolation frequency; According to the real-time interpolation frequency, the interpolation cache processing is carried out on the controller instruction by using the interpolation algorithm, and a new interpolation cache controller instruction sequence is obtained; Based on the frequency error value of the controller instruction and the interpolation cache controller instruction sequence, the frequency error trend and the cache sequence characteristic change are obtained respectively; According to the new interpolation cache controller instruction sequence, combining the frequency error trend and the cache sequence characteristic change, the instruction flow synchronized with the driver execution cycle is obtained as the instruction segmentation prediction rate matching result.

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