A distributed controller-driver instruction partitioning and rate matching method

Abstract

The application discloses a kind of distributed controller-driver instruction segmentation prediction rate matching methods, it is related to distributed control technical field, including: using the clock source of driver to carry out instruction frequency detection, the frequency error numerical value of controller instruction is obtained;Based on the frequency error numerical value of the controller instruction, interpolation algorithm is used to carry out interpolation cache processing to controller instruction, and the controller instruction sequence of interpolation cache is obtained;According to the frequency error numerical value of the controller instruction and the controller instruction sequence of interpolation cache, dynamic interpolation frequency adjustment is carried out, and instruction segmentation prediction rate matching result is obtained.The application can automatically optimize instruction segmentation strategy according to real-time frequency error by dynamic interpolation frequency adjustment mechanism, still maintain high-precision interpolation when controller instruction frequency fluctuates, avoid the cumulative error caused by fixed interpolation, significantly improve control instruction execution precision.

Description

Technical Field

[0001] This invention relates to the field of distributed control technology, and in particular to a method for instruction segmentation prediction rate matching of a distributed controller-driver. Background Technology

[0002] In distributed control systems, the issue cycle of controller commands and the execution cycle of actuators often have a non-integer multiple relationship, leading to "window periods" or "backlogs" of commands at the actuator end. Traditional solutions extend commands by using a fixed interpolation factor, but when the controller command frequency fluctuates, the fixed interpolation strategy introduces accumulated errors, reducing control accuracy. For example, in precision machinery control scenarios, non-uniform interpolation of commands may cause distortion of motion trajectories; while in high-frequency response systems, a fixed number of divisions is difficult to match dynamically changing command frequencies, easily leading to wasted computing power or response delays at the execution end. Furthermore, traditional methods require pre-configuration of interpolation parameters, resulting in poor adaptability to different operating conditions and increasing the complexity of system debugging.

[0003] Therefore, there is an urgent need for a distributed controller-driver instruction segmentation prediction rate matching method to address the shortcomings of existing technologies. Summary of the Invention

[0004] The purpose of this invention is to propose a distributed controller-driver instruction segmentation prediction rate matching method to solve the problems of poor execution continuity, low accuracy, and wasted computing power caused by the non-integer multiples of the controller instruction issuance and driver execution cycle and the fluctuation of instruction frequency.

[0005] To achieve the above objectives, the present invention provides a method for instruction segmentation prediction rate matching of a distributed controller-driver system, comprising the following steps:

[0006] S1. Use the driver's clock source to detect the command frequency and obtain the frequency error value of the controller command;

[0007] S2. Based on the frequency error value of the controller command, an interpolation algorithm is used to perform interpolation caching on the controller command to obtain the interpolated cached controller command sequence;

[0008] S3. Adjust the number of interpolations based on the frequency error value of the controller instruction and the controller instruction sequence in the interpolation cache to obtain the instruction segmentation prediction rate matching result.

[0009] Optionally, S1, using the driver's clock source to detect the command frequency and obtain the frequency error value of the controller command, including:

[0010] The dual timers are initialized based on the clock source of the driver, and the dual timers include a first timer and a second timer;

[0011] The actual control command cycle is obtained using the first timer based on the clock source of the driver;

[0012] The theoretical control command cycle is generated using the second timer;

[0013] The actual control command cycle is compared with the theoretical control command cycle to obtain the frequency error value of the controller command.

[0014] Optionally, S2, based on the frequency error value of the controller command, an interpolation algorithm is used to perform interpolation caching on the controller command, and the interpolated cached controller command sequence is obtained, including:

[0015] Based on the frequency error value of the controller command, set the reference interpolation multiple and the frequency error threshold;

[0016] The interpolation algorithm is determined by using the frequency error value of the controller command and the frequency error threshold.

[0017] Based on the frequency error value of the controller command, the reference interpolation factor is dynamically adjusted using the actual control command period and the theoretical control command period to determine the initial interpolation factor;

[0018] Based on the initial interpolation factor, the interpolation algorithm is used to perform interpolation caching on the controller instructions to obtain the interpolated cached controller instruction sequence.

[0019] Optionally, based on the frequency error value of the controller command, a reference interpolation factor and a frequency error threshold are set, including:

[0020] Determine whether the frequency error value of the controller command is greater than the frequency error threshold. If so, obtain the linear interpolation algorithm as the interpolation algorithm; otherwise, perform the first operation.

[0021] The first operation is as follows: determine whether the frequency error value of the controller command meets the frequency error threshold. If yes, obtain a quadratic polynomial interpolation algorithm as the interpolation algorithm; otherwise, obtain a spline interpolation algorithm as the interpolation algorithm.

[0022] Optionally, based on the frequency error value of the controller command, the reference interpolation factor is dynamically adjusted using the actual control command period and the theoretical control command period to determine the initial interpolation factor, including:

[0023] The deviation rate between the actual control command cycle and the theoretical control command cycle is obtained as the real-time deviation rate by using the actual control command cycle and the theoretical control command cycle.

[0024] The reference interpolation factor adjustment amount is determined based on the frequency error value between the real-time deviation rate and the controller command.

[0025] The interpolation count is adjusted based on the direction of the interpolation count adjustment to obtain the instruction segmentation prediction rate matching result.

[0026] Optionally, based on the initial interpolation factor, the interpolation algorithm is used to perform interpolation caching on the controller instructions to obtain the interpolated cached controller instruction sequence, including:

[0027] Based on the controller instructions and the initial interpolation multiple, determine the synchronization timestamp of the intermediate controller instructions;

[0028] Based on the synchronization timestamp of the intermediate controller instruction, the interpolation algorithm is used to interpolate the controller instruction to obtain the intermediate controller instruction sequence;

[0029] The intermediate controller instruction sequence is subjected to double buffering to obtain the interpolated buffered controller instruction sequence.

[0030] Optionally, S3, dynamically adjusting the number of interpolations based on the frequency error value of the controller instruction and the controller instruction sequence in the interpolation buffer to obtain the instruction segmentation prediction rate matching result, including:

[0031] Using the frequency error value of the controller command and the controller command sequence of the interpolation buffer, the interpolation number adjustment coefficient and the corresponding boundary parameters are set;

[0032] Based on the interpolation number adjustment coefficient and the corresponding boundary parameters, combined with the frequency error value of the controller instruction and the controller instruction sequence of the interpolation buffer, the direction and magnitude of the interpolation number adjustment are determined.

[0033] The interpolation count is adjusted based on the direction of the interpolation count adjustment to obtain the instruction segmentation prediction rate matching result.

[0034] Optionally, using the frequency error value of the controller command and the controller command sequence in the interpolation buffer, an interpolation number adjustment coefficient and corresponding boundary parameters are set, including:

[0035] The historical fluctuation range of the frequency error value is obtained by using the frequency error value of the controller command;

[0036] Based on the historical fluctuation range of the frequency error value, the error interval is divided, including a high error interval, a medium error interval, and a low error interval.

[0037] Based on the error interval, perform feature analysis on the controller instruction sequence of the interpolation buffer to obtain sequence feature parameters;

[0038] Based on the error interval and the sequence feature parameters, the interpolation number adjustment coefficient is obtained;

[0039] Adjust the coefficients according to the interpolation number to obtain the corresponding boundary parameters.

[0040] Optionally, the direction and magnitude of the interpolation number adjustment are determined based on the interpolation number adjustment coefficient and the corresponding boundary parameters, combined with the frequency error value of the controller instruction and the controller instruction sequence in the interpolation buffer, including:

[0041] Based on the controller instruction sequence of the interpolation cache, obtain the actual interpolation volatility and execution feedback deviation of the interpolation cache sequence;

[0042] Determine whether the frequency error value of the controller instruction conforms to the high error range. If so, obtain the frequency error value of the controller instruction as the high frequency error value and perform the second operation; otherwise, perform the third operation.

[0043] The second operation is as follows: based on the actual interpolation volatility and execution feedback deviation of the interpolation cache sequence, combined with the high-frequency error value, the sequence feature parameters, the interpolation number adjustment coefficient and the corresponding boundary parameters, the adjustment direction and adjustment magnitude of the interpolation number in the high error interval are obtained as the interpolation number adjustment direction and the interpolation number adjustment magnitude, respectively.

[0044] The third operation is: determining whether the frequency error value of the controller instruction conforms to the medium error range; if so, obtaining the frequency error value of the controller instruction as the medium frequency error value and performing the fourth operation; otherwise, obtaining the frequency error value of the controller instruction as the low frequency error value and performing the fifth operation.

[0045] The fourth operation is as follows: based on the actual interpolation volatility and execution feedback deviation of the interpolation buffer sequence, combined with the mid-frequency error value, the sequence characteristic parameters, the interpolation number adjustment coefficient and the corresponding boundary parameters, the adjustment direction and adjustment magnitude of the interpolation number in the mid-error interval are obtained as the interpolation number adjustment direction and the interpolation number adjustment magnitude, respectively.

[0046] The fifth operation is as follows: based on the actual interpolation volatility and execution feedback deviation of the interpolation cache sequence, combined with the low-frequency error value, the sequence characteristic parameters, the interpolation number adjustment coefficient and the corresponding boundary parameters, the adjustment direction and adjustment magnitude of the interpolation number in the low error interval are obtained as the interpolation number adjustment direction and the interpolation number adjustment magnitude, respectively.

[0047] Optionally, the interpolation count is adjusted based on the interpolation count adjustment direction to obtain the instruction segmentation prediction rate matching result, including:

[0048] Using the initial interpolation factor, obtain the corresponding initial interpolation count;

[0049] The interpolation count is adjusted based on the initial interpolation count and the direction of the interpolation count adjustment, and the real-time interpolation count is calculated.

[0050] The interpolation algorithm is used to perform interpolation caching on the controller instructions based on the number of real-time interpolations to obtain a new interpolated cached sequence of controller instructions;

[0051] Based on the frequency error value of the controller command and the controller command sequence of the interpolation cache, the frequency error trend and cache sequence feature changes are obtained respectively;

[0052] Based on the controller instruction sequence of the new interpolation cache, combined with the frequency error trend and the characteristic changes of the cache sequence, an instruction stream synchronized with the driver execution cycle is obtained as the instruction segmentation prediction rate matching result.

[0053] Compared with the closest existing technology, the present invention has the following advantages:

[0054] Unlike traditional synchronization mechanisms that rely on master-slave bidirectional communication, this invention innovatively integrates the clock compensation function entirely into the driver side for independent implementation. This completely eliminates the need for transmitting periodic frequency offset data in the uplink / downlink channels of the control loop. This not only avoids additional bandwidth consumption for real-time communication but also avoids the design burden of extending and customizing protocols for synchronization correction, thus fully preserving the standardized interface and compatibility of the existing controller-driver architecture. Specific effects are as follows:

[0055] This invention introduces a dynamic interpolation frequency adjustment mechanism, which automatically optimizes the instruction segmentation strategy based on real-time detected frequency errors. This maintains interpolation accuracy even when the controller instruction frequency fluctuates, effectively avoiding the cumulative errors caused by fixed interpolation and significantly improving the execution accuracy of control instructions. Through instruction segmentation prediction, it achieves "pre-loading" of instructions, eliminating the "window period" of instructions at the driver end, enabling the execution end to respond to controller instructions continuously and smoothly. This is particularly suitable for scenarios with extremely high requirements for instruction continuity, such as precision trajectory control. The dynamic adjustment mechanism can adaptively allocate computing power according to the magnitude of the frequency error. When the error is small, it reduces the number of interpolations to reduce the computational load; when the error is large, it increases the number of interpolations to ensure accuracy, achieving optimal allocation of computing resources. Without the need for pre-configuration of interpolation parameters, the system can automatically adapt to the instruction frequency characteristics under different operating conditions, reducing debugging difficulty and improving the adaptability of the technical solution in complex industrial environments. Attached Figure Description

[0056] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0057] Figure 1 This is a flowchart illustrating a distributed controller-driver instruction segmentation prediction rate matching method according to an embodiment of the present invention. Detailed Implementation

[0058] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0059] The terminology used in the embodiments section of this invention is for the purpose of explaining specific embodiments of the invention only, and is not intended to limit the invention.

[0060] like Figure 1 As shown, this embodiment of the invention provides a method for instruction segmentation prediction rate matching of a distributed controller-driver, comprising:

[0061] S1. Use the driver's clock source to detect the command frequency and obtain the frequency error value of the controller command;

[0062] The driver calculates the time interval between commands issued by the controller in real time using its own clock source and compares it with the theoretical reference time interval to detect the frequency error between the controller and the driver. This step can automatically identify a wide range of frequency deviations, avoiding the complexity of additional communication and protocol synchronization required in traditional solutions. This step achieves efficient and independent detection of the controller command frequency, providing basic data support for subsequent synchronization adjustments.

[0063] S2. Based on the frequency error value of the controller command, an interpolation algorithm is used to perform interpolation caching on the controller command to obtain the interpolated cached controller command sequence;

[0064] The driver determines the frequency error value Δ based on the detected frequency. fThe original instructions issued by the controller are smoothly expanded using interpolation algorithms (such as linear interpolation or spline interpolation) to generate an intermediate instruction sequence, which is then stored in a circular buffer pool. This step effectively eliminates the "window period" problem caused by uneven instruction intervals through high-density instruction caching, providing a continuous and smooth instruction flow foundation for subsequent dynamic segmentation. At the same time, the buffer pool design enables instruction preloading, ensuring that the execution end always has instructions to be processed.

[0065] S3. Adjust the number of interpolations based on the frequency error value of the controller instruction and the controller instruction sequence in the interpolation cache to obtain the instruction segmentation prediction rate matching result;

[0066] By combining real-time frequency error and cache sequence, correlated adjustment parameters and coefficients are set to determine the direction and magnitude of interpolation number adjustment, update the interpolation number and optimize the cache sequence, and predict the pre-adjustment number based on error trends. The final output is an instruction stream that perfectly matches the driver's execution rate. This step, through dynamic adjustment and prediction mechanisms, ensures that the interpolation number accurately adapts to frequency fluctuations, avoiding precision loss under high error conditions and reducing computational redundancy under low error conditions, eliminating execution "idle periods," and achieving an optimal balance between control precision and efficiency.

[0067] In summary, steps S1 to S3 achieve precise coordination between controller commands and driver execution through three closely linked steps: First, the frequency error of the controller commands is detected based on the driver clock source, providing accurate frequency fluctuation data for subsequent processing; next, an appropriate interpolation algorithm is selected based on this error value to generate an interpolated cached command sequence aligned with the driver execution cycle, initially resolving the mismatch between command intervals and execution rhythm; finally, the number of interpolations is dynamically adjusted by combining real-time frequency error and cached sequence characteristics, and the command flow is optimized through a prediction mechanism, ultimately outputting a command sequence that perfectly matches the driver execution rate. The entire process forms a complete closed loop from error detection to command optimization, effectively improving the execution accuracy, continuity, and response efficiency of the control system in frequency fluctuation scenarios.

[0068] As one possible implementation, in the above embodiments, step S1 may specifically include the following steps:

[0069] S1-1. Initialize the dual timers using a driver-based clock source;

[0070] The driver uses its own high-precision clock source to initialize the dual timers (first and second timers). The driver uses these two timers to detect the frequency of controller command issuance. The first timer measures the actual time interval (actual period) between controller commands, while the second timer operates based on a preset theoretical command period (such as a fixed time base). The clock source uses a temperature-compensated crystal oscillator or a temperature-controlled crystal oscillator. The two timers employ a synchronous counter architecture, with their counting pulses directly derived from the driver's clock source after frequency division of the standard clock signal. For example, a 10MHz clock source is divided to 1MHz to ensure a timing accuracy of 1 microsecond.

[0071] During initialization, the system performs synchronous calibration on both timers by sending a reset signal via the internal bus to clear the initial count values ​​of both timers to zero, ensuring strict synchronization at startup with a synchronization error ≤ 1 clock cycle. This step, by sharing the same highly stable clock source and achieving synchronous initialization of both timers, guarantees that the timing reference of the actual control command cycle is completely consistent with that of the theoretical control command cycle. This avoids the error accumulation problem caused by differences in timing references from the source, providing a highly consistent time reference for subsequent frequency error calculations.

[0072] To avoid counting errors caused by timer overflow, this embodiment also includes a dynamic overflow warning mechanism: when the timer's count value reaches 90% of its maximum range, an interrupt signal is triggered. The controller will automatically record the current count value and reset the counter in the interrupt response, ensuring the continuity of the timing process. Furthermore, the dual timers are linked to the driver's clock source calibration module, updating the counting reference synchronously with the automatic calibration of the clock source every hour, eliminating accumulated errors during long-term operation.

[0073] S1-2. Obtain the actual control instruction cycle using the first timer based on the clock source of the driver;

[0074] The first timer is configured in "event-triggered counting mode," which triggers timing by capturing the edge signal (such as rising / falling edge) of the controller's command, records the timestamps of adjacent commands in real time, and calculates the actual control command cycle based on the driver's clock source. Specifically:

[0075] When the driver's signal conditioning circuit detects an edge signal of the control command, it immediately sends a start signal to the first timer, and the timer begins to accumulate counts. When the next edge of the same type is detected, a stop signal is sent, and the counter stops counting. The counting result of the first timer is transmitted to the arithmetic unit in real time via a dedicated data bus. The arithmetic unit divides the count value by the frequency of the driver's clock source (e.g., a 1MHz clock source corresponds to 1 microsecond per counting unit) to obtain the time interval between two adjacent command edges, i.e., the actual control command cycle. In addition, to improve detection accuracy, a multi-cycle averaging method is used to continuously record the measured values ​​of M (M≥5) actual control command cycles. After removing the maximum and minimum values, the arithmetic mean is taken as the final actual control command cycle.

[0076] This step, through edge-triggered real-time counting, can accurately capture the time interval of the command signal. The multi-cycle averaging method effectively suppresses measurement fluctuations caused by instantaneous noise interference, reducing the measurement error of the actual control command cycle. The high-speed transmission of the dedicated data bus ensures that the counting results are transmitted without delay, providing high-fidelity raw data for subsequent error calculation.

[0077] S1-3. Generate the theoretical control command cycle through the second timer;

[0078] The second timer is configured in "fixed period output mode" to generate the theoretical control command cycle. This timer operates independently, unaffected by the actual behavior of the controller, and always provides a stable theoretical cycle reference. Its working principle is as follows: The comparison register value is configured according to the preset theoretical control command frequency (e.g., a nominal 100Hz corresponds to a 10ms cycle), and an automatic reload mode is used to continuously maintain a fixed time interval (e.g., triggering a count every 1ms). Specifically:

[0079] Receives user-defined theoretical control command frequency through the configuration interface. F ref The arithmetic unit converts it into a theoretical period. T ref =1 / F ref And the number of clock pulses corresponding to that period ( T refThe clock source frequency (×) is written to the comparison register of the second timer. The second timer uses an automatic reload mode. When the count reaches the value of the comparison register, an interrupt is automatically triggered and the counter is reset to start the next cycle of counting. At the same time, a synchronization pulse signal is output as a marker of the theoretical instruction cycle. For example, if the theoretical cycle is 1ms and the clock source frequency is 1MHz, the value of the comparison register is set to 1000 (1ms = 1000 microseconds, corresponding to 1000 count units). Every time the second timer counts to 1000, a theoretical cycle completion signal is generated, which can be used for subsequent comparison with the actual instruction cycle. In addition, the system supports dynamic modification of the theoretical control instruction frequency. By writing a new comparison register value, the second timer can switch to the new theoretical cycle within one clock cycle to adapt to the control requirements under different operating conditions.

[0080] The automatic reloading counting mode in this step ensures a stable output of the theoretical control command cycle, and its accuracy is determined solely by the stability of the driver clock source, avoiding theoretical cycle drift caused by software calculation delays. The dynamic switching function enhances the system's flexibility, allowing the theoretical cycle parameters to be updated in real time according to the adjustment of the control strategy, providing a reliable benchmark reference for dynamic comparison of frequency errors.

[0081] S1-4. Compare the actual control command cycle with the theoretical control command cycle to obtain the frequency error value of the controller command;

[0082] This step calculates the frequency error value of the controller command by comparing the actual control command cycle with the theoretical control command cycle, avoiding rounding errors in the frequency conversion process and making the error calculation more accurate.

[0083] In summary, after the driver starts up, steps S1-1 to S1-4 first activate its own clock source, entering the controller command issuance frequency detection stage. Two timers are used to calculate the actual control command cycle and the theoretical control command cycle, respectively, and then a large-range frequency error value is obtained through real-time comparison. Using the driver's own clock source as a reference, the frequency of the commands sent by the controller is detected in real time. The driver's clock source has high stability and accuracy, providing a reliable reference standard for frequency detection. This process, by initializing dual timers with the driver's high-precision clock source, effectively avoids detection errors caused by the instability of external reference sources, ensuring consistency between the actual and theoretical control command cycle timing references, and guaranteeing timing range and continuity. The first timer, combined with a multi-cycle averaging method, accurately obtains the actual cycle, suppressing noise interference. The second timer generates a stable theoretical cycle in automatic reloading mode and supports dynamic switching. Comparing the cycles yields the frequency error, facilitating improvements in the accuracy of control command rate matching, system flexibility, and maintainability, and providing a reliable basis for dynamic adjustment of the control cycle.

[0084] As one possible implementation, in the above embodiments, steps S1-4 may specifically include the following steps:

[0085] S1-4-1. Calculate the actual controller command frequency and the theoretical controller command frequency using the actual control command cycle and the theoretical control command cycle, respectively.

[0086] The actual control command cycle obtained using the first timer T 1. The driver execution cycle is calculated using the reciprocal relationship between frequency and cycle to determine the actual controller command frequency, i.e.:

[0087] Actual controller command frequency f 1 = 1 / T 1;

[0088] At the same time, according to the system's preset theoretical control command cycle T 0 represents the theoretical command cycle of the controller. The theoretical controller command frequency is calculated using the reciprocal relationship:

[0089] Theoretical controller command frequency f 0 = 1 / T 0;

[0090] This step transforms the original time-based periodic differences into frequency parameters that more intuitively reflect the "speed" of command transmission, directly reflecting the clock source offset of the controller and driver, and providing standardized input for subsequent relative frequency error calculations.

[0091] S1-4-2. Calculate the error between the actual controller command frequency and the theoretical controller command frequency, and obtain the relative frequency error between the actual controller command frequency and the theoretical controller command frequency as the relative frequency error of the controller command.

[0092] The relative frequency error is obtained by calculating the difference between the actual controller command frequency and the theoretical controller command frequency, dividing this difference by the theoretical controller command frequency, and multiplying by 100%. This relative frequency error of the controller command is then used as the calculation formula:

[0093] δ f =[( f 1- f 0) / f 0]×100%

[0094] in, δ f This represents the relative frequency error of the controller commands.

[0095] This process eliminates the influence of the absolute value of the frequency on error assessment, and can more accurately reflect the deviation ratio of the actual frequency from the theoretical frequency. For example, the severity of the same absolute error at different theoretical frequencies can be uniformly and objectively assessed through relative error, providing a standardized quantitative indicator for subsequent threshold judgment.

[0096] S1-4-3. Based on the relative frequency error of the controller command and the relative frequency error of the corresponding historical control command, a reference time interval is set;

[0097] By analyzing the relative frequency error of the current controller command and the relative frequency error sequence of the corresponding historical controller commands over a period of time, the fluctuation pattern, trend, and stability of the error are observed, and the reference time interval is dynamically set accordingly. For example, if the historical error fluctuates little in the past 50ms, such as within ±0.5%, and the difference between the current error and the historical error is <1%, then the reference time interval is set to 50ms (reflecting the stable state of the error); if the error fluctuates more than ±5% in the past 20ms, such as jumping from -10% to +8%, then the reference time interval is set to 20ms (capturing high-frequency fluctuations). In this embodiment, the reference time interval is dynamically updated according to the error stability, wherein the interval is increased when stable to reduce the amount of calculation, and decreased when fluctuating to improve the response speed.

[0098] This step extends error analysis from a single moment to trend analysis over time by introducing a reference time interval, avoiding misjudgments caused by instantaneous errors and improving the robustness of error detection. At the same time, by dynamically adjusting the interval size according to the error characteristics, it ensures the accuracy of error monitoring while also taking into account the system's computational efficiency.

[0099] S1-4-4. Obtain the frequency error value of the controller command based on the relative frequency error between the reference time interval and the controller command;

[0100] Based on a pre-set reference time interval, and considering the relative frequency error change of the controller commands within that time interval (e.g., whether the error change is within a preset threshold or whether abnormal fluctuations occur), the frequency error value of the controller commands is determined. If the change in relative frequency error within the reference time interval (e.g., 50ms) is less than or equal to a preset threshold (e.g., ±1%), the average relative error within that time interval is taken as the final frequency error value (e.g., -16.5%). If the change is greater than the threshold (e.g., from -10% to -20% within 50ms), the maximum deviation value within that time interval (e.g., -20%) is taken and marked as "abnormal fluctuation". In this embodiment, the final frequency error value can be described by combining the error magnitude and stability.

[0101] The error value output by this step not only includes information on the magnitude of the deviation, but also incorporates stability characteristics over time, making the error assessment more comprehensive. This provides a more practical basis for decision-making regarding controller calibration, fault diagnosis, and adjustment of system control strategies.

[0102] In summary, steps S1-4-1 to S1-4-4, through quantitative analysis and trend judgment over time, ultimately yield a frequency error value with a wide range that combines accuracy and practicality. This value accurately reflects the degree of deviation of the controller commands and provides an operational basis for system optimization, such as triggering calibration, alarms, or adjusting control strategies based on the error value.

[0103] As one possible implementation, in the above embodiments, step S2 may specifically include the following steps:

[0104] S2-1. Based on the frequency error value of the controller command, set the reference interpolation multiple and the frequency error threshold;

[0105] This step is based on the frequency error value Δ of the controller command. f Determine the appropriate reference interpolation factor N 0 and frequency error threshold Δ f th Reference interpolation factor N 0= floor ( T 0 / T 1) serves as the initial reference for subsequent interpolation calculations, while the frequency error threshold provides a clear boundary for the selection of different interpolation algorithms. floor (∙) represents the floor function. This step lays the foundation for the entire interpolation process. By properly setting these two parameters, the subsequent selection of interpolation algorithms and adjustment of interpolation factors can be more targeted, thereby ensuring the accuracy and stability of the interpolation process. The reference interpolation factor in this embodiment... N =16, frequency error threshold set to 3%≤|Δ f th |<5%.

[0106] S2-2. Determine the interpolation algorithm using the frequency error value of the controller command and the frequency error threshold;

[0107] When determining the interpolation algorithm using the frequency error value from the controller command and the frequency error threshold, the actual frequency error value is compared with the preset threshold to select the optimal interpolation algorithm. This step enables adaptive selection of the interpolation algorithm, allowing for flexible adjustment based on the actual frequency error, effectively improving interpolation accuracy while maintaining processing efficiency.

[0108] S2-3. Based on the frequency error value of the controller command, dynamically adjust the reference interpolation multiple using the actual control command period and the theoretical control command period to determine the initial interpolation multiple;

[0109] The deviation rate between the actual control command cycle and the theoretical control command cycle is calculated, and the initial interpolation factor is further corrected by combining the frequency error value of the controller command. This step ensures that the interpolation factor more closely matches the actual command cycle, avoids interpolation deviations that may be caused by a fixed interpolation factor, and further improves the adaptability and accuracy of the interpolation process.

[0110] S2-4. Based on the initial interpolation factor, the interpolation algorithm is used to perform interpolation caching on the controller instructions to obtain the interpolated cached controller instruction sequence;

[0111] According to the determined interpolation algorithm and interpolation factor, the original controller instructions are interpolated to generate intermediate instructions that are strictly synchronized with the driver's execution cycle, such as one instruction every 1ms. These instructions are then stored in a dual buffer. This step uses a "preloading" mechanism to ensure that there are always instructions input during driver execution, avoiding "idle periods." The resulting intermediate instruction sequence satisfies both smoothness requirements and matches the execution rhythm, providing a continuous and accurate instruction source for subsequent rate matching.

[0112] In summary, steps S2-1 to S2-4, based on the frequency error value of the controller commands, first set a reference interpolation multiple range and a frequency error threshold, then determine the interpolation algorithm based on the error value and the threshold, next determine the initial interpolation multiple by combining the actual and theoretical control command cycles, and finally use the algorithm and multiple to interpolate and buffer the control commands, obtaining an intermediate command sequence synchronized with the driver execution cycle. This process achieves precise adaptation of the interpolation algorithm and multiple, improves interpolation accuracy and adaptability, ensures continuous and accurate intermediate command sequences, and provides a reliable guarantee for subsequent rate matching. As a possible implementation, in the above embodiment, step S2-2 may specifically include the following steps:

[0113] S2-2-1. Determine whether the frequency error value of the controller command is greater than the frequency error threshold. If so, obtain the linear interpolation algorithm as the interpolation algorithm; otherwise, execute S2-2-2.

[0114] S2-2-2. Determine whether the frequency error value of the controller command meets the frequency error threshold. If yes, obtain the quadratic polynomial interpolation algorithm as the interpolation algorithm; otherwise, obtain the spline interpolation algorithm as the interpolation algorithm.

[0115] When the instruction frequency fluctuation is small, i.e. |Δ f|<3%, employing a linear interpolation algorithm with minimal computational load and fastest response, can quickly handle small errors under stable operating conditions due to its low complexity, reducing the computational burden on the driver and ensuring basic control efficiency; when there are moderate fluctuations in the instruction frequency, i.e., 3%≤|Δ f When |<5%, quadratic polynomial interpolation is used. This moderately increases computational complexity to achieve a better fit than linear interpolation. When the error range widens but not drastically, it balances smoothness with computational cost, avoiding trajectory deviation under moderate fluctuations. However, when the instruction frequency fluctuates drastically, i.e., |Δ f |≥5%, using cubic spline interpolation, at the cost of higher computational complexity, through multi-segment continuous smooth polynomial curve fitting, minimizes command abrupt changes caused by drastic fluctuations, effectively suppresses jitter in precision control scenarios, ensures trajectory smoothness and control accuracy under high-frequency fluctuations, and achieves a step-by-step adaptation of "efficiency-smoothness-accuracy" under different fluctuation levels.

[0116] As one possible implementation, in the above embodiments, step S2-3 may specifically include the following steps:

[0117] S2-3-1. Using the actual control command cycle and the theoretical control command cycle, obtain the deviation rate between the actual control command cycle and the theoretical control command cycle as the real-time deviation rate.

[0118] The driver calculates the actual control command cycle in real time using a local clock source. T 1. Theoretical control command cycle T 0% deviation rate δ =| T 1- T 0| / T 0×100% serves as the basic parameter for dynamic adjustment. This step directly quantifies the degree of period deviation, providing a basic reference for subsequent adjustments to the interpolation factor and ensuring that the adjustment direction is consistent with the actual period changes.

[0119] S2-3-2. Determine the reference interpolation multiple adjustment amount based on the real-time deviation rate and the frequency error value of the controller command;

[0120] Based on real-time deviation rate δ and frequency error value Δ f According to the formula Δ N = k × δ × sgn (Δ f ) Calculate the adjustment amount, where, k For adjustment coefficients, k =0.05, sgn (Δ f() represents the direction factor, where +1 indicates a delay requiring acceleration and -1 indicates a lead requiring deceleration. This step achieves a linear / non-linear mapping between the deviation rate and the adjustment amount, such as... δ When the value is greater than 10%, an exponential adjustment is used to avoid under-adjustment or over-adjustment problems caused by a fixed step size.

[0121] S2-3-3. Based on the reference interpolation factor, combined with the frequency error value of the controller command and the adjustment amount of the reference interpolation factor, obtain the initial interpolation factor;

[0122] Based on the reference interpolation factor, an adjustment amount is added, and dynamic corrections are made according to the real-time changes in the frequency error value: when the absolute value of the error increases, an additional compensation coefficient is added to the adjustment amount, such as increasing the adjustment amount by 10% for every 1Hz increase in error; when the error decreases, the adjustment amount is appropriately reduced, such as decreasing the adjustment amount by 5% when the error drops below 0.5Hz, and finally rounded to obtain the initial interpolation factor. N This step achieves fine-grained calibration of the adjustment amount through error feedback, ensuring that the interpolation multiple is highly adapted to the real-time operating conditions. This avoids insufficient or redundant interpolation caused by period deviation, and can dynamically respond to frequency fluctuations, providing a quantitative basis for accurate interpolation.

[0123] In summary, steps S2-3-1 to S2-3-3 achieve accurate determination of the interpolation factor through three collaborative steps: First, the real-time deviation rate between the actual and theoretical control command cycles is calculated to quantify the degree of static deviation of the cycle; then, combined with the frequency error value of the controller command (reflecting dynamic fluctuations), a weighted fusion is performed to obtain the baseline interpolation factor adjustment amount, taking into account both static deviation and dynamic changes; finally, based on the initial interpolation factor, the adjustment amount is added and dynamically corrected in real time according to the frequency error, ultimately determining the initial interpolation factor adapted to the real-time operating conditions. This closed-loop logic avoids the limitations of a fixed factor and ensures that the interpolation factor can accurately match cycle changes and frequency fluctuations through dual-dimensional error considerations, providing key support for the accuracy and adaptability of subsequent interpolation processing.

[0124] In this process, the interpolation multiple is adjusted to a reference setting layer. By incorporating the dual quantization characteristics of frequency error and period deviation into the reference multiple calculation, the initial interpolation density can be adapted to the actual period deviation from the source. For example, when the actual period is extended due to the increase of frequency error, the reference multiple is increased synchronously to increase the number of intermediate instructions, ensuring that the time span of the original instructions is fully covered, avoiding insufficient or redundant initial interpolation due to a fixed reference multiple, and providing basic parameters that match the real-time period characteristics for subsequent interpolation processing.

[0125] As one possible implementation, in the above embodiments, step S2-4 may specifically include the following steps:

[0126] S2-4-1. Based on the controller instructions and the initial interpolation multiple, determine the synchronization timestamp of the intermediate controller instructions;

[0127] The timing of receiving two adjacent controller commands t k and t k+1 As the time boundary, based on the initial interpolation factor N , the time interval t k+1 - t k Divide evenly into N +1 time period, the duration of each time period is strictly equal to the driver execution cycle. T 1, thus determining N Synchronization timestamps of intermediate controller commands t k + T 1. t k +2 T 1, ... t k+1 - T 1. This step ensures that the time base of intermediate instructions is completely synchronized with the execution end by rigidly binding the timestamp with the driver's execution cycle, thus avoiding execution delays or instruction backlogs caused by time misalignment.

[0128] S2-4-2. Based on the synchronization timestamp of the intermediate controller instruction, the interpolation algorithm is used to interpolate the controller instruction to obtain the intermediate controller instruction sequence;

[0129] Based on the synchronization timestamp, a matching interpolation algorithm is invoked, using the original controller command values ​​(such as position and velocity parameters) as a basis for calculation: linear interpolation generates intermediate values ​​through proportional allocation; quadratic polynomial interpolation optimizes the smoothness of moderately fluctuating scenarios through curve fitting; and cubic spline interpolation eliminates abrupt command changes under drastic fluctuations through high-order continuous curves. Finally, a sequence of intermediate command values ​​corresponding one-to-one with the synchronization timestamp is obtained. This step, based on time synchronization, ensures that the variation pattern of the intermediate command values ​​is consistent with the trend of the original commands through algorithm adaptation, maintaining control accuracy while reducing mechanical shock or trajectory distortion at the execution end through smooth transition.

[0130] S2-4-3. Perform double buffering on the intermediate controller instruction sequence to obtain the interpolated buffered controller instruction sequence;

[0131] The generated intermediate instruction sequence is stored in a dual buffer in timestamp order. The dual buffers include a current execution buffer and a preload buffer. The current buffer outputs instructions to the driver in real time according to the timestamp, ensuring no delay in the execution end. The preload buffer pre-calculates and stores the intermediate sequence corresponding to the next set of original instructions. When the number of remaining instructions in the current buffer is lower than a threshold (e.g., N / 3), it automatically switches to the preload buffer and starts the interpolation calculation for the new sequence. This step, through the dual buffer mechanism of "real-time execution + preloading," helps to eliminate the instruction "window" on the driver side, while avoiding the impact of computing power fluctuations in real-time interpolation calculations on execution continuity. The final output buffer sequence can maintain strict synchronization with the execution cycle and dynamically adapt to the frequency fluctuations of controller instructions.

[0132] In summary, steps S2-4-1 to S2-4-3 achieve precise matching between controller instructions and driver execution cycles through three collaborative steps: First, the synchronization timestamp of intermediate instructions is determined based on the interpolation multiple, ensuring a rigid binding between the time base and the driver execution cycle; then, combined with the synchronization timestamp, an appropriate interpolation algorithm is called to generate an intermediate instruction sequence, ensuring smoothness and accuracy of instructions through algorithm optimization while maintaining time synchronization; finally, a dual-buffering mechanism is used to output and preload the intermediate sequence in real time, facilitating the elimination of "idle periods" and balancing computing power fluctuations. This process effectively solves the problems of low execution accuracy and poor continuity caused by non-integer multiples of controller and driver cycles and frequency fluctuations, significantly improving the adaptability and control effect of the distributed control system.

[0133] As one possible implementation, in the above embodiments, step S3 may specifically include the following steps:

[0134] S3-1. Using the frequency error value of the controller instruction and the controller instruction sequence of the interpolation buffer, set the interpolation number adjustment coefficient and the corresponding boundary parameters;

[0135] By combining the frequency error values ​​of the controller commands with the controller command sequence in the interpolation buffer, error intervals and corresponding sequence characteristic parameters are defined, such as interpolation volatility and execution deviation thresholds. Adjustment coefficients and upper and lower limits for the number of interpolations are then matched for different intervals. This step establishes a binding parameter system of "error level - sequence standard - adjustment intensity" by associating frequency error with buffered sequence characteristics. This provides a quantitative basis for subsequent adjustments, avoids blind parameter setting, and ensures that the adjustment logic directly matches the characteristics of actual operating conditions.

[0136] S3-2. Based on the interpolation number adjustment coefficient and the corresponding boundary parameter, combined with the frequency error value of the controller instruction and the controller instruction sequence of the interpolation buffer, determine the direction and magnitude of the interpolation number adjustment;

[0137] This step compares the real-time frequency error, the actual interpolation volatility of the cached sequence, and the execution deviation based on the adjustment parameters and coefficients. It transforms the abstract error and sequence characteristics into specific adjustment directions (increase / decrease) and magnitudes, ensuring that the adjustment decision is both in line with the current working conditions and meets the preset quantitative standards, thus avoiding adjustment inaccuracies caused by a single indicator.

[0138] S3-3. Adjust the number of interpolations based on the direction of the interpolation number adjustment to obtain the instruction segmentation prediction rate matching result;

[0139] Based on the adjustment direction and amplitude, the number of interpolation iterations is updated. The corresponding interpolation algorithm is then invoked to generate an optimized intermediate instruction sequence and update the cache. Combined with error trend prediction, the number of pre-adjustments is calculated, and finally, an instruction stream matching the driver's execution rate is output. This step, through dynamic updating of the interpolation iterations and combining a prediction mechanism, enables the instruction sequence to adapt to frequency fluctuations in real time—that is, to encrypt and improve accuracy when the error is large, and to simplify and reduce the load when the error is small—and to eliminate execution "window periods" in advance. Ultimately, this achieves precise matching between the controller instructions and the driver's execution rate, significantly improving the smoothness and response efficiency of system control.

[0140] In summary, steps S3-1 to S3-3 achieve precise matching between controller commands and driver execution rates through a three-step collaborative process: First, by combining frequency error and buffer sequence characteristics, a correlation system including error range, sequence parameters, and adjustment coefficients is constructed to provide a quantitative standard for adjustment; then, based on this standard, real-time errors and sequence characteristics are transformed into clear interpolation times, adjustment directions, and magnitudes to ensure that decisions align with current operating conditions; finally, the interpolation times are updated based on the adjustment results, generating an optimized intermediate command sequence and pre-adjusting it using a prediction mechanism, ultimately outputting a command flow that matches the driver execution rate. This process forms a closed loop of "standard setting - real-time decision-making - dynamic optimization," effectively improving the smoothness and response efficiency of system control.

[0141] As one possible implementation, in the above embodiments, step S3-1 may specifically include the following steps:

[0142] S3-1-1. Using the frequency error value of the controller command, obtain the historical fluctuation range of the frequency error value;

[0143] The frequency error value Δ based on the controller command fStatistical analysis is performed to extract the historical fluctuation range of the error values. For example, analyzing 2000 sets of error data from the past reveals that the maximum frequency error is 4.5Hz and the minimum is -3.8Hz, thus determining the historical fluctuation range as [-3.8Hz, 4.5Hz]. Simultaneously, the probability distribution of the error in different sub-intervals is recorded, such as 75% within ±2Hz. This step provides a true basis for subsequent interval division, ensuring that subsequent operations are based on the actual frequency fluctuation characteristics of the system.

[0144] S3-1-2. Divide the error interval according to the historical fluctuation range of the frequency error value;

[0145] Based on the obtained historical fluctuation range [-3.8Hz, 4.5Hz], and considering the degree of impact of errors on control performance, the error interval is divided according to the "influence gradient": the interval with a smaller impact on control accuracy is defined as the low error interval, i.e., |Δ f |≤1Hz; the range with moderate influence is defined as the mean error range, i.e., 1Hz<|Δ f |≤3Hz; the range with a significant impact is defined as the high error range, i.e., |Δ f |>3Hz. This division transforms continuous error values ​​into discrete levels, enabling subsequent analysis and adjustments to develop differentiated strategies for different fluctuation intensities.

[0146] S3-1-3. Based on the error interval, perform feature analysis on the controller instruction sequence of the interpolation buffer to obtain sequence feature parameters;

[0147] For each defined error interval, key features of the interpolated buffer instruction sequence within that interval are extracted: the interpolation volatility and execution feedback deviation of adjacent intermediate instructions are calculated, and feature thresholds for each interval are determined in conjunction with the control objective. The interpolation volatility of adjacent intermediate instructions reflects sequence smoothness, while the execution feedback deviation reflects execution accuracy. For example, higher smoothness is required in high-error intervals, so the interpolation volatility threshold is set to ≤5%; for medium-error intervals, it is set to ≤10%; for low-error intervals, it is set to ≤15%; and the execution feedback deviation threshold is uniformly set to ≤±3% to ensure basic accuracy. This step establishes the correlation between error volatility and sequence quality, setting clear standards for sequence performance under different scenarios.

[0148] S3-1-4. Based on the error interval and the sequence feature parameters, obtain the interpolation number adjustment coefficient;

[0149] Based on the correlation between error intervals and sequence feature parameters, the adjustment coefficient for the number of interpolations is: the coefficient corresponding to the high error interval. k h =0.3, using fast encryption instructions to improve smoothness, wherein for every 1Hz increase in error, the interpolation number adjustment range is increased by 30%; the coefficient corresponding to the median error range.k m =0.18, used to balance accuracy and computing power, the coefficient corresponding to the low error range. k l =0.09, fine-tuning when the error is small to avoid over-interpolation.

[0150] S3-1-5. Adjust the coefficients according to the interpolation number to obtain the corresponding boundary parameters;

[0151] Set the boundary parameters for the interpolation degree based on the adjustment coefficient according to the interpolation degree. N min =6、 N max =35, to prevent adjustments from exceeding the system's computing power capacity.

[0152] In summary, steps S3-1-1 to S3-1-5 directly link the dynamic characteristics of frequency error with the quality requirements of the interpolation buffer sequence, constructing a quantitative parameter system of "error level - sequence standard - adjustment intensity". This ensures that subsequent adjustments not only conform to the objective laws of frequency fluctuations but also accurately match the requirements of sequence smoothness and execution accuracy, providing scientific and reusable benchmark rules for dynamic adjustments.

[0153] As one possible implementation, in the above embodiments, step S3-2 may specifically include the following steps:

[0154] S3-2-1. Based on the controller instruction sequence of the interpolation cache, obtain the actual interpolation volatility and execution feedback deviation of the interpolation cache sequence;

[0155] From the controller instruction sequence in the interpolation buffer, extract the numerical difference between adjacent intermediate instructions, and calculate its actual volatility using the following formula: V = (Maximum interpolation between adjacent instructions / Average instruction value in the sequence) × 100%, quantifying sequence smoothness; simultaneously, comparing the theoretical output value of instructions in the sequence with the actual feedback value executed by the driver, calculating the percentage of the absolute value of the deviation relative to the theoretical value, i.e., the execution feedback deviation. D .

[0156] S3-2-2: Determine whether the frequency error value of the controller instruction conforms to the high error range. If yes, obtain the frequency error value of the controller instruction as the high frequency error value and execute S3-2-3. Otherwise, execute S3-2-4.

[0157] This step separates high-error operating conditions from non-high-error operating conditions through initial threshold judgment, ensuring that the adjustment logic is initiated first under extreme frequency fluctuation conditions, thus clarifying the execution path for subsequent operations.

[0158] S3-2-3. Based on the actual interpolation volatility and execution feedback deviation of the interpolation buffer sequence, combined with the high-frequency error value, the sequence characteristic parameters, the interpolation number adjustment coefficient and the corresponding boundary parameters, the adjustment direction and adjustment magnitude of the interpolation number in the high error interval are obtained as the interpolation number adjustment direction and the interpolation number adjustment magnitude, respectively.

[0159] The real-time frequency error value Δ f With this threshold Δ f th In comparison, if |Δ f |>3Hz, which meets the high error range, so the adjustment coefficient for the high error range is applied. k h =0.3) and boundary parameters ( V ≤5%, D ≤±3%), obtained V and D The adjustment direction and magnitude are determined based on four combinations of high error ranges, as detailed below:

[0160] when V >5% and D When the accuracy is greater than 3%, both the smoothness and accuracy of the sequence are not up to standard, and the number of interpolation iterations needs to be increased, such as Δ. f At 4Hz, the adjustment range Δ for the number of interpolations in the high error range N h = k h ×|Δ f |=0.3×4=1.2→Round up to 2, improve sequence quality through encrypted interpolation;

[0161] when V >5% and D When the accuracy is ≤3%, the smoothness is not up to standard but the accuracy is acceptable. The number of interpolations needs to be increased, such as Δ. f At 3.2Hz, the adjustment range Δ of the interpolation number in the high error range N h = k h ×|Δ f =0.3×3.2=0.96→Round up to 1, prioritizing the improvement of sequence smoothness;

[0162] when V ≤5% and D When the accuracy is greater than 3%, the smoothness meets the standard but the accuracy is insufficient, requiring an increase in the number of interpolation iterations, such as Δ. f At 3.8Hz, the adjustment range Δ of the interpolation number in the high error range N h = k h ×|Δf =0.3×3.8=1.14→Round up to the second value to improve tracking accuracy by refining the interpolation;

[0163] when V ≤5% and D When the error rate is ≤3%, both smoothness and accuracy meet the standards. The current interpolation count is maintained, meaning the adjustment range Δ for the interpolation count in the high error range is adjusted. N h =0, to avoid excessive interpolation and increased system load.

[0164] S3-2-4. Determine whether the frequency error value of the controller instruction conforms to the medium error range. If yes, obtain the frequency error value of the controller instruction as the medium frequency error value and execute S3-2-5. Otherwise, obtain the frequency error value of the controller instruction as the low frequency error value and execute S3-2-6.

[0165] This step achieves precise division of the error range through secondary threshold judgment, enabling the orderly triggering of adjustment logic for medium and low error conditions. Combined with the corresponding parameter output, it adapts to adjustment schemes with different fluctuation levels, ensuring that adjustment decisions across the entire error range match the operating conditions.

[0166] S3-2-5. Based on the actual interpolation volatility and execution feedback deviation of the interpolation buffer sequence, combined with the mid-frequency error value, the sequence characteristic parameters, the interpolation number adjustment coefficient and the corresponding boundary parameters, the adjustment direction and adjustment magnitude of the interpolation number in the mid-error interval are obtained as the interpolation number adjustment direction and the interpolation number adjustment magnitude, respectively.

[0167] The real-time frequency error value Δ f With this threshold Δ f th In comparison, if 1Hz < |Δ f |≤3Hz, which meets the standard error range, so the adjustment coefficient for the standard error range is applied. k m =0.18) and boundary parameters ( V ≤10%, D ≤±3%), obtained V and D The adjustment direction and magnitude are determined based on four combinations of the mean error range, as detailed below:

[0168] when V >10% and D When the accuracy is greater than 3%, both smoothness and accuracy are unsatisfactory, and the number of interpolation iterations needs to be increased, such as Δ. f At 2.5Hz, the adjustment range Δ of the interpolation number in the mean error interval N m = km ×|Δ f =0.18×2.5=0.45→Round up to 1, simultaneously optimizing smoothness and accuracy;

[0169] when V >10% and D When the accuracy is ≤3%, the smoothness is not up to standard but the accuracy is acceptable. The number of interpolations needs to be increased, such as Δ. f When the frequency is 1.8Hz, the adjustment range Δ of the interpolation number in the mean error interval is... N m = k m ×|Δ f |=0.18×1.8=0.324→Round up to 1, focusing on improving sequence smoothness;

[0170] when V ≤10% and D When the accuracy is greater than 3%, the smoothness meets the standard but the accuracy is insufficient, requiring an increase in the number of interpolation iterations, such as Δ. f When the frequency is 2.2Hz, the adjustment range Δ of the interpolation number in the mean error interval is... N m = k m ×|Δ f =0.18×2.2=0.396→Rounded up to 1, specifically improving tracking accuracy;

[0171] when V ≤10% and D When the error is ≤3%, both smoothness and accuracy meet the standards. The current interpolation count is maintained, meaning the interpolation count adjustment range Δ within the mean error interval is adjusted. N m =0, balancing control effectiveness and system resource consumption.

[0172] S3-2-6. Based on the actual interpolation volatility and execution feedback deviation of the interpolation buffer sequence, combined with the low-frequency error value, the sequence characteristic parameters, the interpolation number adjustment coefficient and the corresponding boundary parameters, the adjustment direction and adjustment magnitude of the interpolation number in the low error interval are obtained as the interpolation number adjustment direction and the interpolation number adjustment magnitude, respectively.

[0173] The real-time frequency error value Δ f With this threshold Δ f th In comparison, if |Δ f |≤1Hz, which meets the low error range, so the adjustment coefficient for the low error range is applied. k l =0.09) and boundary parameters ( V ≤15%, D ≤±3%), obtainedV and D The adjustment direction and magnitude are determined based on four combinations of low error ranges, as detailed below:

[0174] when V >15% and D When the error rate is greater than 3%, both smoothness and accuracy fail to meet the standards. Reducing the number of interpolations is prohibited; the current number must be maintained, meaning the adjustment range Δ for the number of interpolations in the low error range is [not specified]. N l =0, to avoid performance degradation;

[0175] when V >15% and D When the error is ≤3%, the smoothness is not up to standard but the accuracy is acceptable. Reducing the number of interpolations is prohibited; the current number should be maintained. That is, the adjustment range Δ for the number of interpolations in the low error range is... N l =0, adjust after smoothness improves;

[0176] when V ≤15% and D When the error rate is >3%, the smoothness meets the standard but the accuracy is insufficient. Reducing the number of interpolations is prohibited; the current number should be maintained. This means the adjustment range Δ for the number of interpolations in the low error range is [not specified]. N l =0, prioritizing accuracy;

[0177] when V ≤15% and D When the accuracy is ≤3%, both smoothness and accuracy meet the standards, and the number of interpolation operations can be reduced, such as Δ f At 0.7Hz, the adjustment range Δ of the interpolation number in the low error range N l = k l ×|Δ f =-0.09×0.7=-0.063→Round down to -1, reducing system load.

[0178] In summary, steps S3-2-1 to S3-2-6, through direct comparison of parameters and real-time data, transform abstract errors and sequence characteristics into specific adjustment directions and magnitudes, ensuring that adjustment decisions are both in line with the current working conditions and conform to preset quantitative standards, thus avoiding inaccurate adjustments caused by a single indicator.

[0179] As one possible implementation, in the above embodiments, step S3-3 may specifically include the following steps:

[0180] S3-3-1. Using the initial interpolation multiple, obtain the corresponding initial interpolation count;

[0181] This multiple is directly used as the initial interpolation count, i.e., initial interpolation count = initial interpolation multiple. This step, through the direct mapping between the multiple and the count, provides a baseline starting point for subsequent dynamic adjustments, ensuring that there are executable basic interpolation counts when the system starts, and avoiding instruction breakage due to missing parameters in the initial stage.

[0182] S3-3-2. Based on the initial interpolation count and the direction of the interpolation count adjustment, adjust the interpolation count and calculate the real-time interpolation count;

[0183] Starting with a predetermined initial number of interpolations (e.g., 10), and combining the obtained adjustment direction and magnitude, the real-time interpolation count is calculated: when the adjustment direction is increasing, the real-time count = initial count + adjustment magnitude N = 10 + 2 = 12 counts; when the direction is decreasing, the real-time count = initial count - adjustment magnitude. Simultaneously, it is necessary to verify whether the result is within the preset boundaries. If it exceeds the boundaries, it is forcibly corrected to the nearest boundary value to ensure that the interpolation count is within the system's computing power capacity. This step achieves the transition from the initial benchmark to real-time adaptation, enabling the interpolation count to quickly respond to changes in frequency error.

[0184] S3-3-3: Based on the number of real-time interpolations, the interpolation algorithm is used to perform interpolation caching on the controller instructions to obtain a new interpolated cached controller instruction sequence;

[0185] The updated interpolation count is used to call the matching interpolation algorithm to re-interpolate the original controller instructions. For example, in a high-error scenario, 12 interpolations are used to generate 12 intermediate instructions, whose timestamps are strictly aligned with the driver execution cycle (e.g., 2ms). t k +2ms t k +4ms…), and synchronously update the newly generated sequence to the current execution area and preload area of ​​the interpolation buffer. The current execution area outputs instructions to the driver in real time according to the timestamp, while the preload area stores the interpolation sequence of the next set of original instructions in advance.

[0186] S3-3-4. Based on the frequency error value of the controller instruction and the controller instruction sequence of the interpolation cache, obtain the frequency error trend and cache sequence characteristic changes respectively;

[0187] Frequency error values ​​for the most recent 3-5 control cycles are continuously collected. By calculating the mean error and fluctuation slope, the frequency error trend is determined. Simultaneously, characteristic parameters of the interpolation buffer sequence within the corresponding cycle are extracted, including the interpolation volatility of adjacent intermediate instructions and the mean execution feedback deviation, forming a characteristic change curve of the buffer sequence. This step, through the accumulation of data over multiple cycles, provides historical evidence for subsequent predictions and avoids the influence of the randomness of data from a single cycle on the judgment.

[0188] S3-3-5. Based on the controller instruction sequence of the new interpolation cache, combined with the frequency error trend and the characteristic change of the cache sequence, obtain the instruction stream synchronized with the driver execution cycle as the instruction segmentation prediction rate matching result.

[0189] Using the new interpolation buffer sequence as a basis, and combining the obtained frequency error trend and buffer sequence characteristic changes, the error range of the next cycle is predicted, and the number of interpolations in the preload area is adjusted in advance. When the instruction output of the current execution area reaches 1 / 3 of its remaining value, a buffer switch is triggered, and the sequence of the preload area is seamlessly connected to the current execution area, ensuring that the output instruction stream is always synchronized with the driver execution cycle (e.g., 2ms). The resulting continuous, smooth instruction stream that adapts to the real-time error trend is the instruction segmentation prediction rate matching result, achieving dynamic and accurate matching between controller instructions and driver execution.

[0190] In summary, steps S3-3-1 to S3-3-5 dynamically adapt the intermediate instruction sequence to frequency fluctuations by updating the interpolation count in real time, avoiding insufficient accuracy or wasted computing power caused by a fixed number of interpolations; boundary constraints ensure the stability of system operation; and the predictive optimization and cache switching mechanism completely eliminate the "window period" of instruction output, ultimately achieving precise matching between controller instructions and driver execution rates, significantly improving the continuity and response accuracy of the control process.

[0191] Interpolation count adjustment is a dynamic optimization layer. It dynamically optimizes the interpolation count corresponding to the initial interpolation multiple, combining real-time frequency error fluctuations with the actual execution characteristics of the cached sequence (such as smoothness and bias) for fine-grained adjustments. This compensates for the limitations of the baseline setting in responding to real-time operating conditions, ultimately achieving a precise match between interpolation density and frequency fluctuations and execution requirements. Together, these two elements form a progressive mechanism of "basic anchoring - dynamic calibration," jointly ensuring a balance between the accuracy, continuity, and computational efficiency of the instruction sequence under frequency fluctuation scenarios.

[0192] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0193] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of this application. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0194] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0195] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0196] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the specific implementation of the present invention. Any modifications or equivalent substitutions that do not depart from the spirit and scope of the present invention should be covered within the protection scope of the claims of the present invention.

Claims

1. A method for distributed controller-driver instruction partitioning rate matching, the method comprising: receiving a plurality of instructions from a controller; determining a plurality of driver instructions from the plurality of instructions; and sending the plurality of driver instructions to a plurality of drivers. The method comprises the following steps: S1, using the clock source of the driver to detect the frequency of the instruction, and obtaining the frequency error value of the controller instruction; S2, based on the frequency error value of the controller instruction, using an interpolation algorithm to perform interpolation cache processing on the controller instruction, and obtaining the interpolation cached controller instruction sequence; S3, according to the frequency error value of the controller instruction and the interpolation cached controller instruction sequence, dynamically adjusting the interpolation times, and obtaining the instruction segmentation prediction rate matching result, comprising: Using the frequency error value of the controller instruction and the interpolation cached controller instruction sequence, setting the interpolation times adjustment coefficient and the corresponding boundary parameter; According to the interpolation times adjustment coefficient and the corresponding boundary parameter, combining the frequency error value of the controller instruction and the interpolation cached controller instruction sequence, determining the interpolation times adjustment direction and the interpolation times adjustment amplitude; Based on the interpolation times adjustment direction, adjusting the interpolation times, and obtaining the instruction segmentation prediction rate matching result.

2. The method of claim 1, wherein the method is performed by a distributed controller-driver. S1, using the clock source of the driver to detect the frequency of the instruction, and obtaining the frequency error value of the controller instruction, comprising: Initializing a double timer based on the clock source of the driver, the double timer comprising a first timer and a second timer; According to the clock source of the driver, using the first timer to obtain the actual control instruction period; Generating the theoretical control instruction period through the second timer; Comparing the actual control instruction period with the theoretical control instruction period, and obtaining the frequency error value of the controller instruction.

3. The method of claim 2, wherein the method is performed by a distributed controller-driver. S2, based on the frequency error value of the controller instruction, using an interpolation algorithm to perform interpolation cache processing on the controller instruction, and obtaining the interpolation cached controller instruction sequence, comprising: According to the frequency error value of the controller instruction, setting the reference interpolation multiple and the frequency error threshold value; Using the frequency error value of the controller instruction and the frequency error threshold value to determine the interpolation algorithm; Based on the frequency error value of the controller instruction, dynamically adjusting the reference interpolation multiple using the actual control instruction period and the theoretical control instruction period, and determining the initial interpolation multiple; Based on the initial interpolation multiple, using the interpolation algorithm to perform interpolation cache processing on the controller instruction, and obtaining the interpolation cached controller instruction sequence.

4. The method of claim 3, wherein the method is performed by a distributed controller-driver. According to the frequency error value of the controller instruction, setting the reference interpolation multiple and the frequency error threshold value, comprising: Judging whether the frequency error value of the controller instruction is greater than the frequency error threshold value, if yes, obtaining the linear interpolation algorithm as the interpolation algorithm, otherwise, performing the first operation; Wherein, the first operation is: judging whether the frequency error value of the controller instruction meets the frequency error threshold value, if yes, obtaining the quadratic polynomial interpolation algorithm as the interpolation algorithm, otherwise, obtaining the spline interpolation algorithm as the interpolation algorithm.

5. The method of claim 3, wherein the method is a distributed controller- driver instruction partitioning and predictive rate matching method, and wherein the method further comprises: Based on the frequency error value of the controller instruction, dynamically adjusting the reference interpolation multiple using the actual control instruction period and the theoretical control instruction period, and determining the initial interpolation multiple, comprising: The actual control instruction period and the theoretical control instruction period are used to obtain a deviation rate of the actual control instruction period and the theoretical control instruction period as a real-time deviation rate; A reference interpolation multiple adjustment amount is determined according to the real-time deviation rate and a frequency error value of the controller instruction; An initial interpolation multiple is obtained based on the reference interpolation multiple, the frequency error value of the controller instruction, and the reference interpolation multiple adjustment amount.

6. The method of claim 3, wherein the method is a distributed controller- driver instruction partitioning and predictive rate matching method, and wherein the method further comprises: The interpolation algorithm is used based on the initial interpolation multiple to perform interpolation cache processing on the controller instruction, to obtain an interpolation cached controller instruction sequence, including: An intermediate controller instruction synchronization time stamp is determined based on the controller instruction and the initial interpolation multiple; The interpolation algorithm is used based on the intermediate controller instruction synchronization time stamp to perform interpolation processing on the controller instruction, to obtain an intermediate controller instruction sequence; Double cache processing is performed on the intermediate controller instruction sequence, to obtain the interpolation cached controller instruction sequence.

7. The method of claim 1, wherein the method is performed by a distributed controller-driver. The frequency error value of the controller instruction and the interpolation cached controller instruction sequence are used to set an interpolation times adjustment coefficient and a corresponding boundary parameter, including: The frequency error value of the controller instruction is used to obtain a historical fluctuation range of the frequency error value; Error intervals are divided according to the historical fluctuation range of the frequency error value, including a high error interval, a medium error interval, and a low error interval; Sequence feature parameters are obtained based on the error intervals and the interpolation cached controller instruction sequence; An interpolation times adjustment coefficient is obtained based on the error intervals and the sequence feature parameters; A corresponding boundary parameter is obtained according to the interpolation times adjustment coefficient.

8. The method of claim 7, wherein the method further comprises: The interpolation times adjustment coefficient and the corresponding boundary parameter are used in combination with the frequency error value of the controller instruction and the interpolation cached controller instruction sequence to determine an interpolation times adjustment direction and an interpolation times adjustment amplitude, including: An actual interpolation fluctuation rate of the interpolation cached controller instruction sequence and an execution feedback deviation are obtained according to the interpolation cached controller instruction sequence; It is determined whether the frequency error value of the controller instruction conforms to the high error interval, if yes, the frequency error value of the controller instruction is obtained as a high frequency error value, and a second operation is performed, otherwise, a third operation is performed; The second operation is that the adjustment direction and the adjustment amplitude of the high error interval interpolation times are obtained as the interpolation times adjustment direction and the interpolation times adjustment amplitude, according to the actual interpolation fluctuation rate of the interpolation cached controller instruction sequence and the execution feedback deviation in combination with the high frequency error value, the sequence feature parameters, the interpolation times adjustment coefficient, and the corresponding boundary parameter; The third operation is that it is determined whether the frequency error value of the controller instruction conforms to the medium error interval, if yes, the frequency error value of the controller instruction is obtained as a medium frequency error value, and a fourth operation is performed, otherwise, the frequency error value of the controller instruction is obtained as a low frequency error value, and a fifth operation is performed; The fourth operation is: according to the actual interpolation fluctuation rate of the interpolation cache sequence and the execution feedback deviation, combining the medium frequency error value, the sequence characteristic parameter, the interpolation frequency adjustment coefficient and the corresponding boundary parameter, the adjustment direction and the adjustment amplitude of the interpolation frequency of the medium error interval are obtained as the interpolation frequency adjustment direction and the interpolation frequency adjustment amplitude respectively. The fifth operation is: according to the actual interpolation fluctuation rate of the interpolation cache sequence and the execution feedback deviation, combining the low frequency error value, the sequence characteristic parameter, the interpolation frequency adjustment coefficient and the corresponding boundary parameter, the adjustment direction and the adjustment amplitude of the interpolation frequency of the low error interval are obtained as the interpolation frequency adjustment direction and the interpolation frequency adjustment amplitude respectively.

9. The method of claim 3, wherein the method is a distributed controller- driver instruction partitioning and predictive rate matching method, characterized by, Based on the interpolation frequency adjustment direction, the interpolation frequency is adjusted to obtain the instruction segmentation prediction rate matching result, including: Using the initial interpolation multiple, the corresponding initial interpolation frequency is obtained; Based on the initial interpolation frequency, the interpolation frequency is adjusted based on the interpolation frequency adjustment direction to calculate the real-time interpolation frequency; According to the real-time interpolation frequency, the interpolation cache processing is carried out on the controller instruction by using the interpolation algorithm, and a new interpolation cache controller instruction sequence is obtained; Based on the frequency error value of the controller instruction and the interpolation cache controller instruction sequence, the frequency error trend and the cache sequence characteristic change are obtained respectively; According to the new interpolation cache controller instruction sequence, combining the frequency error trend and the cache sequence characteristic change, the instruction flow synchronized with the driver execution cycle is obtained as the instruction segmentation prediction rate matching result.

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