Counting method, device and storage medium for DDR memory

Abstract

The application relates to the field of semiconductor counting statistics, and discloses a DDR memory counting statistics method, equipment and a storage medium. The method comprises the following steps: when a counting request is received; performing polling allocation combination processing on a counting statistics ID and a counting request value to generate an allocation array; querying a memory statistics value corresponding to the counting statistics ID from a preset DDR memory; accumulating the memory statistics value and the counting request value to generate a new memory statistics value, and writing the new memory statistics value into the DDR memory; when a reading statistics request is received; querying all statistics values corresponding to the reading statistics ID from the DDR memory according to a reading statistics ID to generate a statistics value set, wherein the reading statistics ID is used to poll a Block counter value in a Block counter value set; and calculating a statistics output value corresponding to the reading statistics request based on the statistics value set. In the embodiment of the application, the characteristics of the DDR address are used for addition and subtraction of statistics values, a complex Cache mechanism is not needed, and the logical complexity and timing convergence difficulty are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor counting statistics, and in particular to a DDR memory counting statistics method, device and storage medium. BACKGROUND

[0002] In a network system, since the number of statistics entries is usually more than one million, DDR outside the chip is used for caching. With the modern network bandwidth increasing from 10G to 100G, 200G or even higher, the high performance requirement for using DDR for statistics is increasing day by day, and the requirement for ten million times of statistics per second is needed.

[0003] Using DDR for statistics, simply split into three steps: initiating a DDR read request, waiting for DDR to return read data, and accumulating the request statistics value and DDR returned read data to initiate a DDR write request.

[0004] If the above method is used, since the read request return delay of DDR is relatively large, if the continuous access is the same address of DDR, it is also necessary to ensure that the data is written into DDR before reading, and since the DDR access to the same Bank is limited, the delay is larger, and the performance cannot meet the requirements.

[0005] The prior art improves the performance by adding a Cache between the DDR read rewrite control logic and the DDR, as shown in Figure 1 The steps of statistics are as follows:

[0006] Step 1: When there is a statistics request, the read request module sends a read request to DDR, and at the same time stores the read address into the read address FIFO;

[0007] Step 2: When DDR read data is returned, write the read data into the read return data FIFO;

[0008] Step 3: Compare the read address of the read address FIFO with the address in the Cache; if there is the same address, return the cached statistics data in the Cache to the accumulation statistics module; if there is no same address, return the data of the read return data FIFO to the accumulation statistics module;

[0009] Step 4: The accumulation statistics module writes the statistics data into DDR, and updates to the Cache.

[0010] The above scheme guarantees the consistency of the data statistics of the same address, but needs a complex Cache module, a large address comparison logic, a read data cache FIFO and a read address cache FIFO. The higher the statistical performance requirement is, the larger the DDR read data return delay is, the larger the cache depth and the Cache depth are, and the more the address comparison logic levels are, which increases the chip or FPGA area and power consumption; the large address comparison logic needs a high logic level, which brings challenges to the backend timing; the overall mechanism is relatively complex, and the implementation and maintenance are difficult. Therefore, in order to solve the technical problems of the large read data return delay caused by the logic complexity and timing difficulty to converge of the DDR memory statistics scheme in the prior art, a new technology is needed to solve the current problem. SUMMARY

[0011] The main purpose of the present application is to solve the technical problem of large read data return delay caused by the logic complexity and timing difficulty to converge of the DDR memory statistics scheme in the prior art.

[0012] The first aspect of the present application provides a DDR memory counting statistics method, the DDR memory comprising: an array isolation region, a data array, and a Block, wherein the continuously numbered Blocks are discretely mapped on the array isolation region or discretely mapped on the data array, and the DDR memory counting statistics method comprises the steps of:

[0013] When receiving a counting request, wherein the counting request comprises: a counting statistics ID and a counting request value corresponding to the counting statistics ID;

[0014] Based on the preset Block initial counter value and the preset Block counter value set, the counting statistics ID and the counting request value are processed by polling allocation combination to generate an allocation array, wherein the allocation array comprises: an allocation Block counter value, a counting statistics ID and a counting request value;

[0015] Based on the feature combination of the allocation Block counter value and the counting statistics ID, the memory statistics value corresponding to the counting statistics ID is queried from the preset DDR memory;

[0016] The memory statistics value and the counting request value are accumulated to generate a new memory statistics value, and based on the feature combination of the allocation Block counter value and the counting statistics ID, the new memory statistics value is written into the DDR memory;

[0017] When receiving a read statistics request, wherein the read statistics request comprises: a read statistics ID;

[0018] According to the read statistical ID, polling a Block counter value in the Block counter value set, querying all statistical values corresponding to the read statistical ID from the DDR memory, and generating a statistical value set;

[0019] Based on the statistical value set, calculating a statistical output value corresponding to the read statistical request.

[0020] Optionally, in the first implementation manner of the first aspect, the step of querying a memory statistical value corresponding to the count statistical ID from the preset DDR memory based on the feature combination of the assigned Block counter value and the count statistical ID comprises:

[0021] Converting the feature combination of the assigned Block counter value and the count statistical ID to generate a query DDR request;

[0022] Sending the query DDR request to the preset DDR memory and receiving the memory statistical value corresponding to the count statistical ID fed back by the DDR memory.

[0023] Optionally, in the second implementation manner of the first aspect, the step of performing polling assignment combination processing on the count statistical ID and the count request value based on the preset Block initial counter value and the preset Block counter value set to generate an assignment array comprises:

[0024] Starting from the preset Block initial counter value, polling the preset Block counter value set to perform assignment combination processing on the count statistical ID and the count request value to generate an assignment array;

[0025] Caching the assignment array to a preset FIFO queue.

[0026] Optionally, in the third implementation manner of the first aspect, the step of accumulating the memory statistical value and the count request value to generate a new memory statistical value comprises:

[0027] Reading the count request value in the assignment array from the FIFO queue;

[0028] Accumulating the count request value and the count request value to generate a new memory statistical value.

[0029] Optionally, in the fourth implementation manner of the first aspect, the step of writing the new memory statistical value into the DDR memory based on the feature combination of the assigned Block counter value and the count statistical ID comprises:

[0030] The distribution Block counter value and the feature combination of the count statistic ID are converted to generate a write DDR request;

[0031] The write DDR request is sent to the DDR memory to write the new memory statistic value into the DDR memory at an address corresponding to the feature combination of the distribution Block counter value and the count statistic ID.

[0032] Optionally, in the fifth implementation manner of the first aspect of the present application, the step of polling Block counter values in the Block counter value set according to the read statistic ID to query all statistic values corresponding to the read statistic ID from the DDR memory to generate a statistic value set comprises:

[0033] The Block counter values in the Block counter value set are combined with the read statistic ID to generate a DDR read address set;

[0034] DDR read addresses in the DDR read address set are sent to the DDR memory, and all statistic values corresponding to the read statistic ID returned by the DDR memory are received to obtain a statistic value set.

[0035] Optionally, in the sixth implementation manner of the first aspect of the present application, the step of calculating a statistic output value corresponding to the read statistic request based on the statistic value set comprises:

[0036] All statistic values in the statistic value set are accumulated to generate the statistic output value corresponding to the read statistic request.

[0037] Optionally, in the seventh implementation manner of the first aspect of the present application, after the step of calculating the statistic output value corresponding to the read statistic request based on the statistic value set, the method further comprises:

[0038] The statistic output value is sent to a request address corresponding to the read statistic request.

[0039] The second aspect of the present application provides a DDR memory count statistic device, comprising a memory and at least one processor, the memory stores instructions, and the memory and the at least one processor are interconnected through a circuit; the at least one processor invokes the instructions in the memory to enable the DDR memory count statistic device to perform the DDR memory count statistic method.

[0040] The third aspect of the present application provides a computer readable storage medium, wherein instructions are stored in the computer readable storage medium, and when the instructions are executed on a computer, the computer is caused to perform the counting method of the DDR memory.

[0041] In the embodiment of the present application, by using the attribute of the discrete mapping of the DDR physical internal Block on the array isolation area or the discrete mapping on the data array, each time the statistical record request is written into different Blocks based on the statistical ID, the continuous number of Blocks for reading and writing of the DDR memory is ensured to be processed across the array isolation area and the data array, and the reading and writing performance of the DDR memory is ensured. In addition, the addition and subtraction of the statistical value are implemented by using the characteristics of the DDR address, high-speed statistics are achieved, the complex Cache mechanism is not required, the logical complexity and the timing convergence difficulty are reduced, and the technical problem of large read data return delay caused by the logical complexity and the timing convergence difficulty of the DDR memory statistical scheme in the prior art is solved. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 An embodiment schematic diagram of the prior art DDR read and rewrite control logic in the embodiment of the present application is shown in FIG. 1.

[0043] Figure 2 An embodiment schematic diagram of the counting method of the DDR memory in the embodiment of the present application is shown in FIG. 2.

[0044] Figure 3 An embodiment schematic diagram of the read and rewrite control logic of the counting method of the DDR memory in the embodiment of the present application is shown in FIG. 3.

[0045] Figure 4 An embodiment schematic diagram of the counting device of the DDR memory in the embodiment of the present application is shown in FIG. 4. DETAILED DESCRIPTION

[0046] The embodiment of the present application provides a counting method, a device and a storage medium of a DDR memory.

[0047] The embodiments of the present application will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present application are shown in the drawings, it should be understood that the present application can be implemented in various forms, and should not be interpreted as being limited to the embodiments described herein, but rather, these embodiments are provided to more thoroughly and completely understand the present disclosure. It should be understood that the drawings and embodiments of the present application are only for exemplary purposes, and are not intended to limit the scope of protection of the present application.

[0048] In the description of the embodiments disclosed herein, the term "comprising" and its conjugations are to be understood as open-ended, i.e., "including but not limited to". The term "based on" is to be understood as "based, at least in part, on". The term "one embodiment" or "an embodiment" is to be understood as "at least one embodiment". The terms "a first", "a second", etc. are to be understood as "different or identical" objects. Other explicit or implicit definitions can also be included below.

[0049] For ease of understanding, the specific flow of the embodiments of the present application is described below. Please refer to Figure 2 An embodiment of the counting and statistical method of the DDR memory in the embodiments of the present application includes: an array isolation area, a data array, and a Block, wherein the consecutively numbered Blocks are discretely mapped on the array isolation area or discretely mapped on the data array, and the counting and statistical method of the DDR memory includes the following steps:

[0050] 101, when receiving a counting request, wherein the counting request includes: a counting statistical ID, and a counting request value corresponding to the counting statistical ID;

[0051] In this embodiment, please refer to Figure 3 , Figure 3 The read-write control logic diagram for the counting and statistical method of the DDR memory in the embodiments of the present application. The DDR physically includes different array isolation areas (Groups), and each array isolation area (Group) includes different data arrays (Banks). The access of the same data array (Bank) has timing requirements and cannot be densely accessed, which limits the statistical performance. Therefore, the different array isolation areas (Groups) and different data arrays (Banks) of the DDR are divided into different Blocks, and each Block stores a statistical value; the Block numbers are numbered, and when two consecutive numbers are numbered, the array isolation area (Group) is crossed first, and then the data array (Bank) is crossed. The statistical value is dispersed to different Blocks, and the statistical values stored in each Block are added up to be the actual statistical value.

[0052] The counting request includes: a counting statistical ID, and a counting request value corresponding to the counting statistical ID, and the counting request is received by the Bank discrete module.

[0053] 102, based on the preset Block initial counter value and the preset Block counter value set, the counting statistical ID and the counting request value are polled and allocated and combined to generate an allocation array, wherein the allocation array includes: an allocated Block counter value, a counting statistical ID, and a counting request value;

[0054] In the embodiment, in the Bank discrete module, there is a Block counter triggered by a statistical request, the initial Block counter value is 0, and the Block counter value set has a value range from 0 to Block number-1.

[0055] It is assumed that after the DDR is initialized, all spaces have initial values of 0; the DDR has 2 array isolation groups (Groups), each array isolation group (Group) has 2 data arrays (Banks). There are 4 Blocks, each Block occupies a data array (Bank), and the Block division correspondence table is shown in Table 1.

[0056] Table 1, Block division correspondence table

[0057]

[0058] In the case of the same statistical ID, there are 5 statistical requests, all statistical IDs are 0, and the statistical values are 1, 2, 3, 4 and 5 in turn. The correct statistical value of the statistical ID 0 should be 15.

[0059] The Block counter value of the Bank discrete module is 0; 5 counting requests are received in turn, based on the Block counter value set {0, 1, 2, 3}, the Block counter value is polled to change to 0, 1, 2, 3 and 0 in turn; the values of the allocation Block counter value and the counting statistical ID output to the reading statistical module in turn are {0, 0}, {1, 0}, {2, 0}, {3, 0} and {0, 0}; and the allocation array values of the statistical accumulation module output in turn are {0, 0, 1}, {1, 0, 2}, {2, 0, 3}, {3, 0, 4} and {0, 0, 5}.

[0060] Further, the following specific embodiments are included in the step 102:

[0061] 1021, starting from a preset Block initial counter value, polling a preset Block counter value set, and combining the counting statistical ID and the counting request value to generate an allocation array;

[0062] 1022, caching the allocation array in a preset FIFO queue.

[0063] In the steps 1021-1022, starting from the Block initial counter value 0, polling the Block counter value set {0, 1, 2, 3} from 0, combining the counting statistical ID and the counting request value, and generating the allocation array {allocation Block counter value, counting statistical ID, counting request value}.

[0064] Then, the data of the allocation array {allocation Block counter value, count statistic ID, count request value} is cached in the FIFO queue of the statistic accumulation module for subsequent statistic accumulation.

[0065] 103. Query the memory statistic value corresponding to the count statistic ID from the preset DDR memory based on the feature combination of the allocation Block counter value and the count statistic ID;

[0066] In this embodiment, the memory statistic value corresponding to the count statistic ID is queried from the DDR memory based on the feature combination of {allocation Block counter value, count statistic ID} from the read access address space {array isolation area (Group), data array (Bank), entry (Entry)} of the DDR memory.

[0067] Specifically, the following specific implementation is included in step 103:

[0068] 1031. Convert the feature combination of the allocation Block counter value and the count statistic ID to generate a query DDR request;

[0069] 1032. Send the query DDR request to the preset DDR memory and receive the memory statistic value corresponding to the count statistic ID feedback by the DDR memory.

[0070] In steps 1031-1032, the input {allocation Block counter value (Block_ID), count statistic ID (STAT_ID)} is converted to generate a query DDR request.

[0071] The read access address space {array isolation area (Group), data array (Bank), entry (Entry)} is {0, 0, 0}, {1, 0, 0}, {0, 1, 0}, {1, 1, 0}, {0, 0, 0} in turn, and the memory statistic values found from the corresponding space are 0, 0, 0, 0, and 1 respectively.

[0072] 104. Accumulate the memory statistic value and the count request value to generate a new memory statistic value, and write the new memory statistic value into the DDR memory based on the feature combination of the allocation Block counter value and the count statistic ID;

[0073] In an embodiment, the DDR read request is returned in sequence, and the read returned value is 0, 0, 0, 0, 1 in sequence, and the pre-stored allocation array {allocation Block counter value, count statistics ID, count request value} value is {0, 0, 1}, {1, 0, 2}, {2, 0, 3}, {3, 0, 4}, {0, 0, 5}, 1, 2, 3, 4, 5 are sequentially added to 0, 0, 0, 0, 1 to obtain new memory statistics values 1, 2, 3, 4, 6, and based on {allocation Block counter value, count statistics ID}, the address space and write data {array isolation group, data array bank, entry, new memory statistics value} corresponding value is {0, 0, 0, 1}, {1, 0, 0, 2}, {0, 1, 0, 3}, {1, 1, 0, 4}, {0, 0, 0, 6} in sequence, and the above values are written into the DDR memory.

[0074] Specifically, in step 104, "adding the memory statistics value and the count request value to generate a new memory statistics value" includes the following specific implementation:

[0075] 1041, read the count request value in the allocation array from the FIFO queue;

[0076] 1042, add the count request value and the count request value to generate a new memory statistics value.

[0077] In steps 1041-1042, the FIFO queue is in the statistics accumulation module, and the relevant allocation array has been cached from the FIFO queue. The count request value corresponding to the allocation Block counter value and the count statistics ID is found, the count request value is added to the count request value, and a new memory statistics value is generated. It should be noted that the count request value can be negative, which can realize the subtraction of the memory statistics value.

[0078] Specifically, in step 104, "based on the feature combination of the allocation Block counter value and the count statistics ID, the new memory statistics value is written into the DDR memory" includes the following specific implementation:

[0079] 1043, convert the feature combination of the allocation Block counter value and the count statistics ID and the new memory statistics value to generate a write DDR request;

[0080] 1044, send the write DDR request to the DDR memory, so as to write the new memory statistics value into the DDR memory at the address corresponding to the feature combination of the allocation Block counter value and the count statistics ID.

[0081] In the steps 1043-1044, based on {allocation Block counter value, count statistic ID}, the address space and the write data {array isolation area (Group), data array (Bank), entry (Entry), new memory statistic value} corresponding value of the write access are generated in turn as {0, 0, 0, 1}, {1, 0, 0, 2}, {0, 1, 0, 3}, {1, 1, 0, 4}, {0, 0, 0, 6}, and the write DDR request is generated based on the address space and the write data conversion.

[0082] The write DDR request is sent to the DDR memory, and 1, 2, 3, 4, 6 are written into the address space {array isolation area (Group), data array (Bank), entry (Entry)} in turn as {0, 0, 0}, {1, 0, 0}, {0, 1, 0}, {1, 1, 0}, {0, 0, 0}, that is, the address corresponding to the feature combination of the allocation Block counter value and the count statistic ID is written.

[0083] 105, when receiving a read statistic request, wherein the read statistic request includes: read statistic ID;

[0084] In the embodiment, when receiving the read statistic request, the read statistic request needs to obtain the statistic value of the read statistic ID 0. It should be noted that there is no sequence between the steps 105 and 101, and the two have no sequence relationship, but are related to the type of the received request. When the relevant instruction is received, the corresponding statistic data processing mode is executed.

[0085] 106, according to the read statistic ID, polling the Block counter value in the Block counter value set, querying all statistic values corresponding to the read statistic ID from the DDR memory, and generating a statistic value set;

[0086] In the embodiment, a read statistics request is initiated for each Block, the read statistics ID (Block ID) is 0, and the Block read statistics module reads the statistics value set in the order of {Block counter value (Block_ID), read statistics ID (Block ID)} in the order of {0, 0}, {1, 0}, {2, 0}, {3, 0}, sequentially reads the {array isolation area (Group), data array (Bank), entry (Entry)} space {0, 0, 0}, {1, 0, 0}, {0, 1, 0}, {1, 1, 0}, and finds the corresponding statistics value set {6, 2, 3, 4}. The read request addresses of adjacent two Blocks access the DDR across the array isolation area (Group) and the data array (Bank), which can ensure the performance of the DDR. Since all the Blocks are sequentially polled, the statistics cache value is updated to the new memory statistics value when the DDR reads again in the next polling.

[0087] Specifically, the step 106 includes the following specific implementation:

[0088] 1061. Polling the Block counter value in the Block counter value set and the read statistics ID to generate a DDR read address set by combination and conversion;

[0089] 1062. Sending the DDR read address in the DDR read address set to the DDR memory, receiving all statistics values corresponding to the read statistics ID returned by the DDR memory, and obtaining a statistics value set.

[0090] In the steps 1061-1062, the Block counter value in the Block counter value set {0, 1, 2, 3} and the read statistics ID are combined and converted to generate a DDR read address set {Block counter value (Block_ID), read statistics ID (Block ID)} in the order of {0, 0}, {1, 0}, {2, 0}, {3, 0}.

[0091] Based on the DDR read address set, the {array isolation area (Group), data array (Bank), entry (Entry)} space {0, 0, 0}, {1, 0, 0}, {0, 1, 0}, {1, 1, 0} of the DDR memory is sequentially read and accessed, and the corresponding statistics value set {6, 2, 3, 4} is found.

[0092] 107. Based on the statistics value set, a statistics output value corresponding to the read statistics request is calculated.

[0093] In the embodiment, based on the statistics value set {6, 2, 3, 4}, the statistics output value 15 is obtained.

[0094] In particular, the following specific embodiments are included in step 107:

[0095] 1071, all statistical values are accumulated to generate the statistical output value corresponding to the read statistical request.

[0096] In step 1071, all statistical values returned by the same statistical ID of Block are accumulated to form the total complete statistical value, and all statistical values in the statistical value set {6, 2, 3, 4} are accumulated to generate the statistical output value 15 corresponding to the read statistical request.

[0097] In particular, the following specific embodiments are included after step 107:

[0098] 108, send the statistical output value to the request address corresponding to the read statistical request.

[0099] In step 108, the statistical output value 15 is sent to the request address corresponding to the read statistical request, so as to quickly return the DDR memory record statistical data to the user.

[0100] In another embodiment of steps 101-107, the following embodiments are included for different statistical IDs:

[0101] Five consecutive statistical requests are received, and the statistical IDs are 0, 1, 2, 3, and 0 in sequence, and the statistical values are 1, 2, 3, 4, and 5 in sequence. The correct statistical value of the statistical ID 0 should be 6, the correct statistical value of the statistical ID 1 should be 2, the correct statistical value of the statistical ID 2 should be 3, and the correct statistical value of the statistical ID 3 should be 4.

[0102] The Bank discrete module receives the count request, and the Block counter initial value is 0; five requests are received in sequence, and the Block counter values change to 0, 1, 2, 3, and 0; the values of {assigned Block counter value (Block_ID), count statistical ID (STAT_ID)} output to the read statistical module are {0, 0}, {1, 1}, {2, 2}, {3, 3}, and {0, 0} in sequence; and the values of {assigned Block counter value, count statistical ID, count request value} output to the statistical accumulation module are {0, 1, 1}, {1, 1, 2}, {2, 2, 3}, {3, 3, 4}, and {0, 0, 5} in sequence.

[0103] The read request module sequentially outputs read DDR requests according to inputted {allocation Block counter value (Block_ID), count statistic ID (STAT_ID)} and sequentially outputs the address spaces {array isolation area (Group), data array (Bank), entry (Entry)} as {0, 0, 0}, {1, 0, 1}, {0, 1, 2}, {1, 1, 3}, {0, 0, 0};

[0104] The accumulated statistics module sequentially returns data according to DDR read requests, and sequentially outputs the read return values as 0, 0, 0, 0, 1. The {allocation Block counter value, count statistic ID, count request value} stored in the FIFO are sequentially read out as {0, 1, 1}, {1, 1, 2}, {2, 2, 3}, {3, 3, 4}, {0, 0, 5}, and the count request value is accumulated with the read return value. Based on the characteristic combination of {allocation Block counter value, count statistic ID}, the write DDR access address is converted, and the bit write DDR request is sequentially outputted. The address spaces and write data {array isolation area (Group), data array (Bank), entry (Entry), new memory statistic value} are sequentially outputted as {0, 0, 0, 1}, {1, 0, 1, 2}, {0, 1, 2, 3}, {1, 1, 3, 4}, {0, 0, 0, 6};

[0105] When the read statistic ID required by the outside sequentially outputs the statistic values of 0, 1, 2, and 3, (1) STAT_ID is 0: the statistic block read statistics module sequentially reads and accesses the {array isolation area (Group), data array (Bank), entry (Entry)} spaces as {0, 0, 0}, {1, 0, 0}, {0, 1, 0}, {1, 1, 0} according to the order of {allocation Block counter value (Block_ID), count statistic ID (STAT_ID)} as {0, 0}, {1, 0}, {2, 0}, {3, 0} according to the order of the allocation Block counter value (Block ID);

[0106] (2) read statistic ID is 1: the statistic block read statistics module sequentially reads and accesses the {array isolation area (Group), data array (Bank), entry (Entry)} spaces as {0, 0, 1}, {1, 0, 1}, {0, 1, 1}, {1, 1, 1} according to the order of {allocation Block counter value (Block_ID), count statistic ID (STAT_ID)} as {0, 1}, {1, 1}, {2, 1}, {3, 1} according to the order of the Block ID;

[0107] (3) Read STAT ID = 2: Stat Block read stat module, according to Block ID order, according to {assign Block counter value (Block_ID), count STAT ID (STAT_ID)} in turn {0, 2}, {1, 2}, {2, 2}, {3, 2} order, read access {array isolation area (Group), data array (Bank), entry (Entry)} space in turn: {0, 0, 2}, {1, 0, 2}, {0, 1, 2}, {1, 1, 2};

[0108] (4) Read STAT ID = 3: Stat Block read stat module, according to Block ID order, according to {assign Block counter value (Block_ID), count STAT ID (STAT_ID)} in turn {0, 3}, {1, 3}, {2, 3}, {3, 3} order, read access {array isolation area (Group), data array (Bank), entry (Entry)} space in turn: {0, 0, 3}, {1, 0, 3}, {0, 1, 3}, {1, 1, 3};

[0109] Stat Block Accumulation Module, read DDR data in turn to return respectively for accumulation, generate statistical output value:

[0110] (1) Read STAT ID = 0: 4 Blocks return data in turn 6, 0, 0, 0, accumulate value 6, as the statistical value output. The statistical value is 6, which meets the expected statistical value.

[0111] (2) Read STAT ID = 1: 4 Blocks return data in turn 0, 2, 0, 0, accumulate value 2, as the statistical value output. The statistical value is 2, which meets the expected statistical value.

[0112] (3) Read STAT ID = 2: 4 Blocks return data in turn 0, 0, 3, 0, accumulate value 3, as the statistical value output. The statistical value is 3, which meets the expected statistical value.

[0113] (4) Read STAT ID = 3: 4 Blocks return data in turn 0, 0, 0, 4, accumulate value 4, as the statistical value output. The statistical value is 4, which meets the expected statistical value.

[0114] In the embodiment of the present application, by using the attribute of discrete mapping on the array isolation area or discrete mapping on the data array of the DDR physical internal Block, each statistical record request is written into different Block based on the statistical ID, the continuous number of Blocks for reading and writing of the DDR memory is ensured for the processing across the array isolation area and the data array, and the reading and writing performance of the DDR memory is ensured. In addition, the high-speed statistics is realized by using the characteristics of the DDR address for the addition and subtraction of statistical values, the complex Cache mechanism is not needed, the logical complexity and the timing convergence difficulty are reduced, and the technical problem of large reading data return delay caused by the logical complexity and the timing convergence difficulty of the DDR memory statistics scheme in the prior art is solved.

[0115] Figure 4 Fig. 4 is a structural schematic diagram of a DDR memory counting and statistics device provided by the embodiment of the present application. The DDR memory counting and statistics device 400 can be different due to different configurations or performances, and can include one or more processors (central processing units, CPU) 410 (for example, one or more processors) and a memory 420, one or more storage media 430 (for example, one or more mass storage devices) storing application programs 433 or data 432. The memory 420 and the storage media 430 can be temporary storage or persistent storage. The programs stored in the storage media 430 can include one or more modules (not shown in the figure), and each module can include a series of instruction operations in the DDR memory counting and statistics device 400. Further, the processor 410 can be configured to communicate with the storage media 430 and execute the series of instruction operations in the storage media 430 on the DDR memory counting and statistics device 400.

[0116] The DDR memory counting and statistics device 400 can also include one or more power supplies 440, one or more wired or wireless network interfaces 450, one or more input and output interfaces 460, and / or one or more operating systems 431, such as Windows Server, Mac OS X, Unix, Linux, Free BSD, etc. Those skilled in the art can understand that the DDR memory counting and statistics device 400 can include more or fewer components than those shown in the figure, or some components can be combined, or different components can be arranged. Figure 4 The DDR memory counting and statistics device structure shown does not constitute a limitation on the DDR memory counting and statistics device, and can include more or fewer components than those shown in the figure, or some components can be combined, or different components can be arranged.

[0117] The application further provides a computer readable storage medium, which can be a non-volatile computer readable storage medium, or a volatile computer readable storage medium, and the computer readable storage medium has instructions stored therein, and the instructions, when executed on a computer, cause the computer to perform the steps of the DDR memory counting and statistics method.

[0118] In the context of this disclosure, a machine-readable medium can be a tangible medium that contains or stores a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include but is not limited to an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of the machine-readable storage medium will include one or more lines of electrical connections, portable computer disks, hard disk drives, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or Flash memory), optical fibers, portable compact disc read-only memories (CD-ROMs), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0119] Moreover, while operations can be depicted in a particular, serial order, this should not be understood as requiring or implying that such operations be performed in the particular order shown, or in sequential order, or that all illustrated operations be performed, to achieve desirable results. In certain circumstances, multitasking and parallel processing can be advantageous. Likewise, while certain features can be described in the context of separate embodiments, such separate embodiments can also be implemented in combination with each other. Conversely, various features described in the context of a single embodiment can also be implemented in multiple embodiments separately or in any suitable subcombination. Moreover, although specific implementations have been illustrated and described herein, it will be appreciated that various modifications can be made without departing from the scope of the present disclosure. Accordingly, although specific implementations have been described herein, the scope of the application is not limited to the specific implementations described herein, but only by the claims that follow, the intent being to convey as broadly as possible the present disclosure, and to cover all personal computers relating thereto.

[0120] Although the subject matter has been described in language specific to structural features and / or methodological acts, it is to be understood that the subject defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.

Claims

1. A method for counting statistics of a DDR memory, the method comprising: The DDR memory includes: an array isolation area, a data array, and blocks, wherein the blocks numbered continuously are discretely mapped on the array isolation area or the data array, and a counting method of the DDR memory includes the steps of: When a counting request is received, wherein the counting request includes a counting statistical ID and a counting request value corresponding to the counting statistical ID; Based on a preset block initial counter value and a preset block counter value set, the counting statistical ID and the counting request value are processed by polling allocation combination to generate an allocation array, wherein the allocation array includes an allocation block counter value, a counting statistical ID, and a counting request value; Based on the feature combination of the allocation block counter value and the counting statistical ID, a memory statistical value corresponding to the counting statistical ID is queried from a preset DDR memory; The memory statistical value and the counting request value are accumulated to generate a new memory statistical value, and the new memory statistical value is written into the DDR memory based on the feature combination of the allocation block counter value and the counting statistical ID; When a reading statistical request is received, wherein the reading statistical request includes a reading statistical ID; According to the reading statistical ID, a block counter value in the block counter value set is polled to query all statistical values corresponding to the reading statistical ID from the DDR memory to generate a statistical value set; Based on the statistical value set, a statistical output value corresponding to the reading statistical request is calculated.

2. The method of claim 1, wherein, The step of querying the memory statistical value corresponding to the counting statistical ID from the preset DDR memory based on the feature combination of the allocation block counter value and the counting statistical ID includes: The feature combination of the allocation block counter value and the counting statistical ID is converted to generate a query DDR request; The query DDR request is sent to the preset DDR memory, and the memory statistical value corresponding to the counting statistical ID is received from the DDR memory.

3. The method of claim 1, wherein, The step of processing the counting statistical ID and the counting request value by polling allocation combination based on the preset block initial counter value and the preset block counter value set to generate an allocation array includes: Starting from the preset block initial counter value, the preset block counter value set is polled to allocate and combine the counting statistical ID and the counting request value to generate an allocation array; The allocation array is cached in a preset FIFO queue.

4. The method of claim 3, wherein, The step of accumulating the memory statistical value and the counting request value to generate a new memory statistical value includes: The counting request value in the allocation array is read from the FIFO queue; The counting request value and the counting request value are accumulated to generate a new memory statistical value.

5. The method of claim 1, wherein, The step of writing the new memory statistical value into the DDR memory based on the feature combination of the allocation block counter value and the counting statistical ID includes: Convert the combination of the allocated Block counter value and the feature of the count statistics ID, the new memory statistics value, to generate a write DDR request; Send the write DDR request to the DDR memory, so as to write the new memory statistics value into the DDR memory at the address corresponding to the combination of the allocated Block counter value and the feature of the count statistics ID.

6. The method of claim 1, wherein, The step of polling Block counter values in the Block counter value set according to the read statistics ID, querying all statistics values corresponding to the read statistics ID from the DDR memory, and generating a statistics value set comprises: Polling Block counter values in the Block counter value set and the read statistics ID to generate a DDR read address set; Sending DDR read addresses in the DDR read address set to the DDR memory, receiving all statistics values corresponding to the read statistics ID returned by the DDR memory, and obtaining a statistics value set.

7. The method of claim 1, wherein, The step of calculating a statistics output value corresponding to the read statistics request based on the statistics value set comprises: Accumulating all statistics values in the statistics value set to generate a statistics output value corresponding to the read statistics request.

8. The method of claim 1, wherein, After the step of calculating a statistics output value corresponding to the read statistics request based on the statistics value set, the method further comprises: Sending the statistics output value to a request address corresponding to the read statistics request.

9. A DDR memory counting device, comprising: The count statistics device of the DDR memory comprises a memory and at least one processor, the memory stores instructions, and the memory and the at least one processor are interconnected through a circuit; The at least one processor invokes the instructions in the memory, so that the count statistics device of the DDR memory performs the count statistics method of the DDR memory according to any one of claims 1-8.

10. A computer-readable storage medium having stored thereon a computer program, characterized in that The computer program is executed by a processor to implement the count statistics method of the DDR memory according to any one of claims 1-8.

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