Streaming quantum random number generation method, apparatus and device, medium and program product

Abstract

The invention provides a streaming quantum random number generation method, device and equipment, a medium and a program product. The method comprises the following steps: iteratively executing the following operations in response to a random number generation instruction: stream-receiving an ith original data block in each original random number sequence; on the basis of the clock period of the ith original data block, according to the target pseudo-random sequence and the Hash matrix, pseudo-random character sequence sub-fragments of the clock period are generated in real time; calculating a temporary random subsequence of the clock cycle according to the pseudo-random character sequence subfragment and the ith original data block; and according to the plurality of temporary random subsequences of the plurality of clock periods, respectively generating a target random number sequence and a new target pseudo-random sequence, and processing the next original random number sequence by using the new target pseudo-random sequence.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of quantum information and cryptography, and more particularly, to a streaming quantum random number generation method, device, equipment, medium and program product. BACKGROUND

[0002] A quantum random number generator (QRNG) exploits the fundamental randomness in quantum mechanics to generate high-quality random numbers. However, the raw data directly produced from a quantum random number generator device is usually not uniformly random and can leak some information due to device imperfections. Therefore, a post-processing step called "randomness extraction" is needed to extract high-quality, information-theoretically secure random numbers from the raw data.

[0003] The related art occupies a large amount of logical computing resources and takes a long time to calculate when performing post-processing operations on the raw data directly produced from a quantum random number generator device. SUMMARY

[0004] Therefore, the embodiments of the present application provide a streaming quantum random number generation method, device, equipment, medium and program product.

[0005] One aspect of the embodiments of the present application provides a streaming quantum random number generation method, comprising:

[0006] In response to a random number generation instruction, iteratively performing the following operations:

[0007] Streaming the i-th raw data block in each raw random number sequence;

[0008] Based on the clock period of the i-th raw data block, generating a pseudo-random character sequence sub-segment of the clock period in real time according to a target pseudo-random sequence and a hash matrix;

[0009] According to the pseudo-random character sequence sub-segment and the i-th raw data block, calculating a temporary random sub-sequence of the clock period;

[0010] According to a plurality of temporary random sub-sequences of a plurality of clock periods, respectively generating a target random number sequence and a new target pseudo-random sequence, so as to process the next raw random number sequence using the new target pseudo-random sequence.

[0011] According to the embodiments of the present application, the pseudo-random character sequence sub-segment of the clock period is generated in real time according to the target pseudo-random sequence and the hash matrix, comprising:

[0012] configuring an initial pseudo-random sequence;

[0013] generating the target pseudo-random sequence and the hash matrix according to the initial pseudo-random sequence;

[0014] generating the pseudo-random character sequence sub-segment of the clock cycle according to the target pseudo-random sequence and the hash matrix.

[0015] According to an embodiment of the present application, the hash matrix comprises a plurality of initial sub-matrices divided in column direction, and one of the initial sub-matrices corresponds to one clock cycle.

[0016] According to an embodiment of the present application, generating the pseudo-random character sequence sub-segment of the clock cycle according to the target pseudo-random sequence and the hash matrix comprises:

[0017] determining the target sub-matrix corresponding to the i-th original data block from the plurality of initial sub-matrices of the hash matrix according to the clock cycle of the i-th original data block;

[0018] generating the pseudo-random character sequence sub-segment according to the target pseudo-random sequence and the target sub-matrix, and storing in a register.

[0019] According to an embodiment of the present application, generating the pseudo-random character sequence sub-segment according to the target pseudo-random sequence and the target sub-matrix comprises:

[0020] performing target operation on the target pseudo-random sequence and the target sub-matrix by a matrix-vector calculation sub-unit to obtain the pseudo-random character sequence sub-segment, wherein the target operation comprises at least one of bitwise AND operation and XOR summation operation.

[0021] According to an embodiment of the present application, the target sub-matrix comprises a plurality of rows of matrix elements.

[0022] According to an embodiment of the present application, performing target operation on the target pseudo-random sequence and the target sub-matrix by a matrix-vector calculation sub-unit to obtain the pseudo-random character sequence sub-segment comprises:

[0023] performing logical operation on the row of matrix elements and the target pseudo-random sequence by a calculation sub-unit to generate a bit row segment for each row of the matrix elements;

[0024] performing accumulation processing on a plurality of the bit row segments by an accumulation sub-unit to generate the pseudo-random character sequence sub-segment.

[0025] According to an embodiment of the present application, the logical operation of the matrix elements of different rows is performed in parallel by using a plurality of the above-mentioned computing subunits, wherein the logical operation includes performing a logical operation on the matrix elements of the rows and the target pseudo-random sequence to generate a bit row segment.

[0026] According to an embodiment of the present application, the target random number sequence and the new target pseudo-random sequence are respectively generated according to a plurality of temporary random subsequences of a plurality of clock cycles, including:

[0027] A temporary random number sequence is generated according to a plurality of temporary random subsequences of a plurality of clock cycles stored in a register.

[0028] The temporary random number sequence is segmented according to a preset sequence segmentation rule to obtain the target random number sequence and the new target pseudo-random sequence.

[0029] According to an embodiment of the present application, the length of the temporary random number sequence is equal to the length of the original random number sequence.

[0030] According to an embodiment of the present application, the temporary random number sequence is segmented according to a preset sequence segmentation rule to obtain the target random number sequence and the new target pseudo-random sequence, including:

[0031] The temporary random number sequence is segmented according to the length of the target pseudo-random sequence to obtain the target random number sequence and the new target pseudo-random sequence, wherein the length of the target random number sequence is less than the length of the original random number sequence, and the length of the new target pseudo-random sequence is the same as the length of the target pseudo-random sequence.

[0032] Another aspect of an embodiment of the present application provides a streaming quantum random number generation device, including:

[0033] A receiving module is configured to iteratively receive a streaming receiving the i th original data block in each original random number sequence in response to a random number generation instruction.

[0034] A seed management module is configured to generate a pseudo-random character sequence sub-segment of a clock cycle in real time according to a target pseudo-random sequence and a hash matrix based on the clock cycle of the i th original data block.

[0035] A computing module is configured to calculate a temporary random subsequence of the clock cycle according to the pseudo-random character sequence sub-segment and the i th original data block.

[0036] An accumulation module is configured to generate a target random number sequence and a new target pseudo-random sequence respectively according to a plurality of temporary random subsequences of a plurality of clock cycles, so as to process the next original random number sequence by using the new target pseudo-random sequence.

[0037] Another aspect of the embodiments of the present application provides an electronic device, comprising: one or more processors; a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors implement the method as described above.

[0038] Another aspect of the embodiments of the present application provides a computer readable storage medium, storing computer executable instructions, which when executed, implement the method as described above.

[0039] Another aspect of the embodiments of the present application provides a computer program product, comprising computer executable instructions, which when executed, implement the method as described above.

[0040] According to the embodiments of the present application, each of the original data blocks in the original random number sequence is received in a streaming manner; based on the clock period of the original data block, a pseudo-random character sequence sub-segment is generated in real time according to the target pseudo-random sequence and the hash matrix; a temporary random sub-sequence is calculated according to the pseudo-random character sequence sub-segment and the original data block; and the target random number sequence and the new target pseudo-random sequence are respectively generated according to the plurality of temporary random sub-sequences. Since the plurality of original data blocks in the original random number sequence are received in a streaming manner, the corresponding pseudo-random character sequence sub-segment is determined based on the clock period of each original data block, the temporary random sub-sequence of each original data block is calculated, and the calculation of the target random number sequence is decomposed into a plurality of decomposition algorithms synchronized with the data stream, the problem of occupying a large number of logical computing resources caused by directly using the hash matrix and the original random number sequence for calculation can be avoided, thereby improving the calculation efficiency and reducing the occupancy rate of logical computing resources. BRIEF DESCRIPTION OF DRAWINGS

[0041] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings, in which:

[0042] Figure 1 A flow chart of a streaming quantum random number generation method according to an embodiment of the present application is shown;

[0043] Figure 2 A flow chart of a streaming quantum random number generation method according to another embodiment of the present application is shown;

[0044] Figure 3 A parallel computing schematic diagram according to an embodiment of the present application is shown;

[0045] Figure 4 A generation schematic diagram of a target random number sequence according to an embodiment of the present application is shown;

[0046] Figure 5 a block diagram of a streaming quantum random number generation apparatus according to an embodiment of the present application is shown;

[0047] Figure 6 a block diagram of an electronic device adapted to implement the method described above according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0048] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. It is to be understood, however, that these descriptions are merely exemplary and are intended to provide a thorough and complete disclosure of the embodiments of the present application, as copies can be obtained without undue experimentation by a person having ordinary skill in the art, upon possession of this disclosure. Accordingly, it should be understood that various modifications, adaptations and variations of the embodiments of the present application described herein are possible and within the scope of the present application. Also, it is to be understood that the specific examples given herein are by way of example only and are not meant to limit the present application.

[0049] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the term "including" as well as other forms such as "include", "includes," and / or the like, are intended to mean the inclusion of one or more elements, steps, operations, and / or components, but do not exclude the presence or addition of one or more other elements, steps, operations, and / or components.

[0050] All terms used herein, including technical and scientific terms, have the meanings commonly understood by one of ordinary skill in the art unless otherwise defined herein. It should be further understood that the terms used herein are intended to be interpreted broadly and in a manner consistent with the context of this disclosure, without being limited to a strictly formal base-by-base definition of the term in question.

[0051] In situations where the expression "at least one of A, B, and C, etc." is used, it is generally intended to mean that the expression "at least one of A, B, and C" is equivalent to "A, B, C, A-B, A-C, B-C, and A-B-C, etc." in the sense of an inclusion of any one of the items, any two of the items, any three of the items, any of the items individually, A-B-C, and / or the like. In situations where the expression "at least one of A, B, or C, etc." is used, it is generally intended to mean that the expression "at least one of A, B, and C" is equivalent to "A, B, C, A-B, A-C, B-C, and A-B-C, etc." in the sense of an inclusion of any one of the items, any two of the items, any three of the items, any of the items individually, A-B-C, and / or the like.

[0052] The randomness extraction is essentially the same as the privacy amplification in Quantum Key Distribution (QKD). The technology widely used in the related art is a hash function based on a Toeplitz matrix. However, the scheme based on the Toeplitz matrix in the related art usually adopts a block processing mode, that is, performing a matrix vector multiplication once for a complete original random data block. This mode brings significant technical bottlenecks in practical applications:

[0053] (1) Real-time bottleneck: Toeplitz matrix multiplication is a typical block operation of "accumulation first and processing later". The system must wait and cache a complete original data block (for example, thousands or tens of thousands of bits) of a fixed size before starting the one-time extraction calculation. This mode introduces unavoidable processing delay, resulting in that the output of the final random number is a burst rather than a continuous stream, which seriously restricts the application in the scene of continuous and low-delay random numbers required by high-speed quantum communication and the like.

[0054] (2) Huge calculation and resource overhead: implementing large-scale Toeplitz matrix multiplication on hardware faces severe resource challenges. When a high proportion of random numbers needs to be extracted from a large amount of original data, the dimension of the Toeplitz matrix used will be very large. This directly leads to high calculation logic consumption: to implement a complete matrix vector multiplication, a large number of parallel multipliers (AND gates) and a large accumulator (XOR tree) are needed. In order to complete the calculation within a limited time, a highly parallel hardware structure is often needed, which not only consumes a large amount of logic resources of the hardware, but also causes significant dynamic power consumption, which becomes the main bottleneck of hardware implementation.

[0055] Therefore, embodiments of the present application provide a streaming quantum random number generation method, device, equipment, medium and program product. The method comprises iteratively performing the following operations in response to a random number generation instruction: streaming receiving an i-th original data block in each original random number sequence; based on a clock period of the i-th original data block, generating a pseudo-random character sequence sub-segment of the clock period in real time according to a target pseudo-random sequence and a hash matrix; calculating a temporary random sub-sequence of the clock period according to the pseudo-random character sequence sub-segment and the i-th original data block; and generating a target random number sequence and a new target pseudo-random sequence according to a plurality of temporary random sub-sequences of a plurality of clock periods, so as to process the next original random number sequence by using the new target pseudo-random sequence.

[0056] Figure 1 A flowchart of a streaming quantum random number generation method according to an embodiment of the present application is shown.

[0057] As Figure 1As shown, the streaming quantum random number generation method comprises iteratively performing operation S101 to operation S104 in response to a random number generation instruction.

[0058] In operation S101, a streaming receives an i th original data block in each original random number sequence.

[0059] In operation S102, a pseudo-random character sequence sub-segment of a clock cycle is generated in real time according to a target pseudo-random sequence and a hash matrix based on a clock cycle of the i th original data block.

[0060] In operation S103, a temporary random sub-sequence of a clock cycle is calculated according to the pseudo-random character sequence sub-segment and the i th original data block.

[0061] In operation S104, a target random number sequence and a new target pseudo-random sequence are respectively generated according to a plurality of temporary random sub-sequences of a plurality of clock cycles, so as to process a next original random number sequence by using the new target pseudo-random sequence.

[0062] According to an embodiment of the present application, the random number generation instruction can be input by an operator on a quantum communication device or other electronic device, and the electronic device automatically generates the random number generation instruction in response to the operation. The streaming can refer to receiving one by one.

[0063] According to an embodiment of the present application, the original random number sequence can be generated by a device capable of providing original random numbers such as an entropy source, and the original random number sequence may be a random number sequence with a length of n (for example, n = 1536) and a slight deviation (i.e., conforming to a Gaussian distribution).

[0064] According to an embodiment of the present application, for each original random number sequence, a streaming receives an i th original data block with a length of k-bit in the original random number sequence , a pseudo-random character sequence sub-segment of a clock cycle i is generated in real time according to a target pseudo-random sequence and a hash matrix M based on the clock cycle i of the i th original data block . Wherein, the clock cycle can be determined by a clock signal.

[0065] According to an embodiment of the present application, a temporary random sub-sequence of a clock cycle is calculated according to the pseudo-random character sequence sub-segment and the i th original data block , as shown in formula (1):

[0066] (1)

[0067] Wherein, ​This indicates a splicing operation.

[0068] According to an embodiment of the present invention, in the original random number sequence of After all the original data blocks have completed the calculation of the temporary random subsequence, it can be based on multiple clock cycles. Each temporary random subsequence generates a target random number sequence and a new target pseudo-random sequence. The target random number sequence serves as the final output corresponding to the original random number sequence, while the new target pseudo-random sequence can be further combined with a hash matrix to generate pseudo-random character sequence fragments for processing the next original random number sequence.

[0069] According to an embodiment of the present invention, each original data block in the original random number sequence is received in a streaming manner; based on the clock period of the original data block, pseudo-random character sequence segments are generated in real time according to the target pseudo-random sequence and hash matrix; temporary random subsequences are calculated based on the pseudo-random character sequence segments and the original data block; and a target random number sequence and a new target pseudo-random sequence are generated based on multiple temporary random subsequences. Since this embodiment receives multiple original data blocks in the original random number sequence in a streaming manner, determines the corresponding pseudo-random character sequence segments based on the clock period of each original data block, and calculates the temporary random subsequence for each original data block, by decomposing the calculation of the target random number sequence into multiple decomposition algorithms synchronized with the data stream, the problem of consuming a large amount of logical computing resources caused by directly using the hash matrix and the original random number sequence for calculation can be avoided, thereby improving computational efficiency and reducing the occupancy rate of logical computing resources.

[0070] Figure 2 A flowchart of a streaming quantum random number generation method according to another embodiment of the present invention is shown.

[0071] According to an embodiment of the present invention, see Figure 2 Based on the target pseudo-random sequence and hash matrix, pseudo-random character sequence sub-fragments for the clock cycle are generated in real time, including: configuring the initial pseudo-random sequence; generating the target pseudo-random sequence and hash matrix based on the initial pseudo-random sequence; and generating pseudo-random character sequence sub-fragments for the clock cycle based on the target pseudo-random sequence and hash matrix.

[0072] According to an embodiment of the present invention, the initial pseudo-random sequence can be configured by the staff, for example, the staff provides a sequence of length m+n-1 as the initial pseudo-random sequence.

[0073] According to an embodiment of the present invention, the target pseudo-random sequence can be obtained by splitting the initial pseudo-random sequence. and A hash matrix M of dimension, where the target pseudo-random sequence Length of the initial pseudo-random sequence The length can be any value between 256 and 2048 bits, for example, 1536 bits. The value of n and m can be adjusted according to actual needs, for example, n is 1536 and m is 1024, in bits.

[0074] In a specific embodiment, a fixed-length subsequence can be periodically cut from the initial pseudo-random sequence as the data of a submatrix of the hash matrix, which can reduce the use of computing resources.

[0075] According to an embodiment of the present application, according to the target pseudo-random sequence and the hash matrix M, a pseudo-random character sequence sub-segment corresponding to the clock period of the original data block can be generated.

[0076] According to an embodiment of the present application, the hash matrix M includes initial submatrices divided in the column direction, denoted as , one initial submatrix corresponds to one clock period, and each initial submatrix has a length of .

[0077] According to an embodiment of the present application, referring to Figure 2 , according to the target pseudo-random sequence and the hash matrix, a pseudo-random character sequence sub-segment of a clock period is generated, including: according to the clock period of the i-th original data block, determining a target submatrix corresponding to the i-th original data block from the plurality of initial submatrices of the hash matrix; according to the target pseudo-random sequence and the target submatrix, generating a pseudo-random character sequence sub-segment and storing it in a register.

[0078] According to an embodiment of the present application, according to the clock period i of the i-th original data block from 0 to , a target submatrix of dimensions corresponding to the i-th original data block is determined from the plurality of initial submatrices of the hash matrix . According to the target pseudo-random sequence and the target submatrix , a pseudo-random character sequence sub-segment is generated.

[0079] According to an embodiment of the present application, by decomposing the hash matrix into submatrices corresponding to different clock periods, the huge matrix operation is decomposed into operations within clock periods, the calculation load of each clock period is small and fixed, thereby achieving the best balance between resource occupation and calculation efficiency. ​​

[0080] According to an embodiment of the present application, generating a pseudo-random character sequence sub-segment according to a target pseudo-random sequence and a target sub-matrix comprises: performing a target operation on the target pseudo-random sequence and the target sub-matrix by using a matrix-vector calculation sub-unit to obtain the pseudo-random character sequence sub-segment, wherein the target operation comprises at least one of a bitwise AND operation and an XOR summation operation.

[0081] According to an embodiment of the present application, the function of the matrix-vector calculation sub-unit is to perform a logical operation on hash matrix data and pseudo-random vector data. This module can generate a pseudo-random character sequence sub-segment according to a target pseudo-random sequence and a target sub-matrix , as shown in equation (2):

[0082] (2)

[0083] wherein “ ” in equation (2) represents a bitwise AND operation or an XOR summation operation, and the purpose is to perform a calculation of different dimensions on matrix-form data and vector-form data .

[0084] According to an embodiment of the present application, by using the matrix-vector calculation sub-unit to distribute the calculation of different pseudo-random character sequence sub-segments , the occupancy rate of logical calculation resources can be reduced, and the calculation efficiency can be improved.

[0085] Figure 3 A parallel calculation schematic diagram according to an embodiment of the present application is shown.

[0086] According to an embodiment of the present application, the target sub-matrix comprises multiple rows of matrix elements.

[0087] According to an embodiment of the present application, performing a target operation on the target pseudo-random sequence and the target sub-matrix by using the matrix-vector calculation sub-unit to obtain the pseudo-random character sequence sub-segment comprises: for each row of matrix elements, performing a logical operation on the row of matrix elements and the target pseudo-random sequence by using a calculation sub-unit to generate a bit row segment; and performing accumulation processing on multiple bit row segments by using an accumulation sub-unit to generate the pseudo-random character sequence sub-segment.

[0088] According to an embodiment of the present application, when the matrix-vector calculation sub-unit is calculating, it can calculate according to the rows of the target sub-matrix, and specifically, for each row of matrix elements, one calculation sub-unit can be used to perform a logical operation on the row of matrix elements and the target pseudo-random sequence ​Perform logical operations to generate bit row segments corresponding to each row. Therefore, for n / k target submatrices, they can be processed in parallel by n / k computational subunits (e.g., ...). Figure 3 In the computational subunits (components 1, 2, ..., n / k), after the matrix elements of all rows have been calculated, the pseudo-random character sequence sub-fragments are obtained by accumulating multiple bit row segments through an accumulation subunit. .

[0089] According to embodiments of the present invention, when performing logical calculations using computational subunits, multiple computational subunits can be used to perform calculations on multiple rows of matrix elements simultaneously in parallel, thereby further improving computational efficiency, such as... Figure 3 As shown. Specifically, taking advantage of the parallelization of hardware circuits, multiple parallel computing sub-units are created through a genvar loop. Within one clock cycle, bitwise AND (&) and XOR summation (^) operations are performed on the input target submatrix and target pseudo-random sequence simultaneously, thereby obtaining pseudo-random character sequence sub-fragments.

[0090] Figure 4 A schematic diagram illustrating the generation of a target random number sequence according to an embodiment of the present invention is shown.

[0091] According to an embodiment of the present invention, generating a target random number sequence and a new target pseudo-random sequence based on multiple temporary random subsequences of multiple clock cycles includes: generating a temporary random number sequence based on multiple temporary random subsequences of multiple clock cycles stored in a register; and segmenting the temporary random number sequence based on a preset sequence segmentation rule to obtain the target random number sequence and the new target pseudo-random sequence.

[0092] According to an embodiment of the present invention, see Figure 4 The calculation module can calculate a temporary random subsequence corresponding to each original data block under the action of a counter and a clock signal. The counter stores the results in a register within the accumulator module. Based on the clock signal and the valid signal of the original random number, the counter can count the values. At this time, the accumulator module can store multiple temporary random subsequences corresponding to multiple clock cycles in the register. Accumulate the results to generate a temporary random number sequence. .

[0093] According to an embodiment of the present invention, the accumulation module further performs the accumulation on the temporary random number sequence based on a preset sequence segmentation rule. The target random number sequence can then be obtained. and new target pseudo-random sequence .

[0094] According to an embodiment of the present application, the length of the temporary random number sequence is equal to the length of the original random number sequence.

[0095] According to an embodiment of the present application, the temporary random number sequence is segmented based on a preset sequence segmentation rule to obtain a target random number sequence and a new target pseudo-random sequence, including:

[0096] The temporary random number sequence is segmented based on the length of the target pseudo-random sequence to obtain a target random number sequence and a new target pseudo-random sequence, wherein the length of the target random number sequence is less than the length of the original random number sequence, and the length of the new target pseudo-random sequence is the same as the length of the target pseudo-random sequence.

[0097] According to an embodiment of the present application, when the accumulation module performs the segmentation operation of the temporary random number sequence with a length of n, the first m bits can be used as the final output random number sequence corresponding to the original random number sequence, i.e. the target random number sequence , and a random number validity signal can be sent to indicate that the target random number sequence is valid, and then bits are used as the target pseudo-random sequence required for calculation of the next original random number sequence.

[0098] It should be noted that the initial pseudo-random sequence can be updated in response to an update instruction of a staff (for example Figure 2 , an update frequency is set) so that the initial pseudo-random sequence can be reset in a certain period. For example, after resetting the new initial pseudo-random sequence, the original initial pseudo-random sequence can be used to calculate the current incomplete original random number sequence, and after the original random number sequence is completed, the new initial pseudo-random sequence is used for calculation, and the new target pseudo-random sequence generated in the last original random number sequence processing is no longer used.

[0099] Figure 5 A block diagram of a streaming quantum random number generation device according to an embodiment of the present application is shown.

[0100] As Figure 5 shown, the streaming quantum random number generation device 500 includes a receiving module 510, a seed management module 520, a calculation module 530, and an accumulation module 540.

[0101] The receiving module 510 is configured to iteratively receive a streaming receiving the i-th original data block in each original random number sequence in response to a random number generation instruction.

[0102] The seed management module 520 is configured to generate a pseudo-random character sequence sub-segment of a clock cycle in real time based on the clock cycle of the i-th original data block, according to the target pseudo-random sequence and the hash matrix.

[0103] The computing module 530 is configured to compute a temporary random sub-sequence of clock cycles according to the pseudo-random character sequence sub-segment and the i-th original data block.

[0104] The accumulating module 540 is configured to generate a target random number sequence and a new target pseudo-random sequence respectively according to a plurality of temporary random sub-sequences of a plurality of clock cycles, so as to process the next original random number sequence by using the new target pseudo-random sequence.

[0105] According to the embodiment of the present application, each original data block in the original random number sequence is received in a streaming manner; a pseudo-random character sequence sub-segment is generated in real time according to a target pseudo-random sequence and a hash matrix based on the clock cycle of the original data block; a temporary random sub-sequence is computed according to the pseudo-random character sequence sub-segment and the original data block; and a target random number sequence and a new target pseudo-random sequence are generated respectively according to a plurality of temporary random sub-sequences. Since the plurality of original data blocks in the original random number sequence are received in a streaming manner in the embodiment, the corresponding pseudo-random character sequence sub-segment is determined based on the clock cycle of each original data block, and the temporary random sub-sequence of each original data block is computed, and by decomposing the computation of the target random number sequence into a plurality of decomposition algorithms synchronized with the data stream, the problem of occupying a large number of logical computing resources caused by directly using the hash matrix and the original random number sequence for computation can be avoided, thereby improving the computing efficiency and reducing the occupancy rate of logical computing resources.

[0106] According to the embodiment of the present application, the seed management module 520 includes a configuration sub-module, a first generation sub-module, and a second generation sub-module.

[0107] The configuration sub-module is configured to configure an initial pseudo-random sequence.

[0108] The first generation sub-module is configured to generate a target pseudo-random sequence and a hash matrix according to the initial pseudo-random sequence.

[0109] The second generation sub-module is configured to generate a pseudo-random character sequence sub-segment of clock cycles according to the target pseudo-random sequence and the hash matrix.

[0110] According to the embodiment of the present application, the hash matrix includes a plurality of initial sub-matrices divided in a column direction, and one initial sub-matrix corresponds to one clock cycle.

[0111] According to the embodiment of the present application, the second generation sub-module includes a determination unit and a first generation unit.

[0112] The determination unit is configured to determine a target sub-matrix corresponding to the i-th original data block from a plurality of initial sub-matrices of the hash matrix according to the clock cycle of the i-th original data block.

[0113] The first generating unit is configured to generate a pseudo-random character sequence sub-segment according to the target pseudo-random sequence and the target sub-matrix, and store the pseudo-random character sequence sub-segment in the register.

[0114] According to an embodiment of the present application, the first generating unit comprises a matrix-vector calculation sub-unit.

[0115] The matrix-vector calculation sub-unit is configured to perform a target operation on the target pseudo-random sequence and the target sub-matrix to obtain the pseudo-random character sequence sub-segment, wherein the target operation comprises at least one of a bitwise AND operation and an XOR summation operation.

[0116] According to an embodiment of the present application, the target sub-matrix comprises a plurality of rows of matrix elements.

[0117] According to an embodiment of the present application, the matrix-vector calculation sub-unit comprises a calculation sub-unit and an accumulation sub-unit.

[0118] The calculation sub-unit is configured to, for each row of matrix elements, perform a logical operation on the row of matrix elements and the target pseudo-random sequence by using the calculation sub-unit to generate a bit row segment.

[0119] The accumulation sub-unit is configured to accumulate the plurality of bit row segments to generate the pseudo-random character sequence sub-segment.

[0120] According to an embodiment of the present application, a plurality of calculation sub-units perform the logical operation on different rows of matrix elements in parallel, wherein the logical operation comprises performing a logical operation on the row of matrix elements and the target pseudo-random sequence to generate a bit row segment.

[0121] According to an embodiment of the present application, the accumulation module 540 comprises a second generating unit and an obtaining unit.

[0122] The second generating unit is configured to generate a temporary random number sequence according to a plurality of temporary random sub-sequences stored in the register for a plurality of clock cycles.

[0123] The obtaining unit is configured to perform segmentation processing on the temporary random number sequence based on a preset sequence segmentation rule to obtain a target random number sequence and a new target pseudo-random sequence.

[0124] According to an embodiment of the present application, the length of the temporary random number sequence is equal to the length of the original random number sequence.

[0125] According to an embodiment of the present application, the obtaining unit comprises an obtaining sub-unit.

[0126] The obtaining sub-unit is configured to perform segmentation processing on the temporary random number sequence based on the length of the target pseudo-random sequence to obtain a target random number sequence and a new target pseudo-random sequence, wherein the length of the target random number sequence is less than the length of the original random number sequence, and the length of the new target pseudo-random sequence is the same as the length of the target pseudo-random sequence.

[0127] Any one or more of the modules, units, and subunits, or at least a portion thereof, of the functions of any one or more of them according to embodiments of the present invention can be implemented in one module. Any one or more of the modules, units, and subunits according to embodiments of the present invention can be implemented by dividing them into multiple modules. Any one or more of the modules, units, and subunits according to embodiments of the present invention can be at least partially implemented as hardware circuits, such as Field Programmable Gate Arrays (FPGAs), Programmable Logic Arrays (PLAs), Systems-on-Chip, Systems-on-Substrate, Systems-on-Package, Application-Specific Integrated Circuits (ASICs), or implemented by hardware or firmware through any other reasonable means of integrating or packaging circuits, or implemented by any one of software, hardware, and firmware, or by a suitable combination of any of these. Alternatively, one or more of the modules, units, and subunits according to embodiments of the present invention can be at least partially implemented as computer program modules, which, when run, can perform corresponding functions.

[0128] For example, any plurality of the receiving module 510, seed management module 520, calculation module 530, and accumulation module 540 can be combined into one module / unit / subunit, or any one of these modules / units / subunits can be split into multiple modules / units / subunits. Alternatively, at least part of the functionality of one or more of these modules / units / subunits can be combined with at least part of the functionality of other modules / units / subunits and implemented in one module / unit / subunit. According to embodiments of the present invention, at least one of the receiving module 510, seed management module 520, calculation module 530, and accumulation module 540 can be at least partially implemented as hardware circuitry, such as a field-programmable gate array (FPGA), a programmable logic array (PLA), a system-on-a-chip, a system-on-a-substrate, a system-on-package, an application-specific integrated circuit (ASIC), or any other reasonable means of integrating or packaging the circuitry, or implemented in software, hardware, or firmware, or in any suitable combination of any of these three implementation methods. Alternatively, at least one of the receiving module 510, seed management module 520, calculation module 530, and accumulation module 540 may be implemented at least partially as a computer program module, which can perform corresponding functions when the computer program module is run.

[0129] It should be noted that the stream quantum random number generation device part in the embodiments of the present application corresponds to the stream quantum random number generation method part in the embodiments of the present application, and the description of the stream quantum random number generation device part is specifically referred to the stream quantum random number generation method part, which will not be repeated here.

[0130] Figure 6 A block diagram of an electronic device suitable for implementing the method described above according to an embodiment of the present application is shown. Figure 6 The electronic device shown is merely an example and should not bring any limitation to the function and use range of the embodiments of the present application.

[0131] As shown in Figure 6 The electronic device 600 according to an embodiment of the present application includes a processor 601 which can perform various appropriate actions and processes according to programs stored in a Read-Only Memory (ROM) 602 or loaded from a storage portion 608 into a Random Access Memory (RAM) 603. The processor 601 may, for example, include a general-purpose microprocessor (e.g., a CPU), an instruction set processor, and / or a related chipset, and / or a special-purpose microprocessor (e.g., an Application-Specific Integrated Circuit (ASIC)), etc. The processor 601 can also include an on-board memory for cache use. The processor 601 can include a single processing unit or multiple processing units for performing different actions of the method processes according to embodiments of the present application.

[0132] In the RAM 603, various programs and data required for the operation of the electronic device 600 are stored. The processor 601, the ROM 602, and the RAM 603 are connected to each other through a bus 604. The processor 601 performs various operations of the method processes according to embodiments of the present application by executing programs in the ROM 602 and / or the RAM 603. It should be noted that the programs can also be stored in one or more memories other than the ROM 602 and the RAM 603. The processor 601 can also perform various operations of the method processes according to embodiments of the present application by executing programs stored in the one or more memories.

[0133] According to an embodiment of the present application, the electronic device 600 can further include an input / output (I / O) interface 605 that is also connected to the bus 604. The electronic device 600 can further include one or more of the following components connected to the input / output (I / O) interface 605: an input part 606 including a keyboard, a mouse, etc.; an output part 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage part 608 including a hard disk, etc.; and a communication part 609 including a network interface card such as a LAN card, a modem, etc. The communication part 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the input / output (I / O) interface 605 as necessary. A removable medium 611 such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc. is mounted on the drive 610 as necessary, so that a computer program read therefrom is installed in the storage part 608 as necessary.

[0134] According to an embodiment of the present application, the method flow according to the embodiments of the present application can be implemented as a computer software program. For example, the embodiments of the present application include a computer program product comprising a computer program carried on a computer-readable storage medium, the computer program containing program codes for executing the methods shown in the flowcharts. In such embodiments, the computer program can be downloaded and installed from a network by the communication part 609, and / or installed from the removable medium 611. When the computer program is executed by the processor 601, the above-described functions defined in the system implementing the embodiments of the present application are performed. According to an embodiment of the present application, the system, device, apparatus, module, unit, etc. described above can be implemented by computer program modules.

[0135] The present application also provides a computer-readable storage medium, which can be included in the device / apparatus / system described in the above embodiments; or can exist separately without being assembled into the device / apparatus / system. The above computer-readable storage medium carries one or more programs, which when executed, implement the method according to the embodiments of the present application.

[0136] According to an embodiment of the present application, the computer readable storage medium can be a non-transitory computer readable storage medium. For example, it can include, but is not limited to, a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, a portable compact disc read-only memory (CD-ROM), an optical memory device, a magnetic memory device, or any suitable combination of the foregoing. In the present application, a computer readable storage medium can be any tangible medium that contains or stores a program, which can be used by or in connection with an instruction execution system, apparatus, or device.

[0137] For example, according to an embodiment of the present application, the computer readable storage medium can include one or more memories of ROM 602 and / or RAM 603 and / or other than ROM 602 and RAM 603 described above.

[0138] Embodiments of the present application also include a computer program product, which includes a computer program containing program codes for executing the method provided by the embodiments of the present application, and when the computer program product is run on an electronic device, the program codes are used to make the electronic device implement the method provided by the embodiments of the present application.

[0139] When the computer program is executed by the processor 601, the above-mentioned functions defined in the system / device / apparatus of the embodiments of the present application are executed. According to an embodiment of the present application, the system, apparatus, module, unit, etc. described above can be implemented by computer program modules.

[0140] In one embodiment, the computer program can rely on tangible storage media such as optical storage media, magnetic storage media, etc. In another embodiment, the computer program can also be transmitted, distributed, downloaded and installed in the form of a signal on a network medium through the communication part 609 and / or installed from the detachable medium 611. The program codes contained in the computer program can be transmitted by any appropriate network medium, including but not limited to wireless, wired, etc., or any suitable combination of the foregoing.

[0141] According to embodiments of the present application, program code for implementing the computer programs provided by embodiments of the present application can be written in any combination of one or more programming languages, and can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. The programming language can include, but is not limited to, Java, C++, python, "C" language, or similar programming languages. The program code can execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the remote computing device, or entirely on the remote computing device or server. In the latter scenario, the remote computing device can be connected to the user's computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computing device, such as through the Internet using an Internet Service Provider.

[0142] The computer program instructions can also be loaded onto a computer or other programmable information processing apparatus to cause a series of operations to be performed on the computer or other programmable information processing apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable information processing apparatus implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0143] The above-described embodiments of the present application are merely descriptive and are not intended to be limiting. Although the above embodiments have been described with respect to the various embodiments of the present application, it is apparent that the measures in the various embodiments can be advantageously used in combination. The scope of the present application is defined by the embodiments and their equivalents. Various substitutions and modifications can be made to the embodiments without departing from the scope of the present application.

Claims

1. A method for generating streaming quantum random numbers, characterized in that, The method comprises the following steps: In response to a random number generation instruction, iteratively perform the following operations: Streaming receiving the i-th original data block in each original random number sequence; Based on the clock cycle of the i-th original data block, generating a pseudo-random character sequence sub-segment of the clock cycle in real time according to a target pseudo-random sequence and a hash matrix; According to the pseudo-random character sequence sub-segment and the i-th original data block, calculating a temporary random sub-sequence of the clock cycle; According to a plurality of temporary random sub-sequences of a plurality of clock cycles, respectively generating a target random number sequence and a new target pseudo-random sequence to process the next original random number sequence using the new target pseudo-random sequence.

2. The method of claim 1, wherein, Generating a pseudo-random character sequence sub-segment of the clock cycle in real time according to a target pseudo-random sequence and a hash matrix comprises: Configuring an initial pseudo-random sequence; Generating the target pseudo-random sequence and the hash matrix according to the initial pseudo-random sequence; Generating the pseudo-random character sequence sub-segment of the clock cycle according to the target pseudo-random sequence and the hash matrix.

3. The method of claim 2, wherein, The hash matrix comprises a plurality of initial sub-matrices divided in the column direction, and one of the initial sub-matrices corresponds to one clock cycle; Wherein, generating the pseudo-random character sequence sub-segment of the clock cycle according to the target pseudo-random sequence and the hash matrix comprises: According to the clock cycle of the i-th original data block, determining a target sub-matrix corresponding to the i-th original data block from a plurality of initial sub-matrices of the hash matrix; Generating the pseudo-random character sequence sub-segment according to the target pseudo-random sequence and the target sub-matrix, and storing it in a register.

4. The method of claim 3, wherein, Generating the pseudo-random character sequence sub-segment according to the target pseudo-random sequence and the target sub-matrix comprises: Performing target operation on the target pseudo-random sequence and the target sub-matrix by using a matrix-vector calculation sub-unit to obtain the pseudo-random character sequence sub-segment, wherein the target operation includes at least one of bitwise AND operation and XOR summation operation.

5. The method of claim 4, wherein, The target sub-matrix comprises a plurality of rows of matrix elements; Wherein, performing target operation on the target pseudo-random sequence and the target sub-matrix by using a matrix-vector calculation sub-unit to obtain the pseudo-random character sequence sub-segment comprises: For each row of the matrix elements, performing logical operation on the row of matrix elements and the target pseudo-random sequence by using a calculation sub-unit to generate a bit row segment; Performing accumulation processing on a plurality of the bit row segments by using an accumulation sub-unit to generate the pseudo-random character sequence sub-segment.

6. The method of claim 5, wherein, The logical operations of the matrix elements of different rows are performed in parallel by using a plurality of the calculation sub-units, wherein the logical operations include performing logical operation on the row of matrix elements and the target pseudo-random sequence to generate a bit row segment.

7. The method of claim 1, wherein, According to a plurality of temporary random sub-sequences of a plurality of clock cycles, respectively generating a target random number sequence and a new target pseudo-random sequence comprises: Generating a temporary random number sequence according to a plurality of temporary random sub-sequences of a plurality of clock cycles stored in a register; The temporary random number sequence is segmented based on a preset sequence segmentation rule to obtain the target random number sequence and the new target pseudo-random sequence.

8. The method of claim 7, wherein, The length of the temporary random number sequence is equal to the length of the original random number sequence. The temporary random number sequence is segmented based on a preset sequence segmentation rule to obtain the target random number sequence and the new target pseudo-random sequence, including: The temporary random number sequence is segmented based on the length of the target pseudo-random sequence to obtain the target random number sequence and the new target pseudo-random sequence, wherein the length of the target random number sequence is less than the length of the original random number sequence, and the length of the new target pseudo-random sequence is the same as the length of the target pseudo-random sequence.

9. A streaming quantum random number generator device, comprising: including: The receiving module is configured to iteratively receive a first original data block in each original random number sequence in a streaming manner in response to a random number generation instruction; The seed management module is configured to generate a pseudo-random character sequence sub-segment for a clock cycle in real time according to a target pseudo-random sequence and a hash matrix based on a clock cycle of the first original data block; The computing module is configured to calculate a temporary random sub-sequence for the clock cycle according to the pseudo-random character sequence sub-segment and the first original data block; The accumulation module is configured to generate a target random number sequence and a new target pseudo-random sequence respectively based on a plurality of temporary random sub-sequences for a plurality of clock cycles, so as to process a next original random number sequence by using the new target pseudo-random sequence.

10. An electronic device, comprising: One or more processors; Memory for storing one or more programs, When the one or more programs are executed by the one or more processors, the one or more processors implement the method of any one of claims 1 to 8. The instruction, when executed by a processor, causes the processor to implement the method of any one of claims 1 to 8.

11. A computer-readable storage medium having stored thereon executable instructions that cause a processor-based system to perform steps comprising: The computer program, when executed by a processor, implements the method according to any one of claims 1 to 8.

12. A computer program product comprising a computer program, characterized in that, ​

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