Chip design verification method and verification device

Abstract

The invention discloses a chip design verification method and verification device. The method comprises the steps that use case data content is obtained, and the data content comprises register configuration, RAM configuration, data input, an interrupt processing process and result comparison; storing the data content in a first file according to a preset format; obtaining a preset compiling program, and compiling the first file by utilizing the compiling program; and running the compiled program to obtain a chip verification result. According to the scheme provided by the invention, the verification speed and verification efficiency can be improved.

Description

Technical Field

[0001] This invention relates to the field of chip design technology, and in particular to a chip design verification method and verification device. Background Technology

[0002] In chip design, unit testing (UT) and integration testing (IT) are two key stages in the verification process, used to ensure the correctness and reliability of chip functionality. Unit testing verifies the correctness of the function of each individual component at the module level, such as an adder or a logic unit. Integration testing, on the other hand, aims to combine these modules and test their interactions and overall functionality.

[0003] In chip UT / IT verification, a test case is a concrete instantiation of a verification scenario. By simulating actual functional scenarios or boundary conditions, it drives the design module or system to run and verifies whether its behavior meets expectations. A test case includes register configuration, RAM configuration, data input, interrupt handling, and result comparison. Traditionally, test cases are compiled using hard-coding, meaning that after modifying a test case, it must be compiled before running and debugging. Debugging a test case successfully involves multiple steps, including checking for syntax errors and configuration errors, requiring multiple modifications and compilations, which is inefficient. Eliminating these multiple compilation steps can significantly improve verification speed. Summary of the Invention

[0004] To address the technical problem of low efficiency caused by the need for multiple debugging attempts in the existing chip verification simulation stage, this invention provides a chip design verification method and verification device.

[0005] The technical solution of this invention is implemented as follows:

[0006] This invention provides a chip design verification method, the method comprising:

[0007] Obtain use case data, which includes register configuration, RAM configuration, data input, interrupt handling process, and result comparison.

[0008] The data content is stored in a first file according to a preset format;

[0009] Obtain a preset compiler, compile the first file using the compiler, and run the compiled program to obtain chip verification results.

[0010] In one embodiment, after obtaining the chip verification result, the method further includes:

[0011] determine whether the use case needs to be modified according to the chip verification result;

[0012] In the case of determining that the use case needs to be modified, obtain the modified use case data content;

[0013] update the first file according to the modified use case data content;

[0014] compile the updated first file by using the compiler, run the compiled program, and obtain the chip verification result again.

[0015] In an embodiment, the first file is a TXT format file.

[0016] In an embodiment, the preset compiler is obtained, including:

[0017] program code is written for the first file in the preset format; the program code is used to parse the first file to obtain the data content of each part of the use case, and call the corresponding system component to perform operation according to the data content of each part of the use case;

[0018] generate the compiler according to the program code.

[0019] The embodiment of the application further provides a chip design verification device, the device comprising: a processor and a memory for storing a computer program capable of running on the processor; wherein the processor is used to run the computer program, and perform the following steps:

[0020] obtain use case data content, the data content comprising register configuration, RAM configuration, data input, interrupt processing process and result comparison;

[0021] store the data content into a first file according to a preset format;

[0022] obtain a preset compiler, compile the first file by using the compiler, run the compiled program, and obtain a chip verification result.

[0023] In an embodiment, the processor is used to run the computer program, and further perform the following steps:

[0024] determine whether the use case needs to be modified according to the chip verification result;

[0025] In the case of determining that the use case needs to be modified, obtain the modified use case data content;

[0026] update the first file according to the modified use case data content;

[0027] Compiling the first file after the update by using the compiler; and running the compiled program to obtain the chip verification result again.

[0028] In an embodiment, the first file is a TXT format file.

[0029] In an embodiment, the processor, when running the computer program, further performs the following steps:

[0030] For the first file in the preset format, program code is written; the program code is used to parse the first file to obtain data content of each part of the use case, and to call corresponding system components to perform operations according to the data content of each part of the use case;

[0031] The compiler is generated according to the program code.

[0032] The embodiment has the following beneficial effects:

[0033] The embodiment sets the first file in the preset format according to the data content of the use case. Since the format of the first file is fixed, the program code can be written in advance to generate the compiler, and the first file in the preset format is compiled by using the compiler. In this way, when only the content of the first file needs to be modified, only the first file needs to be modified, and the content belonging to the compiler part does not need to be modified. Therefore, the number of modifications of the compiler part is reduced, the compiling time is saved, and the verification speed and efficiency are improved. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 The figure is a flowchart of a chip design verification method of an embodiment of the present application.

[0035] Figure 2 The figure is an internal structure diagram of a computer device of an embodiment of the present application. DETAILED DESCRIPTION

[0036] The present application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0037] An embodiment of the present application provides a chip design verification method, as shown in the figure, the method comprises the following steps. Figure 1

[0038] Step 101: obtaining use case data content, the data content comprising register configuration, RAM configuration, data input, interrupt processing process and result comparison;

[0039] Step 102: storing the data content into a first file according to a preset format;

[0040] ​Step 103: obtaining a preset compiler, using the compiler to compile the first file, and running the compiled program to obtain a chip verification result.

[0041] In the past chip UT / IT verification simulation stage, the compiler mainly adopts UVM+SystemVerilog, and the construction of the compiler and the use case adopts a hard coding manner. In the traditional manner, a use case includes a large number of register configurations, RAM configurations, data inputs, interrupt processing, result comparisons and the like. After modifying the use case, a binary executable program needs to be compiled first, and then the simulation program can be run. A use case generally needs to be modified, compiled and debugged multiple times to pass the simulation. The compilation time is generally determined by the complexity, size of the simulation hardware code and the running speed of the server, and generally accounts for 30% of the use case debugging time, which is low in efficiency.

[0042] The use case data content (register configuration, RAM configuration, data input, interrupt processing, result comparison and the like) is abstracted into a general format file in the present application, and the compiler is mainly used for parsing the general format file, extracting the above data content, performing related operations, realizing equivalent operations as the traditional use case mode, including register configuration, RAM configuration, data input, interrupt processing, result comparison and the like. The whole compilation process mainly works on providing different txt files based on the above format, and the compiler does not need to be compiled multiple times, which greatly improves the verification efficiency.

[0043] Specifically, the register configuration, RAM configuration, data input, interrupt processing process and result comparison of the use case are abstracted into a specific data format and recorded in a txt file, which is transmitted to the compiler to stimulate the device under test (DUT) and achieve the verification purpose.

[0044] The main work of the compiler is to accurately parse the formatted txt file, find the register configuration data content, find the RAM configuration, find the data input part content, and then issue it to the compiler to call the corresponding UVC component to configure the register, configure the RAM, input the data, and after the DUT generates an interrupt, process the interrupt and compare the results.

[0045] The main work of the verification engineer is to fill in the register configuration, RAM configuration, data input, interrupt processing and result comparison according to the specified format and save it as a txt file.

[0046] When the verification engineer debugs the use case, the compiler needs to be compiled only once (because the txt file format is fixed, and this part of code has been debugged), and each time the use case is debugged, the latest txt file is transmitted, and then the use case is run to check the result. If the register configuration value is wrong, or other errors, or the use case is run again, only the txt file needs to be modified, and then the use case is run again, without the need to recompile the program, and the modification of the txt file can be almost ignored, without the need to recompile the program, thereby achieving the effect of saving this part of time and greatly improving the verification efficiency.

[0047] In order to implement the method of the embodiment of the application, the embodiment of the application further provides a chip design verification device, comprising a processor and a memory for storing a computer program capable of running on the processor; wherein the processor is used to run the computer program, and executes the steps of the method.

[0048] The above device and the above method embodiment provided by the embodiment of the application belong to the same concept, and the specific implementation process is detailed in the method embodiment, which will not be described here.

[0049] In order to implement the method of the embodiment of the application, the embodiment of the application further provides a computer program product, which comprises computer instructions stored in a computer readable storage medium. The processor of the computer device reads the computer instructions from the computer readable storage medium, and the processor executes the computer instructions, so that the computer device executes the steps of the above method.

[0050] Based on the hardware implementation of the above program module, and in order to implement the method of the embodiment of the application, the embodiment of the application further provides an electronic device (computer device). Specifically, in one embodiment, the computer device can be a terminal, and its internal structure diagram can be as shown in Figure 2As shown in the figure. The computer device includes a processor A01, a network interface A02, a display screen A04, an input device A05 and a memory (not shown in the figure) connected through a system bus. Among them, the processor A01 of the computer device is used to provide computing and control capabilities. The memory of the computer device includes an internal memory A03 and a non-volatile storage medium A06. The non-volatile storage medium A06 stores an operating system B01 and a computer program B02. The internal memory A03 provides an environment for the operating system B01 and the computer program B02 in the non-volatile storage medium A06 to run. The network interface A02 of the computer device is used to communicate with the external terminal through the network connection. The computer program is executed by the processor A01 to implement the method of any one of the above embodiments. The display screen A04 of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device A05 of the computer device can be a touch layer overlaid on the display screen, or a key, trackball or touchpad arranged on the shell of the computer device, or an external keyboard, touchpad or mouse, etc.

[0051] Those skilled in the art can understand that, Figure 2 The skilled in the art can understand that,

[0052] The device provided by the embodiment of the present application includes a processor, a memory and a program stored in the memory and executable on the processor. The processor executes the program to implement the method of any one of the above embodiments.

[0053] Those skilled in the art can understand that the embodiments of the present application can be provided as a method, a system or a computer program product. Therefore, the present application can be in the form of a complete hardware embodiment, a complete software embodiment or an embodiment combining software and hardware aspects. Moreover, the present application can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0054] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof.

[0055] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof.

[0056] The computer program instructions can also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer-implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart block or blocks. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof. Figure 1 one or more flowcharts and / or blocks in the flowcharts and / or combination thereof.

[0057] In one typical configuration, the computing device includes one or more processors (CPUs), input / output interfaces, network interfaces, and memory.

[0058] The memory can include non-persistent memory and / or volatile memory, such as a random access memory (RAM) including a cache area for the temporary storage of data. The memory can also include non-volatile memory, such as read only memory (ROM) for storing structural information and / or instruction code to boot an operating system. The memory can also include solid state non-volatile memory (e.g., flash memory), disk drives, disk arrays, RAID storage systems, other data storage systems, or a combination of these. The disk drives can include computer storage media in the form of magnetic or optical disks, or tape. The memory can include any other volatile or non-volatile computer storage media and / or storage devices.

[0059] Computer-readable media includes permanent and non-permanent, moveable and non- moveable media that can be implemented in any method or technology for storage of information, such as computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, without limitation, phase-change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disc read-only memory (CD-ROM), digital versatile disks (DVDs) or other optical storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other non-transmission medium that can be used to store information for access by a computing device. According to the definitions herein, computer-readable media does not include transitory media, such as modulated data signals and carrier waves.

[0060] It can be understood that the memory of the embodiments of the present application can be a volatile memory or a non-volatile memory, and can also include both volatile and non-volatile memories. Among them, the non-volatile memory can be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a ferromagnetic random access memory (FRAM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM). The magnetic surface memory can be a disk memory or a tape memory. The volatile memory can be a random access memory (RAM) used as an external cache. By way of example but not limitation, many forms of RAM can be used, such as static random access memory (SRAM), synchronous static random access memory (SSRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), sync link dynamic random access memory (SLDRAM), and direct rambus random access memory (DRRAM).The memory described in the embodiments of the present application is intended to include, but not be limited to, the memory of these and any other suitable type of memory.

[0061] It should also be noted that the terms "comprising", "comprises", "including", "includes" or any other variation thereof are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. An element proceeded by "comprises a... " does not, without more constraints, exclude the existence of additional identical elements in the process, method, article, or apparatus that comprises the element.

[0062] The above only describes the embodiments of the present application and is not intended to limit the present application. The present application can have various modifications and changes for those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of claims of the present application.

Claims

1. A method of chip design verification, the method comprising: The method comprises: obtaining use case data content, the data content comprising register configuration, RAM configuration, data input, interrupt processing process and result comparison; storing the data content in a first file in a preset format; obtaining a preset compiler, using the compiler to compile the first file, and running the compiled program to obtain a chip verification result.

2. The chip design verification method of claim 1, wherein, After obtaining the chip verification result, the method further comprises: determining whether the use case needs to be modified according to the chip verification result; in the case of determining that the use case needs to be modified, obtaining modified use case data content; updating the first file according to the modified use case data content; using the compiler to compile the updated first file, and running the compiled program to obtain a chip verification result again.

3. The chip design verification method of claim 1, wherein, The first file is a TXT format file.

4. The chip design verification method of claim 1, wherein, Obtaining a preset compiler comprises: writing program code for the first file in a preset format; the program code is used to parse the first file to obtain data content of each part of the use case, and call corresponding system components to perform operations according to the data content of each part of the use case; generating a compiler according to the program code.

5. A chip design verification apparatus, characterized by comprising: The device comprises a processor and a memory for storing a computer program capable of running on the processor; wherein the processor is used to execute the following steps when running the computer program: obtaining use case data content, the data content comprising register configuration, RAM configuration, data input, interrupt processing process and result comparison; storing the data content in a first file in a preset format; obtaining a preset compiler, using the compiler to compile the first file, and running the compiled program to obtain a chip verification result.

6. The chip design verification apparatus according to claim 5, wherein The processor is used to execute the following steps when running the computer program: determining whether the use case needs to be modified according to the chip verification result; in the case of determining that the use case needs to be modified, obtaining modified use case data content; updating the first file according to the modified use case data content; using the compiler to compile the updated first file, and running the compiled program to obtain a chip verification result again.

7. The apparatus of claim 5, wherein the at least one processor is configured to determine the at least one design error by comparing the at least one design error with a design error database. The first file is a TXT format file.

8. The apparatus of claim 5, wherein the at least one processor is configured to determine the at least one design error by comparing the at least one design error with a design error database. The processor is used to execute the following steps when running the computer program: writing program code for the first file in a preset format; the program code is used to parse the first file to obtain data content of each part of the use case, and call corresponding system components to perform operations according to the data content of each part of the use case; generating a compiler according to the program code.

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