Integrated conditional execution flag register, computing control method and processor architecture
By integrating bit-width mode, security policy, and floating-point rounding mode control bits into a single register, the processor achieves fast and flexible computational control in high-performance and high-security tasks, solving the problem of computational latency and security policy mismatch in traditional architectures.
Patent Information
- Application Number
- CN202510936152.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-07
- Publication Date
- 2025-11-07
AI Technical Summary
In the current processor architecture, bit width control, floating-point mode, and security policies are managed in different registers, which leads to problems such as latency in switching computational precision and a mismatch between security policies and computational requirements, making it difficult to meet the needs of high-performance computing and high security.
The bit-width mode control bit, security policy control bit, and floating-point rounding mode control bit are integrated into a single register to achieve joint updates and atomic state switching. The control complexity is reduced by hardware-triggered rules and opcode direct-write mapping.
It improves the efficiency and flexibility of computational control, reduces clock cycle overhead, ensures dynamic matching between security policies and computational accuracy, and enhances processor performance in mixed-precision and high-security tasks.
Smart Images
Figure CN120909648A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the field of computer systems, in particular to an integrated conditional execution flag register, a computing control method and a processor architecture. BACKGROUND
[0002] In the current mainstream processor architecture, the key information for controlling the computing precision, floating point operation behavior and safe access permission is usually stored in multiple different registers. This "field configuration" design mode exposes obvious efficiency bottlenecks and resource waste problems when facing today's complex computing tasks, especially artificial intelligence, high-performance computing and multi-level security applications.
[0003] From the perspective of computing control, bit width control is usually used to determine the effective number of bits of operands in the data path, such as dynamic switching of 32-bit or 16-bit execution paths; floating point mode affects rounding mode, exception handling and precision strategy, commonly used in IEEE754 compatible floating point units; and security domain configuration controls whether the execution context has privileged permissions, security isolation, resource access restrictions and the like through register fields. These three types of parameters are managed in independent registers in traditional processors, resulting in the need to access multiple registers for state saving and restoring whenever the execution context is switched, especially from low-precision AI training mode to high-precision inference mode, or from non-secure domain to secure domain (or vice versa). Since each register access is essentially an independent operation on the bus resources, it needs to go through multiple processing stages such as instruction decoding, permission verification, bus scheduling and write-back confirmation, and cross-domain state switching will result in at least 5 to 7 additional clock cycle overheads.
[0004] In addition, in the traditional architecture, the floating point mode control register is often regarded as a system critical resource, limited to privileged level access, meaning that each mode switch requires privileged mode entry, completion of configuration and return to user mode. This process is not only complex, but also increases the delay, which restricts the real-time performance of mixed precision and the utilization of computing resources. More importantly, the traditional security control system relies on the "privileged level separation" mechanism for physical and logical access isolation, resulting in decoupling of security policy and computing precision, making it difficult to dynamically adjust the security level according to the precision requirements of the task. Since the configuration of the secure domain is independent of the computing configuration, there is a lack of linkage mechanism, and the system cannot automatically adjust the computing path and security policy based on the business intent, which can easily cause the problem of mismatch between the security policy and the current demand.
[0005] Therefore, the design of managing bit width control, floating point mode and security policy in different registers in the current processor architecture cannot meet the needs of high-performance scenarios (such as financial AI and medical edge computing) that require real-time switching of computing precision and simultaneous protection of data security. SUMMARY
[0006] The embodiment of the present application aims to provide an integrated conditional execution flag register, a calculation control method and a processor architecture.
[0007] In a first aspect, the embodiment of the present application provides an integrated conditional execution flag register, comprising:
[0008] a control bit and a reserved bit; the control bit comprises a bit width mode control bit, a security policy control bit and a floating point rounding mode control bit;
[0009] The field of the bit width mode control bit is used to control the bit width of an operation unit.
[0010] The field of the security policy control bit is used to define the memory encryption strength and access permission.
[0011] The field of the floating point rounding mode control bit is used to specify the floating point rounding mode under the IEEE binary floating point number arithmetic standard.
[0012] The field of the reserved bit is used to extend the security policy and / or the floating point rounding mode.
[0013] Optionally, relative to the reserved bit, the control bit is located at the higher bit of the integrated conditional execution flag register, and is distributed in the order of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit from the high bit to the low bit.
[0014] Optionally, the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit are all 4 bits.
[0015] In a second aspect, the embodiment of the present application provides a calculation control method based on the integrated conditional execution flag register in the first aspect, and the calculation control method comprises:
[0016] decoding the received operation code based on an instruction decoder to obtain the decoding result of the operation code;
[0017] determining whether the control bit parameter of the bit width mode control bit is defined in the operation code based on the decoding result of the operation code;
[0018] if the control parameter of the bit width mode control bit is different from the current field value of the bit width mode control bit of the integrated conditional execution flag register, then using a bypass write circuit to jointly update the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register based on the control parameter of the bit width mode control bit defined in the operation code;
[0019] Based on the updated field values of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit in the integrated conditional execution flag register, the execution units corresponding to each control bit are configured to perform calculation based on the configured execution units.
[0020] Optionally, the joint updating of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register based on the control parameter of the bit width mode control bit defined in the operation code comprises:
[0021] The joint updating of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register based on the control parameter of the bit width mode control bit defined in the operation code, or based on the control parameters of the bit width mode control bit and the floating point rounding mode control bit defined in the operation code;
[0022] When the control parameter of the bit width mode control bit is 4bit, the field value of the bit width mode control bit of the integrated conditional execution flag register is updated to 4bit, and the field values of the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register are forcibly updated to forced encryption and RTZ rounding, respectively.
[0023] When the control parameter of the bit width mode control bit is 32bit, the field value of the bit width mode control bit of the integrated conditional execution flag register is updated to 32bit, the field value of the security policy control bit of the integrated conditional execution flag register is updated based on the current execution domain, and the field value of the floating point rounding mode control bit of the integrated conditional execution flag register is updated based on the control parameter of the floating point rounding mode control bit defined in the operation code.
[0024] Optionally, the method further comprises:
[0025] When the operation code involves privileged operations, register access or cross-memory domain access, sequentially perform operation code permission check, register security policy check and memory access domain check, and perform the operation corresponding to the operation code after the operation code permission check, the register security policy check and the memory access domain check all pass.
[0026] Optionally, the sequentially performing operation code permission check, register security policy check and memory access domain check comprises:
[0027] Extract the high three-bit field value of the operation code from the decoding result of the operation code, and compare the high three-bit field value with the permission mapping table in the processor microcode;
[0028] If the high three-bit field value is greater than or equal to the minimum privilege allowed by the current security domain specified in the privilege mapping table, indicating that the opcode privilege check passes, it is determined whether the current operation corresponding to the opcode hits the operation corresponding to the disable operation bit in the security policy control bit of the integrated conditional execution flag register;
[0029] If the current operation corresponding to the opcode does not hit the operation corresponding to the disable operation bit in the security policy control bit of the integrated conditional execution flag register, indicating that the register security policy check passes, a memory access domain check is performed based on the physical address of the requested memory corresponding to the opcode, the current process security domain ID, the operation type and the encryption state identifier.
[0030] In a third aspect, an embodiment of the present application provides a processor architecture, characterized in that the processor comprises the integrated conditional execution flag register of the first aspect.
[0031] In a fourth aspect, an embodiment of the present application provides a chip, characterized in that the chip comprises the integrated conditional execution flag register of the first aspect.
[0032] In a fifth aspect, an embodiment of the present application provides a storage medium having computer program instructions stored thereon, characterized in that the computer program instructions, when executed, implement the computing control method of the second aspect.
[0033] The integrated conditional execution flag register, the computing control method and the processor architecture provided by the embodiments of the present application integrate the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit into a single register, support integrated joint update of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit when the bit width mode changes, eliminate access delay, and realize atomic update of the state by using a hardware automatic triggering rule, and reduce control complexity by using opcode direct write mapping, so as to realize more efficient and flexible computing control strategies under the premise of ensuring security, eliminate the risk of software configuration delay and state inconsistency in the traditional scheme by integrating the state at the hardware level, and enable the processor to complete execution state management with fewer clock cycles, smaller switching cost and higher strategy consistency when facing mixed precision, high security, floating point intensive and other tasks. BRIEF DESCRIPTION OF DRAWINGS
[0034] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required to be used in the embodiments of the present application will be briefly introduced below.
[0035] Figure 1 is a structural schematic diagram of the integrated conditional execution flag register provided by the embodiments of the present application.
[0036] Figure 2 is a flowchart of a computing control method based on the integrated conditional execution flag register provided by an embodiment of the present application;
[0037] Figure 3 is a flowchart of a three-level security verification mechanism provided by an embodiment of the present application;
[0038] Figure 4 is a matching diagram of memory access domain verification provided by an embodiment of the present application. DETAILED DESCRIPTION
[0039] The technical solutions in the embodiments of the present application will be described below with reference to the drawings in the embodiments of the present application.
[0040] Similar reference numerals and letters refer to like items in the following drawings, and thus, once an item is defined in one drawing, it need not be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms “first”, “second”, and the like are only used for differentiation in description, and cannot be understood as indicating or implying relative importance.
[0041] In the current mainstream processor architecture, the key information for controlling the computing precision, floating point operation behavior and security access permission is usually stored in multiple different registers. However, the three types of parameters are managed in independent registers in the traditional processor, resulting in the need to access multiple registers respectively, perform state saving and restoration, and cause additional clock cycle overhead every time the execution context is switched, especially from low-precision AI training mode to high-precision inference mode, or from non-secure domain to secure domain (or vice versa). In addition, the floating point mode control register is often regarded as a system critical resource, which is limited to privileged level access, meaning that the privileged mode needs to be entered every time the mode is switched, the configuration is completed, and then returned to the user state, which restricts the real-time performance and computing resource utilization of mixed precision. More importantly, the traditional security control system relies on the “privilege separation” mechanism for physical and logical access isolation, resulting in decoupling of the security policy and the computing precision, making it difficult to dynamically adjust the security level according to the precision requirements of the task, and easily causing the problem of mismatch between the security policy and the current requirements.
[0042] To this end, an embodiment of the present application provides an integrated conditional execution flag register, which integrates the key fields for controlling the computing bit width, floating point behavior and security policy in a single register, supports atomic update, fast access and automatic decoding, so as to realize more efficient and flexible computing control strategy under the premise of ensuring security.
[0043] Figure 1is a structural diagram of an integrated conditional execution flag register provided by an embodiment of the present application, as shown in Figure 1 The integrated conditional execution flag register includes control bits and reserved bits; the control bits include bit width mode control bits, security policy control bits, and floating point rounding mode control bits;
[0044] The bit width mode control bits are used to control the bit width of an operation unit.
[0045] The security policy control bits are used to define the memory encryption strength and access permission.
[0046] The floating point rounding mode control bits are used to specify the floating point rounding mode under the IEEE binary floating point arithmetic standard.
[0047] The reserved bits are used to extend the security policy and / or the floating point rounding mode.
[0048] Here, the integrated conditional execution flag register aims to uniformly manage three types of key control information closely related to the computing execution behavior, namely, operation bit width control, security policy control, and floating point rounding mode control, to simplify the control path, reduce the state switching overhead, and improve the response capability and flexibility of the processor in a multi-task, high-security, and high-performance computing environment.
[0049] The integrated conditional execution flag register has a general structure composed of two parts: control bit fields and reserved bit fields. The control bit fields are used to carry the state information actually used to control the processor operation, and the reserved bit fields provide space for future functional expansion.
[0050] The control bits include bit width mode control bits, security policy control bits, and floating point rounding mode control bits. The bit width mode control bits are used to control the bit width of an operation unit, the security policy control bits are used to define the memory encryption strength and access permission, and the floating point rounding mode control bits are used to specify the floating point rounding mode under the IEEE binary floating point arithmetic standard.
[0051] In some embodiments, considering that the high bit fields are usually close to the starting bit line of the register, in order to facilitate the first extraction of the control bit fields and input into the control logic unit in the shortest clock period, the control bits can be deployed in the high bit part of the register, the reserved bits can be deployed in the low bit part, and the bit width mode control bits, the security policy control bits, and the floating point rounding mode control bits can be distributed in order from high to low. In other embodiments, the bit width mode control bits, the security policy control bits, and the floating point rounding mode control bits each occupy 4 bits.
[0052] Specifically, the bit-width mode control bits are 4 bits wide in the current embodiment, i.e. occupying the highest 4 bits of the register (e.g. bits [31:28]). The role of this field is to directly control the data path bit-width setting in the processor execution unit. By modifying the value of this field, the system can dynamically switch between different precision modes such as 4-bit, 8-bit, 16-bit, and 32-bit, to adapt to the needs of different application scenarios for operation precision and energy efficiency.
[0053] Next is the security policy control bit, which occupies the next 4 bits of the register (e.g. bits [27:24]) and is used to indicate the security level of the current computing task. The content of this field can be mapped to different memory access permissions, encryption strengths, or execution domains, such as 0b0000 representing a non-secure domain, 0b1000 representing a medium encryption level, and 0b1111 representing a fully encrypted and access-isolated state. This control bit field can be read by access control logic during data access and instruction execution and can determine in real time whether the current operation is allowed, effectively improving the system's security protection capability. Especially in tasks with high security level requirements, this field can automatically trigger a hardware-level security state switch, avoiding security gaps caused by software scheduling delays.
[0054] The third part is the floating-point rounding mode control bit, usually located at [23:20] bits, also 4 bits wide. This field is used to specify the rounding method used in floating-point operations, in accordance with the definition of the IEEE-754 standard. This field supports several rounding methods including but not limited to: Round to nearest, ties to even, Round towards zero (RTZ), Round towards +∞, and Round towards -∞. Before the floating-point unit (FPU) performs calculations, the value of this field will be read by the hardware decoding unit and directly used to control the FPU internal rounding logic, thereby ensuring the consistency and predictability of floating-point calculations.
[0055] In addition, to ensure that the register has good scalability, the register also sets a reserved bit field at [19:0] bits. These bits do not currently participate in the real-time control of the register's functions, but are reserved during the hardware design phase to allow for future addition of more control parameters, such as more complex security policy expressions, extended floating-point behavior parameters, or preparation for supporting new instruction set architectures.
[0056] In the working mechanism of the register, the updating of the register is completed by the instruction decoder and the control logic. In the instruction decoding stage, when a specific operation code related to the bit width mode control bit is detected, the system will parse the operation code and write the control parameters corresponding to the operation code into the corresponding control bit field, realizing the integrated joint updating of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit. Among them, the operation code direct writing mapping method can be used to update each control bit field of the register to reduce the control complexity. The control logic notifies the execution unit corresponding to each control bit of the updating event of the register, so that the execution unit executes the operation in the latest bit width mode, security policy and floating point rounding mode.
[0057] Generally, the integrated conditional execution flag register provided by the embodiment of the application integrates the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit into a single register, supports the integrated joint updating of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit when the bit width mode changes, eliminates the access delay, realizes the state atomic update by using the hardware automatic triggering rule, and reduces the control complexity by using the operation code direct writing mapping. Therefore, under the premise of ensuring safety, the more efficient and flexible calculation control strategy can be realized, the software configuration delay and the state inconsistency risk in the traditional scheme are eliminated by the hardware level state integration, and the processor can complete the execution state management with fewer clock cycles, smaller switching cost and higher policy consistency when facing mixed precision, high security and floating point intensive tasks.
[0058] Figure 2 is the flowchart of the calculation control method based on the integrated conditional execution flag register provided by the embodiment of the application, as Figure 2 shown, the calculation control method comprises:
[0059] Step 210, decoding the operation code received by the instruction decoder to obtain the decoding result of the operation code;
[0060] Step 220, determining whether the control parameter of the bit width mode control bit is defined in the operation code based on the decoding result of the operation code;
[0061] Step 230, if the control parameter of the bit width mode control bit is different from the current field value of the bit width mode control bit of the integrated conditional execution flag register, using the bypass writing circuit to jointly update the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register based on the control parameter of the bit width mode control bit defined in the operation code;
[0062] At step 240, based on the updated field values of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit in the integrated conditional execution flag register, the execution unit corresponding to each control bit is configured to perform calculation based on the configured execution unit.
[0063] Here, the operation code from the instruction stream is received by the instruction decoder. The operation code not only carries the operation information of the conventional arithmetic or logical operation, but also can embed one or more control bit parameters for specifying the operation width, security level and floating point rounding mode in which the instruction should be executed. The instruction decoder decodes the operation code and outputs the corresponding decoding result, which includes the operation type, operation number, target register identifier and control bit parameters of the bit width mode control bit, etc.
[0064] Next, based on the decoding result of the operation code, it is analyzed whether the control parameter of the bit width mode control bit is carried in the operation code. If the control parameter exists and the control parameter of the bit width mode control bit is different from the current field value of the bit width mode control bit of the integrated conditional execution flag register, it indicates that the instruction wants to change the bit width mode. At this time, a dedicated bypass write circuit can be enabled. The bypass write circuit is directly connected to the write end of the integrated conditional execution flag register, allowing the control bit parameter of the bit width mode control bit carried in the operation code to be written into the integrated conditional execution flag register in a single cycle.
[0065] It is worth noting that in the embodiment of the present application, not only the field value of the bit width mode control bit of the integrated conditional execution flag register is updated, but also the field values of the security policy control bit and the floating point rounding mode control bit are updated. This is because there is a close coupling relationship between these fields, for example, some security domains may require higher floating point precision or specific rounding strategy. During the updating process, the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit are updated integrally, which can ensure the consistency and atomicity of state switching, thereby avoiding the inconsistency between execution behavior and security policy, calculation precision. In addition, since the bit width mode, security policy and floating point rounding mode are integrated into the same register structure and updated quickly through the unified bypass write circuit, only one register write operation is required for each state switching, which can complete the synchronous change of multiple execution state controls, significantly reducing the delay caused by multiple register switching in the traditional architecture.
[0066] In some embodiments, the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register are jointly updated based on the control parameter of the bit width mode control bit defined in the operation code, or based on the control parameter of the bit width mode control bit and the floating point rounding mode control bit defined in the operation code.
[0067] For example, when the control parameter of the bit width mode control bit is 4 bits, the field value of the bit width mode control bit of the integrated conditional execution flag register is updated to 4 bits, and the field values of the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register are forcibly updated to forced encryption and RTZ rounding, respectively. By so setting, the rigid requirements of security and hardware can be met.
[0068] When the control parameter of the bit width mode control bit is 32 bits, the field value of the bit width mode control bit of the integrated conditional execution flag register is updated to 32 bits, the field value of the security policy control bit of the integrated conditional execution flag register is updated based on the current execution domain (for example, the field value of the security policy control bit is set to the highest security level when the current execution domain is a secure domain, and the field value of the security policy control bit is set to a preset lower security level when the current execution domain is a non-secure domain), and the field value of the floating point rounding mode control bit of the integrated conditional execution flag register is updated based on the control parameter of the floating point rounding mode control bit defined in the operation code. By so setting, the optimal balance between performance and flexibility can be achieved.
[0069] The updated register value will be immediately read by the related control logic, and drive the configuration update of multiple execution units to perform calculation based on the configured execution units. For example, the arithmetic logic unit adjusts its operation path according to the field value of the new bit width mode control bit; the floating point operation unit synchronously loads the new floating point rounding mode setting for controlling the rounding direction of the decimal error in the floating point operations such as addition, subtraction, multiplication and division; the memory access unit and the security engine reconfigure the access authority, encryption strength and cross-domain checking mechanism according to the new security policy field, to ensure the compliance and security of the subsequent access behavior under the new security policy.
[0070] In other embodiments, when the operation code involves privileged operations, register access or cross-memory domain access, such as Figure 3As shown, the opcode permission check, the register security policy check and the memory access domain check can be sequentially performed to realize a three-level check mechanism, and the operation corresponding to the operation code is executed after the opcode permission check, the register security policy check and the memory access domain check all pass. If any level check fails, the processor pipeline is frozen in real time, the specific exception information (for example, the illegal operation code / address / domain ID) is recorded in the security event register, and the forced redirection to 0xFFFF_0000 (that is, the security monitoring firmware entry) is performed.
[0071] Specifically, in the process of sequentially performing the opcode permission check, the register security policy check and the memory access domain check, the high three-bit field value of the operation code can be first extracted from the decoding result of the operation code, and the high three-bit field value is compared with the permission mapping table in the processor microcode to perform the opcode permission check. If the high three-bit field value is greater than or equal to the minimum permission allowed by the current security domain in the permission mapping table, it indicates that the opcode permission check passes, and it is determined whether the current operation corresponding to the operation code hits the operation corresponding to the disable operation bit in the security policy control bit of the integrated conditional execution flag register, to realize the register security policy check. The bit with a value of 0 in the security policy control bit is the disable operation bit. If the current operation corresponding to the operation code does not hit the operation corresponding to the disable operation bit in the security policy control bit of the integrated conditional execution flag register, it indicates that the register security policy check passes, and the memory access domain check is performed based on the physical address of the requested memory, the current process security domain ID, the operation type and the encryption state identifier corresponding to the operation code.
[0072] In some embodiments, the memory access domain check can be realized based on the matching mode as shown in Figure 4 .
[0073] In summary, the computing control method provided by the embodiments of the present application decodes the instruction operation code through the instruction decoder, identifies and analyzes the control parameters contained in the instruction, and then drives the synchronous update of multiple key control fields such as the bit width mode, the security policy and the floating point rounding mode in the integrated register, and accordingly configures each execution unit of the processor, so that the entire system realizes accurate and flexible computing behavior control during running, and realizes fast linkage and atomic update of the processor state, thereby improving the efficiency and consistency of state switching in the computing task.
[0074] The embodiments of the present application also provide a non-transitory computer readable storage medium having a computer program stored thereon, and the computer program is executed by a processor to realize the computing control method provided by each of the above embodiments, for example, including:
[0075] The instruction decoder decodes the received operation code to obtain a decoding result of the operation code.
[0076] Based on the decoding result of the operation code, it is determined whether the control parameter of the bit width mode control bit is defined in the operation code;
[0077] If the control parameter of the bit width mode control bit is different from the current field value of the bit width mode control bit of the integrated condition execution flag register, the joint update of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit of the integrated condition execution flag register is performed based on the control parameter of the bit width mode control bit defined in the operation code by using a bypass write circuit;
[0078] Based on the updated field values of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit in the integrated condition execution flag register, the execution units corresponding to each control bit are configured to perform calculation based on the configured execution units.
[0079] The device embodiments described above are only schematic, wherein the units illustrated as separate components can or can not be physically separate, and the components illustrated as units can or can not be physical units, i.e., can be located in one place or distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the embodiment scheme. Those skilled in the art can understand and implement without creative labor.
[0080] From the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be realized by means of software and necessary general hardware platform, and of course can also be realized by hardware. Based on such understanding, the above technical solutions can be embodied in the form of software product, which can be stored in a computer readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes a plurality of instructions to make a computer device (which can be a personal computer, server, or network device, etc.) execute the method described in each embodiment or some part of the embodiment.
[0081] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement to some technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.
Claims
1. An integrated conditional execution flag register, comprising: The control bits and the reserved bits; the control bits include a bit width mode control bit, a security policy control bit and a floating point rounding mode control bit; The field of the bit width mode control bit is used to control the bit width of the operation unit; The field of the security policy control bit is used to define the memory encryption strength and the access permission; The field of the floating point rounding mode control bit is used to specify the floating point rounding mode under the IEEE binary floating point number arithmetic standard; The field of the reserved bit is used to extend the security policy and / or the floating point rounding mode. The control bits are in the higher bits of the integrated conditional execution flag register relative to the reserved bits, and are arranged in the order of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit from the high bit to the low bit.
2. The integrated conditional execution flag register of claim 1, wherein, The bit width mode control bit, the security policy control bit and the floating point rounding mode control bit are all 4 bits.
3. The integrated conditional execution flag register of claim 2, wherein, The method comprises:
4. A method of computing control based on the integrated conditional execution flag register according to any one of claims 1 to 3, characterized in that, decoding the received operation code based on an instruction decoder to obtain a decoding result of the operation code; determining whether a control bit parameter of the bit width mode control bit is defined in the operation code based on the decoding result of the operation code; if the control parameter of the bit width mode control bit is different from the current field value of the bit width mode control bit of the integrated conditional execution flag register, then using a bypass write circuit to jointly update the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register based on the control parameter of the bit width mode control bit defined in the operation code; configuring the execution units corresponding to each control bit based on the updated field values of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit in the integrated conditional execution flag register, so as to perform calculation based on the configured execution units. The joint update of the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register based on the control parameter of the bit width mode control bit defined in the operation code comprises:
5. The computing control method of claim 4, wherein, jointly updating the bit width mode control bit, the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register based on the control parameter of the bit width mode control bit defined in the operation code, or based on the control parameters of the bit width mode control bit and the floating point rounding mode control bit defined in the operation code; wherein, when the control parameter of the bit width mode control bit is 4 bits, the field value of the bit width mode control bit of the integrated conditional execution flag register is updated to 4 bits, and the field values of the security policy control bit and the floating point rounding mode control bit of the integrated conditional execution flag register are forced to be updated to forced encryption and RTZ rounding respectively. When the control parameter of the bit width mode control bit is 32bit, the field value of the bit width mode control bit of the integrated conditional execution flag register is updated to 32bit, and the field value of the security policy control bit of the integrated conditional execution flag register is updated based on the current execution domain, and the field value of the floating point rounding mode control bit of the integrated conditional execution flag register is updated based on the control parameter of the floating point rounding mode control bit defined in the operation code.
6. The calculation control method according to claim 4 or 5, characterized by, The method further comprises: When the operation code involves a privileged operation, a register access or a cross-memory domain access, sequentially performing operation code permission check, register security policy check and memory access domain check, and performing the operation corresponding to the operation code after the operation code permission check, the register security policy check and the memory access domain check all pass.
7. The computing control method of claim 6, wherein, The sequentially performing operation code permission check, register security policy check and memory access domain check comprises: extracting the high three-bit field value of the operation code from the decoding result of the operation code, and comparing the high three-bit field value with the permission mapping table in the processor microcode; if the high three-bit field value is greater than or equal to the lowest permission allowed by the current security domain specified in the permission mapping table, indicating that the operation code permission check passes, determining whether the current operation corresponding to the operation code hits the operation corresponding to the disable operation bit in the security policy control bit of the integrated conditional execution flag register; if the current operation corresponding to the operation code does not hit the operation corresponding to the disable operation bit in the security policy control bit of the integrated conditional execution flag register, indicating that the register security policy check passes, performing memory access domain check based on the physical address of the requested memory, the current process security domain ID, the operation type and the encryption state identifier corresponding to the operation code.
8. A processor architecture, characterized by The processor architecture comprises the integrated conditional execution flag register of any one of claims 1-3.
9. A chip, characterized by The chip comprises the integrated conditional execution flag register of any one of claims 1-3.
10. A storage medium having stored thereon computer program instructions, characterized in that, The computer program instructions, when executed, implement the computing control method of any one of claims 4-7. The computer program instructions, when executed, implement the computing control method of any one of claims 4-7.