VLIW-oriented RISC-V instruction set expansion method

Abstract

The invention provides a VLIW-oriented RISC-V instruction set expansion method, which comprises the following steps of: modifying an RISC-V instruction set to enable the RISC-V instruction set to support a VLIW instruction format, comprising the following steps of: modifying the meaning of an operation code according to the following modes: using the 0th bit of an instruction as a group end bit to represent whether the instruction and a next instruction belong to the same VLIW instruction packet or not, and determining the end position of the VLIW instruction packet; when the instruction is one instruction in the VLIW instruction packet, the 1-Nth bit of the instruction is used as a slot number field to indicate the position of a VLIW instruction slot to which the instruction belongs, and N is smaller than or equal to 3; the method can support the realization of maximum 2N paths of VLIW, basically covers all special calculation scenes needing VLIW to carry out instruction-level parallel acceleration, and also basically covers the limit of instruction-level parallelism which can be reached by a general program; according to the method, the support on the variable-length VLIW is efficiently completed, and a decoding distribution component at the front end of the processor can be very simply realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computing, specifically to the field of processor or accelerator design, and more specifically to a RISC-V instruction set extension method for VLIW. BACKGROUND

[0002] In recent years, the RISC-V open instruction set and its ecosystem have developed rapidly. A large number of fields are based on the RISC-V standard instruction set and its standard expansion to develop processors and chips. This maximizes the use of tool chains within the RISC-V open ecosystem and enhances the compatibility of the processor. However, in some specialized computing acceleration fields, such as wireless communication baseband processing and robot motion control, compatibility with the open ecosystem is not as important. These fields prioritize the specialization of the processor architecture and maximizing the energy efficiency ratio of the architecture. They usually do not need to be open to external users for secondary development or separate programming. For specialized computing acceleration, there are usually two ways: data-level parallelism and instruction-level parallelism. In terms of data-level parallelism, RISC-V has the standard V and P extensions to implement single instruction multiple data (SIMD) processing. However, in terms of instruction-level parallelism, RISC-V's solution is more geared towards general-purpose computing, such as implementing dynamic multi-issue, which is a complex hardware implementation. In the above-mentioned fields, it is usually desirable to simplify the hardware design of the processor chip as much as possible and to minimize power consumption, so it is more inclined to use very long instruction word (VLIW). The RISC-V standard instruction set and its extensions do not fully support VLIW. The official recommendation for implementing a custom VLIW instruction set based on RISC-V is limited in terms of instruction encoding, as the semantics are restricted by the standard RISC-V encoding. Please refer to Chapter 35 and Section 35.5 of the official manual "The RISC-V Instruction Set Manual Volume I". The official recommendation for designing a VLIW instruction set extension based on the standard RISCV encoding is in Section 35.5 of Annex I. In general, there are four possible solutions. The first three solutions, corresponding to Sections 35.5.1, 35.5.2, and 35.5.3, mainly involve packaging multiple parallel instructions as a whole. When packaging parallel instructions as a whole, if the length of the instruction package is fixed, the instruction-level parallelism may not always reach the corresponding length, resulting in the insertion of many NOP instructions in the running instruction package, affecting code size and wasting code storage area. If the instruction package length is designed to be variable, additional bits are needed to represent the length of the parallel instruction package, which occupies additional bits and reduces the instruction encoding space. The last solution in the official manual, Section 35.5.4, defines the 0th bit as the end-of-group bit to indicate whether the current instruction is parallel with the next instruction. The 1st bit is used to indicate whether the current instruction is executed under certain conditions. The advantage of this solution is that it maintains compatibility with the standard RISCV encoding, as the first two bits of the standard RISC-V 32-bit encoding are both 1, i.e., 11.So they are still correct in the semantics of this new VLIW encoding rule (11: each instruction is not parallel, and the normal execution does not depend on the condition). However, the scheme given in section 35.5.4 of the official manual is limited to the standard RISC-V encoding space, and the semantics is limited, which cannot define a more flexible VLIW instruction package scheme, resulting in limited efficiency in some special processor fields that do not need to support standard RISC-V encoding.

[0003] It should be noted that: the background art is only used to introduce the related information of the present application, so as to help understand the technical scheme of the present application, but it does not mean that the related information must be prior art. The related information is submitted and disclosed together with the present application scheme, and in the absence of evidence that the related information has been publicly disclosed before the filing date of the present application, the related information should not be regarded as prior art. SUMMARY

[0004] Therefore, the purpose of the present application is to overcome the defects of the prior art, and to provide a RISC-V instruction set expansion method for VLIW.

[0005] The purpose of the present application is achieved by the following technical scheme:

[0006] According to the first aspect of the present application, a RISC-V instruction set expansion method is provided, comprising: modifying the RISC-V instruction set so that the RISC-V instruction set supports the VLIW instruction format, including: using the 0th bit of the instruction as the group end bit to represent whether the instruction belongs to a VLIW instruction package with the next instruction and determine the end position of the VLIW instruction package; when the instruction is one of the VLIW instruction package, the 1st-Nth bit of the instruction is used as the slot number field to indicate the position of the VLIW instruction slot to which the instruction belongs, N≤3. This scheme can at least achieve the following beneficial technical effects: this scheme introduces a group end bit to represent the parallelism of the preceding and following instructions, and introduces 1 to N bits adjacent to the 0th bit as a slot number field to represent the corresponding VLIW instruction slot of the instruction. In this way, VLIW implementation with a maximum of 2 N Road VLIW implementation, basically covering all special computing scenarios that need VLIW for instruction-level parallel acceleration, and basically covering the limit of instruction-level parallelism that general programs can achieve; efficiently complete the support of variable-length VLIW, and make the implementation of the processor front-end decoding and distribution component very simple.

[0007] Optionally, the N is 2 or 3, wherein when the N is 2, the first 2 bits of the instruction are used as the slot number field, so that the RISC-V instruction set supports 2-4 way VLIW instructions, and the third bit of the instruction is used as a reserved bit for supporting future functional expansion; when the N is 3, the first 3 bits of the instruction are used as the slot number field, so that the RISC-V instruction set supports 2-8 way VLIW instructions. This scheme can at least achieve the following beneficial technical effects: when N is equal to 2, a maximum of 4-way VLIW instructions can be supported, and since the first 2 bits of the instruction are used as the slot number field, the slot number field is adjacent to the group end bit (the first bit), which facilitates faster access to the concurrency state of the instruction during subsequent processor decoding, efficient identification of the position of the related instructions and their belonging instruction slots within a VLIW instruction package, without decoding the entire instruction.

[0008] Optionally, the modification of the RISC-V instruction set further includes: setting the RISC-V instruction set to not provide semantic support for the standard C extension 16-bit instructions; and widening the representation range of the immediate number field in at least part of the types of jump instructions, so that the target address recorded by the immediate number field has a wider range of offset relative to the address of the jump instruction. This scheme can at least achieve the following beneficial technical effects: since the 0th bit is allocated as the group end bit, the present scheme does not support the standard RISC-V 16-bit compressed instruction C extension. Therefore, for the jump instructions of RV32I, the immediate number field can represent a wider range, because under the present scheme, all instructions are 32 bits, there are no 16-bit and other length basic instructions, so the value of the instruction address is always 0 in the binary representation. The original RV32I encoding considers the possibility of compressed 16-bit instructions, so only the lowest bit of the instruction address is always 0. Therefore, the immediate number field of the jump instruction in the present scheme can represent a range of values that is one bit larger than the original version, making the range of addresses represented by the immediate number field in the jump instruction wider.

[0009] Optionally, when the jump instruction is of type B, the immediate number field uses the 7th-11th and 25th-31st bits of the instruction to store the 2nd-13th bits of the offset of the target address relative to the address of the jump instruction, and omits the 0th and 1st bits of the offset. This scheme can at least achieve the following beneficial technical effects: the present scheme extends the length of the offset of the target address that can be represented by the immediate number field from 12 bits to 13 bits, improving the range of use for subsequent developers and enhancing flexibility.

[0010] Optionally, when the jump instruction is of J type, the immediate number field uses the 2nd-21st bit of the 12th-31st bit of the instruction to store the offset of the target address relative to the address of the jump instruction, and the 0th and 1st bits of the offset are omitted. This scheme can at least achieve the following beneficial technical effects: this scheme expands the length of the offset of the target address of the jump that the immediate number field can represent from 12 bits to 13 bits, improves the usage range of subsequent developers, and enhances flexibility.

[0011] Optionally, the 7th-31st bit field of the R type, I type, S type and U type instructions is defined to remain consistent with the definition in the original RISC-V instruction set.

[0012] Optionally, the modification of the RISC-V instruction set further includes: when N=2, the types of the plurality of RV32I scalar instructions and the allocation positions on the VLIW instruction slots are represented in combination with the 1st-2nd bit and the 3rd-6th bit of the instruction. This scheme can at least achieve the following beneficial technical effects: this scheme effectively implements the allocation of the relevant instruction types on the VLIW instruction slots by representing the plurality of RV32I scalar instructions in combination with the 1st-2nd bit and the 3rd-6th bit of the instruction; and the 3rd bit of the instruction can be used as a reserved bit for subsequent support of other new functions.

[0013] Optionally, the types of the plurality of RV32I scalar instructions are defined according to the following table:

[0014]

[0015] Among them, NOP represents a null instruction, BRANCH represents a conditional branch instruction of a conditional jump, LUI represents an instruction of reading an immediate number, LOAD represents a load instruction of loading data from a memory to a register, JAL represents an unconditional jump instruction, OP-UIMM represents an instruction with a signed immediate number in the operand, STORE represents an instruction of writing data to a memory, JALR represents an unconditional jump instruction with a jump address in a register, OP-IMM represents an instruction with a signed immediate number in the operand, OP represents an instruction with all operands being registers, / represents a temporarily undefined spare field, and the spare field is used to define other instruction types. This scheme can at least achieve the following beneficial technical effects: as can be seen, under this scheme, not only are the plurality of RV32I scalar instructions defined and allocated, but also there are still many spare fields, which can effectively support the expansion and compatibility of subsequent new instruction types.

[0016] Optionally, the modification of the RISC-V instruction set further includes: when N=3, the types of the plurality of RV32I scalar instructions and the allocation positions on the VLIW instruction slots are represented in combination with the 1st-3rd bit and the 4th-6th bit of the instruction.

[0017] According to a second aspect of the present application, a RISC-V instruction set based processor is provided, which supports a modified RISC-V instruction set according to the method of the first aspect, and is configured to: determine a plurality of parallel instructions belonging to a VLIW instruction packet by reading the 0th bit of an instruction, wherein when the 0th bit of an instruction is a first value, it belongs to a VLIW instruction packet with the next instruction, and when the 0th bit of an instruction is a second value and the previous instruction is the first value, it is the end position of a VLIW instruction packet, and identify the instruction with the second value and all the instructions with the first value appearing continuously before it as a plurality of parallel instructions belonging to a VLIW instruction packet; parse the position of the VLIW instruction slot to which each instruction belongs by reading the 1st-Nth bit of each instruction in the plurality of parallel instructions, and transmit each instruction in the plurality of parallel instructions to the function unit bound in advance at the corresponding position in the same cycle. BRIEF DESCRIPTION OF DRAWINGS

[0018] The embodiments of the present application will be further described below with reference to the accompanying drawings, in which:

[0019] Figure 1 A flowchart of the extension method for the RISC-V instruction set according to the embodiments of the present application;

[0020] Figure 2 A schematic diagram of the instruction structure after modifying the definition of the operation code and widening the representation interval of the immediate number field in at least part of the jump instruction according to the extension method for the RISC-V instruction set according to the embodiments of the present application;

[0021] Figure 3 A schematic diagram of the instruction structure after modifying the definition of the operation code and without widening the representation interval of the immediate number field in the jump instruction according to the extension method for the RISC-V instruction set according to the embodiments of the present application. DETAILED DESCRIPTION

[0022] In order to make the purpose, technical scheme and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and do not limit the present application.

[0023] As mentioned in the background section, the scheme given in section 35.5.4 of the official manual is limited to the standard RISC-V encoding space, the semantics are limited and cannot define a more flexible VLIW instruction packet scheme, resulting in limited efficiency in some special processor fields that do not need to support standard RISC-V encoding. The 0th bit in the method of the present application is the same as the naming given in section 35.5.4 of the official manual, which is the group end bit, used to indicate whether the current instruction is parallel to the next instruction (i.e. belongs to the same VLIW instruction packet), but the definition of the 1st bit is different. The method of the present application is to jointly use the 1st-Nth bit (such as the 1st-2nd bit) as a slot number field (also called Slot field), to indicate which lane of the VLIW the current instruction should be located in (i.e. the position of the VLIW instruction slot it belongs to). In this way, although the compatibility with the standard RISC-V encoding is lost, i.e. it becomes a non-standard RISCV extension, the slot number field composed of the 1st and 2nd bits more directly represents the category of the current instruction, which can make the processor supporting the modified RISC-V instruction set of the extension method know faster during decoding and distributing instructions what category the current instruction is and to which functional unit it should be distributed for execution. Thus, the efficiency of decoding and distribution is higher. And, a more aggressive VLIW semantic can be represented, which is not limited by the semantic restrictions brought by compatibility with the standard RISC-V encoding, and is an instruction encoding more suitable for the design of VLIW processors in special fields (such as wireless communication baseband processors, robot motion control processors or neural network processors, etc.).

[0024] Embodiment 1

[0025] This embodiment extends the instruction set of RISC-V 32 (RV32), and the implementer only needs to support a maximum of 4-way parallel VLIW instruction packets, at which time N is set to 2. When N is 2, the 1st-2nd bit of the instruction is used as the slot number field, so that the RISC-V instruction set supports 2-4 way VLIW instructions, and the 3rd bit of the instruction is used as a reserved bit to support future functional extensions.

[0026] According to one embodiment of the present application, as shown in Figure 1 As shown in the background section, the scheme given in section 35.5.4 of the official manual is limited to the standard RISC-V encoding space, the semantics are limited and cannot define a more flexible VLIW instruction packet scheme, resulting in limited efficiency in some special processor fields that do not need to support standard RISC-V encoding. The 0th bit in the method of the present application is the same as the naming given in section 35.5.4 of the official manual, which is the group end bit, used to indicate whether the current instruction is parallel to the next instruction (i.e. belongs to the same VLIW instruction packet), but the definition of the 1st bit is different. The method of the present application is to jointly use the 1st-Nth bit (such as the 1st-2nd bit) as a slot number field (also called Slot field), to indicate which lane of the VLIW the current instruction should be located in (i.e. the position of the VLIW instruction slot it belongs to). In this way, although the compatibility with the standard RISC-V encoding is lost, i.e. it becomes a non-standard RISCV extension, the slot number field composed of the 1st and 2nd bits more directly represents the category of the current instruction, which can make the processor supporting the modified RISC-V instruction set of the extension method know faster during decoding and distributing instructions what category the current instruction is and to which functional unit it should be distributed for execution. Thus, the efficiency of decoding and distribution is higher. And, a more aggressive VLIW semantic can be represented, which is not limited by the semantic restrictions brought by compatibility with the standard RISC-V encoding, and is an instruction encoding more suitable for the design of VLIW processors in special fields (such as wireless communication baseband processors, robot motion control processors or neural network processors, etc.). Figure 2As shown, the impact of the modification is seen in the red letter e and slot in bits 0-2 relative to the standard RISC-V instruction set. Bits 1 and 2 of the instruction are allocated as a slot number field (slot) to indicate the position of the VLIW instruction slot to which the current instruction belongs, which can be 0-3, corresponding to 4-way instruction slots. The definition of bit 3 is reserved, so that the subsequent bit 3 can be extended into the slot number field, and the current two bits together form a 3-bit slot number field, which can support a maximum of 8-way VLIW instructions, reserving instruction architecture expansion. Alternatively, the implementer can also add other new definitions based on bit 3 to realize other functions. Thus, the processor decoding distribution unit can quickly learn the VLIW instruction slot to which the instruction belongs through bits 1-2 after determining that the instruction is a parallel instruction through bit 0, thereby speeding up the decoding and distribution efficiency.

[0027] Figure 2 The meaning of each letter in the above table is as follows:

[0028] The letter on the right side of the rectangular box indicates the instruction type:

[0029] R: R-type instruction;

[0030] I: I-type instruction;

[0031] S: S-type instruction;

[0032] B: B-type instruction;

[0033] U: U-type instruction;

[0034] J: J-type instruction;

[0035] The letter in each cell in the rectangular box indicates a field, which is as follows:

[0036] imm: immediate number;

[0037] rs1: source register 1;

[0038] rs2: source register 2;

[0039] funct3: function area;

[0040] rd: target register;

[0041] opcode: instruction opcode (note: bits 0-6 together form the instruction opcode, and in the figure, only the slot number field slot and the group end bit e are highlighted);

[0042] slot: slot number of VLIW instruction slot;

[0043] e: end-of-group bit.

[0044] According to one embodiment of the present application, when the RISC-V instruction set is used in a 32-bit system, the modification of the RISC-V instruction set further comprises: setting the RISC-V instruction set not to provide semantic support for the 16-bit instructions of the standard C extension; and widening the representation range of the immediate number field in at least part of the types of jump instructions, so that the target address recorded by the immediate number field has a wider range of offset relative to the address of the jump instruction. The original RV32I encoding supports the 16-bit instructions of the standard C extension. Since the possibility of compressing 16-bit instructions needs to be considered, only the lowest bit of the instruction address is always 0, and the 0-1 bits of the instruction can be used to distinguish between 16-bit and 32-bit instructions. However, since the 0th bit is allocated as the group end bit and the 1st-2nd bits are used as the slot number field in the method of the present application, it is not possible to support the 16-bit instructions of the standard C extension in the present application, and only 32-bit instructions need to be supported. In the case of only supporting 32-bit instructions, the RISC-V instruction must be 4-byte aligned (the lowest 2 bits of the offset of the destination address are always 0), so the lowest 2 bits of all control flow offsets must be 0, and the lowest 2 bits of the immediate number field of the jump instruction can be omitted to widen the representation range of the immediate number field.

[0045] Optionally, when the RISC-V instruction set is used in the case of only supporting 32-bit encoding and the jump instruction is of the B type, the immediate number field uses the 7th-11th bits and the 25th-31st bits of the instruction to store the 2nd-13th bits of the offset of the target address relative to the address of the jump instruction, and the 0th bit and the 1st bit of the offset are omitted. One example of this modification can be seen in the 7th-11th bits and the 25th-31st bits of the immediate number field of the B type of instruction of Figure 2 , relative to the standard RISC-V instruction set, the impact of this modification can be seen in the red part.

[0046] Optionally, when the RISC-V instruction set is used in the case of only supporting 32-bit encoding and the jump instruction is of the J type, the immediate number field uses the 12th-31st bits of the instruction to store the 2nd-21st bits of the offset of the target address relative to the address of the jump instruction, and the 0th bit and the 1st bit of the offset are omitted. One example of this modification can be seen in the 12th-31st bits of the immediate number field of the J type of instruction of Figure 2 , relative to the standard RISC-V instruction set, the impact of this modification can be seen in the red part.

[0047] According to one embodiment of the present application, referring to Figure 2 , the field definitions of the 7th-31st bits of the R type, I type, S type and U type instructions remain consistent with the definitions in the original RISC-V instruction set.

[0048] Embodiment 2

[0049] The embodiment differs from embodiment 1 in that the embodiment does not widen the representation range of the immediate number field in the jump instruction. Thus, some types of instructions in the embodiment are as shown in Table 1. Figure 3 Figure 3 The definitions of the letters in each column are consistent with those in Figure 2 and will not be repeated here.

[0050] Embodiment 3

[0051] The embodiment can be based on embodiment 1 or 2 to define types of various RV32I scalar instructions.

[0052] According to one embodiment of the present application, the modification of the RISC-V instruction set further includes that when N=2, the types of various RV32I scalar instructions and the allocation positions on each VLIW instruction slot are represented in combination with the 1st-2nd bits and the 3rd-6th bits of the instruction. Illustratively, the types of various RV32I scalar instructions are defined according to the following table:

[0053] Table 1

[0054]

[0055] Among them, NOP represents the empty instruction, BRANCH represents the conditional branch type instruction of conditional jump, LUI represents the instruction of reading immediate number, LOAD represents the load instruction of loading data from memory to register, JAL represents the unconditional jump instruction, OP-UIMM represents the instruction with unsigned immediate number in the operand, STORE represents the instruction of writing data to memory, JALR represents the unconditional jump instruction with jump address in register, OP-IMM represents the instruction with signed immediate number in the operand, OP represents the instruction with register as the operand, / represents the temporarily undefined spare field, and the spare field is used to define other instruction types.

[0056] It should be noted that in Table 1, the first row represents the 1st-2nd bits of the instruction, i.e. the slot number field, and the first table represents the 3rd-6th bits of the instruction, which together with the 0th bit (e bit) form the encoding domain of the operation code of the instruction. When allocating, the 3rd bit is reserved and no instruction is allocated, so that the subsequent 3rd bit can be extended into the slot number field and together with the original two bits form a 3-bit slot number field, which can support a maximum of 8-way VLIW instruction, and the reserved instruction architecture extension. The spare field of Table 1 can be allocated as needed to add other instructions. The present scheme maintains the scalability of the VLIW instruction architecture, and supports the simple front-end implementation of the VLIW architecture processor through non-standard extension of the original RISC-V instruction code.

[0057] Embodiment 4

[0058] ​The embodiment is different from the embodiments 1-3 in that N is set to 3, so that the RISC-V instruction set supports 2-8-way VLIW instructions.

[0059] According to one embodiment of the present application, the modification of the RISC-V instruction set further comprises: when N=3, the types of the plurality of RV32I scalar instructions and the allocation positions on the VLIW instruction slots are represented in combination with the 1st-3rd bits and the 4th-6th bits of the instruction.

[0060] Illustratively, the types of the plurality of RV32I scalar instructions are defined according to the following table:

[0061] Table 2

[0062]

[0063] This embodiment, although less spare fields than the embodiment 3, can support larger number of VLIW instruction packets, and can provide greater parallel computing efficiency in some special acceleration fields (such as image neural network accelerator).

[0064] In addition, it should be noted that Table 1 and Table 2 are only preferred examples, and those skilled in the art can also make fine adjustments to obtain other alternative examples. For example, the positions of different types of instructions in the same column of Table 1 or Table 2 are exchanged, or a certain instruction is moved to another position in the same column.

[0065] Embodiment 5

[0066] The embodiment is different from the embodiments 1-4 in that the embodiment extends the instruction set of RISC-V 64 (RV64) or RISC-V 128 (RV128). For RV64I and RV128I, only the length of the registers processed by the instructions is lengthened, and becomes 64 bits and 128 bits respectively. Since the instruction length of the basic instructions of RV64 and RV128 is still 32 bits, and the operation code is also the 0th-6th bits of the instruction, the beginning code is the same as that of RV32. Therefore, the scheme of embodiments 1-4 can still be used to design an efficient non-standard VLIW extension. Only the standard C extension of RISCV changes the length of the instruction itself to 16 bits per instruction. Therefore, the VLIW instruction set designed by the method of the present application cannot support the standard C extension. The standard C extension needs to use the 0th and 1st bits to represent the information that the instruction itself is 16 bits, which conflicts with the design of the 0th and 1st bits in the method of the present application.

[0067] According to one embodiment of the present application, the way of extending the instruction set of RV64I or RV128I is set with reference to embodiments 1-4, including setting the end bit, the definition of the slot number field or the way of extending the representation interval of the immediate number field in at least part of the type of jump instructions, which will not be repeated here.

[0068] Embodiment 6

[0069] The embodiment provides a RISC-V instruction set-based processor, which supports a RISC-V instruction set modified according to the extension method for the RISC-V instruction set as in the foregoing embodiments, and is configured to: determine a plurality of parallel instructions belonging to one VLIW instruction package by reading the 0th bit of an instruction, wherein when the 0th bit of an instruction is a first value, the instruction and the next instruction belong to one VLIW instruction package, when the 0th bit of an instruction is a second value and the previous instruction is the first value, the instruction is the end position of one VLIW instruction package, and all instructions with the 0th bit being the first value appearing continuously before the instruction with the 0th bit being the second value are identified as the plurality of parallel instructions belonging to one VLIW instruction package; and parse the position of the VLIW instruction slot to which each instruction belongs by reading the 1st-Nth bit of each instruction in the plurality of parallel instructions, and transmit each instruction in the plurality of parallel instructions to a function unit bound in advance at a corresponding position in the same cycle.

[0070] For example, assume that the first value is set as 0 and the second value is set as 1. Then, by reading one instruction, the multiple parallel instructions belonging to one VLIW instruction package are determined by the group end bit. If the group end bit of one instruction is 0, it indicates that the instruction is not the end position of one group (one VLIW instruction package), and the next instruction is also in the same group and parallel with the current instruction. On the contrary, if the group end bit is 1, it indicates that the instruction is the last instruction of the current parallel, and the next instruction is not parallel with the current group. Therefore, the setting of the 0th bit depends on the parallel condition of the instruction, and the 0th bit is set in advance before running, i.e., during the program compilation. If N is set as 2, the maximum parallel mode of the instruction can be achieved, and the 0th bit of four consecutive instructions should be in the mode of 0-0-0-1, i.e., four instructions are parallel, and the VLIW instruction slot is full. In general, the setting of the 0th bit is manually determined by the compiler or the programmer who writes the program, and when the M-way VLIW parallel is maximized, the mode of the 0th bit of the multiple consecutive instructions is M-1 0s followed by one 1. If N is 2, the VLIW instruction slot is divided into four positions, and for the multiple parallel instructions of one group, the position of each instruction in the VLIW instruction slot can be determined by the different values (such as 00, 01, 10, and 11) of the slot number field of the 1st-2nd bits (2 bits) adjacent to the 0th bit. In this way, the multiple parallel instructions belonging to one VLIW instruction package and the position of each instruction in the VLIW instruction slot can be efficiently identified.

[0071] It should be noted that although the above describes the steps in a specific order, it does not mean that the steps must be performed in the above specific order. In fact, some of the steps can be performed concurrently or even in reverse order, as long as the desired function can be achieved.

[0072] The present application can be a system, a method, and / or a computer program product. The computer program product can include a computer readable storage medium (or media) having computer readable program instructions thereon for causing a processor to carry out aspects of the present application.

[0073] A computer readable storage medium can be a tangible device that can retain and store instructions for use by an instruction execution device. The computer readable storage medium can be, for example, but is not limited to, an electronic storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium include the following: a portable computer diskette, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), a static random access memory (SRAM), a portable compact disc read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanically encoded device such as punch-cards or raised structures in a groove having instructions recorded thereon, and any suitable combination of the foregoing. A computer readable storage medium, as used herein, is not to be construed as being transitory signals per se, such as radio waves or other freely propagating electromagnetic waves.

[0074] Embodiments of the application have been described above, with the understanding that these embodiments are exemplary only, and are not restrictive, in terms of the scope of the embodiments disclosed. Many modifications and variations of the described embodiments are possible, in light of the above teachings, without departing from the scope and spirit of the described embodiments. The choice of words in this document is intended to best explain the principles of the embodiments, practical application, or technical improvement in the art, or to enable others skilled in the art to utilize the embodiments disclosed herein.

Claims

1. A method of extending for a RISC-V instruction set, comprising: The modification of the RISC-V instruction set makes the RISC-V instruction set support a VLIW instruction format, including modifying the meaning of the opcode in the following manner: The 0th bit of the instruction is used as a group end bit to represent whether the instruction belongs to a VLIW instruction packet with the next instruction and determine the end position of the VLIW instruction packet; When the instruction is one of the VLIW instruction packet, the 1st-Nth bit of the instruction is used as a slot number field to indicate the position of the VLIW instruction slot to which the instruction belongs, N≤3.

2. The method of claim 1, wherein, The N is 2 or 3, When N is 2, the 1st-2nd bit of the instruction is used as a slot number field, so that the RISC-V instruction set supports 2-4 way VLIW instructions, and the 3rd bit of the instruction is used as a reserved bit for future functional expansion; When N is 3, the 1st-3rd bit of the instruction is used as a slot number field, so that the RISC-V instruction set supports 2-8 way VLIW instructions.

3. The method of claim 1, wherein, The modification of the RISC-V instruction set also includes: The RISC-V instruction set is not semantically supported for 16-bit instructions of the standard C extension; The representation interval of the immediate number field in at least part of the jump instruction is widened, so that the target address recorded by the immediate number field has a wider range of offset relative to the address of the jump instruction.

4. The method of claim 3, wherein, When the jump instruction is of type B, the immediate number field uses the 7th-11th bit and the 25th-31st bit of the instruction to store the 2nd-13th bit of the offset of the target address relative to the address of the jump instruction, and the 0th bit and the 1st bit of the offset are omitted.

5. The method of claim 3, wherein, When the jump instruction is of type J, the immediate number field uses the 12th-31st bit of the instruction to store the 2nd-21st bit of the offset of the target address relative to the address of the jump instruction, and the 0th bit and the 1st bit of the offset are omitted.

6. The method according to one of claims 3 to 5, characterized in that The field of the 7th-31st bit of the R, I, S, and U type instructions is defined in accordance with the definition in the original RISC-V instruction set.

7. The method of claim 1, wherein, The modification of the RISC-V instruction set also includes, when N=2, combining the 1st-2nd bit and the 3rd-6th bit of the instruction to represent the types of a plurality of RV32I scalar instructions and the allocation positions on each VLIW instruction slot.

8. The method of claim 7, wherein, The types of the plurality of RV32I scalar instructions are defined according to the following table: Among them, NOP represents the null instruction, BRANCH represents the conditional branch type instruction of conditional jump, LUI represents the instruction of reading immediate number, LOAD represents the load instruction of loading data from memory to register, JAL represents the unconditional jump instruction, OP-UIMM represents the instruction with unsigned immediate number in the operand, STORE represents the instruction of writing data to memory, JALR represents the unconditional jump instruction with jump address in register, OP-IMM represents the instruction with signed immediate number in the operand, OP represents the instruction with all register operands, / represents the temporarily undefined spare field, and the spare field is used to define other instruction types.

9. The method of claim 1, wherein, The modification of the RISC-V instruction set also includes, when N=3, combining the 1st-3rd bit and the 4th-6th bit of the instruction to represent the types of a plurality of RV32I scalar instructions and the allocation positions on each VLIW instruction slot.

10. A RISC-V instruction set based processor, the processor supporting a modified RISC-V instruction set according to the method of any one of claims 1-8, and the processor being configured to: By reading the 0th bit of the instruction, a plurality of parallel instructions belonging to one VLIW instruction packet is determined, wherein, identify a first value of a 0th bit of an instruction as indicating that the instruction is part of a VLIW instruction packet with a next instruction, identify a second value of the 0th bit of an instruction as indicating that the instruction is an end position of a VLIW instruction packet when preceded by an instruction having the first value, and identify a plurality of parallel instructions of a VLIW instruction packet as including all instructions having the second value of the 0th bit and all instructions having the first value of the 0th bit that precede the instructions having the second value of the 0th bit; read 1st-Nth bits of each instruction of the plurality of parallel instructions to determine a VLIW instruction slot of each instruction, and in a same cycle, issue each instruction of the plurality of parallel instructions to a function unit that is pre-bound to a corresponding position of the VLIW instruction slot.

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