Processor scoreboard under VLIW architecture, processor and electronic equipment

Abstract

The invention provides a processor scoreboard under a VLIW architecture, a processor and electronic equipment, after entering a current clock period, a first scoreboard is used for writing risk information sent by an nth decoding slot and received in a previous clock period into an nth record entry in a target entry, and marking the nth record entry as a valid state; and after entering the current clock period, the first scoreboard is also used for moving the record entry in the effective state in the kth table entry to the corresponding record entry in the (k-1) th table entry and marking the record entry as the effective state. The execution cycle number of the pipelined instruction in the execution unit is dynamically represented through the table item number, the execution state of the instruction is efficiently tracked, the write-back information is dynamically updated, hardware logic is remarkably simplified, execution management of an indefinite cycle instruction and a pipelined instruction is supported, and hardware efficiency and instruction execution throughput are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor, in particular to a processor scoreboard under VLIW architecture, a processor and an electronic device. BACKGROUND

[0002] In computer processor architecture, Very Long Instruction Word (VLIW) is a kind of Explicit Parallel Instruction Computing (EPIC) architecture. Unlike traditional processors, VLIW architecture transfers the discovery and scheduling of instruction-level parallelism from hardware to compiler, and implements instruction-level parallelism by packing multiple instructions that can be executed in parallel into a very long instruction word at compile time.

[0003] In VLIW architecture, a very long instruction word corresponds to multiple operation slots, and each operation slot can independently execute a basic operation. These operation slots usually include integer operation units, floating point operation units, load / store units, branch jump units, etc.

[0004] Scoreboard technology is a kind of dynamic scheduling algorithm, which is used to track data dependencies between instructions and perform instruction scheduling. How to design a scoreboard that can run efficiently and accurately under VLIW architecture has become a difficult problem for those skilled in the art. SUMMARY

[0005] The purpose of the present application is to provide a processor scoreboard under VLIW architecture, a processor and an electronic device to improve the above problems.

[0006] In order to achieve the above purpose, the technical solutions adopted by the embodiments of the present application are as follows: In a first aspect, the embodiments of the present application provide a processor scoreboard under VLIW architecture, which comprises a first scoreboard, the first scoreboard comprises K+1 table entries, and each table entry comprises N record entries; After entering the current clock cycle, the first scoreboard is used to write the hazard information sent by the nth decoding slot received in the last clock cycle into the nth record entry in the target table entry, and mark it as valid; Wherein, the hazard information includes the execution period of microcode instruction, execution unit identifier, forwarding function identifier and destination register identifier, when the execution period of microcode instruction is X, the target table entry is the X+1 table entry, and X is less than or equal to K; After entering the current clock cycle, the first scoreboard is further configured to move a record entry in the kth entry in an active state to a corresponding record entry in the k-1th entry and mark the corresponding record entry as in the active state.

[0007] Optionally, the processor scoreboard further comprises a second scoreboard, and the second scoreboard comprises a state mark bit of each destination register. When it is determined that the microcode instruction corresponding to the ith record entry in the kth entry in the active state is an indefinite period instruction, the second scoreboard is further configured to modify the state mark bit of the destination register corresponding to the ith record entry in the kth entry to the occupied state; and the first scoreboard is further configured to erase the ith record entry in the kth entry. The second scoreboard is configured to modify the state mark bit of the destination register corresponding to the completed indefinite period instruction to the idle state when receiving the indefinite period instruction completion indication. The first scoreboard is configured to write the hazard information corresponding to the completed indefinite period instruction into the ith record entry in the first entry, where I represents the decoding slot number corresponding to the indefinite period instruction.

[0008] Optionally, after entering the current clock cycle, the first scoreboard is further configured to erase all the record entries in the first entry.

[0009] In a second aspect, an embodiment of the present application provides a processor under a VLIW architecture, which comprises N decoding slots, an execution unit, and the above-mentioned processor scoreboard. When the nth decoding slot obtains valid decoding information in the current clock, the nth decoding slot is configured to estimate whether the nth record entry in the target entry is in the occupied state in the next clock cycle and determine whether there is a hazard conflict. If the nth record entry in the target entry is in the idle state in the next clock cycle and there is no hazard conflict, the nth decoding slot is configured to send the valid decoding information to the back end for calling by the execution unit and send the hazard information in the valid decoding information to the first scoreboard.

[0010] Optionally, when the target entry is the k+1th entry, the nth decoding slot is configured to determine that the nth record entry in the target entry is in the idle state in the next clock cycle. When the target entry is the jth entry, the nth decoding slot is further configured to determine that the nth record entry in the jth entry is in the occupied state in the next clock cycle when the nth record entry in the j+1th entry in the current clock cycle is in the occupied state, and determine that the nth record entry in the jth entry is in the idle state in the next clock cycle when the nth record entry in the j+1th entry in the current clock cycle is in the idle state, where 2≤j≤K.

[0011] Optionally, the nth decoding slot is further configured to determine whether the source register and the destination register in the valid decoding information are the same as the occupied registers recorded in the processor scoreboard, and determine that there is an adventure conflict if there is any same.

[0012] Optionally, the nth decoding slot is further configured to determine whether the execution unit in the valid decoding information is the same as the occupied execution unit recorded in the processor scoreboard, and determine that there is an adventure conflict if they are the same.

[0013] Optionally, the execution unit is configured to send a first type of state modification instruction to a second scoreboard in the processor scoreboard and send an erase instruction to the first scoreboard when it is determined that the microcode instruction corresponding to the i-th record entry in the k-th table entry in the effective state is an indefinite period instruction. The second scoreboard is configured to modify the state flag corresponding to the destination register in the i-th record entry in the k-th table entry to the occupied state when the first type of state modification instruction is received. The first scoreboard is further configured to erase the i-th record entry in the k-th table entry when the erase instruction is received.

[0014] Optionally, the execution unit is configured to send an indefinite period instruction completion indication to the second scoreboard in the current clock cycle if the i-th record entry in the second table entry is in the idle state in the current clock cycle when the indefinite period instruction operation is completed. The second scoreboard is configured to modify the state flag of the destination register corresponding to the indefinite period instruction completion indication received in the last clock cycle to the idle state. The first scoreboard is configured to write the adventure information corresponding to the indefinite period instruction completion indication received in the last clock cycle into the i-th record entry in the first table entry, wherein I represents the decoding slot number corresponding to the indefinite period instruction.

[0015] In a third aspect, an embodiment of the present application provides an electronic device comprising the processor described above.

[0016] With respect to the prior art, the processor scoreboard under the VLIW architecture and the processor and the electronic device provided by the embodiment of the present application, the processor scoreboard comprises a first scoreboard, the first scoreboard comprises K+1 table entries, each table entry comprises N record entries, after entering a current clock cycle, the first scoreboard is used for writing the hazard information sent by an nth decoding slot received in a previous clock cycle into an nth record entry in a target table entry, and marking the nth record entry as an effective state, 1≤n≤N; wherein, the hazard information comprises an execution cycle of a microcode instruction, an execution unit identifier, a forwarding function identifier and a destination register identifier, when the execution cycle of the microcode instruction is X, the target table entry is an (X+1)th table entry, and X is less than or equal to K; after entering the current clock cycle, the first scoreboard is further used for moving the record entry in the kth table entry in the effective state to a corresponding record entry in a (k-1)th table entry, and marking the corresponding record entry as the effective state. The number of table entries is used to dynamically represent the number of execution cycles of the pipelined instruction in the execution unit. The design can efficiently track the execution state of the instruction and dynamically update the write-back information. This is the core of the scoreboard design, which significantly simplifies the hardware logic, supports the execution management of the indefinite period instruction and the pipelined instruction, and improves the hardware efficiency and the instruction execution throughput. The hazard information is managed by the first scoreboard, which is convenient, fast and accurate, and is beneficial to the efficient operation of the processor.

[0017] In order to make the above objectives, characteristics and advantages of the present application more apparent, the following preferred embodiments are specifically described below, and the accompanying drawings are referred to, and the detailed description is as follows. BRIEF DESCRIPTION OF DRAWINGS

[0018] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0019] Figure 1 One of the architecture schematic diagrams of the processor scoreboard provided by the embodiment of the present application.

[0020] Figure 2 The second architecture schematic diagram of the processor scoreboard provided by the embodiment of the present application.

[0021] Figure 3 The third architecture schematic diagram of the processor scoreboard provided by the embodiment of the present application.

[0022] Figure 4 The fourth architecture schematic diagram of the processor scoreboard provided by the embodiment of the present application. DETAILED DESCRIPTION

[0023] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present application with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only some but not all of the embodiments of the present application. The components of the embodiments of the present application described and shown in the drawings can be arranged and designed in various different configurations.

[0024] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of the application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work are within the scope of protection of the present application.

[0025] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second" and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0026] It should be noted that: similar reference numerals and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. Meanwhile, in the description of the present application, the terms "first", "second" and the like are only used to distinguish description, and cannot be understood as indicating or implying relative importance.

[0027] In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, or the orientation or positional relationship commonly placed when the product of the present application is used, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application.

[0028] In the description of the present application, it is also necessary to explain that, unless otherwise explicitly specified and limited, the terms "set", "connected" should be understood broadly, for example, can be fixedly connected, or can be detachably connected, or integrally connected; can be mechanically connected, or can be electrically connected; can be directly connected, or can be indirectly connected through an intermediate medium, or can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0029] Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The following examples and features in the examples can be combined with each other without conflict.

[0030] Please refer to Figure 1 and Figure 2 , Figure 1 one of the architecture schematic diagrams of the processor scoreboard provided by the embodiments of the present application, Figure 2 one of the architecture schematic diagrams of the processor scoreboard provided by the embodiments of the present application. The processor scoreboard under the VLIW architecture includes a first scoreboard (also referred to as a main scoreboard), the first scoreboard includes K+1 table entries (K is the maximum execution period of pipelined instructions), each table entry includes N groups of record entries, and N is the total number of decode slots in the processor.

[0031] In the drawings provided by the embodiments of the present application, K=2 and N equal to 4 are taken as examples for description, but this is not a limitation.

[0032] After entering the current clock cycle, the first scoreboard is used to write the hazard information sent by the nth decode slot received in the last clock cycle into the nth record entry in the target table entry, and mark it as an effective state, 1≤n≤N.

[0033] Among them, the hazard information includes the execution period of the microcode instruction decoded by the nth decode slot in the last clock cycle, the execution unit identifier, the forwarding function identifier (whether it has forwarding capability) and the destination register identifier, when the execution period of the microcode instruction is X, the target table entry is the X+1 table entry, and X is less than or equal to K.

[0034] Please refer to Figure 1 , the execution period in the hazard information sent by the third decode slot is 1, so the corresponding target table entry is the second table entry, the execution period in the hazard information sent by the first decode slot, the second decode slot and the third decode slot is 2, so the corresponding target table entry is the third table entry.

[0035] It should be noted that when the operation result corresponding to the microcode instruction has forwarding capability, the forwarding function identifier indicates that it can be forwarded, and when the operation result corresponding to the microcode instruction does not have forwarding capability, the forwarding function identifier indicates that it cannot be forwarded, for example, it is empty.

[0036] Optionally, when the nth decoding slot sends the hazard information in the previous clock cycle, it has already determined that in the next clock cycle (i.e., the current clock cycle), the nth record entry in the target table is in an idle state and there is no hazard conflict in the microcode instruction.

[0037] After entering the current clock cycle, the first scoreboard is also used to move the record entry that is in a valid state in the k-th entry to the corresponding record entry in the (k-1)-th entry and mark it as valid.

[0038] Optionally, a shift register is used to move the valid record entry in the k-th entry to the corresponding record entry in the (k-1)-th entry. The n-th record entry in the k-th entry corresponds to the n-th record entry in the (k-1)-th entry, where 2 ≤ k ≤ K+1. Optionally, the K entries can be moved simultaneously, or the movement can start from k=2 and continue until k=K+1.

[0039] like Figure 2 As shown, Figure 2 The corresponding previous clock cycle is Figure 1 As shown, in the current clock cycle, the valid record entries in the third entry can be moved to their corresponding entries in the second entry, and the valid record entries in the second entry can be moved to their corresponding entries in the first entry. Simultaneously, the hazard information received from the nth decoder slot in the previous clock cycle will be written to the nth record entry in the target entry. For example... Figure 2 In the previous clock cycle, the execution cycle corresponding to the hazard information sent by the nth decoding slot is 2, so it is written into the 4th record entry in the 3rd table.

[0040] In the processor scoreboard under the VLIW architecture provided in this embodiment of the invention, the number of cycles in which a pipelined instruction is executed in the execution unit is dynamically represented by the entry number. This design can efficiently track the execution status of instructions and dynamically update write-back information. This is the core of the scoreboard design, which significantly simplifies the hardware logic and supports the execution management of both indeterminate-cycle instructions and pipelined instructions, thereby improving hardware efficiency and instruction execution throughput. Managing hazard information through the first scoreboard is convenient, fast, and accurate, which is beneficial to the efficient operation of the processor.

[0041] Please refer to Figure 3 , Figure 3 This is the third schematic diagram of the processor scoreboard architecture provided in an embodiment of the present invention. Figure 3 As shown, the processor scoreboard also includes a second scoreboard (also known as an indefinite-cycle instruction scoreboard), which includes status flag bits for each destination register. Figure 3Take M destination registers as an example for description.

[0042] When it is determined that the microcode instruction corresponding to the i-th record entry in the k-th table entry in the active state is an indefinite period instruction, the second score board is further configured to modify the state mark bit corresponding to the destination register in the i-th record entry in the k-th table entry to the occupied state; and the first score board is further configured to delete (or modify to the invalid state) the i-th record entry in the k-th table entry, 1≤i≤N.

[0043] Please refer to Figure 4 , Figure 4 The fourth architecture schematic diagram of the processor score board provided by the embodiment of the present application. Figure 4 With Figure 2 The microcode instruction corresponding to the 2nd record entry in the 3rd table entry in the active state is an indefinite period instruction, for example. After the hazard information sent by the n-th decoding slot received in the last clock cycle is written into the n-th record entry in the target table entry, the first score board deletes (or modifies to the invalid state) the 2nd record entry in the 3rd table entry. The second score board is further configured to modify the state mark bit corresponding to the destination register in the 2nd record entry in the 3rd table entry to the occupied state.

[0044] In an optional implementation, the second score board is configured to modify the state mark bit of the destination register corresponding to the indefinite period instruction that has been completed to the idle state when receiving the indefinite period instruction completion indication.

[0045] The first score board is configured to write the hazard information corresponding to the indefinite period instruction that has been completed into the I-th record entry in the 1st table entry when receiving the indefinite period instruction completion indication, wherein I represents the decoding slot number corresponding to the indefinite period instruction.

[0046] In an optional implementation, after entering the current clock cycle, the first score board is further configured to delete (or modify to the invalid state) all the record entries in the 1st table entry. After deletion, the active record entries in the 2nd table entry can be moved to the 1st table entry, and the 1st table entry is deleted as the earliest action after the current clock cycle.

[0047] In the embodiment of the present application, the first score board (main score board) and the second score board (non-periodic instruction score board) work together to improve the instruction correlation detection capability. Specifically, the double-layer structure design of the main score board and the non-periodic instruction score board is adopted. When the instruction cannot be confirmed as a non-periodic instruction at the decoding time, it is first recorded in the main score board; after the execution stage is confirmed, it is transferred to the non-periodic instruction score board, and then returned to the main score board until the end of execution. This dynamic instruction life cycle management method realizes accurate detection of instruction correlation. The processing of non-periodic instructions is more flexible, effectively solving the execution delay problem caused by the inability to distinguish non-periodic instructions in the traditional scheme. It reduces the conflict risk of register resource occupation and optimizes the pipeline performance. It enhances the support capability of multi-instruction correlation detection and scheduling in the out-of-order execution scenario. It solves the problem of non-periodic instruction and pipeline instruction correlation detection, dynamically adjusts the instruction scheduling process, and reduces the performance loss caused by conflicts.

[0048] The embodiment of the present application also provides a processor under a VLIW architecture, which comprises N decoding slots, an execution unit and the processor score board.

[0049] When the nth decoding slot obtains valid decoding information at the current clock, the nth decoding slot is used to estimate whether the nth record entry in the target table entry is in an occupied state at the next clock period, and determine whether there is an adventure conflict (including read-after-write conflict, write-after-write conflict and execution unit conflict).

[0050] If the nth record entry in the target table entry is in an idle state at the next clock period, and there is no adventure conflict, the nth decoding slot is used to send the valid decoding information to the back end for calling by the execution unit, and send the adventure information in the valid decoding information to the first score board.

[0051] If the nth record entry in the target table entry is in an occupied state at the next clock period, or there is an adventure conflict, the nth decoding slot will not send the valid decoding information to the back end, nor send the adventure information in the valid decoding information to the first score board, and it needs to be cached until the corresponding condition is met.

[0052] Optionally, when the target table entry is the K+1 table entry, the nth decoding slot is used to determine that the nth record entry in the target table entry is in an idle state at the next clock period.

[0053] When the target entry is the jth entry, the nth decoding slot is further configured to determine that the nth record entry in the jth entry is in an occupied state in the next clock cycle when the nth record entry in the jth+1 entry in the current clock cycle is in the occupied state, and determine that the nth record entry in the jth entry is in an idle state in the next clock cycle when the nth record entry in the jth+1 entry in the current clock cycle is in the idle state, 2≤j≤K.

[0054] Optionally, the nth decoding slot is further configured to determine whether the source register and the destination register in the valid decoding information are the same as the occupied registers recorded in the processor scoreboard, and determine that there is an hazard conflict (read-after-write conflict or write-after-write conflict) if there is any same.

[0055] Optionally, the nth decoding slot is further configured to determine whether the execution unit in the valid decoding information is the same as the occupied execution unit recorded in the processor scoreboard, and determine that there is an hazard conflict (execution unit conflict) if the same.

[0056] In the embodiment of the present application, the number of register file read ports can be 8, but this structure can also be applicable to larger register file read ports such as 10, 12, etc. The number of register file write ports is 4, but this structure can also be applicable to larger register file read ports such as 6, 8, etc.

[0057] The processor provided by the embodiment of the present application can optimize the register conflict detection mechanism, and jointly judge the read-after-write conflict and the write-after-write conflict through the register numbers in the main scoreboard and the indefinite period instruction scoreboard. The mechanism of judging the register resource conflict based on the valid signal is adopted, and the new instruction can quickly judge whether there is a register conflict by querying the valid signal of the corresponding entry in the main scoreboard and the related information in the indefinite period instruction scoreboard. The number of pipeline stalls is reduced, and the instruction execution efficiency is improved. The performance loss caused by the register conflict is significantly reduced. The accuracy and real-time performance of instruction scheduling in out-of-order execution are improved.

[0058] In an optional implementation, the execution unit is configured to, when determining that the microcode instruction corresponding to the ith record entry in the kth entry in an effective state is an indefinite period instruction, send a first type of state modification instruction (specifically, send to the state flag bit corresponding to the destination register in the ith record entry in the kth entry) to a second scoreboard in the processor scoreboard, and send an erase instruction (including the identification of the ith record entry in the kth entry) to the first scoreboard.

[0059] The second scoreboard is configured to, when receiving the first type of state modification instruction, modify the state flag bit corresponding to the destination register in the ith record entry in the kth entry to the occupied state.

[0060] The first scoreboard is also configured to delete (or modify to an invalid state) the i-th record entry in the k-th table entry when a delete instruction is received.

[0061] Optionally, the execution unit is configured to, when the i-th record entry in the second table entry is in an idle state at a current clock cycle, send an indefinite period instruction completion indication (indicating that the operation result of the instruction has been obtained, but has not been written back to the corresponding destination register) to the second scoreboard at the current clock cycle when the indefinite period instruction operation is completed.

[0062] The second scoreboard is configured to modify the state flag bit of the destination register corresponding to the indefinite period instruction completion indication (the completed indefinite period instruction) received at the last clock cycle to an idle state.

[0063] The first scoreboard is configured to write the hazard information corresponding to the indefinite period instruction completion indication (the completed indefinite period instruction) received at the last clock cycle into the i-th record entry in the first table entry, wherein i represents the decode slot number corresponding to the indefinite period instruction.

[0064] Optionally, the processor under the VLIW architecture is provided with four decode slots, and the front-end module splits the VLIW into four microcode instructions and sends them to the corresponding decode slots.

[0065] The embodiment of the present application also provides an electronic device comprising the processor.

[0066] In summary, the processor scoreboard, the processor and the electronic device provided by the embodiment of the present application are described as follows: the processor scoreboard comprises a first scoreboard, the first scoreboard comprises K+1 table entries, each table entry comprises N record entries; after entering a current clock cycle, the first scoreboard is configured to write the hazard information sent by the n-th decode slot received at the last clock cycle into the n-th record entry in the target table entry and mark it as an effective state, 1≤n≤N; wherein the hazard information comprises an execution period of a microcode instruction, an execution unit identifier, a forwarding function identifier and a destination register identifier, when the execution period of the microcode instruction is X, the target table entry is the X+1 table entry, and X is less than or equal to K; after entering the current clock cycle, the first scoreboard is also configured to move the record entry in the k-th table entry in the effective state to the corresponding record entry in the k-1 table entry and mark it as an effective state. The number of table entries is used to dynamically represent the number of execution periods of the pipelined instruction in the execution unit. The design can efficiently track the execution state of the instruction and dynamically update the write-back information. This is the core of the scoreboard design, which significantly simplifies the hardware logic, supports the execution management of indefinite period instructions and pipelined instructions, and improves the hardware efficiency and the instruction execution throughput. The hazard information is managed by the first scoreboard, which is convenient, fast and accurate, and is beneficial to the efficient operation of the processor.

[0067] The above description is only preferred embodiments of the present application and is not intended to limit the present application. The present application can be variously changed and modified by those skilled in the art without departing from the spirit and principles of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principles of the present application should be included in the scope of the present application.

[0068] It will be apparent to those skilled in the art that the present application is not limited to the details of the foregoing exemplary embodiments, and that the present application can be carried out in other specific forms without departing from the spirit or essential characteristics of the present application. Thus, the present embodiments are to be considered in all respects as illustrative and not restrictive, the scope of the present application being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. No reference signs in the claims should be considered as limiting the scope of the claims in any way.

Claims

1. A processor scoreboard under a VLIW architecture, characterized in that, The processor scoreboard includes a first scoreboard, which includes K+1 entries, and each entry includes N sets of record entries. Upon entering the current clock cycle, the first scoreboard is used to write the hazard information received from the nth decoder slot in the previous clock cycle into the nth record entry in the target table and mark it as valid. The hazard information includes the execution cycle of the microcode instruction, the execution unit identifier, the forwarding function identifier, and the destination register identifier. When the execution cycle of the microcode instruction is X, the target entry is the (X+1)th entry, where X is less than or equal to K. After entering the current clock cycle, the first scoreboard is also used to move the record entry that is in a valid state in the k-th entry to the corresponding record entry in the (k-1)-th entry and mark it as valid.

2. The processor scoreboard under VLIW architecture as recited in claim 1, wherein, The processor scoreboard also includes a second scoreboard, which includes status flag bits for each destination register; When it is determined that the microcode instruction corresponding to the i-th record entry in the k-th entry is an indefinite periodic instruction, the second scoring board is also used to modify the status flag bit corresponding to the destination register in the i-th record entry in the k-th entry to the occupied state; the first scoring board is also used to erase the i-th record entry in the k-th entry. The second scoring board is used to modify the status flag bit of the destination register corresponding to the completed indefinite period instruction to the idle state when it receives the indefinite period instruction completion indication; The first scoreboard is used to write the hazard information corresponding to the completed indefinite periodic instruction into the I record entry in the first table entry, where I represents the decoding slot number corresponding to the indefinite periodic instruction.

3. The processor scoreboard under VLIW architecture as recited in claim 1, wherein, Upon entering the current clock cycle, the first scoreboard is also used to erase all entries recorded in the first table entry.

4. A processor under a VLIW architecture, characterized by, The processor includes N decoding slots, an execution unit, and a processor scoreboard as described in any one of claims 1-3; When the nth decoding slot obtains valid decoding information in the current clock, the nth decoding slot is used to estimate whether the nth record entry in the target table will be occupied in the next clock cycle, and to determine whether there is a risk conflict. If the nth record entry in the estimated target table is idle in the next clock cycle and there is no hazard conflict, the nth decoding slot is used to send the valid decoding information to the backend for the execution unit to call, and to send the hazard information in the valid decoding information to the first scoreboard.

5. The processor under VLIW architecture as recited in claim 4, wherein, The nth decoding slot is used to determine that the nth record entry in the target table is in an idle state in the next clock cycle when the target table entry is the (K+1)th table entry. When the target entry is the j-th entry, the n-th decoding slot is also used to determine that the n-th record entry in the j+1-th entry of the current clock cycle is occupied, and that the n-th record entry in the j-th entry is occupied in the next clock cycle; and when the n-th record entry in the j+1-th entry of the current clock cycle is idle, to determine that the n-th record entry in the j-th entry is idle in the next clock cycle, where 2≤j≤K.

6. The processor under VLIW architecture as recited in claim 4, wherein, The n-th decoding slot is further configured to determine whether the source register and the destination register in the valid decoding information are the same as the occupied registers recorded in the processor scoreboard, and if there is any same, it is determined that there is an adventure conflict.

7. The processor under VLIW architecture as recited in claim 4, wherein, The n-th decoding slot is further configured to determine whether the execution unit in the valid decoding information is the same as the occupied execution unit recorded in the processor scoreboard, and if the same, it is determined that there is an adventure conflict.

8. The processor under VLIW architecture as recited in claim 4, wherein, The execution unit is configured to send a first type of state modification instruction to a second scoreboard in the processor scoreboard and send an erase instruction to the first scoreboard when it is determined that the microcode instruction corresponding to the i-th record entry in the k-th table entry in the effective state is an indefinite period instruction. The second scoreboard is configured to modify the state flag corresponding to the destination register in the i-th record entry in the k-th table entry to the occupied state when the first type of state modification instruction is received. The first scoreboard is further configured to erase the i-th record entry in the k-th table entry when the erase instruction is received.

9. The processor under VLIW architecture as recited in claim 8, wherein, The execution unit is configured to send an indefinite period instruction completion indication to the second scoreboard in the current clock cycle when the i-th record entry in the second table entry is in the idle state in the current clock cycle after the indefinite period instruction operation is completed. The second scoreboard is configured to modify the state flag of the destination register corresponding to the indefinite period instruction completion indication received in the last clock cycle to the idle state. The first scoreboard is configured to write the adventure information corresponding to the indefinite period instruction completion indication received in the last clock cycle into the i-th record entry in the first table entry, wherein I represents the decoding slot number corresponding to the indefinite period instruction.

10. An electronic device, comprising: The processor according to any one of claims 4-9.

Images