Access latency acquisition method and electronic device

Abstract

The disclosure provides a memory access latency acquisition method and an electronic device, and relates to the technical field of communication. A target memory region corresponding to a cache of a processor is divided, and a region set is acquired. The length of each region in the region set is the same as the cache line size of the processor. An integer array corresponding to the region set is randomized, and a random linked list corresponding to the region set is acquired. A loop traversal memory access operation is performed on the random linked list, and traversal information is acquired. The traversal information includes a traversal duration, a traversal frequency, and a number of traversal nodes corresponding to the random linked list. The memory access latency corresponding to the cache of the processor is acquired according to the traversal information. The generality and portability of the memory access latency acquisition can be improved, and the convenience and accuracy of the memory access latency acquisition can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of communication technology, and in particular to a method for obtaining memory access latency and an electronic device. Background Technology

[0002] With the development of science and technology, the requirements for storage and servers in the fields of big data and artificial intelligence (AI) are becoming increasingly demanding, and the performance of storage and servers is constantly improving. Among these, memory performance has a critical impact on the overall system performance. Latency parameters are an important measure of memory performance. For example, latency can be obtained by setting the corresponding low-level instruction code of the Central Processing Unit (CPU). However, different CPU architectures require different low-level instruction codes, resulting in architecture-specific dependencies, poor portability, and limited ease of obtaining memory access latency. Summary of the Invention

[0003] This disclosure provides a method and electronic device for obtaining memory access latency. Its main purpose is to solve the problem that different CPU architectures require different underlying CPU instruction codes, resulting in dependency on specific CPU architectures, poor portability, and thus poor convenience in obtaining memory access latency.

[0004] According to a first aspect of this disclosure, a method for obtaining memory access latency is provided, comprising:

[0005] The target memory region corresponding to the processor's cache is divided to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor;

[0006] Randomize the integer array corresponding to the region set to obtain a random linked list corresponding to the region set;

[0007] The random linked list is traversed and memory accessed in a loop to obtain traversal information, wherein the traversal information includes traversal duration, traversal count and the number of traversed nodes corresponding to the random linked list;

[0008] Based on the traversal information, the memory access latency corresponding to the processor's cache is obtained.

[0009] According to a second aspect of this disclosure, a memory access latency acquisition apparatus is provided, comprising:

[0010] The set acquisition unit is used to divide the target memory region corresponding to the processor's cache and acquire a region set, wherein the length of each region in the region set is the same as the size of the processor's cache line;

[0011] The linked list acquisition unit is used to randomize the integer array corresponding to the region set and obtain the random linked list corresponding to the region set.

[0012] The linked list traversal unit is used to perform a loop traversal memory access operation on the random linked list to obtain traversal information, wherein the traversal information includes traversal duration, traversal count and the number of traversal nodes corresponding to the random linked list;

[0013] The memory access latency acquisition unit is used to acquire the memory access latency corresponding to the processor's cache based on the traversal information.

[0014] According to a third aspect of this disclosure, an electronic device is provided, comprising:

[0015] At least one processor; and

[0016] A memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect above.

[0018] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in the first aspect above.

[0019] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0020] This disclosure involves dividing the target memory region corresponding to the processor's cache to obtain a region set, wherein the length of each region in the region set is the same as the size of the processor's cache line; randomizing the integer array corresponding to the region set to obtain a random linked list; performing a loop traversal memory access operation on the random linked list to obtain traversal information, wherein the traversal information includes traversal duration, traversal count, and the number of traversed nodes corresponding to the random linked list; and obtaining the memory access latency corresponding to the processor's cache based on the traversal information. Therefore, by constructing a random linked list and looping through it, the memory access latency corresponding to the processor's cache can be obtained without setting different CPU underlying instruction codes for different CPU architectures. This reduces dependence on specific CPU architectures and reduces the limitation of memory access latency application scenarios due to poor portability of CPU underlying instruction codes. Furthermore, it reduces the probability of hitting accessed cache lines and CPU prefetched cache lines, improving the universality and portability of memory access latency acquisition, and enhancing the convenience and accuracy of memory access latency acquisition.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0022] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0023] Figure 1 A flowchart illustrating a method for obtaining memory access latency provided in an embodiment of this disclosure;

[0024] Figure 2 A schematic diagram illustrating another method for obtaining memory access latency provided in this embodiment of the present disclosure;

[0025] Figure 3 A flowchart illustrating a memory access latency acquisition method provided in an embodiment of this disclosure;

[0026] Figure 4 This is a schematic diagram illustrating an example of an integer array provided in an embodiment of this disclosure;

[0027] Figure 5 This is an example schematic diagram of a processed integer array provided in an embodiment of the present disclosure;

[0028] Figure 6 This is a schematic diagram of a memory access latency acquisition device provided in an embodiment of the present disclosure. Detailed Implementation

[0029] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0030] The memory access latency acquisition method and electronic device of the present disclosure are described below with reference to the accompanying drawings.

[0031] Figure 1 This is a flowchart illustrating a method for obtaining memory access latency provided in an embodiment of this disclosure. Figure 1 As shown, the method includes the following steps:

[0032] Step 101: Divide the target memory region corresponding to the processor's cache to obtain a region set, wherein the length of each region in the region set is the same as the size of the processor's cache line.

[0033] According to some embodiments, the implementing entity of this disclosure may be, for example, an electronic device. The name of the electronic device is not limited. The electronic device does not specifically refer to a particular fixed device. For example, when the structure of the electronic device changes, the electronic device may also change accordingly. For example, when the device identifier of the electronic device changes, the electronic device may also change accordingly.

[0034] In some embodiments, the processor cache may be a processor-specific cache, such as the CPU cache. The processor cache does not specifically refer to a single, fixed cache. For example, when the processor changes, the processor cache may also change accordingly.

[0035] According to some embodiments, the target memory region may be, for example, a memory region requested for the processor's cache. The name of the target memory region is not limited. For example, the target memory region may also be called a memory region, a requested memory region, etc. The target memory region does not specifically refer to a fixed area. For example, when the size of the target memory region changes, the target memory region may also change accordingly. For example, when the processor's cache changes, the target memory region may also change accordingly.

[0036] According to some embodiments, a set of regions can be, for example, a collection of at least one region. This set of regions does not specifically refer to a fixed set. For example, the set of regions can change when the number of regions changes. Similarly, the set of regions can change when the length of each region in the set changes.

[0037] In some embodiments, the length of each region in the region set is the same as the size of the processor's cache line.

[0038] According to some embodiments, the target memory region corresponding to the processor's cache can be divided to obtain a region set, wherein the length of each region in the region set is the same as the size of the processor's cache line.

[0039] Step 102: Randomize the integer array corresponding to the region set to obtain the random linked list corresponding to the region set;

[0040] According to some embodiments, the randomized linked list may be a linked list obtained by randomly processing a set of regions. This randomized linked list does not specifically refer to a fixed linked list. For example, the randomized linked list may change accordingly when the randomization method changes. For example, the randomized linked list may change accordingly when the set of regions changes. For example, the randomized linked list may change accordingly when the algorithm used for randomization changes.

[0041] According to some embodiments, the integer array corresponding to the region set is randomized to obtain the random linked list corresponding to the region set.

[0042] Step 103: Perform a loop traversal memory access operation on the random linked list to obtain traversal information, including traversal duration, number of traversals, and number of traversal nodes corresponding to the random linked list.

[0043] In some embodiments, memory access operations can, for example, traverse nodes in a random linked list, and read memory regions based on the addresses corresponding to each node. The memory access operation involving traversing the random linked list can be performed once or multiple times; this disclosure does not limit this.

[0044] In some embodiments, the traversal information may be information obtained during a circular traversal and memory access operation on a random linked list. This traversal information does not specifically refer to any fixed information. For example, the traversal information may change if the type of information it includes changes. Similarly, the traversal information may change if the number of pieces of information corresponding to the traversal information changes. Furthermore, the traversal information may change if the memory access operation changes.

[0045] In some embodiments, a random linked list can be traversed and accessed in memory to obtain traversal information, which includes traversal duration, number of traversals, and number of traversed nodes corresponding to the random linked list.

[0046] According to some embodiments, the traversal duration can be, for example, the total time corresponding to the circular traversal and memory access operations on a random linked list. This traversal duration is not specifically a fixed duration. The traversal duration can also change when the specific value corresponding to it changes. For example, the traversal duration can also change when the traversal and memory access operations change.

[0047] In some embodiments, the number of traversals can be, for example, the number of memory access operations performed on the random linked list. For instance, it could be the number of times the random linked list has been traversed.

[0048] According to some embodiments, the number of nodes traversed corresponding to the random linked list may be, for example, the total number of nodes accessed when performing a circular traversal memory access operation on the random linked list.

[0049] Step 104: Based on the traversal information, obtain the memory access latency corresponding to the processor's cache.

[0050] In some embodiments, memory access latency can be, for example, a memory access latency parameter, which can be, for example, the time required to access memory. The memory access latency corresponding to the processor's cache can be obtained based on the traversal information.

[0051] This disclosure involves dividing the target memory region corresponding to the processor's cache to obtain a region set, where the length of each region in the region set is the same as the size of the processor's cache line; randomizing the integer array corresponding to the region set to obtain a random linked list; performing a loop traversal of the random linked list to obtain traversal information, including traversal duration, number of traversals, and the number of traversed nodes in the random linked list; and obtaining the memory access latency corresponding to the processor's cache based on the traversal information. Therefore, by constructing a random linked list and looping through it, the memory access latency corresponding to the processor's cache can be obtained without setting different CPU underlying instruction codes for different CPU architectures. This reduces dependence on specific CPU architectures and mitigates the limitations imposed by poor portability of CPU underlying instruction codes on memory access latency application scenarios. Furthermore, it reduces the probability of hitting already accessed cache lines and CPU prefetched cache lines, improving the universality and portability of memory access latency acquisition, and enhancing the convenience and accuracy of memory access latency acquisition.

[0052] Furthermore, in one possible implementation of this embodiment, Figure 2 This is a flowchart illustrating another method for obtaining memory access latency provided in an embodiment of this disclosure. Figure 2 As shown, the method includes the following steps:

[0053] Step 201: Divide the target memory region corresponding to the processor's cache to obtain a region set, wherein the length of each region in the region set is the same as the size of the processor's cache line.

[0054] The relevant processes can be as described above, and will not be repeated here.

[0055] In some embodiments, the memory access latency acquisition method of this disclosure can be applied to the performance evaluation and optimization of system platforms.

[0056] In some embodiments, the processor cache is a L3 cache, and the method further includes the following steps before partitioning the target memory region corresponding to the processor cache:

[0057] Based on the memory size corresponding to the processor's L3 cache, allocate a target memory region, where the size of the target memory region is greater than the memory size.

[0058] In some embodiments, the processor's cache may be, for example, the CPU cache, and a memory region, i.e., the target memory region, much larger than the CPU cache can be requested. The L3 cache may be, for example, a cache architecture within the CPU, which may be integrated onto the CPU chip. The CPU's L3 cache is not specifically defined as a fixed cache. For example, when the size of the memory corresponding to the CPU's L3 cache changes, the CPU's L3 cache may also change accordingly. Similarly, when the CPU itself changes, its L3 cache may also change accordingly.

[0059] According to some implementations, a memory region much larger than the CPU cache can be requested; specifically, it can be at least several times the total size of the CPU's Level 3 (L3) cache. For system platforms with a Non-Uniform Memory Access (NUMA) architecture, both the memory region and the CPU performing the memory access test need to specify their respective NUMA nodes. This is because cross-NUMA memory access latency and local memory access latency can differ significantly due to the distance between NUMA nodes; therefore, specifying the NUMA node can improve the accuracy of memory access latency acquisition.

[0060] Step 202: Randomize the integer array corresponding to the region set to obtain the random linked list corresponding to the region set;

[0061] The relevant processes can be as described above, and will not be repeated here.

[0062] According to some embodiments, for example, the Knuth shuffle algorithm can be used to randomize the integer array corresponding to the region set to obtain a random linked list corresponding to the region set. The Knuth shuffle algorithm can be called the Knuth shuffle algorithm.

[0063] In some embodiments, the integer array corresponding to the region set is randomized to obtain a random linked list corresponding to the region set, including:

[0064] Obtain the index number corresponding to each region in the region set according to the address order;

[0065] Based on the index number of each region, obtain the integer array corresponding to the region set;

[0066] Randomizing the integer array yields a random linked list corresponding to the region set. Therefore, obtaining the random linked list using an index and an integer array improves the accuracy of random linked list retrieval and memory access latency estimation.

[0067] According to some embodiments, the index number can be used to mark different regions, and different regions can correspond to different index numbers. The index number does not specifically refer to a fixed index number. For example, when the region changes, the index number can also change accordingly. For example, when the composition of the index number changes, the index number of each region can also change accordingly.

[0068] According to some embodiments, the memory region address is aligned to CPU cache lines (e.g., 64 bytes) and divided into small regions according to the CPU cache line size. The length of each small region is equal to the CPU cache line size. Each small region has a corresponding index number in address order, and the address of each small region can be calculated using the index number. According to some embodiments, Figure 3 This is a flowchart illustrating a method for obtaining memory access latency provided in an embodiment of this disclosure. Figure 3 As shown, the index number of the first small region is idx=1, and its address is equal to the starting address m_addr of the entire memory region (target memory region) requested; the index number of the second small region is idx=2, and its address is m_addr+Cache_Line, where Cache_Line represents the size of the CPU cache line, that is, the length of the small region; the index number of the third small region is idx=3, and its address is m_addr+2*Cache_Line; the index number of the j-th small region is idx=j, and its address is m_addr+(j-1)*Cache_Line.

[0069] Each small region of memory can be constructed as a node in a linked list, as defined below:

[0070] struct node {

[0071] struct node *next_node;

[0072] bytepad[Cache_Line - sizeof(struct node *)];

[0073] },

[0074] Here, `next_node` represents the address of the next sub-region in the linked list, and `pad` is used for byte padding. Therefore, accessing each sub-region can be done, for example, by reading the `next_node` field of each sub-region.

[0075] In some embodiments, the integer array is randomized to obtain a random linked list corresponding to the region set, including:

[0076] Iterate through the integer array starting from the first element, and randomly select the second element corresponding to the first element from the integer array, where the first element is the last element of the integer array;

[0077] If the second element satisfies the element requirements, the first and second elements are swapped.

[0078] After processing the first element, the third element in the integer array is randomized until all elements in the integer array are randomized, resulting in a random linked list corresponding to the region set. The third element is the element preceding the first element. Therefore, by randomizing each element, the accuracy of obtaining the random linked list and the accuracy of memory access latency can be improved. Furthermore, the judgment of the second element reduces the need to swap elements that have already been processed, further improving the accuracy of obtaining the random linked list.

[0079] According to some embodiments, the first element may be, for example, the last element of the integer array, and the second element may be, for example, an element randomly selected from the integer data corresponding to the first element. That is, the second element is an element randomly selected from the integer array excluding the first element. This second element is not a fixed element; for example, when the random selection method changes, the second element may also change accordingly.

[0080] According to some embodiments, the element requirement may be, for example, a requirement on whether to swap the first element and the second element. This element requirement may be, for example, that a randomly selected element lies between the starting element and the first element of the integer array. If the second element satisfies the element requirement (i.e., the second element is between the starting element and the first element of the integer array), then the first and second elements can be swapped. If the second element does not satisfy the element requirement (i.e., the second element is not between the starting element and the first element of the integer array), then the first and second elements may not be swapped, and the second element can be obtained again.

[0081] According to some embodiments, the third element may be, for example, the element preceding the first element. The third element is used to distinguish the other elements and does not specifically refer to a certain fixed element.

[0082] In some embodiments, the method further includes:

[0083] After the randomization operation on the integer array is completed, obtain the number of swapped elements in the integer array.

[0084] If the number of swapped elements matches the number of elements in the integer array, it is confirmed that all elements in the integer array have been randomized. Therefore, this improves the accuracy of randomized list retrieval, reduces the probability of elements not being randomized, and enhances the accuracy of memory access latency estimation.

[0085] According to some embodiments, the index numbers of each small region can be stored sequentially in an integer array idx_array[N]. The contents of array idx_array[N] could be, for example, as follows: Figure 4 As shown. The integer array can be, for example, a data structure, and does not specifically refer to a fixed array. The integer array can be, for example, a set of integers, where each integer can be, for example, an element of the array. The integer array can be, for example, composed of at least one element. For example, when the number of elements in the integer array changes, the integer array can also change accordingly.

[0086] Specifically, randomizing idx_array using the classic Gartner shuffle algorithm can include:

[0087] 1) Start traversing from the last element of idx_array and move backward to the second element;

[0088] 2) For the current element idx_array[i], randomly select an idx_array[j] such that 0 <= j <= i; then swap the values ​​of idx_array[i] and idx_array[j].

[0089] 3) Continue processing the previous element until the second element of idx_array has been processed. The processed integer array can be, for example, as shown below. Figure 5 As shown. Here, rand_i, rand_j, rand_p ... rand_k, rand_m ... can be the index numbers of the regions shuffled by the Gartner shuffle algorithm.

[0090] In some embodiments, the integer array is randomized to obtain a random linked list corresponding to the region set, including:

[0091] Randomize the integer array and obtain the processed integer array;

[0092] Based on the index number of the region corresponding to each position in the processed integer array, obtain the address of the region corresponding to each position;

[0093] The addresses are converted, linked list nodes are constructed, and these nodes are inserted into a random linked list. Therefore, a random linked list can be obtained from the processed integer array, improving the accuracy of random linked list retrieval, reducing the probability of hitting previously accessed cache lines and CPU-prefetched cache lines during memory access, and improving the accuracy of memory access latency estimation.

[0094] According to some embodiments, the process of constructing a linked list can be, for example, traversing the array idx_array, converting the address of each small region based on its index number, and then constructing the memory of each small region as a linked list node and inserting them one by one into the linked list. The specific process is as follows:

[0095] We can select the small region with index idx = rand_i, whose address is m_addr + (rand_i - 1) * Cache_line. We perform a type cast on this address, construct a `struct node` structure for the linked list defined above, and insert it into the linked list as the head node. Then, we select the small region with index idx = rand_j, whose address is m_addr + (rand_j - 1) * Cache_line. We perform a type cast on this address, construct a linked list node, and insert it into the linked list. We can process `rand_p`, ..., `rand_k`, `rand_m` one by one and insert them into the linked list. Finally, a linked list with randomized addresses is generated, i.e., a randomized linked list is obtained.

[0096] Step 203: Perform a loop traversal memory access operation on the random linked list to obtain traversal information, including traversal duration, number of traversals, and number of traversal nodes corresponding to the random linked list.

[0097] The relevant processes can be as described above, and will not be repeated here.

[0098] In some embodiments, performing a circular traversal memory access operation on a random linked list includes:

[0099] Read the pointer information in the random linked list each time a memory access operation is performed by looping through the random linked list;

[0100] Based on the pointer information, the random linked list is traversed. Therefore, since the next node of each node in the linked list is random, each memory access operation reduces the probability of hitting previously accessed cache lines and CPU prefetched cache lines, requiring each memory access to read from memory, which improves the accuracy of memory access latency estimation.

[0101] The memory access operation involves traversing the nodes in the linked list. When accessing these small areas, only one read operation is required. For example, only the next pointer can be read, which may be 4 or 8 bytes.

[0102] In some embodiments, the method further includes:

[0103] The number of iterations is determined based on the latency precision information corresponding to the processor's cache. Therefore, the matching between latency precision information and iteration count can be improved, thus increasing the accuracy of iteration count acquisition and memory access latency acquisition.

[0104] According to some embodiments, the delay precision information does not specifically refer to a fixed piece of information. For example, when a modification instruction for the delay precision information is received, the delay precision information may also change accordingly. For example, when the precision value corresponding to the delay precision information changes, the delay precision information may also change accordingly. For instance, a higher delay precision information may correspond to a greater number of traversals.

[0105] In some embodiments, the number of traversals can also be determined based on a number setting instruction.

[0106] Step 204: Based on the number of traversals and the number of traversed nodes corresponding to the random linked list, obtain the total number of traversed nodes corresponding to the cyclic traversal memory access operation of the random linked list.

[0107] The relevant processes can be as described above, and will not be repeated here.

[0108] In some embodiments, the number of nodes traversed can be, for example, the number of nodes traversed in one random linked list. This number of nodes is not specifically a fixed number. When the specific value corresponding to this number of nodes changes, the number of nodes traversed can also change accordingly.

[0109] According to some embodiments, the total number of nodes traversed can be, for example, the total number of nodes traversed during the entire process of performing a circular traversal memory access operation on a random linked list. This total number of nodes traversed is not specifically a fixed number. For example, the total number of nodes traversed can also change when the number of traversals changes. For example, the total number of nodes traversed can also change when the number of traversed nodes corresponding to the random linked list changes.

[0110] In some embodiments, the total number of nodes traversed for a random linked list during a cyclic traversal memory access operation is obtained based on the number of traversals and the number of traversed nodes corresponding to the random linked list.

[0111] Step 205: Based on the traversal time and the total number of nodes, obtain the memory access latency corresponding to the processor's cache.

[0112] The relevant processes can be as described above, and will not be repeated here.

[0113] In some embodiments, the memory access latency corresponding to the processor's cache is obtained based on the traversal time and the total number of nodes.

[0114] According to some implementations, a total time can be obtained by iterating through a random linked list constructed using a shuffling algorithm, i.e., the traversal time. The memory access latency is equal to the total time divided by the number of nodes traversed. For example, if the number of nodes traversed in the random linked list is N, the number of iterations is M, and the total time is t, then the memory access latency is t / (N*M).

[0115] In one or related embodiments, the total number of nodes traversed corresponding to the random linked list memory access operation is obtained based on the number of traversals and the number of traversed nodes corresponding to the random linked list; the memory access latency corresponding to the processor's cache is obtained based on the traversal duration and the total number of nodes. Therefore, by traversing the random linked list, the probability of hitting accessed cache lines and CPU prefetched cache lines can be reduced, reducing dependence on CPU architecture and exhibiting good versatility and portability.

[0116] According to embodiments of this disclosure, this disclosure also provides a memory access latency acquisition device.

[0117] For example, Figure 6 This is a schematic diagram of a memory access latency acquisition device provided in an embodiment of the present disclosure. The memory access latency acquisition device 600 includes: a set acquisition unit 601, a linked list acquisition unit 602, a linked list traversal unit 603, and a memory access latency acquisition unit 604; wherein...

[0118] The set acquisition unit 601 is used to divide the target memory region corresponding to the processor's cache and acquire a region set, wherein the length of each region in the region set is the same as the size of the processor's cache line.

[0119] The linked list acquisition unit 602 is used to randomize the integer array corresponding to the region set and acquire the random linked list corresponding to the region set.

[0120] The linked list traversal unit 603 is used to perform a cyclic traversal memory access operation on the random linked list to obtain traversal information, including traversal duration, number of traversals and number of traversal nodes corresponding to the random linked list.

[0121] The memory access latency acquisition unit 604 is used to acquire the memory access latency corresponding to the processor's cache based on the traversal information.

[0122] Furthermore, the processor's cache is a level 3 cache, and the set acquisition unit 601 is used, specifically, before partitioning the target memory region corresponding to the processor's cache, for:

[0123] Based on the memory size corresponding to the processor's L3 cache, allocate a target memory region, where the size of the target memory region is greater than the memory size.

[0124] Furthermore, the linked list traversal unit 603, used for performing circular traversal and memory access operations on the random linked list, is specifically used for:

[0125] Read the pointer information in the random linked list each time a memory access operation is performed by looping through the random linked list;

[0126] Based on the pointer information, traverse the random linked list.

[0127] Furthermore, the linked list acquisition unit 602 is used to randomize the integer array corresponding to the region set, and specifically to acquire the random linked list corresponding to the region set.

[0128] Obtain the index number corresponding to each region in the region set according to the address order;

[0129] Based on the index number of each region, obtain the integer array corresponding to the region set;

[0130] Randomize the integer array to obtain the random linked list corresponding to the region set.

[0131] Furthermore, the linked list acquisition unit 602 is used to randomize the integer array and acquire the random linked list corresponding to the region set, including:

[0132] Iterate through the integer array starting from the first element, and randomly select the second element corresponding to the first element from the integer array, where the first element is the last element of the integer array;

[0133] If the second element satisfies the element requirements, the first and second elements are swapped.

[0134] After the first element has been processed, the third element in the integer array is randomized until all elements in the integer array have been randomized. The random linked list corresponding to the region set is obtained, where the third element is the previous element adjacent to the first element.

[0135] Furthermore, the linked list retrieval unit 602 is also used for:

[0136] After the randomization operation on the integer array is completed, obtain the number of swapped elements in the integer array.

[0137] If the number of swapped elements is the same as the number of elements in the integer array, then all elements in the integer array have been randomized.

[0138] Furthermore, the linked list acquisition unit 602 is used to randomize the integer array and, specifically, to acquire the random linked list corresponding to the region set.

[0139] Randomize the integer array and obtain the processed integer array;

[0140] Based on the index number of the region corresponding to each position in the processed integer array, obtain the address of the region corresponding to each position;

[0141] The addresses are converted, linked list nodes are constructed, and the linked list nodes are inserted into a random linked list.

[0142] Furthermore, the linked list traversal unit 603 is also specifically used for:

[0143] The number of iterations is determined based on the latency precision information corresponding to the processor's cache.

[0144] Furthermore, the memory access latency acquisition unit 604 is used to acquire the memory access latency corresponding to the processor's cache based on the traversal information, specifically for:

[0145] Based on the number of traversals and the number of traversed nodes corresponding to the random linked list, obtain the total number of traversed nodes corresponding to the cyclic traversal and memory access operation of the random linked list;

[0146] Based on the traversal time and the total number of nodes, obtain the memory access latency corresponding to the processor's cache.

[0147] It should be noted that the description of the features in the embodiment corresponding to the memory access latency acquisition device can be found in the relevant description of the embodiment corresponding to the memory access latency acquisition method, and will not be repeated here.

[0148] Embodiments of this disclosure also provide an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to perform the steps in any of the above embodiments of the memory access latency acquisition method.

[0149] Embodiments of this disclosure also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above embodiments of the memory access latency acquisition method when it is run.

[0150] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0151] The embodiments of this disclosure also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above embodiments of the memory access latency acquisition method.

[0152] Embodiments of this disclosure also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps in any of the above-described memory access latency acquisition method embodiments.

[0153] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this disclosure.

[0154] The foregoing has provided a detailed description of a method for obtaining memory access latency. Specific examples have been used to illustrate the principles and implementation methods of this disclosure. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and its core ideas. It should be noted that those skilled in the art can make various improvements and modifications to this disclosure without departing from its principles, and these improvements and modifications also fall within the protection scope of the claims of this disclosure.

Claims

1. A method for obtaining memory access latency, characterized in that, include: The target memory region corresponding to the processor's cache is divided to obtain a region set, wherein the length of each region in the region set is the same as the cache line size of the processor; Randomize the integer array corresponding to the region set to obtain a random linked list corresponding to the region set; The random linked list is traversed and memory accessed in a loop to obtain traversal information, wherein the traversal information includes traversal duration, traversal count and the number of traversed nodes corresponding to the random linked list; Based on the traversal information, obtain the memory access latency corresponding to the processor's cache; The randomization process of the integer array to obtain the random linked list corresponding to the region set includes: Starting from the first element of the integer array, traverse the array and randomly select the second element corresponding to the first element, where the first element is the last element of the integer array. If the second element satisfies the element requirements, the first element and the second element are swapped. After the first element has been processed, the third element in the integer array is randomized until all elements in the integer array have been randomized, and a random linked list corresponding to the region set is obtained, wherein the third element is the previous element adjacent to the first element; The step of obtaining the memory access latency corresponding to the processor's cache based on the traversal information includes: Based on the number of traversals and the number of traversed nodes corresponding to the random linked list, obtain the total number of traversed nodes corresponding to the cyclic traversal memory access operation of the random linked list. Based on the traversal time and the total number of nodes, the memory access latency corresponding to the processor's cache is obtained.

2. The method according to claim 1, characterized in that, The processor's cache is a level 3 cache. Before partitioning the target memory region corresponding to the processor's cache, the method further includes: Based on the memory size corresponding to the processor's L3 cache, the target memory region is requested, wherein the size of the target memory region is greater than the memory size.

3. The method according to claim 1, characterized in that, The step of performing a circular traversal and memory access operation on the random linked list includes: In each instance of performing a loop traversal and memory access operation on the random linked list, the pointer information in the random linked list is read; Based on the pointer information, the random linked list is traversed.

4. The method according to claim 1, characterized in that, The step of randomizing the integer array corresponding to the region set to obtain the random linked list corresponding to the region set includes: Obtain the index number corresponding to each region in the region set according to the address order; Based on the index number corresponding to each region, obtain the integer array corresponding to the region set; Randomize the integer array to obtain a random linked list corresponding to the region set.

5. The method according to claim 1, characterized in that, The method further includes: Once the randomization operation on the integer array is completed, obtain the number of swapped elements corresponding to the integer array; If the number of swapped elements is the same as the number of elements in the integer array, then all elements in the integer array have been randomized.

6. The method according to claim 4, characterized in that, The randomization process of the integer array to obtain the random linked list corresponding to the region set includes: The integer array is randomized to obtain the processed integer array; Based on the index number of the region corresponding to each position in the processed integer array, obtain the address of the region corresponding to each position; The address is converted, a linked list node is constructed, and the linked list node is inserted into the random linked list.

7. The method according to claim 1, characterized in that, The method further includes: The number of iterations is determined based on the latency precision information corresponding to the processor's cache.

8. An electronic device, characterized in that, include: processor; Memory used to store the processor's executable instructions; The processor is configured to execute the instructions to implement the memory access latency acquisition method as described in any one of claims 1 to 7.

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