Multi-core processor system-oriented formal verification system

Abstract

The invention discloses a formalized verification system for a multi-core processor system. The formalized verification system comprises a state extraction module, a verification attribute extraction module, a functional model construction module and a formalized verification module. According to the method, verification personnel are helped to exclude non-ideal parts in a circuit through an error occurrence point of a counter-example precise positioning system, and model detection has the advantages of high automation degree, capability of generating a counter example and support of full-state space search, so that the method is most suitable for function and safety verification in an integrated circuit design stage and targeted positioning of a necessary state; and carrying out simplified model construction on the functional model. According to the automatic method, the problem of state explosion of a traditional cache consistency verification method is relieved to a great extent, verification attributes are simplified through attribute extraction, and the time overhead of the verification process is effectively reduced.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of multi-core processors, and particularly relates to a formal verification system for a multi-core processor system. BACKGROUND

[0002] With the popularization of related applications such as big data, artificial intelligence and cloud computing, computer technology has made a qualitative leap, and CPU, as the core of various computers, is also undergoing rapid development. However, the access speed of the memory cannot match the high speed of the CPU for a long time. In order to solve the problem of imbalance between the speed of the memory and the CPU, a multi-core shared cache structure emerges as the times require.

[0003] The multi-core shared cache processor system has multiple CPU cores, and the data of the cache connects the CPU core and the memory. While having the advantages of fast processing speed, high resource utilization and low power consumption, the multi-core processor system also faces serious resource conflicts and resource pollution problems, so the industry has begun to research the functional verification of the cache design.

[0004] The traditional simulation-based verification method has high time cost and cannot achieve full coverage of functions, and is not suitable for complete verification of the multi-core shared cache design. The formal verification method is a verification method based on mathematical reasoning, which can cover all reachable states of integrated circuits and fully guarantee the functional correctness of the system. SUMMARY

[0005] The purpose of the application is to solve the above-mentioned problems, and provide a formal verification system for a multi-core processor system to complete the formal verification problem.

[0006] The technical scheme adopted by the application is as follows:

[0007] A formal verification system for a multi-core processor system comprises a state extraction module, a verification attribute extraction module, a functional model construction module, a formal verification module and a to-be-tested circuit standard database.

[0008] The to-be-tested circuit standard database contains the behavior-level circuit source code of the to-be-tested circuit, and the to-be-tested circuit refers to a multi-core processor to-be-tested circuit, wherein the multi-core processor to-be-tested circuit comprises n processor cores, and the processor core is a core function description of the behavior-level circuit source code.

[0009] The state extraction module extracts the state from the behavior-level circuit source code of the to-be-tested circuit and sends the valid state data to the functional model construction module.

[0010] The verification property extraction module extracts the to-be-verified properties from the behavior-level circuit source code of the to-be-tested circuit, converts the to-be-verified properties into a verification language format according to the language requirement of the function model construction module, generates a to-be-verified property library after the conversion, and sends the to-be-verified property library to the formal verification module;

[0011] The function model construction module receives the effective state data sent by the state extraction module, performs formal processing on the data to generate a function model, sends the function model to the formal verification module, and sends the language requirement to the verification property extraction module;

[0012] The formal verification module receives the function model sent by the function model construction module and the to-be-verified property library of the verification property extraction module, performs passability verification of the to-be-verified property library on the function model, and presents the verification result in a visual form. When an unexpected result occurs, the problem can be located manually.

[0013] Further, the state extraction module comprises a to-be-tested circuit state machine generation module and a redundant state removal module.

[0014] The to-be-tested circuit state machine generation module performs formal state extraction on the behavior-level source code of the to-be-tested circuit, extracts the states of all functional registers, and numbers the states;

[0015] The redundant state removal module filters all states, analyzes all functional registers according to the logic of the to-be-tested circuit, only retains the effective states related to the to-be-tested function, and sends the finally retained effective state data to the function model construction module.

[0016] Further, the functional register refers to a register corresponding to each functional component in the to-be-tested circuit.

[0017] Further, the verification property extraction module comprises a verification property generation module and a formal language adaptation module.

[0018] The verification property generation module generates verification logic by matching the to-be-tested circuit and the to-be-verified function. The formal language adaptation module ensures that the verification logic adapts to the language requirement sent by the function model construction module, then converts the formal verification language of the function point through logical analysis, and sends the finally generated verification property library to the formal verification module.

[0019] Further, the formal verification language conversion specifically refers to converting natural language into formal verification language.

[0020] Further, the function model construction module comprises an effective state recombination module and a state transition condition generation module.

[0021] The effective state reorganization module receives the effective state data sent by the state extraction module, reorganizes the effective state data after logical analysis, generates a formal model with different functional states, and sends the formal model to the formal verification module; the state transition condition generation module matches the transition conditions between states according to the effective states, that is, language requirements, and sends the language requirements to the formal verification module in the format of a formal language.

[0022] Further, the definition of the formal model is that the formal model is an abstract model based on mathematical symbols and logical rules.

[0023] Further, the formal verification module comprises a pass verification module and an counterexample positioning module.

[0024] The pass verification module verifies the pass of different verification attributes on the formal model with the transition conditions, which represents whether the function meets the expectations of the verification personnel; the counterexample positioning module performs positioning analysis on the attributes that fail to pass the verification, and specifically locates the error state or the error state transition condition.

[0025] Further, n is greater than or equal to 4.

[0026] Further, the circuit to be tested is an RTL circuit.

[0027] As described above, due to the adoption of the technical solutions, the present application has the following beneficial effects:

[0028] 1. In the present application, the verification method with simple entry and strong robustness, that is, model detection, is selected, so that the verification personnel can master the verification method and verification skills in a short time to verify the model, and the verification method is most suitable for the functional and safety verification in the integrated circuit design stage.

[0029] 2. In the present application, a formal verification system capable of directly analyzing the RTL circuit description file is proposed, and the necessary state is targeted and positioned to construct a simplified model of the functional model. This automatic method can first construct a formal model of cache coherence in an automatic form by analyzing the behavior characteristics of the code, and generate a model interface and a verification interface in the verification tool UPPAAL, so that the user can perform positive and negative bidirectional verification on the system according to the verification requirements, effectively reducing the modeling difficulty and improving the modeling efficiency.

[0030] 3. In the present application, the extraction technology based on the verification attribute is researched, the verification attribute to be verified is simplified, the problem of traditional verification attribute description is solved, the verification efficiency is greatly improved, and the cache coherence is accurately and completely verified at a high level through the generation of counterexamples. BRIEF DESCRIPTION OF DRAWINGS

[0031] Figure 1A structural schematic diagram of the present application;

[0032] Figure 2 A theorem proving flow in the present application;

[0033] Figure 3 A key variable behavior tracking schematic diagram in the present application;

[0034] Figure 4 An automatic modeling flow of a parent circuit module in the present application;

[0035] Figure 5 A logic language reduction table in the present application. DETAILED DESCRIPTION

[0036] The verification method proposed by the present application can directly analyze the behavior level circuit file, and the modeling manner is different from that of only analyzing the register unit in the net list file, so that the original function behavior information of the circuit is retained, and the method is also applicable to the combination logic. The present application performs logic analysis on the behavior level circuit by taking the to-be-verified function as a guide, realizes function type construction based on the behavior level circuit, effectively reduces the modeling difficulty, and improves the modeling efficiency.

[0037] As shown in Figure 1 , the present application proposes a formal verification system for a multi-core processor, which comprises a state extraction module, a verification attribute extraction module, a function model construction module, a formal verification module and a to-be-tested circuit standard database.

[0038] The to-be-tested circuit standard database contains the behavior level circuit source code of the to-be-tested circuit, and the to-be-tested circuit refers to a multi-core processor to-be-tested circuit, wherein the multi-core processor to-be-tested circuit comprises n processor cores, and the processor core is the core function description of the behavior level circuit source code; (n≥4, the to-be-tested circuit is an RTL circuit)

[0039] The state extraction module extracts the state from the behavior level circuit source code of the to-be-tested circuit, and sends the effective state data to the function model construction module.

[0040] The verification attribute extraction module extracts the to-be-verified attribute from the behavior level circuit source code of the to-be-tested circuit, converts the to-be-verified attribute into a verification language format according to the language requirement of the function model construction module, generates a to-be-verified attribute library after the conversion, and sends the to-be-verified attribute library to the formal verification module;

[0041] The function model construction module receives the effective state data sent by the state extraction module, performs formal processing on the data to generate a function model, sends the function model to the formal verification module, and sends the language requirement to the verification attribute extraction module.

[0042] The formal verification module receives the functional model sent by the functional model construction module and the to-be-verified attribute library of the verification attribute extraction module, performs passability verification of the to-be-verified attribute library on the functional model, and presents the verification result in a visual form, and when an unexpected result occurs, the problem can be located by manual operation.

[0043] Further, the state extraction module comprises a generating to-be-tested circuit state machine and a redundant state removal module.

[0044] The generating to-be-tested circuit state machine performs formal state extraction on the behavior level source code of the to-be-tested circuit, extracts the states of all functional registers and numbers the states.

[0045] The redundant state removal module screens all states, analyzes all functional registers according to the logic of the to-be-tested circuit, only retains the effective states related to the to-be-tested function, and sends the finally retained effective state data to the functional model construction module. The functional register refers to the register corresponding to each functional component in the to-be-tested circuit.

[0046] Further, the verification attribute extraction module comprises a verification attribute generation module and a formal language adaptation module.

[0047] The verification attribute generation module generates verification logic by matching the to-be-tested circuit and the to-be-verified function; the formal language adaptation module ensures that the verification logic adapts to the language requirement sent by the functional model construction module, then converts the formal verification language of the function point through logical analysis, and sends the finally generated verification attribute library to the formal verification module. The formal verification language conversion specifically refers to converting natural language into formal verification language.

[0048] Further, the functional model construction module comprises an effective state recombination module and a state transition condition generation module.

[0049] The effective state recombination module receives the effective state data sent by the state extraction module, recombines the effective state data after logical analysis, generates a formal model with different functional states, and sends the formal model to the formal verification module; the state transition condition generation module matches the transition conditions between states according to the effective states, that is, the language requirements, and sends the language requirements to the formal verification module in the format of formal language. The definition of the formal model: the formal model is an abstract model based on mathematical symbols and logical rules.

[0050] Further, the formal verification module comprises a pass verification module and an counterexample positioning module; the pass verification module verifies the pass of different verification attributes on the formal model with transition conditions, representing whether the function meets the expectation of the verification personnel; the counterexample positioning module performs positioning analysis on the attributes that fail to pass the verification, and specifically positions to an error state or an error state transition condition.

[0051] Embodiments

[0052] The formal verification system for the multi-core processor system comprises a state extraction module, a verification attribute extraction module, a function model construction module, a formal verification module and a to-be-tested circuit standard database.

[0053] The to-be-tested circuit standard database contains the behavior-level circuit source code of the to-be-tested circuit, and the to-be-tested circuit refers to a multi-core processor to-be-tested circuit, wherein the multi-core processor to-be-tested circuit comprises n processor cores, and the processor core is a core function description of the behavior-level circuit source code.

[0054] The state extraction module and the function model construction module of the application comply with the following process: behavior-level module information analysis, tracking of effective states and transition conditions according to key signals, and standardized output (as shown in Figure 2 ).

[0055] Firstly, module information analysis, due to the complexity of the integrated circuit system, the application will screen the circuit according to the function information of the system, and only retain the part related to the function verification requirement for model construction, so as to improve the efficiency of subsequent verification. In the sequential logic circuit, the names S1 and S2 of the state signals before and after the timing sequence need to be determined, wherein the signal S1 represents the state before the logic action jump, and the signal S2 represents the state after the jump.

[0056] Secondly, key signal tracking, in the RTL-level circuit, the signals S1 and S2 are the key signals affecting the multi-core shared cache coherence, and the circuit behavior will be tracked below. The main idea of this part is to screen the states and conditions related to the key signals, and only take the S1 and S2 signal names and the initial code as the input to complete the construction of the formal model, and the steps are as follows: (as shown in Figure 3 ).

[0057] 1. Traverse all the signal S2 assignment statements in the dcache code, i.e. the cache line signal jump statements, and sequentially mark the line numbers, and create a signal jump statement line number list sig2_line = [], and then sequentially perform the following operations on all S2 assignment statements.

[0058] ②Judge whether the assigned statement is in the conditional judgment if or else if loop statement, that is, traverse all the statements with "if" and "endif" in the code, mark the line number, and create the if statement line list if_line = [] and the begin statement line list if_begin_line = [] and the end statement line list if_end_line = [] corresponding thereto.

[0059] ③Judge whether the assigned statement is in the conditional judgment case loop statement, that is, traverse all the statements with "case" and "endcase" in the code, mark the line number, and create the case statement line list case_line = [] and the endcase statement line list endcase_line = [].

[0060] ④Select the minimum effective code segment, create the list mapping relationship of ② and ③, and mark the code segment. As known, a begin must correspond to an end, and each case under the conditional judgment statement has its corresponding endcase. Therefore, if_begin_line and if_end_line have a one-to-one corresponding pair, the entire code is divided into several assignment statement code segments by the begin and end, but if there is a nested if statement, the end list is used to reversely map the if list to accurately divide the assignment statement code segment: that is, as long as the S2 assignment statement appears in any one-to-one relationship of the begin and end, the conditional statement segment is set as an effective code segment. Similarly, case_line and endcase_line are also the same, and the corresponding effective code segment can also be screened out. Due to the occurrence of the conditional nesting relationship, all the effective code segments appearing above take the maximum value, that is, the minimum union of all the effective code segments is screened out, and the minimum union first line to the S2 assignment statement appearing part is selected, which is called the minimum effective code segment.

[0061] ⑤Delete unnecessary conditions, only select relevant condition lines, and further refine and simplify. From ④, for all possible conditions of the S2 assignment statement, they have all appeared in the minimum effective code segment, and the top-level condition is the first condition of the effective code segment. To filter out unnecessary conditions, it is necessary to observe from the S2 assignment statement whether there is an end statement. If there is, it means that the condition line of the if statement to which the end statement belongs is an unnecessary condition line. If there are n end statements, it means that n unnecessary conditions need to be filtered out. As for the case statement, on the basis of filtering out unnecessary case statements, it is also necessary to filter out unnecessary case judgment statements, as shown in the figure, that is, only value2 is selected as the necessary condition, and value1 needs to be filtered out.

[0062] The last step of formal modeling is to normalize the output, as shown in Figure 4 After the above operations are completed, the system obtains a plurality of S2 assignment statements and the necessary conversion condition statements corresponding thereto, at which time the normalization output of the finite state machine is required. The finite state machine is composed of three parts: the initial state, the end state, and the specific condition that can generate transformation. The output format adopted by the present application is:

[0063] S1-->S2::C1::C2::…::Cn

[0064] Where S1 represents the initial state, that is, the state before the logical jump; S2 represents the end state, that is, the state after the logical jump; C1, C2, …, Cn represent the conversion conditions, and each condition is a parallel “and” relationship. In Figure 2 the example, it can be known that the initial state of the state transition is state1, the end state is state2, and the conversion conditions are: A == value2 and condition1, so the output of the state transition should be:

[0065] state1-->state2::A==value2::condition1

[0066] However, in the related conditions of part of the S2 assignment statement, there is no statement containing the S1 state before the jump, which means that no matter what the initial state is, when it satisfies the related conditions of the assignment statement, the end state is the assigned state. When the initial state is the assigned state itself, the conversion condition and the end state are also the same. Therefore, for any S2 assignment statement, one or more state transition statements as shown in the above formula can be obtained. By traversing all S2 assignment statements in the RTL code and outputting line by line according to the format, the normalized finite state machine model can be obtained.

[0067] For the verification system, the verification property is the direct influencing factor of whether the system can meet the verification requirement. The verification property extraction module includes a verification property generation module and a formal language adaptation module. The verification property generation module generates verification logic by matching the circuit under test and the function to be verified. The formal language adaptation module ensures that the verification logic adapts to the language requirement sent by the function model construction module, then converts the formal verification language of the function point through logical analysis, and sends the finally generated verification property library to the formal verification module, as shown in Figure 5 .

[0068] The formal verification module receives the function model sent by the function model construction module and the verification property library of the verification property extraction module, and implements the passability verification of the verification property library on the function model. The verification result is presented in a visual form. When unexpected results occur, problem positioning can be performed manually.

[0069] The formal verification module includes a passability verification module and a counterexample positioning module. The passability verification module verifies the passability of different verification properties on the formal model with transition conditions, which represents whether the function meets the expectations of the verification personnel. The counterexample positioning module performs positioning analysis on the properties that do not pass the verification, and specifically locates the error state or error state transition condition.

[0070] The verification property extraction process mainly includes two parts: writing natural language according to the verification target and writing formal language adapted by the verification tool according to the natural language. Finally, a verification property library is generated, as shown in Figure 5 . The properties in it are divided into five types, corresponding to five formal language forms. The property library describes the verification property from five aspects of reachability, determinacy, invariance, consistency and directionality. The basic formula of the formal language based on CTL (Computation Tree Logic) is as follows:

[0071] A[]Process.state1

[0072] A<>Process.state1

[0073] E[]Process.state1

[0074] E<>Process.state1

[0075] Process.state1-->Process.state2

[0076] Wherein A represents all paths, E represents the existence of a path, [] represents all states on the path, < > represents a future state, Process represents a model, state1 and state2 represent a state in a model, and --> represents the logic state of "lead to". The logic language expression equivalent to --> is A [] (Process.state1 imply A <> Process.state2).

[0077] For the formal verification system of the present application, the method of verifying all state transition jump cases one by one is low in efficiency. In order to improve the verification efficiency, the present application intends to adopt a "white list" verification strategy guided by the verification target. First, the verification target is classified and the core behavior characteristics are analyzed in depth, and then multiple verification attribute "white lists" are created according to the specific behaviors of the functions: if the system can realize correct state jump under certain conditions, it means that the model meets the function, and its expression form is:

[0078] (ProcessA.state1 and condition1)-->ProcessA.state2

[0079] Wherein ProcessA represents the model to be verified, state1 represents the initial state, state2 represents the end state, and condition1 represents the transition condition. The meaning of this verification statement is: if the condition satisfies condition1, then state state1 can be transferred to state state2 at a future time.

[0080] The present application can automatically generate a functional model detection interface by analyzing the underlying logic of the UPPAAL model, based on the verification model that can be recognized by the automatic generation tool of RTL hardware language.

[0081] In the modeling process of the first part, the present application has obtained the normative state transition file, and on this basis, it is converted into a model language xml that can be recognized by the tool, and the conversion process is as follows:

[0082] ① All parameters need to be declared first, written into <declaration>Part. The parameter refers to all the conditional statements appear to be judged signal name: for example, the content of condition1 is data1 == = 1, then need to declare int data1 in the parameter declaration.

[0083] ② For all states to declare the position, write <location>Part. Since the tool is visualized, the state needs to be located in the xml modeling language first, in order to avoid the graphical interface being too cluttered, the application will determine the total number of states and open the direction to the nearest state position: for example, there are 4 states, and each state position is placed in the form of equidistant 2*2; if there are 8 states, each position is placed in the form of equidistant 3*3, and the last position is a blank position.

[0084] ③ read each state transition row of the state transition file in turn, and write <transition>Part. According to the name, the initial condition and the end condition consistent with ② are selected, the directed connection processing is performed, and the transition condition is added into the "guard" content.

[0085] The parts not described in detail in the present application are well known to those skilled in the art.< / transition> < / location> < / declaration>

Claims

1. A formal verification system for a multi-core processor system, the system comprising: The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system.

2. The formal verification system for multi-core processor system according to claim 1, wherein: The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system.

3. The formal verification system for multi-core processor system of claim 2, wherein: The application relates to a multi-core processor test circuit formal verification system.

4. The formal verification system for multi-core processor system of claim 1, wherein: The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system.

5. The formal verification system for multi-core processor system according to claim 4, wherein: The application relates to a multi-core processor test circuit formal verification system.

6. The formal verification system for multi-core processor system of claim 4, wherein: The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to a multi-core processor test circuit formal verification system. The application relates to 7. The formal verification system for a multi-core processor system according to claim 6, wherein: The definition of the formal model: the formal model is an abstract model based on mathematical symbols and logical rules.

8. The formal verification system for multi-core processor system of claim 6, wherein: The formal verification module comprises a pass verification module and a counterexample positioning module. The pass verification module verifies the pass of different verification attributes on the formal model with transition conditions, which represents whether the function meets the expectations of the verification personnel; the counterexample positioning module performs positioning analysis on the attributes that fail to pass the verification, and specifically positions to an error state or an error state transition condition.

9. The formal verification system for multi-core processor system of claim 1, wherein: n is greater than or equal to 4.

10. The formal verification system for multi-core processor system of claim 1, wherein: The circuit to be tested is an RTL circuit.

Images