Dynamic erasing balance method and system of embedded Flash memory

Abstract

The invention discloses a dynamic erasing balance method and a dynamic erasing balance system for an embedded Flash memory, which are used for realizing efficient and balanced use of Flash memory through virtual address mapping, a binary search algorithm and a CRC7 (Cyclic Redundancy Check 7) verification technology. The system comprises a storage management module, an initialization module, a write-in control module and an erasure management module, has the advantages of prolonging the service life of Flash, improving data reliability, optimizing storage performance and the like, and is particularly suitable for embedded application scenes needing to frequently update small data volume.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of embedded system storage technology, in particular to a dynamic erase-write balancing method and system for embedded Flash memory. BACKGROUND

[0002] In embedded systems, Flash memory is the preferred medium for storing critical parameters and data due to its non-volatility, low power consumption, and high reliability. However, there are two inherent characteristics that limit its use: first, each memory cell has a limited number of erase-write cycles, typically around 100,000, beyond which the memory cell will fail; second, Flash must perform erase operations in blocks or pages (typically 512B-4KB in size), and data can only be written after erasing. These characteristics pose significant challenges in practical applications. Traditional storage methods typically use fixed address mapping, repeatedly erasing and writing to the same physical address, which leads to rapid wear-out of frequently updated data regions (such as system configuration parameters), while other regions are underutilized, forming a "hot spot" problem. Statistics show that this uneven wear can reduce the lifespan of local memory cells to 1 / 100 of their theoretical value.

[0003] Existing wear leveling techniques can be divided into three categories: dynamic address mapping, wear monitoring, and region rotation. Dynamic address mapping algorithms achieve balance by maintaining a mapping table of logical addresses to physical addresses, but require additional storage space (typically 5-10% of capacity) to save the mapping relationship, and may have inconsistent mapping tables in the event of unexpected power loss. Wear monitoring methods record the number of erase-write cycles for each block to allocate write locations, but require real-time updates to the count information, increasing write overhead. Region rotation techniques divide the storage area into multiple regions for cyclic use, which is simple to implement but cannot avoid local wear within the region. More importantly, existing solutions have three common problems: first, the check mechanism is weak, with most using simple checksum or parity checks that cannot detect multiple-bit errors; second, storage efficiency is low, with some algorithms requiring more than 30% of the space as a buffer; finally, the implementation complexity is high, requiring the processor to frequently intervene in address translation and state maintenance, which is difficult to apply in resource-constrained embedded environments. In addition, existing solutions lack support for cross-page writing and exception handling, requiring application programs to manually split when writing data across Flash page boundaries, increasing development complexity. These deficiencies severely restrict the application of wear leveling technology in low-cost embedded systems. SUMMARY

[0004] In view of the problems existing in the prior art, the present application proposes an innovative dynamic erase-write balancing method that achieves efficient and balanced use of Flash memory through virtual address mapping, CRC checking, and optimized binary search. The specific method is as follows:

[0005] Step 1, dynamic mapping of virtual address to physical address.

[0006] Step 2, locate the free block using binary search algorithm; divide the storage space into equal length units, each unit contains data area and address area, search from the starting position of the storage space, determine the unit state by comparing the unit header mark, 0xFFFF indicates free, use binary search to quickly locate the first free unit.

[0007] Step 3, use CRC7 data algorithm for verification; use x 7 +x 3 +1 polynomial to calculate CRC checksum value, initial value uses 0x95, byte by byte XOR, mix data by byte and CRC register, bit processing loop, after each bit left shift, if the highest bit is 1, XOR the polynomial, finally shift the mask, right shift 1 bit and mask 0x7F.

[0008] Step 4, automatic cross-page writing processing; first calculate the page boundary of the data span, then write the data in different pages in segments, and finally automatically process the page boundary alignment.

[0009] A kind of embedded Flash memory's erase-write balancing system is composed of storage structure management module, write control module, data verification module, space recycling module, the specific functions of each module are as follows: storage structure management module: define and manage the data structure containing the following fields: Variable size (var_size) Address field size (var_addrsize) Flash page size (page_size) Starting address (addr_s) and total capacity (capcity) Erase function pointer (pfuncErase) Write function pointer (pfuncWrite) Write control module, execute the following steps: Receive virtual address and data to be written, use binary search algorithm to locate writable physical address, calculate data CRC checksum value and combine with virtual address, handle cross-page writing situation, mark the used storage unit. Data verification module: use improved algorithm to verify the stored data, and store the high bit of the verification value and the virtual address. Space recycling module: when the storage space is exhausted, perform a whole erase operation.

[0010] The beneficial effects of the present application: the present application balances the distribution of write operation, so that the write operation is not concentrated on some storage units, avoiding excessive erasing and writing, which can effectively prolong the service life of the Flash. The address mark and CRC double-checking mechanism are used to ensure the integrity of the data and improve the data reliability. Through the compact storage structure design, the additional overhead is only 5% in the case of realizing the above functions, and the storage efficiency is high. The binary search algorithm makes the time complexity of the idle position search O(logn), which is high in search efficiency and good in real-time performance. And it supports variable size configuration and cross-page writing to adapt to different application scenarios. BRIEF DESCRIPTION OF DRAWINGS

[0011] Fig. 1 is a write data flowchart of the present application;

[0012] Fig. 2 is a CRC check calculation flowchart of the present application; DETAILED DESCRIPTION

[0013] Embodiment 1

[0014] As Figs. 1-2 shown, in order to better illustrate the present application, the present application is implemented in the STM32 series MCU, and the initial configuration is as follows: page size 2KB, variable size 32 bytes, address field size 2 bytes, and total capacity 64KB.

[0015] The write process includes: calling the virtual address mapping balanced write algorithm to perform data writing, the virtual address mapping balanced write algorithm mainly includes the following functions: (1) dynamic address mapping (virtual address→physical address); (2) data integrity check (CRC7); (3) cross-page write support; (4) wear leveling control.

[0016] The system finds the idle position by binary search, and the core idea of finding the position is: 1) using binary search to find the first idle block: in the Flash storage area, searching for the first unoccupied storage unit (i.e. the unit with address mark 0xFFFF) from the low address to the high address, ensuring that the write operation always uses the lowest address idle block first, thereby realizing balanced wear. 2) logical index conversion: the returned is a logical index number, not a physical address, and the actual physical address calculation formula is: physical address = start address + index number × (data size + address mark size).

[0017] Calculate the data CRC check value: use x 7+x 3 +1 polynomial to calculate CRC check value, the specific implementation steps are as follows: (1) initial value 0x95, 0x95 and the bit pattern of polynomial 0x09 are complementary, which enhances the error detection capability, in addition, the initial value 0x95 (10010101) is right shifted by 1 bit to become 0x4A (01001010), and the lower 7 bits are still 0x4A, this feature can adjust the bit sequence or alignment mode of the CRC value, and optimize the generation process of the CRC value. (2) byte by byte XOR, the data is mixed with the CRC register by byte; (3) bit processing loop, after each bit left shift, if the highest bit is 1, then XOR the polynomial; (4) final shift mask, right shift 1 bit and mask 0x7F.

[0018] Combine the CRC value and the virtual address to write in the address area

[0019] Write in the data area, automatically handle the cross-page case

[0020] The reading process adopts the reverse search strategy: (1) scan from the end of the storage area to the front; (2) match the virtual address; (3) check the CRC value; (4) return the first data version that passes the check.

[0021] Although the specific embodiments of the present application are described in detail above, the present application is not limited to the above embodiments, within the knowledge range of ordinary skilled in the art, various changes can be made without departing from the purpose of the present application, and the modifications or deformations without creative labor are still within the protection range of the present application.

Claims

1. A method for dynamic erase-write balancing of embedded Flash memory, comprising: The method comprises the following steps: Step 1, dynamic mapping of virtual address to physical address; Step 2, locating the free block by using binary search algorithm; Step 3, checking by using CRC7 data algorithm; Step 4, automatic cross-page writing processing.

2. The method for balancing dynamic erase-write of embedded Flash memory according to claim 1, wherein: The binary search algorithm for locating the free block comprises the following steps: Step 5, dividing the storage space into equal-length units, each unit comprising a data area and an address area; Step 6, starting searching from the starting position of the storage space; Step 7, judging the unit state by comparing the unit header mark, 0xFFFF indicating free; Step 8, using binary method to quickly locate the first free unit.

3. The method of claim 1, wherein: the embedded Flash memory is a NAND Flash memory. The CRC7 data algorithm comprises the following steps: Step 9, using the 0x09 polynomial of the CRC-7 standard to calculate the CRC check value, the initial value being 0x95; Step 10, byte-by-byte XOR, mixing the data with the CRC register by byte; Step 11, bit processing loop, after each bit left shift, if the highest bit is 1, then XOR the polynomial; Step 12, final shift mask, right shift 1 bit and mask 0x7F.

4. The method for dynamic erase / write balancing of an embedded Flash memory according to claim 1, characterized in that: The automatic cross-page writing comprises the following steps: Step 13, calculating the page boundary crossed by the data; Step 14, segmented writing of the data in different pages; Step 15, automatically processing the page boundary alignment.

5. An embedded Flash dynamic erase balancing system using the embedded Flash dynamic erase balancing method of claim 1, wherein: The method comprises a storage structure management module, a writing control module, a data checking module and an erasing management module; The storage structure management module defines and manages the data structure, the writing control module writes data into the storage unit, the data checking module checks the stored data, the high bits of the check value are combined with the virtual address for storage, and the erasing management module performs the whole-plate erasing operation when the storage space is exhausted.

6. The system for balancing dynamic erase-write of an embedded Flash memory according to claim 5, wherein: The storage structure management module comprises the following field data structure: variable size, address field size, Flash page size, starting address and total capacity, erasing function pointer and writing function pointer.

7. The system for balancing dynamic erase-write of an embedded Flash memory according to claim 5, wherein: The writing control module performs the following steps: receiving the virtual address and the data to be written; locating the writable physical address by using the binary search algorithm; calculating the data CRC check value and combining it with the virtual address; processing the cross-page writing condition; and marking the used storage unit.

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