Inter-chip communication bus interface and communication system

Abstract

This invention provides an inter-chip communication bus interface and a communication system. The data channel of this inter-chip communication bus interface includes a cascaded first register slice and a second register slice. The first register slice is coupled to a master device. Both the first and second register slices contain at least one stage of data register circuitry. Each stage of the data register circuitry is used to transmit multiple bits of data signal in parallel after completing the handshake of the handshake signal pair in the data channel. The first stage of the data register circuitry in the first register slice with the shortest signal path to the master device is de-driven by the handshake signal sent by the master device in the handshake signal pair. The remaining stages of the data register circuitry in the second register slice and / or the first register slice are all driven by the handshake signal pair. By reducing the driving force of one handshake signal, the timing pressure of the communication handshake in the data channel is reduced, which is beneficial for achieving timing convergence.

Description

Technical Field

[0001] This invention relates to the field of communication technology, and in particular to an inter-chip communication bus interface and communication system. Background Technology

[0002] In digital systems across various fields such as consumer electronics, data centers, automotive electronics, and industrial applications, suitable inter-chip communication bus interfaces, such as AXI (Advanced eXtensible Interface), are commonly used to achieve inter-chip communication and data transmission between two devices. Each channel of these bus interfaces typically uses a handshake signal pair (e.g., a valid signal and a ready signal) to control the two devices on the bus to perform high-speed and reliable addressing and data transmission according to the bus protocol. The device initiating data transmission uses one handshake signal (e.g., the valid signal) to indicate when the data is valid, and the receiving device generates another handshake signal (e.g., the ready signal) to indicate that it is ready to receive data. When both are high, data transmission is initiated.

[0003] Currently, in data transmission applications with large data bit widths, how to reduce the timing pressure of inter-chip handshake communication and achieve timing convergence to support high-speed synchronous transmission of large data bit widths between chips and ensure the accuracy and stability of data is one of the hot issues that urgently need to be solved by those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide an inter-chip communication bus interface and communication system that can reduce the timing pressure of inter-chip communication handshake, complete timing convergence, support large data bit width, high-speed synchronous inter-chip data transmission, and ensure data accuracy and stability.

[0005] To achieve the above objectives, the present invention provides an inter-chip communication bus interface, which is coupled between a master device and a slave device and has at least one data channel. The data channel has a cascaded first register slice and a second register slice. The first register slice is coupled to the master device. Both the first register slice and the second register slice have at least one level of data register circuit. Each level of the data register circuit is used to transmit multiple bits of data signal in parallel after completing the handshake of the handshake signal pair in the data channel.

[0006] In this case, the first-level data register circuit in the first register slice with the shortest signal path to the master device is removed from the handshake signal pair sent by the master device to the first register slice. The remaining data register circuits in the second register slice and / or the first register slice are all driven by the handshake signal pair.

[0007] Optionally, each stage of the data register circuit includes multiple parallel data register branches, each data register branch is configured to correspond one-to-one with each bit of the data signal, and is driven by the handshake signal pair or one of the handshake signals in the handshake signal pair.

[0008] Optionally, each handshake signal in the handshake signal pair is a single-bit signal, and the handshake signal pair synchronously drives the multiple parallel data register branches corresponding to the same level of the data register circuit.

[0009] Optionally, each of the data register branches includes combinational logic and a one-bit data register coupled to the combinational logic, and the handshake signal synchronously drives the combinational logic in the multiple parallel data register branches corresponding to the same level of the data register circuit.

[0010] Optionally, the first register slice is a forward register slice, a backward register slice, or a bidirectional register slice, and the second register slice is a forward register slice, a backward register slice, or a bidirectional register slice; wherein, the forward register slice has a forward register circuit, the backward register slice has a backward register circuit, and the bidirectional register slice is composed of a combination of a forward register circuit and a backward register circuit.

[0011] Optionally, the at least one data channel includes a write data channel for transmitting the multi-bit data signal from the master device to the slave device after completing the handshake of the handshake signal pair in its channel; and in the first register slice of the write data channel, the first-level data register circuit with the shortest signal path to the master device is located in the forward register circuit of the first register slice and is de-driven by the handshake signal sent by the master device, so as to be driven only by the handshake signal received by the master device.

[0012] Optionally, the inter-chip communication bus interface further includes:

[0013] A write address channel is used to transmit a write address from the master device to the slave device after the handshake of the handshake signal pair within the channel is completed;

[0014] A write response channel is used to transmit a write response signal from the slave device to the master device after completing the handshake of the handshake signal pair within its channel.

[0015] Optionally, the at least one data channel includes a read data channel, which is used to transmit the multi-bit data signal from the slave device to the master device after completing the handshake of the handshake signal pair in its channel; and in the first register slice of the read data channel, the first-level data register circuit with the shortest signal path to the master device is located in the backward register circuit of the first register slice and is de-driven by the handshake signal sent by the master device.

[0016] Optionally, the inter-chip communication bus interface further includes a read address channel, which is used to transmit a read address from the master device to the slave device after completing the handshake of the handshake signal pair in its channel.

[0017] Optionally, the handshake signal pair includes a valid signal and a ready signal.

[0018] Optionally, the master device is integrated in the first chip, and the slave device and the inter-chip communication bus interface are integrated in the second chip.

[0019] Optionally, the first chip and the second chip are stacked vertically and directly connected through through-silicon vias.

[0020] Based on the same inventive concept, the present invention provides a communication system, which includes a master device, a slave device, and an inter-chip communication bus interface as described in the present invention.

[0021] Compared with the prior art, the present invention provides an inter-chip communication bus interface and communication system. The data channel of the inter-chip communication bus interface is provided with a cascaded first register slice and a second register slice. The first register slice is coupled to the master device. Both the first register slice and the second register slice are provided with at least one level of data register circuit. Each level of the data register circuit is used to transmit multiple bits of data signal in parallel after completing the handshake of the handshake signal pair (e.g., valid signal and ready signal) in the data channel. The first level of data register circuit in the first register slice with the shortest signal path to the master device is removed from the driving of the handshake signal sent by the master device in the handshake signal pair (e.g., when writing data, the handshake signal sent by the master device in the handshake signal pair is the valid signal; when reading data, the handshake signal sent by the master device in the handshake signal pair is the ready signal). The remaining levels of data register circuits in the second register slice and / or the first register slice are all driven by the handshake signal pair.

[0022] This approach, while increasing the number of toggle operations on the multi-bit data signals buffered by the data register circuit at this stage, does not affect the handshake of the handshake signal pairs in the data channel. Moreover, since the first-level data register circuit with the shortest signal path to the master device in the first register slice eliminates the driving force of the handshake signal sent by the master device, the number of data registers driven by the handshake signal (i.e., the number of loads) is reduced, thereby reducing the timing pressure of communication handshake in the data channel. This facilitates the rapid completion of timing convergence of the data channel, supports large data bit width, high-speed synchronous inter-chip data transmission, and ensures data accuracy and stability. The remaining data register circuits are still driven by the handshake signal pairs, which can prevent the additional power consumption caused by frequent toggle operations on their buffered data. Attached Figure Description

[0023] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0024] Figure 1 This is a schematic diagram of the architecture of an inter-chip communication bus interface and communication system according to an embodiment of the present invention.

[0025] Figure 2 This is a schematic diagram of the inter-chip communication bus interface and communication system channel according to an embodiment of the present invention.

[0026] Figure 3 This is a schematic diagram of an example structure of an inter-chip communication bus interface and communication system according to an embodiment of the present invention when applied to writing data.

[0027] Figure 4 yes Figure 3 The diagram shows the inter-chip communication bus interface and the timing diagram of the communication system when writing data.

[0028] Figure 5 yes Figure 3 The diagram shows the inter-chip communication bus interface and the timing diagram of the internal registers used by the communication system when writing data.

[0029] Figure 6 This is a schematic diagram of an example structure of an inter-chip communication bus interface and communication system of the present invention when applied to reading data.

[0030] Figure 7 yes Figure 6 The diagram shows the timing of the inter-chip communication bus interface and the internal registers used by the communication system when reading data.

[0031] Figure 8 This is another example structural diagram of the inter-chip communication bus interface and communication system of an embodiment of the present invention when applied to writing data.

[0032] Figure 9 This is another example structural diagram of the inter-chip communication bus interface and communication system of an embodiment of the present invention when applied to reading data.

[0033] Figure 10 This is a schematic diagram of the packaging structure of an inter-chip communication bus interface and communication system according to an embodiment of the present invention.

[0034] Figure 11 This is a schematic diagram of the packaging structure of an inter-chip communication bus interface and communication system applied to a memory according to an embodiment of the present invention.

[0035] Figure 12 This is a schematic diagram of the communication structure of an inter-chip communication bus interface and communication system applied to a memory according to an embodiment of the present invention. Detailed Implementation

[0036] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described in order to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The same reference numerals denote the same elements throughout. It should be understood that when an element is referred to as "connected to" or "coupled to" other elements, it may be directly connected to other elements, or there may be intervening elements. Conversely, when an element is referred to as "directly connected to" other elements, there are no intervening elements. As used herein, the singular forms "a," "an," and "the" are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0037] Please refer to Figure 1An embodiment of the present invention provides an inter-chip communication bus interface 20, which is coupled between a master device 10 and a slave device 30 and has a data channel (not shown). The data channel is used to transmit a multi-bit (e.g., nbit, where n is an integer greater than 1) data signal after the handshake of a handshake signal pair (which consists of a handshake signal sent by the master device 10 to the slave device 30 and another handshake signal sent by the slave device 30 to the master device 10, such as a valid signal and a ready signal) is completed.

[0038] The data channel includes a cascaded first register slice 201 and a second register slice 202. The first register slice 201 is also coupled to the master device 10, and optionally, the second register slice 202 is also coupled to the slave device 30. Each of the first register slice 201 and the second register slice 202 includes at least one stage of data register circuit 200a. Each stage of the data register circuit 200a is used to transmit the multi-bit data signal "data" in parallel after completing the handshake of the handshake signal pair (e.g., valid signal and ready signal) in the data channel.

[0039] In this case, the first-level data register circuit 200a in the first register slice 201 with the shortest signal path to the master device 10 is de-driven by the handshake signal sent by the master device 10 to the first register slice 201 (i.e., the handshake signal sent by the master device 10 to the slave device 30) in the handshake signal pair (e.g., valid signal and ready signal). The remaining level data register circuits 200a in the second register slice 202 and / or the first register slice 201 are all driven by the handshake signal pair.

[0040] In one example, please refer to Figure 1When the data signal is an n-bit signal, each stage of the data register circuit 200a in the first register slice 201 and the second register slice 202 includes n parallel data register branches. Each data register branch is configured to correspond one-to-one with each bit of the data signal data and is driven by a handshake signal pair or one of the handshake signals in the handshake signal pair. Each handshake signal in the handshake signal pair is a 1-bit signal, and the handshake signal pair can synchronously drive the n parallel data register branches corresponding to the same stage of the data register circuit 200a. In a further embodiment, each data register branch includes combinational logic comb and a one-bit data register data reg coupled to the combinational logic comb. The handshake signals (e.g., valid signal and ready signal) synchronously drive the combinational logic comb in the n parallel data register branches corresponding to the same stage of the data register circuit 200a. For example, when n=1024 and the handshake signal pair is valid and ready, each stage data register circuit 200a can transmit 1024 bits of data signal data in parallel under the drive of 1 bit of valid signal and / or 1 bit of ready signal.

[0041] Alternatively, please refer to Figure 1 Each stage of data register circuit 200a in the first register slice 201 and the second register slice 202 further includes a first handshake signal transmission circuit 200b and a second handshake signal transmission circuit 200c. The first handshake signal transmission circuit 200b is used to transmit one handshake signal in the handshake signal pair, and the second handshake signal transmission circuit 200c is used to transmit the other handshake signal in the handshake signal pair.

[0042] In this embodiment, a two-level register slice design is inserted into the data channel of the inter-chip communication bus interface, and the driving of the same handshake signal is reduced for each data register branch in the first-level data register circuit 200a with the shortest signal path to the master device. Although this method increases the number of toggle operations of the buffered data in this level of data register circuit 200a, it does not affect the handshake of handshake signal pairs (e.g., valid and ready signals) in the data channel. Moreover, since this level of data register circuit 200a reduces the driving of the handshake signal sent by the master device, it can reduce the load of the handshake signal (i.e., reduce the number of parallel data register branches it drives), thereby reducing the timing pressure of communication handshake in the data channel. This is conducive to completing the timing convergence of communication handshake in the data channel as soon as possible, supporting large data bit width and high-speed synchronous transmission between chips, and ensuring the accuracy and stability of the data. In addition, the remaining levels of data register circuits are still driven by handshake signal pairs (e.g., valid and ready signals), which can prevent the additional power consumption caused by frequent data toggle operations.

[0043] Please refer to Figure 3 , Figure 6 and Figures 8 to 9 The first register slice 201 can be a forward register slice (FR), a backward register slice (BR), or a full register slice, and the present invention does not specifically limit it.

[0044] Here, "forward" refers to the direction in which the data sender (source) transmits data to the data receiver (destination). Please refer to [reference needed]. Figure 1 and Figure 8 The forward register slice has a forward register circuit FR, which includes a first-level data register circuit 200a, a first handshake signal transmission circuit 200b, and a second handshake signal transmission circuit 200c. The data register circuit 200a has n data register branches (for clarity, ...). Figure 8 Only one data register branch is shown in the diagram. Furthermore, each data register branch consists of combinational logic comb0 and a 1-bit data register wdata reg0. Figure 8Only one data register branch of this data register circuit is shown. Each data register branch can stamp its transmitted 1-bit data signal "data". The first handshake signal transmission circuit 200b consists of combinational logic comb2 and a first handshake signal register valid reg0. This first handshake signal transmission circuit is used to transmit one handshake signal (e.g., the valid signal) in the handshake signal pair and stamps the handshake signal during transmission. The second handshake signal transmission circuit 200c consists of combinational logic comb4, which is used to transmit the other handshake signal (e.g., the ready signal) in the handshake signal pair. The forward register slice FR will stamp both the n-bit data signal "data" in the channel and one handshake signal (e.g., the valid signal) in the handshake signal pair.

[0045] Backward refers to the direction in which the data receiver sends the ready signal to the data transmitter. The backward register slice contains backward register circuitry; please refer to... Figure 1 and Figure 9 The backward register circuit BR includes a primary data register circuit 200a, a first handshake signal transmission circuit 200b, and a second handshake signal transmission circuit 200c. The data register circuit 200a has n data register branches (for clarity, ...). Figure 9 Only one data register branch is shown in the diagram. Furthermore, each data register branch consists of combinational logic comb1 and a 1-bit data register rdata reg1. Figure 9 Only one data register branch of this data register circuit is shown. Each data register branch can stamp the 1-bit data signal 'data' it transmits. The first handshake signal transmission circuit 200b consists of combinational logic comb3 and a first handshake signal register valid reg1. This first handshake signal transmission circuit 200b is used to transmit one handshake signal (e.g., the valid signal) in the handshake signal pair and stamps the handshake signal during transmission. The second handshake signal transmission circuit 200c consists of combinational logic comb5 and a second handshake signal register ready reg0. It is used to transmit the other handshake signal (e.g., the ready signal) in the handshake signal pair and stamps the handshake signal during transmission. The backward register slice BR can stamp both the handshake signal pair and the n-bit data signal 'data' in the data channel to prevent data omissions or duplicate sampling.

[0046] Please combine Figure 1 and Figure 3The bidirectional register slice is composed of a forward register circuit FR and a backward register circuit BR, including a first handshake signal transmission circuit 200b, a second handshake signal transmission circuit 200c, and two cascaded data register circuits 200a. The first handshake signal transmission circuit 200b in this bidirectional register slice can be formed by sequentially coupling combinational logic comb2, the first handshake signal register valid reg0, combinational logic comb3, and the first handshake signal register validreg1, enabling it to time the first handshake signal (e.g., the valid signal). The second handshake signal transmission circuit 200c in this bidirectional register slice can be formed by sequentially coupling combinational logic comb4, the second handshake signal register readyreg0, and combinational logic comb5, enabling it to time the second handshake signal (e.g., the ready signal). Each stage of the data register circuit 200a in this bidirectional register slice has n data register branches (for clarity, ...). Figure 3 Only one data register branch is shown in the diagram. Each data register branch in the first-level data register circuit 200a consists of a corresponding combinational logic comb0 and a data register wdata reg0. Each data register branch in the second-level data register circuit 200a consists of a corresponding combinational logic comb1 and a data register wdata reg1. The data register branches in the two-level data register circuits 200a are configured and connected in a one-to-one correspondence, thereby slicing the data of that bit. Therefore, this bidirectional register slice can slice both the handshake signal pairs and the n-bit data signal data in the data channel.

[0047] Similarly, please refer to Figure 1 , Figure 3 , Figure 6 and Figures 8 to 9 The second register slice 202 can be a forward register slice (FR), a backward register slice (BR), or a full register slice; this invention does not specifically limit this. The second register slice 202 can use the same circuit design as the first register slice 201, or it can use a different circuit design. For example, in... Figure 3 and Figure 6 In the example shown, both the second register slice 202 and the first register slice 201 employ the same bidirectional register slice circuit design; Figure 8 In the example shown, both the second register slice 202 and the first register slice 201 use the same forward register slice circuit design; Figure 9In the example shown, both the second register slice 202 and the first register slice 201 employ the same backward register slice circuit design. In other examples, the first register slice 201 employs a forward register slice circuit design, and the second register slice 202 employs a bidirectional register slice circuit design, or the first register slice 201 employs a bidirectional register slice circuit design, and the second register slice 202 employs a backward register slice circuit design, and so on.

[0048] It should be understood that the inter-chip communication bus interface 20 of this embodiment can support any suitable bus protocol for communication handshake using handshake signal pairs (e.g., valid and ready), such as the AXI (Advanced eXtensible Interface) bus protocol. The master device 10 and slave device 20 coupled to the inter-chip communication bus interface 20 can be any suitable device form such as a module, a packaged chip, or an unpackaged die. The inter-chip communication bus interface 20 and the master device 10, as well as the slave device 20, can communicate and connect using any suitable method such as through-silicon vias, multilayer interconnects, rewiring, or soldered leads. This invention does not impose any specific limitations on this.

[0049] Furthermore, please refer to Figure 2 The data channels in the inter-chip communication bus interface 20 can include a write data channel 20b or a read data channel 20e, or both. Furthermore, the inter-chip communication bus interface 20 can have more than just data channels; it can also have other required signal channels, such as a write address channel 20a, a read address channel 20d, and a write response channel 20c, etc. Each channel contains a set of information signals and handshake signal pairs, and each channel uses the handshake signal pairs within that channel for handshaking.

[0050] The following section uses the handshake signal pair of valid and ready signals as an example, and provides a detailed explanation with reference to the corresponding attached diagrams.

[0051] Please refer to Figure 2The write address channel 20a is used to transmit the write address (i.e., the starting address of the data to be written) waddr from the master device 10 to the slave device 30 after completing the handshake between the write address valid signal awvalid and the write address ready signal awready in this channel. The write address valid signal awvalid is sent by the master device 10 to the slave device 30; awvalid=1 indicates that the write address and control information in the write address channel 20a are valid, and awvalid=0 indicates that the write address and control information in the write address channel 20a are invalid. The write address ready signal awready is sent by the slave device 30 to the master device 10; awready=1 indicates that the slave device 30 is ready to receive the write address and control information in the write address channel 20a, and awready=0 indicates that the slave device 30 is not yet ready to receive the write address and control information in the write address channel 20a. The transmission of the write address waddr in the write address channel 20a only actually occurs when awready=1 and awvalid=1.

[0052] Please refer to Figure 2The write data channel 20b is used to transmit n bits of write data (i.e., data to be written) signal wdata from the master device 10 to the slave device 30 after completing the handshake between the write data valid signal wvalid and the write data ready signal wready. The write data channel 20b can include a data bus with a data width of 8 to 1024 bits (i.e., n = 8 to 1024), such as 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, 256-bit, 512-bit, or 1024-bit. The write data channel 20b can support burst data transmission to continuously transmit multiple blocks of data in a single transaction. The write data channel 20b can identify the last data transmission cycle of a burst transmission using the write end signal wlast. During burst transmission, each byte channel consists of eight bits of data. The write data channel 20b can specify the byte channel containing valid information in its data bus using the write byte enable signal wstrb (Write strobes). The write data valid signal wvalid is sent from the master device 10 to the slave device 30. wvalid=1 indicates that the write data signal wdata (which is nbit) and control information in the write data channel 20b are valid, while wvalid=0 indicates that the write data signal wdata (which is nbit) and control information in the write data channel 20b are invalid. The write data ready signal wready is sent from the slave device 30 to the master device 10. wready=1 indicates that the slave device 30 is ready to receive the write data signal wdata (which is nbit) and control information in the write data channel 20b, while wready=0 indicates that the slave device 30 is not yet ready to receive the write data signal wdata (which is nbit) and control information in the write data channel 20b. Only when wready=1 and wvalid=1 does the transmission of the write data signal wdata (which is nbit) in the write data channel 20b actually occur.

[0053] Please refer to Figure 2The write response channel 20c is used to transmit the write response status signal wresp from the slave device 30 to the master device 10 after completing the handshake between the write response valid signal bvalid and the write response ready signal bready within the channel, indicating that the write data operation is complete. Specifically, the write response valid signal bvalid is sent from the slave device 30 to the master device; bvalid=1 indicates that the write response status signal wresp and control information in the write response channel 20c are valid, and bvalid=0 indicates that the write response status signal wresp and control information in the write response channel 20c are invalid. The write response ready signal bready is sent from the master device 10 to the slave device 30; bready=1 indicates that the master device is ready to receive the write response status signal wresp and control information in the write response channel 20c, and bready=0 indicates that the master device 10 is not yet ready to receive the write response status signal wresp and control information in the write response channel 20c. The transmission of the write response status signal wresp in the write response channel 20c only actually occurs when bready=1 and bvalid=1. wresp=1 indicates that the nbit write data signal wdata was successfully written, and wresp=0 indicates that the nbit write data signal wdata failed to be written.

[0054] Please refer to Figure 2 The read address channel 20d is used to transmit the read address (i.e., the starting address of the data to be read) raddr from the master device 10 to the slave device 30 after completing the handshake between the read address valid signal arvalid and the read address ready signal arready in this channel. The read address valid signal arvalid is sent by the master device 10 to the slave device 30. arvalid=1 indicates that the read address and control information in the read address channel 20d are valid, and arvalid=0 indicates that the read address and control information in the read address channel 20d are invalid. The read address ready signal arready is sent by the slave device 30 to the master device 10. arready=1 indicates that the slave device 30 is ready to receive the read address and control information in the read address channel 20d, and arready=0 indicates that the slave device 30 is not yet ready to receive the read address and control information in the read address channel 20d. The transmission of the read address raddr in the read address channel 20d only actually occurs when arready=1 and arvalid=1.

[0055] Please refer to Figure 2The read data channel 20e is used to transmit an n-bit read data signal (i.e., the data to be read) rdata from the slave device 30 to the master device 10 after completing the handshake between the read data valid signal rvalid and the read data ready signal rready in the channel. The read data channel 20e can include a data bus with a data width of 8 to 1024 bits, such as 8-bit, 16-bit, 32-bit, 64-bit, 128-bit, 256-bit, 512-bit, or 1024-bit. The read data channel 20e can support burst data transmission to continuously transmit multiple blocks of data in a single transaction. The read data channel 20e can use the read end signal rlast to identify the last data transmission cycle of a burst transmission. The read data valid signal (rvalid) is sent from the slave device 30 to the master device 10. rvalid=1 indicates that the read data signal rdata (nbit) and control information in the read data channel 20b are valid; rvalid=0 indicates that the read data signal rdata (nbit) and control information in the read data channel 20b are invalid. The read data ready signal (rready) is sent from the slave device 10 to the master device 30. rready=1 indicates that the master device 10 is ready to receive the read data signal rdata (nbit) and control information in the read data channel 20b; rready=0 indicates that the master device 10 is not yet ready to receive the read data signal rdata (nbit) and control information in the read data channel 20b. Only when rready=1 and rvalid=1 does the transmission of the read data rdata (nbit) in the read data channel 20b actually occur.

[0056] In this embodiment, please refer to Figures 1-3 and Figure 8The inter-chip communication bus interface 20 has a write data channel 20b, into which two levels of register slices, a first register slice 201 and a second register slice 202, are inserted. The first register slice 201 is coupled between the master device 10 and the second register slice 202, and the second register slice 202 is coupled between the first register slice 201 and the slave device 30. The first-level data register circuit 200a in the first register slice 201 with the shortest signal path to the master device 10 has had the drive of the write data valid signal wvalid sent by the master device 10 removed from the handshake signal pair (e.g., wvalid / wready). The remaining levels of data register circuits 200a are all driven by the corresponding write data valid signal wvalid and write data ready signal wready. Compared with the remaining levels of data register circuits 200a, the first-level data register circuit 200a with the shortest signal path to the master device 10 in the first register slice 201 has reduced the drive of the write data valid signal wvalid (i.e., reduced the amount of write data valid signal wvalid load).

[0057] In one example, please combine Figure 1 and Figure 3Both the first register slice 201 and the second register slice 202 adopt a bidirectional register slice circuit design. The first-level data register circuit with the shortest signal path between the first register slice 201 and the master device 10 is the data register circuit 200a in the forward register circuit FR of the first register slice 201, which has n data register branches (furthermore, each data register branch is composed of the corresponding combinational logic comb0 and write data register wdata reg0 in the first register slice 201), and each data register branch is driven only by the write data ready signal wready. The remaining data register circuits include: (1) a data register circuit 200a in the backward register circuit BR of the first register slice 201, which has n data register branches (furthermore, each data register branch is composed of combinational logic comb1 and write data register wdata reg1 in the first register slice 201), and each data register branch is driven by the write data valid signal wvalid and the write data ready signal wready; (2) a data register circuit 200a in the forward register circuit FR of the second register slice 202, which has n data register branches (furthermore, each data register branch is composed of combinational logic comb0 and write data register wdata in the second register slice 202). (3) The data register circuit 200a in the backward register circuit BR of the second register slice 202 has n data register branches (furthermore, each data register branch is composed of combinational logic comb1 and write data register wdata reg1 in the second register slice 202), and each data register branch is driven by the write data valid signal wvalid and write data ready signal wready. Comparing the first-stage data register circuit 200a in the first register slice 201 and the second register slice 202 (furthermore, it has n combinational logic comb0s and n write data registers wdata reg0, with one comb0 and one wdata reg0 forming a data register branch), it can be found that the data register circuit 200a in the first register slice 201 is not driven by the write data valid signal wvalid, but only by the write data ready signal wready, while the data register circuit 200a in the second register slice 201 is driven by the write data valid signal wvalid (see... Figure 3 (As shown by the red line in the image) and the write data ready signal wready work together to drive it.

[0058] When the master device 10 writes data to the slave device 30 through the inter-chip communication bus interface 20, the write timing in the inter-chip communication bus interface 20 is as follows: Figure 4 As shown, the signal timing of the write response channel and the first register slice 201 in the write data channel of the inter-chip communication bus interface 20 is as follows: Figure 5 As shown. Please refer to... Figure 3 and Figure 5 As shown in the red box, when wvalid is 0, the switching of wdata provided by the master device 10 will also cause the data cached in the data register wdata_reg0 inside the first register slice 201 (i.e., the data register in the data register circuit 200 with the shortest signal path between the master device 10 and the data register) to switch (toggle). This will lead to a certain increase in power consumption, but it will not affect the handshake between wvalid and wready in the write data channel. Moreover, since the combinational logic comb0 coupled to the data register wdata_reg0 eliminates the need for the wvalid driver, the number of wvalid drivers in the write data channel is reduced, thereby reducing the timing pressure of the handshake in the write data channel and making it easier for the timing convergence of the write data channel. This will enable the support of large data bit width and high-speed synchronous transmission between chips, ensuring the accuracy and stability of the master device 10 writing data to the slave device 30. In addition, the data register circuit in the second register slice 202 is still driven by the wvalid and wready signals, which can prevent the additional power consumption caused by frequent data switching (toggle).

[0059] In another example, please combine Figure 1 and Figure 8Both the first register slice 201 and the second register slice 202 adopt a forward register slice circuit design. Specifically, the data register circuit 200a in the first register slice 201 has the shortest signal path to the master device 10, and it has n data register branches (furthermore, each data register branch consists of a corresponding combinational logic comb0 and a write data register wdata reg0 in the first register slice 201), and each data register branch is driven by the write data ready signal wready. The data register circuit 200a in the second register slice 202 also has n data register branches (furthermore, each data register branch consists of a corresponding combinational logic comb0 and a write data register wdata reg0 in the second register slice 202), and each data register branch is jointly driven by the write data valid signal wvalid and the write data ready signal wready. This example not only enables the wvalid and wready handshake in the write data channel, reducing the timing pressure of the handshake and facilitating timing convergence of the write data channel, but also supports large data bit width and high-speed synchronous transmission between chips, ensuring data accuracy and stability. Furthermore, it is relatively... Figure 3 The example shown has a simpler circuit and lower circuit cost.

[0060] In this embodiment, please refer to Figure 2 , Figure 6 and Figure 9 The inter-chip communication bus interface 20 has a read data channel 20e, into which two levels of register slices, a first register slice 201 and a second register slice 202, are inserted. The first register slice 201 is coupled between the master device 10 and the second register slice 202, and the second register slice 202 is coupled between the first register slice 201 and the slave device 30. The first-level data register circuit 200a in the first register slice 201 with the shortest signal path to the master device 10 has had the drive of the read data ready signal rready sent by the master device 10 removed from the handshake signal pair (e.g., rvalid / rready). The remaining levels of data register circuits 200a are all driven by the corresponding read data valid signal rvalid and read data ready signal rready.

[0061] In one example, please refer to Figure 6Both the first register slice 201 and the second register slice 202 adopt a bidirectional register slice circuit design. The first-level data register circuit with the shortest signal path between the first register slice 201 and the master device 10 is the data register circuit 200a in the backward register circuit BR of the first register slice 201, which has n data register branches (furthermore, each data register branch is composed of the corresponding combinational logic comb1 and read data register rdata reg1 in the first register slice 201). The remaining data register circuits include: (1) a data register circuit 200a in the forward register circuit FR of the first register slice 201, which has n data register branches (furthermore, each data register branch is composed of the corresponding combinational logic comb0 and read data register rdata reg0 in the first register slice 201), and each data register branch is driven by the read data valid signal rvalid and the read data ready signal rready; (2) a data register circuit 200a in the backward register circuit BR of the second register slice 202, which has n data register branches (furthermore, each data register branch is composed of the corresponding combinational logic comb1 and read data register rdata in the second register slice 202). (3) The data register circuit 200a in the forward register circuit FR of the second register slice 202 has n data register branches (furthermore, each data register branch is composed of combinational logic comb0 and read data register rdatareg0 in the second register slice 202), and each data register branch is driven by read data valid signal rvalid and read data ready signal rready. Comparing the data register circuits 200a closest to the master device 10 in the first register slice 201 and the second register slice 202 (each of which consists of a corresponding combinational logic comb1 and a read data register rdata reg1), it can be found that the data register circuit 200a in the first register slice 201 is not driven by the read data ready signal rready provided by the master device 10, while the data register circuit 200a in the second register slice 201 is driven by the read data ready signal rready provided by the first register slice 201 (see...). Figure 6 (As shown by the red line in the image) and the read data valid signal rvalid work together to drive the system.

[0062] When the master device 10 reads data from the slave device 30 through the inter-chip communication bus interface 20, the signal timing of the first register slice 201 in the read data channel of the inter-chip communication bus interface 20 is as follows: Figure 7 As shown. Please refer to... Figure 6 and Figure 7 As shown in the red box, when ready_reg0 is 0, the switching of the n-bit read data rdata provided by the slave device 30 will also cause the data cached in the data register rdata_reg1 inside the first register slice 201 (i.e., the data register in the first-level data register circuit 200a with the shortest signal path between the master device 10) to switch (toggle). This will bring a certain increase in power consumption, but it will not affect the handshake signal for rvalid and rready in the read data channel. Moreover, since each data register branch in this level of data register circuit 200 (furthermore, composed of the combinational logic comb1 coupled to the read data register rdata_reg1) is exempt from the rready driver sent by the master device 10, the load of rready driver is reduced, thereby reducing the timing pressure of the handshake in the read data channel, which is more conducive to the timing convergence of the read data channel. This enables the support of large data bit width and high-speed synchronous transmission between chips, ensuring the accuracy and stability of the master device 10 reading data from the slave device 30. In addition, the data register circuit 200a in the second register slice 202 is still driven by the handshake signal pairs rvalid and rready, which can prevent the additional power consumption caused by frequent data switching (toggle).

[0063] In another example, please refer to Figure 9 Both the first register slice 201 and the second register slice 202 adopt a backward register slice circuit design. Specifically, the data register circuit 200a in the first register slice 201, which has the shortest signal path to the master device 10, has n data register branches (furthermore, each data register branch consists of a corresponding combinational logic comb1 and a read data register rdata reg1 in the first register slice 201), reducing the driving force of the read data ready signal rready provided by the master device 10. The data register circuit 200a in the second register slice 202 also has n data register branches (furthermore, each data register branch consists of a corresponding combinational logic comb1 and a read data register rdata reg1 in the second register slice 202), and each data register branch in the data register circuit 200a in the second register slice 202 is driven by both the read data valid signal rvalid and the read data ready signal rready.

[0064] Alternatively, please refer to Figure 2 and Figure 10In this embodiment, the inter-chip communication bus interface 20 can be integrated with the slave device 30 in the second chip 50, and the master device 10 can be integrated in the first chip 60. The first chip 60 and the second chip 50 are stacked vertically. For example, the first chip 60 is a logic chip or logic die with computing capabilities, and the second chip 50 is a buffer die or buffer chip. The first chip 60 and the second chip 50 are stacked vertically.

[0065] Furthermore, the first chip 60 and the second chip 50 can be either packaged chips or unpackaged bare chips, etc., in any suitable form, and the present invention does not limit them.

[0066] Further optional, please refer to Figure 11 The device 30 is a memory controller. The first chip 60, the second chip 50 and the three-dimensional stacked memory chip 4 are vertically stacked in sequence, and / or the first chip 60 and the second chip 50, the second chip 50 and the three-dimensional stacked memory chip 4 and the memory bare dies in the three-dimensional stacked memory chip 4 are all directly connected through through silicon vias (TSVs).

[0067] Based on the same inventive concept, please refer to Figures 1 to 12 This embodiment also provides a communication system, which includes a master device 10, a slave device 30, and an inter-chip communication bus interface 20 as described in this invention.

[0068] The inter-chip communication bus interface 20 and the communication system having the inter-chip communication bus interface 20 of this embodiment can be applied to any technical field that requires reading or writing data, such as the field of memory such as DRAM.

[0069] In one example, please refer to Figure 11 The slave device 30 is a memory controller and is also coupled to memory 4, which can be any suitable type of memory such as dynamic random access memory (DRAM).

[0070] The main device 10 may include any type of processing device with computing capabilities, such as a central processing unit (CPU), digital signal processor (DSP), network processor, application processor (AP), field-programmable gate array (FPGA), or dedicated processor. This processing device can be configured to execute instructions or software (including code, operating system, or application programs), firmware, or a combination thereof, executable by one or more computers. The main device 10 may be integrated into a first chip 60, which may be a packaged logic chip or an unpackaged logic die.

[0071] The inter-chip communication bus interface 20 can perform interface conversion between the master device 10 and the memory controller (i.e., slave device 30). Thus, the memory controller (i.e., slave device 30) can convert read, write, refresh, and other instructions sent by the master device 10 to the memory 4 into signals that the memory 4 can recognize. It can also complete the decoding of write or read addresses, data format conversion (such as data bit width), and operation instruction transmission between the master device 10 and the memory 4, thereby realizing the necessary control of refresh operations, read and write operations, and other accesses to the memory 4 (including the control of address signals, data signals, and various instruction signals).

[0072] Therefore, please refer to Figure 12 In this application scenario, the inter-chip communication bus interface 20 has a write address channel 20a, a write data channel 20b, a write response channel 20c, a read address channel 20d, and a read data channel 20e. The signal and circuit design of these channels can be referred to the corresponding content above, and will not be repeated here. The write data channel 20b and read data channel 20e of the inter-chip communication bus interface 20 are both inserted with corresponding first register slice 201 and second register slice 202. In the first register slice 201 of the write data channel 20b, the first-level data register circuit 200a with the shortest signal path to the master device 10 has been removed from the handshake signal pair (wvalid and wready) from driving the write data valid signal wvalid sent by the master device 10 (it can be driven only by the write data ready signal wready). In the first register slice 201 of the read data channel 20e, the data register circuit 200a with the shortest signal path to the master device 10 has been removed from driving the read data ready signal rready sent by the master device 10 in the handshake signal pair (rvalid and rready).

[0073] Alternatively, please continue to refer to Figure 11The master device 10 can be integrated into the first chip 60 (which can be a packaged logic chip or an unpackaged logic die). The memory controller (i.e., slave device 30) can be integrated with the inter-chip communication bus interface 20 into the same second chip 50 (which can be a packaged buffer chip or an unpackaged buffer die). The memory 4 is a three-dimensional stacked memory, which can include j+1 layers of memory dies 400~40j stacked together. Each memory die 400~40j can be DRAM or other suitable type of memory die structure. The memory dies 400~40j are connected to each other and to the second chip 50 (e.g., a buffer die), and the second chip 50 is connected to the first chip 60 where the master device is located (e.g., a logic die or logic chip with computing capabilities) through through-silicon vias (TSVs) for hybrid bonding (or direct connection through TSVs).

[0074] In summary, this invention provides an inter-chip communication bus interface and communication system. The data channel of this inter-chip communication bus interface includes a cascaded first register slice and a second register slice. The first register slice is coupled to a master device. Both the first and second register slices contain at least one level of data register circuitry. Each level of data register circuitry is used to transmit multiple bits of data signal in parallel after completing the handshake of a handshake signal pair (e.g., valid and ready) in the data channel. The first level of data register circuitry in the first register slice with the shortest signal path to the master device is de-driven by the handshake signal sent by the master device in the handshake signal pair (e.g., valid and ready). (For example, when writing data, the handshake signal sent by the master device is valid; when reading data, the handshake signal sent by the master device is ready.) The remaining levels of data register circuitry in the second register slice and / or the first register slice are all driven by the handshake signal pair.

[0075] This approach, while increasing the number of toggle operations on the multi-bit data signals buffered by the data register circuit at this stage, does not affect the handshake of the handshake signal pairs in the data channel. Moreover, since the first-level data register circuit with the shortest signal path to the master device in the first register slice eliminates the driving force of the handshake signal sent by the master device, the number of data registers driven by the handshake signal (i.e., the number of loads) is reduced, thereby reducing the timing pressure of communication handshake in the data channel. This facilitates the rapid completion of timing convergence of the data channel, supports large data bit width, high-speed synchronous inter-chip data transmission, and ensures data accuracy and stability. The remaining data register circuits are still driven by the handshake signal pairs, which can prevent the additional power consumption caused by frequent toggle operations on their buffered data.

[0076] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. An inter-chip communication bus interface, coupled between a master device and a slave device and having at least one data channel, characterized in that, The data channel is provided with cascaded first register slices and second register slices, the first register slices are coupled to the master device, and each of the first register slices and the second register slices is provided with at least one level of data register circuit, and each level of the data register circuit is used for transmitting a multi-bit data signal in parallel after completing handshaking of a handshake signal pair in the data channel. Among the first register slices, the level of data register circuit with the shortest signal path between the master device is removed from driving of the handshake signal sent by the master device to the first register slice in the handshake signal pair, and the second register slice and / or the remaining level of data register circuit in the first register slice are commonly driven by the handshake signal pair. In the case of writing data, the handshake signal pair includes a write data valid signal and a write data ready signal, and the level of data register circuit with the shortest signal path is removed from driving of the write data valid signal sent by the master device; in the case of reading data, the handshake signal pair includes a read data valid signal and a read data ready signal, and the level of data register circuit with the shortest signal path is removed from driving of the read data ready signal sent by the master device.

2. The interchip communication bus interface of claim 1, wherein, Each level of the data register circuit includes a plurality of parallel data register branches, each of the data register branches is provided in one-to-one correspondence with each bit of the data signal, and is driven by the handshake signal pair or one handshake signal in the handshake signal pair.

3. The interchip communication bus interface of claim 2, wherein, Each handshake signal in the handshake signal pair is a one-bit signal, and the handshake signal pair synchronously drives the plurality of parallel data register branches of the data register circuit at the same level.

4. The inter-chip communication bus interface of claim 2 or 3, wherein, Each of the data register branches includes combinational logic and a one-bit data register coupled to the combinational logic, and the handshake signal pair synchronously drives the combinational logic in the plurality of parallel data register branches of the data register circuit at the same level.

5. The interchip communication bus interface of claim 1, wherein, The first register slice is a forward register slice, a backward register slice or a bidirectional register slice, and the second register slice is a forward register slice, a backward register slice or a bidirectional register slice; wherein the forward register slice has a forward register circuit, the backward register slice has a backward register circuit, and the bidirectional register slice is composed of a forward register circuit and a backward register circuit.

6. The interchip communication bus interface of claim 1, wherein, The at least one data channel includes a write data channel, the write data channel is used for transmitting the multi-bit data signal from the master device to the slave device after completing handshaking of the handshake signal pair in the channel, and in the first register slice of the write data channel, the level of data register circuit with the shortest signal path between the master device is located in the forward register circuit of the first register slice and is removed from driving of the handshake signal sent by the master device to be driven only by the handshake signal received by the master device.

7. The interchip communication bus interface of any of claims 1-3 and 5-6, wherein, The inter-slice communication bus interface further includes: a write address channel for transmitting a write address from the master device to the slave device after completing handshaking of a handshake signal pair in the channel; a write response channel for transmitting a write response signal from the slave device to the master device upon completion of the handshake of the handshake signal pair in its channel.

8. The interchip communication bus interface of any of claims 1-3 and 5-6, wherein, The at least one data channel includes a read data channel for transmitting the multi-bit data signal from the slave device to the master device upon completion of the handshake of the handshake signal pair in its channel; and in the first register slice of the read data channel, a level of data register circuits with the shortest signal path to the master device are located in the backward register circuits of the first register slice and are removed from the driving of the handshake signal sent by the master device.

9. The interchip communication bus interface of claim 8, wherein, The inter-chip communication bus interface further includes a read address channel for transmitting a read address from the master device to the slave device upon completion of the handshake of the handshake signal pair in its channel.

10. The interchip communication bus interface of any of claims 1-3, 5-6, 9, wherein, The master device is integrated in a first chip, and the slave device and the inter-chip communication bus interface are integrated in a second chip.

11. The interchip communication bus interface of claim 10, wherein, The first chip and the second chip are vertically stacked and directly connected through a through-silicon via.

12. An interchip communication system, characterized by comprising: An inter-chip communication bus interface as claimed in any one of claims 1-11, a master device, and a slave device.

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