Hardware partitioning for cloud server

Abstract

A system for hardware partitioning of a cloud server includes one or more processor cores. The first processor core executes instructions to partition at least a portion of the one or more processor cores into one or more partitions. The system includes one or more distributed virtual memory (DVM) interposers, each DVM interposer including a respective partition identifier that identifies a partition. Each DVM interposer performs a prevention action in response to receiving a DVM message that includes a partition identifier that is different from the partition identifier of the DVM interposer. The system includes one or more interrupt interposers. Each interrupt interposer is associated with a processor core of the one or more processor cores. Each interrupt interposer prevents a first interrupt originating from the associated processor core from being provided to processor cores outside the partition of the associated processor core.

Description

TECHNICAL FIELD

[0001] This specification generally relates to computing devices. More specifically, this specification relates to hardware partitioning for cloud servers. BACKGROUND

[0002] Cloud computing includes network-based computing in which a collection of computing devices (e.g., servers, processing units, data storage devices) and software (e.g., computer programs, database tools) provide computing resources and data storage for remote end users. Cloud servers typically include hardware (e.g., processor devices, memory devices, IO devices, etc.) for implementing software that executes on the cloud server. SUMMARY

[0003] Systems and methods for hardware partitioning of cloud servers are disclosed herein. One aspect of the disclosure includes a system. The system includes one or more processor cores. A first processor core of the one or more processor cores executes instructions to partition at least a portion of the one or more processor cores into one or more partitions. The system includes one or more distributed virtual memory (DVM) mediators. Each DVM mediator includes a respective identifier that identifies a partition of the one or more partitions. Each DVM mediator performs a preventative action in response to receiving a first DVM message that includes a partition identifier that is different from the partition identifier of the DVM mediator. The system includes one or more interrupt mediators. Each interrupt mediator is associated with a processor core of the one or more processor cores. Each interrupt mediator prevents a first interrupt originating from the associated processor core from being provided to a processor core outside of a partition of the associated processor core.

[0004] Another aspect of the disclosure includes a method. The method includes partitioning one or more processor cores into one or more partitions. The method includes configuring a DVM mediator to include a first partition identifier associated with a first partition of the one or more partitions. The method includes configuring the DVM mediator to perform a preventative action in response to receiving, at the DVM mediator, a first DVM message that includes a second partition identifier that is different from the first partition identifier. The method includes configuring an interrupt mediator to be associated with a first processor core of the one or more processor cores. The first processor core belongs to the first partition. The method includes configuring the interrupt mediator to prevent a first interrupt originating from the first processor core from being provided to a processor core outside of the first partition.

[0005] Another aspect of the disclosure includes a non-transitory computer- readable storage medium including instructions. The instructions, when executed by a processing device, cause the processing device to perform operations. The operations include configuring a DVM shim to include a first partition identifier associated with a first partition of the one or more partitions. The operations include configuring the DVM shim to perform a preventative action in response to receiving a DVM message that includes a second partition identifier that is different than the first partition identifier. The operations include configuring an interrupt shim to be associated with a first processor core of the one or more processor cores. The first processor core belongs to the first partition. The operations include preventing, at the interrupt shim, a first interrupt originating from the first processor core from being provided to a processor core outside of the first partition. BRIEF DESCRIPTION OF DRAWINGS

[0006] Aspects and implementations of the disclosure will be more fully understood from the following detailed description, taken together with the drawings, wherein like reference numerals refer to like elements throughout the several figures, which are not drawn to scale.

[0007] Figure 1 An example computing device for hardware partitioning of a cloud server is schematically illustrated in which some aspects of the disclosure can be implemented, in accordance with one or more embodiments.

[0008] Figure 2 An example computing device for hardware partitioning of a cloud server is schematically illustrated in which some components have been partitioned into a plurality of partitions and in which some aspects of the disclosure can be implemented, in accordance with one or more embodiments.

[0009] Figure 3 A portion of an example computing device for hardware partitioning of a cloud server is schematically illustrated in which some aspects of the disclosure can be implemented, in accordance with one or more embodiments.

[0010] Figure 4 A flow diagram illustrating an example method for practicing some aspects of the disclosure is depicted, in accordance with one or more embodiments.

[0011] Figure 5 A flow diagram illustrating an example method for practicing some aspects of the disclosure is depicted, in accordance with one or more embodiments.

[0012] Figure 6 A flow diagram illustrating an example method for practicing some aspects of the disclosure is depicted, in accordance with one or more embodiments.

[0013] Figure 7 A block diagram of an example computer device capable of creating hardware partitions for a cloud server is depicted, in accordance with some implementations of the disclosure. DETAILED DESCRIPTION

[0014] A cloud provider can provide a cloud computing environment to customer end users. The cloud provider typically provides two types of cloud computing environments: a bare-metal cloud computing environment and a virtual machine (VM) cloud computing environment. In a bare-metal cloud environment, the cloud provider dedicates an entire cloud server to a customer end user. The customer end user can then use all of the computing resources (e.g., processor devices, memory devices, input / output (IO) devices, etc.) of the cloud server. Although the customer end user using a bare-metal cloud environment does not share any computing resources with other customers of the cloud provider, the customer end user typically has to pay for the entire cloud server, even if the customer end user does not use all of the computing resources of the cloud server.

[0015] In a VM cloud environment, a customer end user can select a desired computing resource configuration for a VM (e.g., number and type of processor devices, amount of memory, amount of storage space, type of IO devices, etc.), and the cloud provider can use a hypervisor to create and run the VM with the selected configuration. Due to computing resource availability, the hypervisor can run the VM on multiple cloud servers. If the customer end user uses only a portion of the cloud server hardware needed for the VM, the VM can share the computing resources of the cloud server with other customers’ VMs, which can use the computing resources and can act as a medium to attack the customer end user’s VM. Moreover, the VM is managed by the hypervisor, which can use the computing resources of the cloud server and can also act as a medium to attack the customer end user’s VM.

[0016] Aspects and implementations of the present disclosure address the above deficiencies and others by providing a cloud computing system that statically partitions the computing resources of a cloud server such that a customer end user uses only the computing resources it requests (unlike a bare-metal cloud environment) and such that different cloud provider customers do not use the same computing resources or hypervisor (unlike a VM cloud environment). The system can include a plurality of processor cores. One of the processor cores (e.g., a management core) can execute instructions (e.g., firmware) that can partition at least a portion of the other processor cores into one or more partitions. The instructions can configure the processor cores such that they are unable to communicate with or cause actions on processor cores outside of their respective partitions.

[0017] In some implementations, the system includes one or more distributed virtual memory (DVM) mediators. A DVM mediator can be associated with a partition. A DVM mediator can include a partition identifier that identifies the partition associated with the DVM mediator and is unique to the partition. In response to a DVM mediator receiving an instruction (e.g., a transactional lookaside buffer (TLB) invalidate instruction) that includes a partition identifier that is different from the partition identifier of the DVM mediator (which can indicate that the instruction originated outside of the partition), the DVM mediator can perform a preventative action (e.g., an action that prevents the instruction from being executed within the partition).

[0018] In some implementations, the system includes one or more interrupt mediators. An interrupt mediator can be associated with a processor core. An interrupt mediator can prevent an interrupt originating from an associated processor core from being provided to a processor core outside of a partition to which the associated processor core belongs. The system can include other components that prevent components in one partition from acting on another partition. For example, an instruction that partitions a processor core can configure a system address map (SAM) of the processor core such that the processor core can only access memory blocks that have been assigned to a partition to which the processor core belongs. The system can include instructions (e.g., firmware) that cause a processor core to emulate one or more IO devices such that there is logical separation with respect to the partition of the IO devices.

[0019] Some advantages of the present disclosure can provide technical effects that result from or are caused by technical solutions to technical problems. For example, one technical problem can relate to inefficient use of computing resources resulting from a bare-metal cloud environment in which customer end users are assigned an entire cloud server but can not use all of the computing resources of the cloud server. One of the technical solutions to this technical problem can include using a system disclosed herein in which computing resources are partitioned such that different customer end users efficiently use them. As a result, wasted computing resources are reduced or eliminated. One technical problem can relate to a hypervisor using computing resources that could instead be used by customer end user software. One of the technical solutions to this technical problem can include a system disclosed herein in which a hypervisor is not used, thereby allowing customer end users to use the computing resources. As a result, computing resources used by customer end users rather than a cloud provider are increased. Another technical problem can relate to security vulnerabilities in a hypervisor or processor core that can be used as a medium for attacks. One of the technical solutions to this technical problem can include a system disclosed herein in which a hypervisor is not used and communications, interrupts, etc. from one partition are not continued or accepted by another partition. As a result, such security vulnerabilities are mitigated or eliminated.

[0020] Figure 1 is a schematic block diagram illustrating an example computing device 100, in accordance with some embodiments. The computing device 100 can include a computing device 100 used in a cloud computing system. For example, the computing device 100 can include a cloud server, a cloud system on a chip (SoC), or some other computing device 100 that can be included in a cloud computing system.

[0021] A cloud computing system can include one or more computing devices (or portions of cloud computing devices) provided by a cloud provider to an end user. An end user can utilize a portion of the cloud computing system to host content for use or access by other parties or to perform other computing tasks. In some implementations, the cloud computing system is configured to allow an end user to use a portion of a computing device 100 (e.g., only certain hardware, software, or other computer system resources). The cloud computing system can include a private cloud, a public cloud, or a hybrid cloud. The cloud computing system can provide infrastructure as a service (IaaS), platform as a service (PaaS), or software as a service (SaaS) computing. The cloud computing system can provide serverless computing.

[0022] In one implementation, the computing device 100 includes one or more processor cores 110A-110F. One or more of the processor cores 110A-110F can include a respective system address map (SAM) 112A-112F. The computing device 100 can include one or more distributed virtual memory (DVM) mediators 114A-114F. The computing device can include one or more interrupt mediators 116A-116N. The computing device 100 can include one or more memory devices 120A-120B. While Figure 1 The computing device 100 of FIG. 1 includes six of each of the processor cores 110A-110F, the SAMs 112A-112F, the DVM mediators 114A-114F, and the interrupt mediators 116A-116F, the computing device 100 can include other numbers of such components. The computing device 100 can include other numbers of memory devices 120A-120B.

[0023] In some implementations, a processor core 110 includes an electronic device that executes instructions. The processor core 110 can include an arithmetic logic unit (ALU) for performing computations, a control unit for retrieving and decoding instructions, or a register for temporary data storage. The processor core 110A can operate independently or can cooperate with other processor cores 110B-110F. The processor core 110 can sometimes be referred to as a “processing element” or “PE.”

[0024] In one implementation, a first processor core 110A of the one or more processor cores 110A-110F includes instructions to partition at least a portion of the computing resources of the computing device 100 into one or more partitions. The computing resources that can belong to a partition can include processor cores 110, SAMs 112, DVM mediation layers 114, interrupt mediation layers 116, memory blocks of the memory device 120, or other computing resources. The first processor core 110A can include instructions to manage the one or more partitions. The instructions can include firmware or other software. The first processor core 110A can be referred to as a “management core.”

[0025] In some implementations, the instructions to partition one or more computing resources of the computing device 100 can be executed on an electronic device separate from the computing device 100. The separate electronic device can be dedicated to partitioning and managing the one or more processor cores 110A-110F. The instructions can be executed on a microcontroller located on the computing device 100 or in data communication with a component of the computing device 100.

[0026] In one or more implementations, as used herein, “partition” refers to a collection of computing resources configured by the instructions of the management core to not affect and / or be affected by communications from computing resources of another partition. In one or more implementations, a computing resource belongs to one and only one partition.

[0027] In some implementations, the management core 110A partitions the one or more processor cores 110A-110F into partitions in response to receiving a command, instruction, or the like from a management computing device of a cloud computing system. The management computing device can include a cloud management computing device, a hypervisor, or some other management computing device for the cloud computing system. The management computing device can provide the command, instruction, or the like in response to a terminal user of the cloud computing system requesting cloud computing resources. The command, instruction, or the like can include data specifying a configuration of the requested partition (e.g., a number of processor cores 110; types, processing capabilities, or the like of the processor cores 110; an amount of memory; an amount of storage space, or the like).

[0028] In one or more implementations, management core 110A is further configured to shut down a partition. Management core 110A may shut down a partition in response to receiving commands, instructions, etc., from a management computing device. Shutting down a partition may include restarting components of the partition. Restarting components of the partition may include restoring components to a state as if the computing device 100 had been restarted. For example, restarting processor core 110 may include clearing one or more caches or registers, SAM 112, or other components of processor core 110. Restarting DVM intermediary layer 114 or interrupt intermediary layer 116 may include clearing data from such intermediary layers 114, 116. Restarting a memory block allocated to a partition may include emptying the memory block (e.g., overwriting the memory block with null or garbage values, etc.). The restarted components of the partition can then be used as components in one or more other partitions (e.g., newly created partitions).

[0029] In some implementations, there are instructions—instructions that partition one or more components of computing device 100 into one or more partitions—that execute processor core 110A, including a processor core 110 dedicated to executing such instructions. Processor core 110A may not form part of any partition. In one or more implementations, the processor core 110A dedicated to executing instructions does not include the associated DVM intermediary layer 114A or interrupt intermediary layer 116A. In some implementations, the management computing device of the cloud computing system selects a processor core 110 that is not currently in use or is not currently part of a partition as the processor core for executing instructions.

[0030] In one implementation, computing device 100 includes one or more SAM 112A-112F. For example, as Figure 1 As shown, each processor core 110A-110F may include a corresponding SAM 112A-112F. SAM 112 may include one or more entries, and each entry may include a memory block and a corresponding channel of mesh interconnect, with the channel leading to the memory block. The following section discusses... Figure 2 Further details regarding SAM 112A-112F will be discussed.

[0031] The computing device 100 can include one or more DVM mediation layers 114A-114F. DVMs can include a memory management technique used in multi-processor systems, such as the computing device 100, to efficiently and transparently manage memory across multiple processing cores 110A-110F. Even though physical memory is physically distributed across different locations (e.g., across memory devices 120A-120B), a DVM can create an abstraction of a single unified memory space that is accessible by multiple processors. In some implementations, a first processor core 110B sends a DVM message (sometimes referred to as a “DVM operation” or “transaction”) to another processor core 110C to maintain a DVM of the computing device 100. A DVM mediation layer 114 can include a component disposed between two processor cores of the one or more 110A-110F. In one implementation, a management core 110A configures the DVM mediation layer 114B to be associated with the first processor core 110B. The management core 110A can configure the DVM mediation layer 114B to perform a preventative action in response to the DVM mediation layer 114B receiving a DVM message originating outside of a partition to which the associated first processor core 110B belongs. The management core 110A can configure the DVM mediation layer 114B to modify a DVM message from the associated processor core 110B such that such DVM message does not affect processor cores 110C-110F outside of the original partition. Further information regarding the DVM mediation layers 114A-114F is provided further below.

[0032] The computing device 100 can include one or more interrupt mediation layers 116A-116F. An interrupt mediation layer 116B can include a component disposed between an associated processor core 110B and another processor core 110A, 110C-110F of the one or more processor cores 110A-110F. The management core 110A can configure the interrupt mediation layer 116B to prevent a first interrupt originating from the associated processor core 110B from being provided to processor cores 110A, 110C-110F outside of a partition of the associated processor core 110B. An interrupt can include a request to a processor core 110 to suspend currently executing code in order to handle an event. An interrupt can include a hardware interrupt or a software interrupt (e.g., software-generated interrupt (SGI)). Further information regarding the interrupt mediation layers 116A-116F is discussed further below.

[0033] In one implementation, the memory device 120 can include a data storage device that can store data for use by at least some of the one or more processor cores 110A-110F of the computing device 100. The memory device 120 can include a random access memory (RAM) or some other type of volatile data storage. In some implementations, the computing device 100 can include other types of computing resources (e.g., non-volatile data storage, IO devices, or other types of computing resources) that the management core 110A can allocate (or can allocate a portion of) to a partition.

[0034] Figure 2 An example computing device 100 that has been partitioned by firmware of the management core 110A is depicted. The firmware of the processor core 110A can partition the remaining processor cores 110B-110F into three partitions 202A-202C: (1) a first partition 202A that includes processor cores 110B-110C, DVM mid- layers 114B-114C, interrupt mid-layers 116B-116C, and memory blocks 0x00000000 - 0x37FFFFFF of the memory device 120A; (2) a second partition 202B that includes processor core 110D, DVM mid-layer 114D, interrupt mid-layer 116D, and memory blocks 0x38000000 - 0x6FFFFFFF of the memory device 120A; and (3) a third partition 202C that includes processor cores 110E-110F, DVM mid-layers 114E-114F, interrupt mid-layers 116E-116F, and memory blocks 0x70000000 - 0xDFFFFFFF of the memory device 120A. Although the computing device 100 of FIG. 2 includes three partitions 202A-202C with various numbers of processor cores 110B-110F and various sizes of memory blocks, the computing device 100 can also include other numbers of partitions 202, and the partitions can have other numbers of processor cores 110, memory block sizes, or other component configurations. Figure 2 Although the computing device 100 of FIG. 2 includes three partitions 202A-202C with various numbers of processor cores 110B-110F and various sizes of memory blocks, the computing device 100 can also include other numbers of partitions 202, and the partitions can have other numbers of processor cores 110, memory block sizes, or other component configurations.

[0035] As discussed above, the SAM 112 can include one or more entries that each can map a memory block to a corresponding destination of the mesh interconnect. The destination can lead to the corresponding memory block. For example, the first processor core 110A can have access to four blocks within the first memory device 120A. The SAM 112A of the processor core 110A can be:

[0036] In some implementations, the computing device 100 includes a mesh interconnect. The mesh interconnect can include one or more lanes from one or more processor cores 110A-110F to one or more memory blocks of the memory devices 120A-120B. A single processor core 110A can include multiple lanes from the processor core 110A to different memory blocks of the memory devices 120A-120B. In some implementations, lanes from different processor cores 110A-110F go to the same memory block.

[0037] In some implementations, a SAM 112 is associated with a partition 202 of the one or more partitions 202A-202C. For example, as discussed above, each of the one or more processor cores 110A-110F can include a respective SAM 112. In another example, a subset of the one or more processor cores 110A-110F of a partition 202 can include a respective SAM 112. In some implementations, the SAM 112 is stored in a separate electronic device assigned to the associated partition 202.

[0038] The SAM 112 can limit memory accesses to one or more physical address space blocks allocated to the partition 202 associated with the SAM 112. A physical address space can refer to a memory, a memory mapped IO device, or some other component that can be pointed to by a physical address. In one implementation, the management core 110A partitioning the processor cores 110B-110F into one or more partitions 202A-202C configures the SAMs 112B-112F to include only entries to memory blocks assigned to the partition 202 associated with the SAM 112B-112F. For example, as discussed above, the first partition 202A can include the processor cores 110B-110C, the DVM mediate layers 114B-114C, the interrupt mediate layers 116B-116C, and the memory block 0x00000000 - 0x37FFFFFF of the memory device 120A. The management core 110A can remove from the SAMs 112B-112C any entries that include memory addresses outside of the memory block 0x00000000 - 0x37FFFFFF.

[0039] In some implementations, by removing entries from the SAM 112 that reference memory portions not allocated to the partition 202, the processor cores 112A-112F assigned to the partition 202 are unable to access memory portions assigned to other partitions 202 and thus are unable to interfere with the memory assigned to the other partitions 202.

[0040] In one implementation, the management core 110A partitioning the computing resources into one or more partitions 202A-C includes the management core 110A assigning a partition identifier to each of the one or more DVM shim layers 114A-F. The partition identifier can include data that uniquely identifies the partition 202. The DVM shim layers 114A-F that belong to the same partition 202 can each include the same partition identifier. In response to a DVM shim layer 114 receiving a DVM message that includes a different partition identifier than the partition identifier of the DVM shim layer 114, the DVM shim layer 114 can perform a preventative action.

[0041] In some implementations, the DVM shim layer 114B is configured to receive a DVM message from the processor core 110B associated with the DVM shim layer 114B. The DVM shim layer 114B can insert the partition identifier of the partition 202A associated with the processor core 110B (e.g., the partition identifier assigned to the DVM shim layer 114B by the management core 110A) into the DVM message. The DVM shim layer 114B can then provide the DVM message to one or more other DVM shim layers 114C-F as specified in the DVM message.

[0042] In one or more implementations, the DVM message includes a translation lookaside buffer (TLB) invalidate instruction. The processor core 110 can include a memory cache that stores recent translations of DVMs to physical memory, and this memory cache can be referred to as a TLB. Sometimes, a first processor core 110B interacting with a DVM can cause the TLB of that processor core 110B or the TLB of another processor core 110C-F to expire. Accordingly, the first processor core 110B can send a TLB invalidate instruction to the other processor cores 110C-F so that the other processor cores 110C-F will not use outdated data in their respective TLBs.

[0043] In one implementation, the DVM shim layer 114 receives the TLB invalidate instruction. The DVM shim layer 114 can analyze the TLB invalidate instruction to identify the partition identifier included in the TLB invalidate instruction. In response to the partition identifier of the TLB invalidate instruction being different than the partition identifier assigned to the DVM shim layer 114 (which indicates that the TLB invalidate instruction originated from a processor core 110 outside of the partition 202 of the DVM shim layer 114), the DVM shim layer 114 can perform a preventative action. The preventative action can include the DVM shim layer 114 sending a completion response to the processor core 110 that sent the TLB invalidate instruction. The preventative action can include the DVM shim layer 114 not providing the TLB invalidate instruction to the associated processor core 110.

[0044] In some implementations, the DVM message includes a cache invalidation instruction. Processor core 110 can include a memory cache that stores contents of external memory (e.g., some of the contents stored in first memory device 120A). At times, first processor core 110B, which interacts with external memory, can cause the memory cache of that processor core 110B or the memory cache of another processor core 110C-110F to expire. Accordingly, first processor core 110B can send a cache invalidation instruction to the other processor cores 110C-110F so that the other processor cores 110C-110F will not use stale data in their respective caches.

[0045] In one implementation, DVM mediation layer 114 receives the cache invalidation instruction. DVM mediation layer 114 can analyze the cache invalidation instruction to identify a partition identifier included in the cache invalidation instruction. In response to the partition identifier of the cache invalidation instruction being different from the partition identifier assigned to DVM mediation layer 114 (which indicates that the cache invalidation instruction originated from a processor core 110 outside of the partition 202 of DVM mediation layer 114), DVM mediation layer 114 can perform a preventative action. The preventative action can include DVM mediation layer 114 sending a completion response to the processor core 110 that sent the cache invalidation instruction. The preventative action can include DVM mediation layer 114 not providing the cache invalidation instruction to the associated processor core 110.

[0046] In one or more implementations, the DVM message includes a branch predictor invalidation instruction. Processor core 110 can include a branch predictor, which can include a component that attempts to predict the outcome of a branch instruction prior to executing the branch instruction. At times, first processor core 110B can send a branch predictor invalidation instruction to the additional processor cores 110C-110F so that the other processor cores 110C-110F will not use predictions generated by their respective branch predictors or so that other data associated with the branch predictor is invalidated.

[0047] In one implementation, the DVM shim 114 receives a branch predictor invalidate instruction. The DVM shim 114 can analyze the branch predictor invalidate instruction to identify a partition identifier included in the branch predictor invalidate instruction. In response to the partition identifier of the branch predictor invalidate instruction being different than the partition identifier assigned to the partition 202 of the DVM shim 114 (which indicates that the branch predictor invalidate instruction originated from a processor core 110 outside of the partition 202 of the DVM shim 114), the DVM shim 114 can perform a preventative action. The preventative action can include the DVM shim 114 sending a completion response to the processor core 110 that sent the branch predictor invalidate instruction. The preventative action can include the DVM shim 114 not providing the branch predictor invalidate instruction to the associated processor core 110.

[0048] In one or more implementations, the DVM message includes a DVM synchronization instruction. The first processor core 110B can send the DVM synchronization instruction to another processor core 110C to determine whether a previously issued DVM operation has completed. In some implementations, the DVM shim 114 receives the DVM synchronization instruction. The DVM shim 114 can analyze the DVM synchronization instruction to identify a partition identifier included in the DVM synchronization instruction. In response to the partition identifier of the DVM synchronization instruction being different than the partition identifier assigned to the DVM shim 114 (which indicates that the DVM synchronization instruction originated from a processor core 110 outside of the partition 202 of the DVM shim 114), the DVM shim 114 can perform a preventative action. The preventative action can include the DVM shim 114 sending a completion response to the processor core 110 that sent the DVM synchronization instruction. The preventative action can include the DVM shim 114 not providing the DVM synchronization instruction to the associated processor core 110.

[0049] In some implementations, the preventative action includes the DVM shim 114 or the associated processor core 110B-110F notifying the management core 110A of the DVM message from the processor core 110B-110F outside of the partition 202. Receiving a DVM message from outside of the partition 202 can indicate that there is a security issue, and the management core 110A can perform one or more actions to correct the security issue. For example, the management core 110A can analyze the DVM shim 114 associated with the processor core 110 that sent the DVM message to determine whether the DVM shim 114A-114F is misconfigured. The management core 110A can analyze the software executing on the processor core 110 that sent the DVM message to determine whether the software is malicious. The management core 110A can perform other security related actions.

[0050] In one implementation, the management core 110A configures the interrupt mediation layer 116 to include a processor core identifier for each processor core 110 in the partition 202 to which the interrupt mediation layer 116 belongs. The processor core identifier can include data that uniquely identifies the associated processor core 110 from among other processor cores 110 of the computing device 100. For example, Figure 2 The interrupt mediation layer 116B can store a processor core identifier for the processor core 110B and a processor core identifier for the processor core 110C. In some implementations, the interrupt mediation layer 116B does not store the processor core identifier for the processor core 110B with which the interrupt mediation layer 116B is associated. The management core 110A can configure the interrupt mediation layer 116B to prevent interrupts originating from the processor core 110B or 110C from being provided to processor cores 110A, 110D-110F outside of the partition 202A to which the processor core 110B or 110C belongs.

[0051] Figure 3 A portion of the computing device 100 is depicted that includes processor cores 110B-110F and interrupt mediation layers 116B-116F. The computing device 100 can further include one or more interrupt distributors 302. The interrupt distributors 302 can include components that provide routing or priority configuration of interrupts. The computing device 100 can include one or more interrupt redistributors 304B-304F. The processor core 110B can be associated with an interrupt redistributor 304. The interrupt redistributor 304 can include components that manage priority of interrupts or delivery of interrupts to the processor core 110B, store configuration data related to interrupts, or assist the associated processor core 110B in other interrupt-related functionality. The interrupt mediation layer 116B can be disposed between the interrupt redistributor 304B and the associated processor core 110B. In one implementation, the processor core 110B provides a first interrupt request to the interrupt mediation layer 116B. The interrupt mediation layer 116B can generate one or more second interrupt requests based on the first interrupt request to prevent the interrupt from being provided to processor cores 110C-110F outside of the partition 202 to which the processor core 110B that provided the first interrupt request belongs. The interrupt mediation layer 116B can send the one or more second interrupt requests to the interrupt redistributor 304B associated with the processor core 110B. For each second interrupt request, the interrupt redistributor 304B can generate an interrupt based on the respective interrupt request, and the interrupt redistributor 304B can provide the one or more interrupts to the interrupt distributor 302, which can route the one or more interrupts to one or more destination processor cores 110C-110F.

[0052] In one implementation, the first interrupt includes a broadcast interrupt. The broadcast interrupt can include an interrupt configured to be sent to all processor cores 110A-110F of the computing device 100, all processor cores 110A-110F within an affinity cluster of the computing device 100, or some other group of processor cores 110A-110F. The prevention of the first interrupt originating from the associated processor core 110B from being provided to processor cores 110A-110F outside of the partition 202A of the associated processor core 110B can include the interrupt mediation layer 116B generating an interrupt request targeted to each processor core 110C in the partition 202A of the associated processor core 110B (the interrupt mediation layer 116B can not generate an interrupt request targeted to the associated processor core 110B). Thus, the interrupt mediation layer 116B can replace the broadcast interrupt request with multiple interrupt requests, and each interrupt request can be configured to cause a corresponding second interrupt to be sent to a respective processor core 110C in the partition 202A.

[0053] In some implementations, the first interrupt includes a non-broadcast interrupt. The non-broadcast interrupt can include an interrupt configured to be sent to a list of specific processor cores 110A-110F, and the interrupt can include the list of processor cores 110A-110F. The prevention of the first interrupt originating from the associated processor core 110B from being provided to processor cores 110A-110F outside of the partition 202A of the associated processor core 110B can include the interrupt mediation layer 116B removing from the list of processor cores 110A-110F requested by the first interrupt processor core identifiers of processor cores 110A, 110D-110F that are in a different partition 202A than the associated processor core 110B. Removing the processor core identifiers from the list can include masking the list against processor core identifiers of processor cores 110B-110C in the partition 202A, clearing processor core identifiers of processor cores 110A, 110D-110F outside of the partition 202A from the list, or some other action.

[0054] In response to the interrupt mediation layer 116B generating one or more second interrupt requests, as discussed above, the interrupt mediation layer 116B can provide the second interrupt requests to the associated interrupt redistributor 304B. The interrupt redistributor 304B can generate one or more second interrupts and cause the one or more second interrupts to be provided to one or more processor cores 110C-110F that are targets of the same partition 202 as the associated processor core 110B. The interrupt redistributor 304B can provide the one or more second interrupts to the interrupt distributor 302, which can route the one or more second interrupts to their respective target processor cores 110C-110F.

[0055] In some implementations, the one or more processor cores 110A-110F include an IO processor core 110. The IO processor core 110 can execute instructions of one or more IO devices of the emulated computing device 100. In one implementation, the IO processor core 110 or the management core 110A executing their respective instructions includes allocating a simulated IO device of the one or more simulated IO devices to a partition 202 of the one or more partitions 202A-202C. In this way, each partition 202 can include a set of simulated IO devices that only interact with components of the partition 202 to which the simulated IO devices are allocated. The IO processor core 110 emulating the one or more simulated IO devices can prevent data associated with different partitions 202A-202C and provided to or received from the simulated IO devices from being combined. The IO device emulated by the IO processor core 110 can include a peripheral component interconnect (PCI) device, a memory management unit (MMU), an interrupt distributor, an interrupt redistributor, a serial port, a clock, a power management interface, or some other IO device. In some implementations, the management core 110A intercepts some accesses to the memory devices 120A-120B where the memory accesses are related to IO device functionality.

[0056] Figure 4is a flow diagram illustrating one embodiment of a method 400 for hardware partitioning for a cloud server, in accordance with some implementations of the present disclosure. A processing device, having one or more central processing units (CPUs), one or more graphics processing units (GPUs), and / or a memory device communicatively coupled with the one or more CPUs and / or GPUs, can perform the method 400 and / or one or more of the individual functions, routines, subroutines, or operations of the method 400. In certain implementations, a single processing thread performs the method 400. Alternatively, two or more processing threads can perform the method 400, each thread performing one or more individual functions, routines, subroutines, or operations of the method. In the illustrative example, the processing threads implementing the method 400 can be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization mechanisms). Alternatively, the processing threads implementing the method 400 can be executed asynchronously with respect to one another. The various operations of method 400 can be performed in a different (e.g., reverse) order compared to those illustrated herein without departing from the scope of the present disclosure. Some operations can be omitted within various implementations. Some operations can be performed concurrently. Some operations can be optional. In some implementations, the management core 110A performs one or more operations of the method 400 by executing firmware or other instructions, as discussed herein. In other implementations, a separate electronic device in data communication with the computing device 100 performs one or more operations of the method 400, as discussed herein. Figure 4

[0057] At block 410, the processing logic partitions the one or more processor cores 110B-110F into one or more partitions 202A-202C. Partitioning the processor cores 110B-110F into one or more partitions 202A-202C can include configuring the one or more processor cores 110B-110F as instructions (e.g., firmware executing on the management core 110A) for use in the one or more partitions 202A-202C. For example, as explained above, the instructions can cause the one or more processor cores 110B-110F to be included in the one or more partitions 202A-202C to be rebooted. As discussed above, the first processor core 110B can include a SAM 112B that includes one or more entries, and each entry can include a memory block and a corresponding channel to the memory block. Partitioning the one or more processor cores 110B-110F into one or more partitions 202A-202C can include configuring the SAM 112B by removing an entry of the one or more entries, where the removed entry includes a channel to a memory block that is not assigned to the first partition 202A.

[0058] ​At block 420, the processing logic configures the DVM shim 114B to include a first partition identifier associated with a first partition 202A of the one or more partitions 202A-202C. For example, as discussed above, the instruction (e.g., firmware executing on the management core 110A) can include an instruction to assign the first partition identifier to the DVM shim 114B. The instruction can configure the DVM shim 114B to insert the partition identifier of the first partition 202A in DVM messages received from the associated processor core 110B.

[0059] At block 430, the processing logic configures the DVM shim 114B to perform a preventative action in response to receiving, at the DVM shim 114B, a first DVM message that includes a second partition identifier different from the first partition identifier. For example, as discussed above, the preventative action can include the DVM shim 114B sending a completion response to the processor core 110D-110F that sent the first DVM message, the DVM shim 114B not providing the first DVM message to the associated processor core 110B, the DVM shim 114B discarding the first DVM message, the DVM shim 114B sending a response (e.g., null data) to the processor core 110D-110F that sent the first DVM message, the DVM shim 114B or the associated processor core 110B notifying the management core 110A of the DVM message from the processor core 110D-110F outside of the partition 202A, or some other preventative action.

[0060] At block 440, the processing logic configures the interrupt shim 116B to be associated with the first processor core 110B (e.g., the processor core 110 associated with the interrupt shim 116B). Configuring the interrupt shim 116B can include an instruction (e.g., firmware executing on the management core 110A) to configure the interrupt shim 116B to prevent a first interrupt originating from the associated processor core 110B from being provided to processor cores 110D-110F outside of the partition 202A of the associated processor core 110B. Configuring the interrupt shim 116B can include the interrupt shim 116 storing processor core identifiers for each processor core 110B-110C in the partition 202A to which the interrupt shim 116B belongs.

[0061] At block 450, the processing logic configures the interrupt mediation layer 116B to prevent a first interrupt originating from the first processor core 110B from being provided to processor cores 110C-110F outside of the first partition 202A. As discussed above, for a broadcast interrupt, the interrupt mediation layer 116B can cause one or more second interrupts based on the first interrupt to be provided to each processor core 110B-110C in the first partition 202A. The interrupt mediation layer 116B can generate an interrupt request targeted to each processor core 110C-110F in the partition 202A and provide the interrupt request to the interrupt re-distributor 304B to generate one or more corresponding second interrupts, and the interrupt re-distributor 304B and interrupt distributor 302 can route the second interrupts to the respective processor cores 110C within the partition 202A, as discussed above. For a non-broadcast interrupt, the interrupt mediation layer 116B can remove from the list of processor cores 110B-110F of the interrupt request processor core identifiers that identify processor cores 110A, 110D-110F that are not in the same partition 202A as the associated processor core 110B.

[0062] Figure 5 FIG. 5 is a flow diagram illustrating one embodiment of a method 500 for operating a DVM mediation layer 114, in accordance with some implementations of the present disclosure. The DVM mediation layer 114 can perform the method 500 and / or one or more of the individual functions, routines, subroutines, or operations of the method 500. In some implementations, a single processing thread performs the method 500. Alternatively, two or more processing threads can perform the method 500, each thread performing one or more individual functions, routines, subroutines, or operations of the method. In the illustrative example, the processing threads implementing the method 500 can be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization mechanisms). Alternatively, the processing threads implementing the method 500 can be performed asynchronously with respect to one another. The various operations of method 500 can be performed in the order shown in FIG. 5, in a different, e.g., reverse, order, or concurrently. Figure 5 Some operations of the method 500 can be performed concurrently with other operations. Some operations can be optional.

[0063] At block 510, the DVM mediation layer 114B obtains a first partition identifier. The first partition identifier can be associated with a first partition 202A, and the DVM mediation layer 114B can belong to the first partition 202A. For example, the DVM mediation layer 114B can receive the first partition identifier from a management core 110A. The DVM mediation layer 114B can store the first partition identifier.

[0064] At block 520, the DVM shim layer 114B obtains the DVM message. For example, the first DVM shim layer 114B can receive the DVM message from the processor core 110. At block 530, the DVM shim layer 114B determines that the DVM message includes a second partition identifier. The second partition identifier can be different from the first partition identifier, indicating that the DVM message originated outside of the first partition 202A to which the DVM shim layer 114B belongs.

[0065] At block 540, the DVM shim layer 114B performs a preventative action. The preventative action can prevent the DVM message from affecting computing resources of the first partition 202A. For example, as discussed above, the DVM message can include a TLB invalidate instruction, and the preventative action can include the DVM shim layer 114B sending a completion response to the processor core 110 that sent the TLB invalidate instruction. The preventative action can further include the DVM shim layer 114B not providing the TLB invalidate instruction to the processor core 110B belonging to the first partition 202A.

[0066] Figure 6 is a flow diagram illustrating one embodiment of a method 600 for operating an interrupt shim layer 116, in accordance with some implementations of the present disclosure. The interrupt shim layer 116 can perform the method 600 and / or one or more of the individual functions, routines, subroutines, or operations of the method 600. In some implementations, a single processing thread performs the method 600. Alternatively, two or more processing threads can perform the method 600, each thread performing one or more individual functions, routines, subroutines, or operations of the method. In the illustrative example, the processing threads implementing the method 600 can be synchronized (e.g., using semaphores, critical sections, and / or other thread synchronization mechanisms). Alternatively, the processing threads implementing the method 600 can be executed asynchronously with respect to one another. The various operations of method 600 can be performed in the order shown in FIG. 6, in a different, e.g., reverse, order, or concurrently. Figure 6 Some operations of the method 600 can be performed concurrently with other operations. Some operations can be optional.

[0067] At block 610, the interrupt shim layer 116B is associated with the processor core 110B. The processor core 110B can belong to the first partition 202A. If the first partition 202A includes multiple processor cores 110B-110C, block 610 can include the interrupt shim layer 116B being associated with each processor core 110B-110C belonging to the first partition 202A. Being associated with the processor core 110B can include the interrupt shim layer 116 storing a processor core identifier of the associated processor core 110B.

[0068] At block 620, the interrupt mediation layer 116B obtains a first interrupt. The first interrupt can originate from a processor core 110B associated with the interrupt mediation layer 116B. At block 630, the interrupt mediation layer 116B determines that the first interrupt is targeted to one or more processor cores 110 outside of the first partition 202A. Determining that the first interrupt is targeted to one or more processor cores 110 outside of the first partition 202A can include checking a type of the first interrupt (e.g., broadcast, non-broadcast, etc.), a list of destinations of the first interrupt (e.g., a list of processor core identifiers corresponding to processor cores 110 to which the interrupt is to be sent), or other data contained in or associated with the first interrupt.

[0069] At block 640, the interrupt mediation layer 116B prevents the first interrupt from being provided to the processor cores 110D-110F outside of the first partition 202A. As discussed above, for a broadcast interrupt, the interrupt mediation layer 116B can cause one or more second interrupts based on the first interrupt to be provided to each of the processor cores 110B-110C in the first partition 202A. For a non-broadcast interrupt, the interrupt mediation layer 116B can remove from a list of processor cores 110B-110F of the first interrupt processor core identifiers that identify processor cores 110A, 110D-110F that are not in the same partition 202A as the processor core 110B.

[0070] In one implementation, the one or more processor cores 110A-110F are disposed on the same computing device 100. The computing device 100 can include a system on a chip (SoC), an application-specific integrated circuit (ASIC), or some other integrated circuit (IC). The one or more DVM mediation layers 114A-114F, the one or more interrupt mediation layers 116A-116F, or other components discussed herein can be disposed on the same computing device 100.

[0071] In some implementations, one or more processor cores 110 of a partition 202 execute firmware or a bootloader provided by an end user of a cloud computing system. For example, a management core 110A can generate a partition 202 that includes one or more components (e.g., processor cores 110, memory blocks, etc.), and the management core 110A can receive firmware or a bootloader and store them in a memory block of the partition 202. The management core 110A can provide the memory locations of the firmware or the bootloader to the processor cores 110 of the partition, so the processor cores 110A can execute the firmware or the bootloader.

[0072] In some implementations, partition 202 is configured to perform a confidential computing environment. Confidential computing includes providing a hardware-based trusted execution environment (TEE) that executes on one or more hardware components of a computing device. The TEE can include a secure enclave that is isolated from data and hardware outside of the TEE such that data and processes within the TEE cannot be directly accessed by other hardware components, operating systems, or other software of the computing device that includes the TEE. The TEE can be secured using embedded encryption keys, and embedded attestation operations can prevent access to those keys except for authorized application code. Attempts by unauthorized code can result in the denial of providing the keys to the code. Confidential computing can include the TEE receiving encrypted data, the TEE decrypting the encrypted data using encryption keys, the TEE processing unencrypted data using authorized code, the TEE encrypting data resulting from the processing, and the TEE outputting encrypted data from the TEE. In this way, in some instances, encrypted data can only be processed in the TEE, which is isolated from and secure from other portions of the computing device.

[0073] In one implementation, partition 202 can include a TEE. The TEE can include one or more processor cores 110, one or more DVM mediate layers 114, one or more interrupt mediate layers, one or more memory blocks of one or more memory devices 120, or other components of partition 202. The TEE can attest to an initial state of partition 202 and encrypt data in memory blocks belonging to partition 202. The TEE can prevent access by unauthorized code associated with other partitions 202 or other computing devices using the partition 202 isolation mechanisms and processes discussed herein. In some implementations, the TEE includes a secure enclave within processor core 110 that is isolated from data and hardware outside of processor core 110 such that data and processes within the TEE cannot be directly accessed by other hardware or software of computing device 100.

[0074] Figure 7 is a block diagram illustrating an example computer system 700, in accordance with implementations of the present disclosure. The computer system can be a computing device (e.g., Figure 1The computer system 700 can operate in a client-server network environment or a peer-to-peer network environment, on a server or as a peer machine in peer-to-peer (or distributed) network environments. The machine can be a server, a client, a peer node, or some other type of machine in a server-client network environment, a peer-to-peer network environment, or some other type of network environment. Further, while only a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to

[0075] The example computer system 700 can include a processing device 702, volatile memory 704, non-volatile memory 706 (e.g., flash memory, static random access memory (SRAM), etc.), and / or data storage device 716, which communicate with one another via a bus 730.

[0076] The processing device 702 can be representative of one or more general- purpose processing devices such as a microprocessor, a CPU, a GPU, a processor core (e.g., processor core 110 of computing device 100), a graphics processing unit (GPU), a Figure 1 The processing device 702 can be representative of one or more general- purpose processing devices such as a microprocessor, a CPU, a GPU, a processor core (e.g., processor core 110 of computing device 100), a graphics processing unit (GPU), a

[0077] The volatile memory 704 can include read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), double data rate (DDR SDRAM), or DRAM (RDRAM), or some other type of volatile memory. The volatile memory 704 can store instructions 726 for execution by the processing device 702. Figure 1 The volatile memory 704 can include memory devices 120A-120B of computing device 100. The volatile memory 704 can store at least a portion of the instructions 726.

[0078] The computer system 700 can further include a network interface device 708. The network interface device 708 can facilitate data communications between the computing device and other devices. The computing device 700 also can include a video display unit 710 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an input device 712 (e.g., a keyboard and a pointing device such as a mouse, a motion sensing input device, a touchscreen), a cursor control device 714 (e.g., a mouse), and a signal generation device 718 (e.g., a speaker).

[0079] The data storage device 716 can include a non-transitory machine-readable storage medium 724 (also can be a computer-readable storage medium) on which is stored one or more sets of instructions 726. The instructions can embody one or more of the methods or logic described herein. The instructions can also reside completely, or at least partially, within the volatile memory 704 and / or within the processing device 702 during execution thereof by the computer system 700, the volatile memory 704 and the processing device 702 also constituting machine-readable storage media that can store instructions. The instructions 726 can further be transmitted or received over a network 720 via the network interface device 708.

[0080] In one implementation, the instructions 726 include instructions for hardware partitioning of a cloud server. The instructions 726 can include firmware (e.g., firmware of the management core 110A). The instructions 726 can include instructions for partitioning one or more components of the computing device 100 into one or more partitions 202. The instructions 726 can include instructions provided to components of the computing device 100, such as the DVM mediation layer 114 or the interrupt mediation layer 116, to perform operations as discussed herein.

[0081] While the computer-readable storage medium 724 (machine-readable storage medium) is shown in an example implementation to be a single medium, the terms “computer-readable storage medium” and “machine-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store the one or more sets of instructions. The terms “computer-readable storage medium” and “machine-readable storage medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by a machine and that cause the machine to perform any one or more of the methodologies of the present disclosure. The terms “computer-readable storage medium” and “machine-readable storage medium” accordingly shall be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media.

[0082] In the foregoing description, numerous specific details are set forth. However, it is understood that embodiments of the disclosure can be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the present disclosure.

[0083] Some portions of the detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, is conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0084] It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless specifically stated otherwise as apparent from the following discussion, it is appreciated that throughout the description, discussions utilizing terms such as "receiving", "displaying", "moving", "adjusting", "replacing", "determining", "playing", or the like, refer to the actions and processes of a computer system, or similar electronic computing device, that manipulates and transforms data represented as physical (e.g., electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system memories or registers or other such information storage, transmission or display devices.

[0085] For simplicity of explanation, the methods (e.g., methods 400, 500, or 600) are depicted and described as a series of acts. However, acts in accordance with this disclosure can occur in various orders and / or concurrently, and with other acts not presented and described herein. Furthermore, not all illustrated acts can be required to implement the methods in accordance with the disclosed subject matter. In addition, those skilled in the art will understand and appreciate the context of the methods in accordance with the disclosed subject matter and that act can be implemented by a structure as would be known or is taught by the present disclosure.

[0086] Certain implementations of the present disclosure also relate to an apparatus for performing the operations herein. This apparatus can be specially constructed for the intended purposes, or it can include a general purpose computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program can be stored in a computer readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magnetic-optical disks, read-only memories (ROMs), random access memories (RAMs), EPROMs, EEPROMs, magnetic or optical cards, or any type of media suitable for storing electronic instructions.

[0087] Reference throughout this specification to “one implementation”, “an implementation”, “some implementations”, “one embodiment”, “an embodiment” or “some embodiments” means that a particular feature, structure, or characteristic described in connection with the implementation or embodiment is included in at least one implementation or embodiment. Thus, the appearances of the phrase “in one implementation” or “in an implementation” or other similar phrases in various places throughout this specification are not necessarily all referring to the same implementation. Additionally, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or”. Furthermore, the word “example” or similar phrases denoting examples are used herein to mean serving as an example, instance, or illustration. Any aspect or design described herein as “example” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, the word “example” or similar phrases are used as a tool for

[0088] The use of “first”, “second”, “third”, etc. throughout the disclosure is merely for clarity and distinguishing purposes and does not imply a particular order of assembly or operation. Further, in some implementations, unless explicitly stated otherwise, reference to a “first” component and a “second” component can refer to the same component.

[0089] As used in the specific description of implementations or in the claims, the terms “includes”, “including”, “has”, “contains”, variants thereof, and other similar words are meant to be inclusive in a manner similar to the term “comprising” as an open transition word without precluding any additional or other elements.

[0090] As used in this application, the terms "component," "module," "system" and the like are generally intended to refer to a computer-related entity, either hardware (e.g., a circuit), software, a combination of hardware and software, or an entity that is related to an operational machine with one or more specific functionalities. For example, a component can be, but is not limited to being, a process running on a processor (e.g., a digital signal processor), a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a controller and the controller can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, co-resident, and / or distributed amongst one computer or across multiple computers. Further, a "device" can come in the form of specially designed hardware; a general purpose hardware specially designed to execute software that makes the hardware specially designed for a particular function (e.g., generating points of interest and / or descriptors); software on a computer readable medium; or a combination thereof.

[0091] The aforementioned systems, circuits, modules and the like can be described as interacting between several components and / or blocks. It can be appreciated that such systems, circuits, components, blocks and the like can include those components or specified sub-components, some of the specified components or sub-components, and / or additional components, and according to various permutations and combinations of the foregoing. Sub-components can also be implemented as components communicatively coupled to other components rather than included within parent components (hierarchically). Additionally, it should be noted that one or more components can be combined into a single component providing aggregate functionality or separated into several separate sub-components, and that any one or more intermediate layers, such as a management layer, can be provided to communicatively couple to such sub-components in order to provide integrated functionality. Any component described herein can also interact with one or more other components not specifically described herein but known by those of skill in the art.

[0092] It is to be understood that the above description is intended to be illustrative, and not restrictive. Many other implementations will be apparent to those of skill in the art upon reading and understanding the above description. The scope of the disclosure should, therefore, be determined not with reference to the above description, but instead with reference to the appended claims, along with their full scope of equivalents.

Claims

1. A system comprising: a plurality of processor cores including a first processor core that executes instructions to partition at least a portion of the plurality of processor cores into one or more partitions; a plurality of distributed virtual memory (DVM) mediators, wherein each DVM mediator of the plurality of DVM mediators: includes a respective partition identifier that identifies a partition of the one or more partitions, and in response to receiving a first DVM message that includes a partition identifier that is different from the respective partition identifier of the DVM mediator, performs a preventative action; and a plurality of interrupt mediators, wherein each interrupt mediator of the plurality of interrupt mediators: is associated with a respective processor core of the plurality of processor cores, and prevents a first interrupt originating from the respective processor core from being provided to processor cores outside of the partition of the respective processor core.

2. The system of claim 1, further comprising a plurality of system address map (SAM), wherein each SAM: is associated with a respective partition of the one or more partitions; and restricts memory accesses to a block of physical address space that is allocated to the respective partition.

3. The system of claim 2, further comprising a mesh interconnect coupled to the plurality of processor cores and a memory device, wherein each SAM of the plurality of SAMs includes a plurality of entries, each entry including a memory block and a corresponding lane of the mesh interconnect to the memory block.

4. The system of claim 1, wherein: the first DVM message includes a translation lookaside buffer (TLB) invalidate instruction; and the preventative action includes sending a completion response to a processor core of the plurality of processor cores that sent the first DVM message.

5. The system of claim 1, wherein: the first DVM message includes a cache invalidate instruction; and the preventative action includes sending a completion response to a processor core of the plurality of processor cores that sent the first DVM message.

6. The system of claim 1, wherein each DVM mediator of the plurality of DVM mediators further: receives a second DVM message from a corresponding processor core associated with the DVM mediator; and inserts the partition identifier of the partition associated with the corresponding processor core into the second DVM message.

7. The system of claim 1, wherein the first interrupt includes a software generated interrupt (SGI).

8. The system of claim 1, wherein: the first interrupt includes a broadcast interrupt; and preventing the first interrupt from being provided to processor cores outside of the partition of the respective processor core includes causing one or more second interrupts based on the first interrupt to be provided to each processor core in the partition of the respective processor core.

9. The system of claim 1, wherein: the system further comprises an input / output (IO) processor core that executes instructions to emulate one or more IO devices; and the first interrupt includes an IO interrupt. the first processor core of the plurality of processor cores is not included in any of the one or more partitions.

10. The system of claim 1, wherein the first processor core of the plurality of processor cores is not included in any of the one or more partitions.

11. The system of claim 1, wherein each DVM shim layer of the plurality of DVM shim layers is associated with processor cores belonging to the partition identified by the partition identifier of the DVM shim layer.

12. A method comprising: partitioning a plurality of processor cores into one or more partitions; configuring a distributed virtual memory (DVM) shim layer to include a first partition identifier associated with a first partition of the one or more partitions; configuring the DVM shim layer to perform a preventative action in response to receiving a first DVM message that includes a second partition identifier different from the first partition identifier; configuring an interrupt shim layer to be associated with a first processor core of the plurality of processor cores, the first processor core belonging to the first partition; and configuring the interrupt shim layer to prevent a first interrupt originating from the first processor core from being provided to processor cores outside of the first partition.

13. The method of claim 12, wherein the plurality of processor cores are disposed on a same system on chip (SoC).

14. The method of claim 12, wherein: the first processor core includes a system address map (SAM) that includes a plurality of entries, each entry including a memory block and a corresponding lane to the memory block; and partitioning the plurality of processor cores into the one or more partitions includes configuring the SAM by removing an entry of the plurality of entries, wherein the removed entry includes a lane pointing to a memory block that is not assigned to the first partition.

15. The method of claim 12, wherein: the first DVM message includes a translation lookaside buffer (TLB) invalidate instruction; and performing the preventative action includes sending a completion response to a processor core of the plurality of processor cores that sent the first DVM message.

16. The method of claim 12, wherein: the first DVM message includes a branch predictor invalidate instruction; and the preventative action includes sending a completion response to a processor core of the plurality of processor cores that sent the first DVM message.

17. The method of claim 12, further comprising: receiving, at the DVM shim layer, a second DVM message from a processor core of the plurality of processor cores that is associated with the first partition; and inserting the first partition identifier into the second DVM message.

18. The method of claim 12, wherein: the first interrupt includes a broadcast interrupt; and the interrupt shim layer is configured to prevent the broadcast interrupt from being provided to processor cores outside of the first partition. ​ ​ Preventing the first interrupt from being provided to processor cores outside of the first partition at the interrupt mediation layer includes causing one or more second interrupts based on the first interrupt to be provided to each processor core in the first partition.

19. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations comprising: partitioning a plurality of processor cores into one or more partitions; configuring a distributed virtual memory (DVM) mediation layer to include a first partition identifier associated with a first partition of the one or more partitions; configuring the DVM mediation layer to perform a preventative action in response to receiving a first DVM message that includes a second partition identifier different from the first partition identifier; configuring an interrupt mediation layer to be associated with a first processor core of the plurality of processor cores, the first processor core belonging to the first partition; and configuring the interrupt mediation layer to prevent a first interrupt originating from the first processor core from being provided to processor cores outside of the first partition.

20. The computer-readable storage medium of claim 19, wherein: the first DVM message includes a translation lookaside buffer (TLB) invalidate instruction; and performing the preventative action includes sending a completion response to a processor core of the plurality of processor cores that sent the first DVM message. ​

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