High-efficiency heat dissipation method and system integrating super-junction with SiC

Abstract

The application relates to the technical field of power semiconductors, and relates to a high-efficiency heat dissipation method and system integrated with super junction and SiC, which comprises the following steps: depositing a transition layer on a super junction silicon epitaxial wafer to obtain a transition super junction wafer, bonding the transition super junction wafer at low temperature to obtain a heterogeneous integrated wafer, thinning and activating the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer, constructing a micro flow channel by using an activated silicon carbide layer and a heat dissipation path to obtain a sealed micro flow channel, detecting the cooling performance of the sealed micro flow channel, obtaining an optimal heat dissipation path, cooling the optimal heat dissipation path, recording the output power of the device, obtaining an output power set, obtaining an optimal flow speed based on the gradient flow speed and the output power set, obtaining a plurality of heat dissipation wafers based on the optimal heat dissipation path and the optimal flow speed, verifying the reliability of the plurality of heat dissipation wafers, and obtaining a plurality of qualified heat dissipation wafers. The application can solve the problems of performance attenuation and reliability decline caused by heat accumulation in the integration of super junction and SiC.

Description

Technical Field

[0001] This invention relates to the field of power semiconductor technology, and in particular to a high-efficiency heat dissipation method and system for superjunction and SiC integration. Background Technology

[0002] With the rapid development of the power semiconductor industry, new challenges have emerged in heat dissipation methods for superjunction and SiC integration. Superjunction silicon carbide heterostructure wafers can be fabricated through low-temperature bonding, followed by microfluidic heat dissipation path selection and flow rate optimization to address the performance degradation and reliability decline caused by heat accumulation in superjunction and SiC integration.

[0003] Currently, heat dissipation of semiconductor devices is mainly achieved through thermal interface materials and metal heat sinks. Although existing heat dissipation methods have a certain cooling effect, they suffer from low cooling efficiency, high energy consumption, and inaccurate heat dissipation. Therefore, optimizing the heat dissipation method for superjunction and SiC integration is of great significance for improving the working efficiency of superjunction and SiC integration. Summary of the Invention

[0004] This invention provides a highly efficient heat dissipation method and a computer-readable storage medium for superjunction-SiC integration. Its main purpose is to solve the problem of performance degradation and reliability reduction caused by heat accumulation in superjunction-SiC integration.

[0005] To achieve the above objectives, the present invention provides a high-efficiency heat dissipation method for superjunction and SiC integration, comprising:

[0006] Obtain multiple superjunction silicon epitaxial wafers, and perform the following operation on each of the multiple superjunction silicon epitaxial wafers:

[0007] A transition layer was deposited on a superjunction silicon epitaxial wafer to obtain a transition supercrystal circle;

[0008] The transition supercrystallized wafer is used to perform low-temperature bonding under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer;

[0009] The heterogeneous integrated wafer is thinned and activated to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer;

[0010] Obtain three heat dissipation paths, and perform the following operations on each of the three heat dissipation paths:

[0011] Microchannels were constructed using an activated silicon carbide layer and a heat dissipation path to obtain sealed microchannels;

[0012] The cooling performance of the sealed microchannel was tested, and a cooling performance score was obtained.

[0013] The cooling performance scores are summarized to obtain three cooling performance scores, and the optimal heat dissipation path is obtained based on the three cooling performance scores;

[0014] The device is cooled using the optimal heat dissipation path at multiple preset gradient flow rates, and the output power is recorded to obtain the output power set.

[0015] Optimal flow velocity is obtained based on gradient flow velocity and output power set;

[0016] Based on the optimal heat dissipation path, optimal flow rate, and thinning of heterogeneous wafers, heat dissipation wafers are obtained, and these heat dissipation wafers are aggregated to obtain multiple heat dissipation wafers;

[0017] Reliability verification was performed on multiple heat dissipation wafers, and multiple qualified heat dissipation wafers were obtained.

[0018] Optionally, the deposition of a transition layer on the superjunction silicon epitaxial wafer to obtain a transition supercrystal wafer includes:

[0019] The superjunction silicon epitaxial wafer and the pre-confirmed glass substrate are temporarily bonded to obtain a bonded wafer;

[0020] The bonded sheets are mechanically ground to obtain ground bonded sheets;

[0021] The thickness of the polished bonded wafer is measured to obtain the silicon thickness. The silicon thickness is compared with a preset silicon thickness threshold. If the silicon thickness is greater than or equal to the silicon thickness threshold, the polished bonded wafer is used as a bonded wafer. The process of mechanically polishing the bonded wafer is repeated until the silicon thickness is less than the silicon thickness threshold. The polished bonded wafer is then used as a qualified bonded wafer.

[0022] If the silicon thickness is less than the silicon thickness threshold, the polished bonded wafer will be considered a qualified bonded wafer.

[0023] The qualified bonded sheets are mechanically polished to obtain polished bonded sheets;

[0024] The polished bonded sheet is back-plated to obtain a wafer with a transition layer;

[0025] The wafer with the transition layer is peeled and cleaned to obtain the transition supercrystal wafer.

[0026] Optionally, the step of using the transition supercrystallized wafer to perform low-temperature bonding under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer includes:

[0027] Obtaining a silicon carbide substrate;

[0028] The silicon carbide substrate is polished to obtain a polished silicon carbide substrate;

[0029] The roughness of the polished silicon carbide substrate was measured to obtain the roughness.

[0030] The roughness is compared with a preset roughness threshold. If the roughness is greater than or equal to the roughness threshold, the polished silicon carbide substrate is used as the silicon carbide substrate. The process of polishing the silicon carbide substrate is repeated until the roughness is less than the roughness threshold. The polished silicon carbide substrate is then used as the qualified polished substrate.

[0031] If the roughness is less than the roughness threshold, the polished silicon carbide substrate is considered a qualified polishing substrate.

[0032] A qualified polished substrate is subjected to deoxidation treatment to obtain a deoxidized substrate;

[0033] The transition supercrystal wafer and the deoxidized substrate are activated and bonded to obtain a heterogeneous integrated wafer.

[0034] Optionally, obtaining the three heat dissipation paths includes:

[0035] A preset electrical power is applied to the thinned heterogeneous wafer, and a thermal image is acquired to obtain a high-temperature image;

[0036] The high-temperature map is mapped to a gridded heat flux matrix, and the coordinates of multiple high-temperature units are obtained using the gridded heat flux matrix;

[0037] By using the coordinates of the multiple high-heat units and the pre-confirmed historical heat dissipation paths, heat dissipation path planning is performed to obtain multiple planned heat dissipation paths;

[0038] A rapid thermal-fluid coupling simulation was performed on multiple planned heat dissipation paths to obtain multiple heat datasets. Each heat dataset corresponds one-to-one with a planned heat dissipation path and includes the highest temperature and the average temperature.

[0039] Three heat dissipation paths were identified based on multiple thermal datasets.

[0040] Optionally, the three heat dissipation paths identified based on multiple heat datasets include:

[0041] Based on multiple highest temperatures and multiple average temperatures from multiple heat datasets, obtain the maximum value of the highest temperature, the minimum value of the highest temperature, and the comprehensive average temperature.

[0042] Perform the following operation on each of the multiple heat datasets:

[0043] The heat dissipation score is calculated using the highest temperature, average temperature, maximum highest temperature, minimum highest temperature, and overall average temperature from the heat dataset. The calculation formula is shown below:

[0044] ,

[0045] in, Indicates the heat dissipation score. This represents the preset heat peak weighting coefficient. This indicates the highest temperature and maximum value. Indicates the minimum value of the highest temperature. Indicates the highest temperature. This represents the preset average temperature weighting coefficient. Indicates the overall average temperature. Indicates average temperature;

[0046] By summing the aforementioned heat dissipation scores, multiple heat dissipation scores are obtained;

[0047] The multiple heat dissipation scores are sorted in descending order to obtain a heat dissipation score sequence. The heat dissipation paths corresponding to the first three heat dissipation scores in the heat dissipation score sequence are summarized to obtain three heat dissipation paths.

[0048] Optionally, the construction of microchannels using an activated silicon carbide layer and a heat dissipation path to obtain sealed microchannels includes:

[0049] Obtain multiple sets of combined parameters;

[0050] Multiple sets of combined parameters were used to perform etching standard tests on the pre-confirmed test silicon layer to obtain multiple etching trenches;

[0051] Multiple trench parameter sets are obtained based on multiple etched trenches, including trench depth, trench width, and bottom surface roughness.

[0052] For each of the multiple trench parameter sets, perform the following operation:

[0053] The etching score is calculated using the trench depth, trench width, and bottom surface roughness from the trench parameter set.

[0054] By summing the etching scores, multiple etching scores are obtained;

[0055] The maximum etching score is obtained based on the multiple etching scores, and the combined parameters corresponding to the maximum etching score are used as the final processing parameters.

[0056] The activated silicon carbide layer is laser-etched using the aforementioned heat dissipation path and final processing parameters to obtain microchannel grooves.

[0057] The pre-confirmed silicon cap plate is bonded to the microchannel groove to obtain a sealed microchannel.

[0058] Optionally, the cooling performance test of the sealed microchannel to obtain a cooling performance score includes:

[0059] Steady-state heat dissipation test was performed on the sealed microchannel to obtain the thermally steady-state microchannel;

[0060] Inlet temperature, outlet temperature, port pressure difference, and coolant flow rate are obtained based on thermal steady-state microchannels;

[0061] Cooling performance is scored using inlet temperature, outlet temperature, port pressure difference, and coolant flow rate. The calculation formula is shown below:

[0062] ,

[0063] in, This indicates the cooling performance rating. This indicates the preset constant power. Indicates coolant flow rate. Indicates the inlet temperature. Indicates the outlet temperature. This indicates the port pressure difference.

[0064] Optionally, obtaining the optimal flow velocity based on gradient flow velocity and output power set includes:

[0065] Curve fitting is performed on the gradient flow velocity and output power set to obtain the flow velocity-power relationship curve;

[0066] Calculate multiple unit flow velocity power gains based on the flow velocity-power relationship curve and the preset flow velocity range;

[0067] Power gain curves are constructed using power gains at multiple unit flow velocities.

[0068] Peak gain is obtained based on multiple unit flow velocity power gains;

[0069] The gain threshold is obtained based on the peak gain.

[0070] The optimal flow rate was determined based on the gain threshold and power gain curve.

[0071] Optionally, the reliability verification of multiple heat dissipation wafers to obtain multiple qualified heat dissipation wafers includes:

[0072] Perform the following operation on each of the multiple heat dissipation wafers;

[0073] A thermal cycling test was performed on the heat dissipation wafer to obtain the tested wafer.

[0074] Interface images are acquired from the tested wafer;

[0075] Delamination detection is performed on the interface image to obtain the delamination area;

[0076] By summing up the delamination areas, multiple delamination areas are obtained;

[0077] The heat dissipation wafers corresponding to delamination areas less than or equal to the delamination area threshold are considered as qualified heat dissipation wafers. The qualified heat dissipation wafers are then aggregated to obtain multiple qualified heat dissipation wafers.

[0078] To achieve the above objectives, the present invention also provides a high-efficiency heat dissipation system integrating a superjunction and SiC, comprising:

[0079] The device bonding activation module is used to acquire multiple superjunction silicon epitaxial wafers, and performs the following operations on each of the multiple superjunction silicon epitaxial wafers:

[0080] A transition layer was deposited on a superjunction silicon epitaxial wafer to obtain a transition supercrystal circle;

[0081] The transition supercrystallized wafer is used to perform low-temperature bonding under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer;

[0082] The heterogeneous integrated wafer is thinned and activated to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer;

[0083] The heat dissipation path planning module is used to obtain three heat dissipation paths and perform the following operations on each of the three heat dissipation paths:

[0084] Microchannels were constructed using an activated silicon carbide layer and a heat dissipation path to obtain sealed microchannels;

[0085] The cooling performance of the sealed microchannel was tested, and a cooling performance score was obtained.

[0086] The cooling performance scores are summarized to obtain three cooling performance scores, and the optimal heat dissipation path is obtained based on the three cooling performance scores;

[0087] The optimal flow rate confirmation module is used to cool the device using the optimal heat dissipation path at multiple preset gradient flow rates and record the device output power to obtain the output power set.

[0088] Optimal flow velocity is obtained based on gradient flow velocity and output power set;

[0089] The sample quality inspection module is used to obtain heat dissipation wafers based on the optimal heat dissipation path, optimal flow rate, and thinning of heterogeneous wafers, and to summarize the heat dissipation wafers to obtain multiple heat dissipation wafers;

[0090] Reliability verification was performed on multiple heat dissipation wafers, and multiple qualified heat dissipation wafers were obtained.

[0091] To address the above problems, the present invention also provides an electronic device, the electronic device comprising:

[0092] Memory, storing at least one instruction; and

[0093] The processor executes the instructions stored in the memory to implement the high-efficiency heat dissipation method for superjunction and SiC integration described above.

[0094] To address the aforementioned problems, the present invention also provides a computer-readable storage medium storing at least one instruction, which is executed by a processor in an electronic device to implement the aforementioned efficient heat dissipation method for superjunction and SiC integration.

[0095] To address the problems described in the background art, this invention obtains multiple superjunction silicon epitaxial wafers and performs the following operations on each of them: depositing a transition layer to obtain a transition supercrystal wafer; performing low-temperature bonding on the transition supercrystal wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer; and thinning and activating the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer. The thinned heterogeneous wafer includes an activated silicon carbide layer. Thus, this embodiment of the invention, through transition layer deposition and low-temperature bonding, heterogeneously integrates superjunction silicon and silicon carbide and thins and activates them, forming a high-quality, low-defect activated silicon carbide layer, facilitating the subsequent direct construction of an efficient heat dissipation layer on top of this layer. Microchannels provide a reliable foundation for heterogeneous wafers. Based on this, the present invention obtains three heat dissipation paths and performs the following operations on each path: constructing a microchannel using an activated silicon carbide layer and the heat dissipation path to obtain a sealed microchannel; testing the cooling performance of the sealed microchannel to obtain a cooling performance score; summing these scores to obtain three cooling performance scores; and obtaining the optimal heat dissipation path based on these three scores. Thus, the present invention, by constructing and measuring three sealed microchannels in parallel on the activated silicon carbide layer and quantitatively comparing the cooling performance scores, quickly identifies the optimal heat dissipation path, providing a reliable basis for subsequent flow rate optimization and avoiding blind trial and error. Furthermore, the present invention utilizes the optimal heat dissipation path to cool at multiple preset gradient flow rates and records the device output power to obtain an output power set. Based on the gradient flow rates and the output power set, the optimal flow rate is obtained. Thus, the present invention, by gradient scanning the flow rate under the optimal heat dissipation path and recording the output power in real time, accurately identifies the best balance between heat dissipation and energy consumption, obtaining the optimal flow rate that ensures device output while avoiding energy waste. Next, this invention obtains heat dissipation wafers based on optimal heat dissipation paths, optimal flow rates, and thinning of heterogeneous wafers. These heat dissipation wafers are then aggregated to obtain multiple heat dissipation wafers. Reliability verification is performed on these multiple heat dissipation wafers, resulting in multiple qualified heat dissipation wafers. It is evident that this invention, by batch-producing and uniformly verifying heat dissipation wafers under optimal heat dissipation paths and optimal flow rates, allows for the simultaneous screening of multiple qualified heat dissipation wafers, ensuring a high degree of consistency in heat dissipation performance and reliability within each batch. Therefore, this invention can solve the problem of performance degradation and reliability decline caused by thermal accumulation in superjunction and SiC integration. Attached Figure Description

[0096] Figure 1 This is a flowchart illustrating a high-efficiency heat dissipation method for superjunction and SiC integration provided in an embodiment of the present invention.

[0097] Figure 2 A functional block diagram of a high-efficiency heat dissipation system integrating superjunction and SiC provided in an embodiment of the present invention;

[0098] Figure 3 This is a schematic diagram of an electronic device that implements the efficient heat dissipation method for superjunction and SiC integration according to an embodiment of the present invention.

[0099] Explanation of reference numerals in the attached figures:

[0100] 10. Electronic device; 11. Processor; 12. Memory; 13. Bus.

[0101] The realization of the objective, functional features and advantages of the present invention will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0102] It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0103] This application provides a high-efficiency heat dissipation method integrating superjunctions and SiC. The executing entity of this high-efficiency heat dissipation method integrating superjunctions and SiC includes, but is not limited to, at least one of the following electronic devices that can be configured to execute the method provided in this application: a server, a terminal, etc. In other words, the high-efficiency heat dissipation method integrating superjunctions and SiC can be executed by software or hardware installed on a terminal device or a server device, and the software can be a blockchain platform. The server includes, but is not limited to, a single server, a server cluster, a cloud server, or a cloud server cluster.

[0104] Reference Figure 1 The diagram shown is a flowchart illustrating a high-efficiency heat dissipation method for superjunction and SiC integration according to an embodiment of the present invention. In this embodiment, the high-efficiency heat dissipation method for superjunction and SiC integration includes:

[0105] S1. Obtain multiple superjunction silicon epitaxial wafers, and perform the following operation on each of the multiple superjunction silicon epitaxial wafers: deposit a transition layer on the superjunction silicon epitaxial wafer to obtain a transition supercrystal circle.

[0106] It should be explained that the process of depositing a transition layer on the superjunction silicon epitaxial wafer to obtain a transition supercrystal circle includes:

[0107] The superjunction silicon epitaxial wafer and the pre-confirmed glass substrate are temporarily bonded to obtain a bonded wafer;

[0108] The bonded sheets are mechanically ground to obtain ground bonded sheets;

[0109] The thickness of the polished bonded wafer is measured to obtain the silicon thickness. The silicon thickness is compared with a preset silicon thickness threshold. If the silicon thickness is greater than or equal to the silicon thickness threshold, the polished bonded wafer is used as a bonded wafer. The process of mechanically polishing the bonded wafer is repeated until the silicon thickness is less than the silicon thickness threshold. The polished bonded wafer is then used as a qualified bonded wafer.

[0110] If the silicon thickness is less than the silicon thickness threshold, the polished bonded wafer will be considered a qualified bonded wafer.

[0111] The qualified bonded sheets are mechanically polished to obtain polished bonded sheets;

[0112] The polished bonded sheet is back-plated to obtain a wafer with a transition layer;

[0113] The wafer with the transition layer is peeled and cleaned to obtain the transition supercrystal wafer.

[0114] Furthermore, the superjunction silicon epitaxial wafer is an epitaxial wafer with a superjunction charge-balance structure, used for subsequent integration with silicon carbide. A glass substrate is a glass substrate used as a temporary support in semiconductor processes. The purpose of using a glass substrate is to provide mechanical support for the superjunction silicon epitaxial wafer during subsequent processing, preventing warping or breakage. Optionally, a borosilicate glass substrate is used as the glass substrate. Temporary bonding is the process of bonding the superjunction silicon epitaxial wafer and its glass substrate under vacuum and then UV curing. The bonded wafer is a composite structure consisting of the superjunction silicon epitaxial wafer and the glass substrate, obtained after temporary bonding. Mechanical polishing is the process of polishing the substrate on the back side of the bonded wafer. The polished bonded wafer is the bonded wafer after mechanical polishing. Optionally, a polishing process is used as the method for mechanical polishing.

[0115] Understandably, thickness measurement is the process of measuring the silicon layer thickness of a polished bonded wafer using a thickness gauge. Optionally, a laser thickness gauge can be used as the thickness measurement method. Silicon thickness is the thickness of the silicon layer obtained through thickness measurement. The silicon thickness threshold is a preset target thickness value, for example, 20 micrometers. A qualified bonded wafer is a polished bonded wafer with a silicon thickness less than or equal to the silicon thickness threshold. Mechanical polishing is the process of planarizing the silicon backside of a qualified bonded wafer using chemical mechanical polishing. The purpose is to eliminate surface damage layers, microcracks, and stress caused by polishing, resulting in a smooth and defect-free silicon surface. A polished bonded wafer is a qualified bonded wafer after mechanical polishing. Back-plating transition is the process of sputtering a transition layer of 20nm titanium, 100nm tantalum, and 50nm nickel onto the silicon backside of the qualified bonded wafer to obtain a wafer with a transition layer. A wafer with a transition layer is the wafer structure after the transition layer has been deposited on the silicon backside. Wafer removal and cleaning is the process of separating the glass substrate from the wafer with the transition layer and removing the colloid to obtain an independent transition superwafer. Transition supercrystal wafers are silicon wafers obtained after wafer removal and cleaning.

[0116] S2. Using the transition supercrystallized wafer under pre-confirmed activation conditions, low-temperature bonding is performed to obtain a heterogeneous integrated wafer.

[0117] It should be explained that the step of using the transition supercrystal wafer to perform low-temperature bonding under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer includes:

[0118] Obtaining a silicon carbide substrate;

[0119] The silicon carbide substrate is polished to obtain a polished silicon carbide substrate;

[0120] The roughness of the polished silicon carbide substrate was measured to obtain the roughness.

[0121] The roughness is compared with a preset roughness threshold. If the roughness is greater than or equal to the roughness threshold, the polished silicon carbide substrate is used as the silicon carbide substrate. The process of polishing the silicon carbide substrate is repeated until the roughness is less than the roughness threshold. The polished silicon carbide substrate is then used as the qualified polished substrate.

[0122] If the roughness is less than the roughness threshold, the polished silicon carbide substrate is considered a qualified polishing substrate.

[0123] A qualified polished substrate is subjected to deoxidation treatment to obtain a deoxidized substrate;

[0124] The transition supercrystal wafer and the deoxidized substrate are activated and bonded to obtain a heterogeneous integrated wafer.

[0125] Further, the silicon carbide substrate is a 6H-SiC single-crystal wafer used as an integration substrate. The polished silicon carbide substrate is a silicon carbide substrate with reduced roughness after chemical mechanical polishing. Roughness detection is a process of quantitatively measuring the flatness of the polished silicon carbide substrate surface. Optionally, an optical profilometer is used as the instrument for roughness detection. Roughness is the surface roughness of the polished silicon carbide substrate obtained through roughness detection. The roughness threshold is a preset upper limit value for surface roughness to achieve successful bonding, for example, 0.5 nm. The roughness threshold is determined based on extensive process experiments. If the roughness is higher than the roughness threshold, too many voids will be generated at the bonding interface, leading to a sharp increase in thermal resistance and a decrease in bonding strength. A qualified polished substrate is a polished silicon carbide substrate with a roughness lower than the roughness threshold. Deoxidation treatment is a process of removing the silicon dioxide generated by oxidation on the surface of the qualified polished substrate. Optionally, immersion in a diluted hydrofluoric acid solution is used as the method for deoxidation treatment. The deoxidized substrate is a qualified polished substrate after deoxidation treatment. Activation bonding involves activating the surface of the deoxidized substrate and the transition layer surface of the transition supercrystal wafer to create dangling bonds and make them hydrophilic, followed by activation at room temperature (e.g., 26°C). The surface of the deoxidized substrate and the transition layer surface of the transition supercrystal wafer are bonded together, and finally annealed at a low temperature (e.g., 400°C). Annealing is performed to enhance bond strength. Heterogeneous integrated wafers are composite wafer structures obtained through activated bonding.

[0126] S3. The heterogeneous integrated wafer is thinned and activated to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer.

[0127] It should be explained that thinning activation is a composite processing procedure performed on the silicon carbide substrate in a heterogeneous integrated wafer. Specifically, the silicon carbide substrate is thinned to a target thickness (e.g., 50 nm) through mechanical grinding and chemical mechanical polishing. ±5 The thinned heterogeneous integrated wafer was obtained; the silicon carbide substrate of the thinned heterogeneous integrated wafer was subjected to pre-confirmed environmental conditions (argon atmosphere protection, temperature 380°C). ±10 The silicon carbide substrate of the annealed heterogeneous integrated wafer is then subjected to annealing to obtain an annealed heterogeneous integrated wafer. The silicon carbide substrate of the annealed heterogeneous integrated wafer is then subjected to oxygen plasma treatment (300W power, 60 seconds) to obtain a thinned heterogeneous wafer. The thinned heterogeneous wafer is the wafer structure obtained after thinning and activation. The activated silicon carbide layer is the silicon carbide substrate in the thinned heterogeneous wafer after thinning and activation.

[0128] S4. Obtain three heat dissipation paths, and perform the following operations on each of the three heat dissipation paths: construct microchannels using the activated silicon carbide layer and the heat dissipation path to obtain sealed microchannels.

[0129] It should be explained that the three heat dissipation paths are as follows:

[0130] A preset electrical power is applied to the thinned heterogeneous wafer, and a thermal image is acquired to obtain a high-temperature image;

[0131] The high-temperature map is mapped to a gridded heat flux matrix, and the coordinates of multiple high-temperature units are obtained using the gridded heat flux matrix;

[0132] By using the coordinates of the multiple high-heat units and the pre-confirmed historical heat dissipation paths, heat dissipation path planning is performed to obtain multiple planned heat dissipation paths;

[0133] A rapid thermal-fluid coupling simulation was performed on multiple planned heat dissipation paths to obtain multiple heat datasets. Each heat dataset corresponds one-to-one with a planned heat dissipation path and includes the highest temperature and the average temperature.

[0134] Three heat dissipation paths were identified based on multiple thermal datasets.

[0135] Furthermore, the electrical power is the product of a constant operating voltage and current (e.g., 100W) applied to generate heat in the superjunction devices within the thinned heterogeneous wafer, used to simulate the heat source distribution under actual operating conditions. Thermal image acquisition is the process of scanning and recording the temperature field distribution on the surface of the thinned heterogeneous wafer after the electrical power is applied and thermal steady-state is reached. Optionally, an infrared thermal imager is used as the instrument for thermal image acquisition. Thermal steady-state is defined as the rate of temperature change at any point on the thinned heterogeneous wafer over time being less than a preset threshold (e.g., temperature fluctuations at all measuring points do not exceed ±0.1°C over 60 consecutive seconds). The high-temperature map (HTMA) is a heat distribution map obtained through thermal imaging. It visually displays the temperature levels of different regions on the surface of the thinned heterogeneous wafer using different colors, helping to identify hot spots with concentrated heat flux. The gridded heat flux matrix divides the HTMA into N×M uniform grid cells, and based on the center temperature of each grid cell, obtains a numerical matrix that quantitatively describes the heat flux distribution across the entire wafer surface. For example, (2, 3, 40) indicates that the temperature of the grid cell in the second row and third column of the HTMA is 40. The coordinates of high-temperature elements are those whose center temperature exceeds a preset temperature threshold (e.g., 90°C) within the gridded heat flux matrix. The index coordinates corresponding to the grid cells in the heat map. For example, (2, 3) represents the grid cell in the second row and third column of the heat map. Historical heat dissipation paths are microchannel geometric layout patterns with efficient heat dissipation effects summarized from historical device designs, such as serpentine, grid, back-shaped, or biomimetic fractal structures. Heat dissipation path planning is the process of using the coordinates of the multiple heat-generating cells as key path points, combined with the microchannel geometric layout patterns in the historical heat dissipation path library, and applying a path optimization algorithm (such as a genetic algorithm) to obtain a microchannel centerline trajectory connecting the regions corresponding to the coordinates of the multiple heat-generating cells. Optionally, a genetic algorithm is used as the method for heat dissipation path planning. Planning a heat dissipation path is the spatial geometric trajectory of a microchannel centerline obtained through heat dissipation path planning.

[0136] Understandably, rapid thermal-fluid coupling simulation involves numerically simulating a planned heat dissipation path on a 3D model to quickly calculate the temperature field distribution of the thinned heterogeneous wafer and the fluid pressure drop within the microchannels corresponding to the planned heat dissipation path when the coolant flows through them. Optionally, CFD simulation can be used as the method for rapid thermal-fluid coupling simulation. The heat dataset is a collection of rapid thermal-fluid coupling simulation results corresponding to the planned heat dissipation path.

[0137] It should be explained that the three heat dissipation paths identified based on multiple heat datasets include:

[0138] Based on multiple highest temperatures and multiple average temperatures from multiple heat datasets, obtain the maximum value of the highest temperature, the minimum value of the highest temperature, and the comprehensive average temperature.

[0139] Perform the following operation on each of the multiple heat datasets:

[0140] The heat dissipation score is calculated using the highest temperature, average temperature, maximum highest temperature, minimum highest temperature, and overall average temperature from the heat dataset. The calculation formula is shown below:

[0141] ,

[0142] in, Indicates the heat dissipation score. This represents the preset heat peak weighting coefficient. This indicates the highest temperature and maximum value. Indicates the minimum value of the highest temperature. Indicates the highest temperature. This represents the preset average temperature weighting coefficient. Indicates the overall average temperature. Indicates average temperature;

[0143] By summing the aforementioned heat dissipation scores, multiple heat dissipation scores are obtained;

[0144] The multiple heat dissipation scores are sorted in descending order to obtain a heat dissipation score sequence. The heat dissipation paths corresponding to the first three heat dissipation scores in the heat dissipation score sequence are summarized to obtain three heat dissipation paths.

[0145] Furthermore, the maximum maximum temperature is the highest temperature among multiple maximum temperatures. The minimum maximum temperature is the lowest maximum temperature among multiple maximum temperatures. The overall average temperature is the average of multiple maximum temperatures. The heat peak weighting coefficient is a weighting factor characterizing the influence of the maximum temperature on heat dissipation performance, for example, 0.6. The average temperature weighting coefficient is a weighting factor characterizing the influence of the average temperature on heat dissipation performance, for example, 0.4. The heat dissipation score is a numerical value used to quantitatively evaluate the heat dissipation effect of the corresponding heat dissipation path, calculated using the maximum temperature, average temperature, maximum maximum temperature, minimum maximum temperature, and overall average temperature in the heat dataset. A higher heat dissipation score indicates a better heat dissipation effect of the corresponding heat dissipation path. The heat dissipation score sequence is a sequence obtained by sorting multiple heat dissipation scores in descending order. The three heat dissipation paths are the heat dissipation paths corresponding to the first three heat dissipation scores in the heat dissipation score sequence.

[0146] It should be explained that the construction of microchannels using an activated silicon carbide layer and a heat dissipation path to obtain sealed microchannels includes:

[0147] Obtain multiple sets of combined parameters;

[0148] Multiple sets of combined parameters were used to perform etching standard tests on the pre-confirmed test silicon layer to obtain multiple etching trenches;

[0149] Multiple trench parameter sets are obtained based on multiple etched trenches, including trench depth, trench width, and bottom surface roughness.

[0150] For each of the multiple trench parameter sets, perform the following operation:

[0151] The etching score is calculated using the trench depth, trench width, and bottom surface roughness from the trench parameter set.

[0152] By summing the etching scores, multiple etching scores are obtained;

[0153] The maximum etching score is obtained based on the multiple etching scores, and the combined parameters corresponding to the maximum etching score are used as the final processing parameters.

[0154] The activated silicon carbide layer is laser-etched using the aforementioned heat dissipation path and final processing parameters to obtain microchannel grooves.

[0155] The pre-confirmed silicon cap plate is bonded to the microchannel groove to obtain a sealed microchannel.

[0156] Furthermore, the combined parameters are a combination of adjustable parameters in the laser etching process, including laser single-pulse energy, scanning speed, repetition frequency, and number of processing cycles. The test silicon layer is a single-crystal silicon wafer with similar laser absorption rate and thermophysical properties to the activated silicon carbide layer, used for exploring etching process parameters without consuming valuable production wafers. Standard etching testing is the process of etching a straight trench with a standard length and orientation on the test silicon layer using a specific set of combined parameters. The etched trench is a groove formed on the test silicon layer through standard etching testing. The trench parameter set is a set of key parameters used to characterize the geometry and surface quality of the etched trench, including trench depth, trench width, and bottom surface roughness. Trench depth is the vertical distance from the bottom of the etched trench to the surface of the test silicon layer. Trench width is the distance between the two edges at the opening of the etched trench. Bottom surface roughness is a quantitative indicator of the flatness of the bottom surface of the etched trench. The techniques for obtaining the trench parameter set are all existing technologies and will not be elaborated further here. Etching score is an index used to quantitatively evaluate the etching effect of a single set of combined parameters. The formula for calculating the etching score is as follows:

[0157] ,

[0158] in, Indicates the etching score. Indicates the depth weighting coefficient. This represents the width weighting coefficient. This represents the roughness weighting coefficient. Indicates the etching depth. Indicates the target etching depth. Indicates the etching width. Indicates the target etching width. Indicates the surface roughness of the target bottom surface. This indicates the surface roughness.

[0159] Understandably, the depth weighting factor is a weighting factor for the ratio of trench depth to target depth, for example, 0.4. The width weighting factor is a weighting factor for the ratio of trench width to target width, for example, 0.3. The roughness weighting factor is a weighting factor for the ratio of target roughness to actual roughness, for example, 0.3. The target etching depth is the target etching depth value, for example, 150. The target etching width is the target etching width value, for example, 100. The target bottom surface roughness is the target value for the bottom surface roughness, for example, 0.5. The maximum etching score is the etching score with the highest value among multiple etching scores. The final processing parameters are the combined parameters corresponding to the maximum etching score. Laser etching is the process of fabricating the required microchannel grooves on the back side of the activated silicon carbide layer using the final processing parameters and heat dissipation path. The microchannel grooves are open trenches with specific cross-sectional shapes and paths formed on the activated silicon carbide layer by laser etching. The silicon capping plate is a silicon wafer pre-processed with coolant inlet and outlet through-holes to seal the microchannel grooves. Sealing the microchannels is a microchannel system that allows coolant flow after bonding the silicon capping plate to the activated silicon carbide layer with microchannel grooves.

[0160] S5. The cooling performance of the sealed microchannel is tested to obtain a cooling performance score.

[0161] It should be explained that the cooling performance test of the sealed microchannel to obtain a cooling performance score includes:

[0162] Steady-state heat dissipation test was performed on the sealed microchannel to obtain the thermally steady-state microchannel;

[0163] Inlet temperature, outlet temperature, port pressure difference, and coolant flow rate are obtained based on thermal steady-state microchannels;

[0164] Cooling performance is scored using inlet temperature, outlet temperature, port pressure difference, and coolant flow rate. The calculation formula is shown below:

[0165] ,

[0166] in, This indicates the cooling performance rating. This indicates the preset constant power. Indicates coolant flow rate. Indicates the inlet temperature. Indicates the outlet temperature. This indicates the port pressure difference.

[0167] Furthermore, the steady-state heat dissipation test involves introducing a constant flow rate of coolant (e.g., deionized water) into the sealed microchannel while simultaneously applying a constant electrical power to the thinned heterogeneous wafer, maintaining it in a state of thermal equilibrium. The thermally steady-state microchannel is a sealed microchannel that has reached thermal equilibrium. The inlet temperature is the measured temperature of the coolant entering the sealed microchannel. The outlet temperature is the measured temperature of the coolant exiting the sealed microchannel. Optionally, a temperature sensor is used as the instrument for acquiring the inlet and outlet temperatures. The port pressure difference is the measured static pressure difference of the coolant between the inlet and outlet of the sealed microchannel. Optionally, a pressure gauge is used as the instrument for acquiring the port pressure difference. The coolant flow rate is the volume of coolant flowing through the sealed microchannel per unit time. The cooling performance score is a quantitative indicator used to comprehensively evaluate the heat dissipation efficiency of the sealed microchannel. The constant power is the electrical power applied to the thinned heterogeneous wafer, for example, 100W.

[0168] S6. Summarize the cooling performance scores to obtain three cooling performance scores, and obtain the optimal heat dissipation path based on the three cooling performance scores.

[0169] It should be explained that obtaining the optimal heat dissipation path based on the three cooling performance scores means taking the heat dissipation path corresponding to the cooling performance score with the highest value among the three cooling performance scores as the optimal heat dissipation path.

[0170] S7. Cool the device using the optimal heat dissipation path at multiple preset gradient flow rates, record the device output power, obtain the output power set, and obtain the optimal flow rate based on the gradient flow rate and the output power set.

[0171] It should be explained that obtaining the optimal flow velocity based on gradient flow velocity and output power set includes:

[0172] Curve fitting is performed on the gradient flow velocity and output power set to obtain the flow velocity-power relationship curve;

[0173] Calculate multiple unit flow velocity power gains based on the flow velocity-power relationship curve and the preset flow velocity range;

[0174] Power gain curves are constructed using power gains at multiple unit flow velocities.

[0175] Peak gain is obtained based on multiple unit flow velocity power gains;

[0176] The gain threshold is obtained based on the peak gain.

[0177] The optimal flow rate was determined based on the gain threshold and power gain curve.

[0178] Furthermore, the gradient flow rate is a pre-set set of coolant flow rate values, such as 10, 20, 30, 40, 50, 60, 70. Device output power is the maximum stable electrical power output of a superjunction device under cooling conditions with a certain gradient flow rate. It characterizes the actual working capability of thinning heterogeneous wafers under the cooling effect corresponding to that gradient flow rate. The output power set is the collection of device output powers corresponding to multiple gradient flow rates. Curve fitting is the process of fitting multiple device output powers from the output power set to obtain a continuous and smooth function curve. Optionally, the least squares method is used as the curve fitting method. The flow rate-power relationship curve is a curve obtained through curve fitting, plotted with the gradient flow rate as the abscissa and the corresponding power gain per unit flow rate as the ordinate. It characterizes the trend of change between gradient flow rate and device output power. The flow rate range is the range of flow rate variation set for calculating the power gain per unit flow rate, for example, 5... Power gain per unit flow rate is the change in device output power corresponding to a unit flow rate change within a certain flow rate range on the flow rate-power relationship curve. The formula for calculating power gain per unit flow rate is shown below:

[0179] ,

[0180] in, Indicates power gain per unit flow rate. Indicates the flow velocity range. This indicates the change in output power within a flow velocity range.

[0181] Understandably, the power gain curve is plotted with gradient flow velocity on the x-axis and power gain per unit flow velocity on the y-axis. Peak gain is the largest power gain per unit flow velocity among multiple power gains per unit flow velocity. The gain threshold is a threshold set based on the peak gain; for example, with a peak gain of 10%, the peak gain is 6, then the gain threshold is 0.6. The optimal flow velocity is the gradient flow velocity on the power gain curve at which the power gain per unit flow velocity first drops to or below the gain threshold, following the gradient flow velocity from largest to smallest.

[0182] S8. Based on the optimal heat dissipation path, optimal flow rate, and thinning of the heterogeneous wafer, obtain heat dissipation wafers, summarize the heat dissipation wafers to obtain multiple heat dissipation wafers, verify the reliability of multiple heat dissipation wafers, and obtain multiple qualified heat dissipation wafers.

[0183] It should be explained that the reliability verification of multiple heat dissipation wafers to obtain multiple qualified heat dissipation wafers includes:

[0184] Perform the following operation on each of the multiple heat dissipation wafers;

[0185] A thermal cycling test was performed on the heat dissipation wafer to obtain the tested wafer.

[0186] Interface images are acquired from the tested wafer;

[0187] Delamination detection is performed on the interface image to obtain the delamination area;

[0188] By summing up the delamination areas, multiple delamination areas are obtained;

[0189] The heat dissipation wafers corresponding to delamination areas less than or equal to the delamination area threshold are considered as qualified heat dissipation wafers. The qualified heat dissipation wafers are then aggregated to obtain multiple qualified heat dissipation wafers.

[0190] Understandably, obtaining a heat-dissipating wafer based on optimal heat dissipation path, optimal flow rate, and thinned heterogeneous wafer refers to constructing microchannels on a thinned heterogeneous wafer based on the optimal heat dissipation path and delivering coolant at the optimal flow rate to obtain a heat-dissipating wafer. A heat-dissipating wafer is a thinned heterogeneous wafer cooled using the optimal heat dissipation path and optimal flow rate.

[0191] Furthermore, the thermal cycling test involves maintaining the ambient temperature of the heat dissipation wafer at an optimal flow rate (e.g., 125°C). ) and low temperature (e.g., 40 The process involves multiple cycles (e.g., 1000 times) between different layers. This simulates the thermal stress impact caused by environmental temperature changes during actual use of thinned heterogeneous wafers to assess the durability of their structure. The tested wafer is a heat-dissipating wafer after thermal cycling testing. Interface image acquisition is the process of scanning and imaging the key interface (bonding interface between the superjunction device layer and the silicon carbide substrate) of the tested wafer. Optionally, an ultrasonic scanning microscope is used as the interface image acquisition method. The interface image is an image obtained through interface image acquisition for subsequent delamination detection, wherein different material layers exhibit different gray levels in the interface image. Delamination detection is the process of analyzing the interface image, automatically identifying and extracting the separation regions (i.e., delamination regions) caused by thermal stress failure in the bonding interface. Optionally, an edge detection algorithm is used as the delamination detection method. The delamination area is the percentage of the total area of ​​all delamination regions obtained through delamination detection to the entire bonding interface area. The delamination area threshold is a preset upper limit value of a reliability acceptance standard, for example, 1%. If the delamination area exceeds the delamination area threshold, the contact thermal resistance will increase significantly, leading to a sharp degradation in heat dissipation performance and compromising device lifespan. A qualified heat dissipation wafer is one with an interface delamination area less than or equal to the delamination area threshold.

[0192] To address the problems described in the background art, this invention obtains multiple superjunction silicon epitaxial wafers and performs the following operations on each of them: depositing a transition layer to obtain a transition supercrystal wafer; performing low-temperature bonding on the transition supercrystal wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer; and thinning and activating the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer. The thinned heterogeneous wafer includes an activated silicon carbide layer. Thus, this embodiment of the invention, through transition layer deposition and low-temperature bonding, heterogeneously integrates superjunction silicon and silicon carbide and thins and activates them, forming a high-quality, low-defect activated silicon carbide layer, facilitating the subsequent direct construction of an efficient heat dissipation layer on top of this layer. Microchannels provide a reliable foundation for heterogeneous wafers. Based on this, the present invention obtains three heat dissipation paths and performs the following operations on each path: constructing a microchannel using an activated silicon carbide layer and the heat dissipation path to obtain a sealed microchannel; testing the cooling performance of the sealed microchannel to obtain a cooling performance score; summing these scores to obtain three cooling performance scores; and obtaining the optimal heat dissipation path based on these three scores. Thus, the present invention, by constructing and measuring three sealed microchannels in parallel on the activated silicon carbide layer and quantitatively comparing the cooling performance scores, quickly identifies the optimal heat dissipation path, providing a reliable basis for subsequent flow rate optimization and avoiding blind trial and error. Furthermore, the present invention utilizes the optimal heat dissipation path to cool at multiple preset gradient flow rates and records the device output power to obtain an output power set. Based on the gradient flow rates and the output power set, the optimal flow rate is obtained. Thus, the present invention, by gradient scanning the flow rate under the optimal heat dissipation path and recording the output power in real time, accurately identifies the best balance between heat dissipation and energy consumption, obtaining the optimal flow rate that ensures device output while avoiding energy waste. Next, this invention obtains heat dissipation wafers based on optimal heat dissipation paths, optimal flow rates, and thinning of heterogeneous wafers. These heat dissipation wafers are then aggregated to obtain multiple heat dissipation wafers. Reliability verification is performed on these multiple heat dissipation wafers, resulting in multiple qualified heat dissipation wafers. It is evident that this invention, by batch-producing and uniformly verifying heat dissipation wafers under optimal heat dissipation paths and optimal flow rates, allows for the simultaneous screening of multiple qualified heat dissipation wafers, ensuring a high degree of consistency in heat dissipation performance and reliability within each batch. Therefore, this invention can solve the problem of performance degradation and reliability decline caused by thermal accumulation in superjunction and SiC integration.

[0193] like Figure 2 The diagram shown is a functional block diagram of a high-efficiency heat dissipation system integrating superjunction and SiC provided in an embodiment of the present invention.

[0194] The high-efficiency heat dissipation system 100 integrating superjunction and SiC described in this invention can be installed in electronic devices. Depending on the functions implemented, the high-efficiency heat dissipation system 100 integrating superjunction and SiC may include a device bonding activation module 101, a heat dissipation path planning module 102, an optimal flow rate confirmation module 103, and a sample quality detection module 104. The module described in this invention can also be referred to as a unit, which refers to a series of computer program segments that can be executed by the processor of an electronic device and can perform a fixed function, and which are stored in the memory of the electronic device.

[0195] The device bonding activation module 101 is used to acquire multiple superjunction silicon epitaxial wafers, and performs the following operation on each of the multiple superjunction silicon epitaxial wafers:

[0196] A transition layer was deposited on a superjunction silicon epitaxial wafer to obtain a transition supercrystal circle;

[0197] The transition supercrystallized wafer is used to perform low-temperature bonding under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer;

[0198] The heterogeneous integrated wafer is thinned and activated to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer;

[0199] The heat dissipation path planning module 102 is used to obtain three heat dissipation paths and perform the following operations on each of the three heat dissipation paths:

[0200] Microchannels were constructed using an activated silicon carbide layer and a heat dissipation path to obtain sealed microchannels;

[0201] The cooling performance of the sealed microchannel was tested, and a cooling performance score was obtained.

[0202] The cooling performance scores are summarized to obtain three cooling performance scores, and the optimal heat dissipation path is obtained based on the three cooling performance scores;

[0203] The optimal flow rate confirmation module 103 is used to cool the device using the optimal heat dissipation path at multiple preset gradient flow rates and record the device output power to obtain an output power set.

[0204] Optimal flow velocity is obtained based on gradient flow velocity and output power set;

[0205] The sample quality detection module 104 is used to obtain heat dissipation wafers based on the optimal heat dissipation path, optimal flow rate and thinning of heterogeneous wafers, and to summarize the heat dissipation wafers to obtain multiple heat dissipation wafers.

[0206] Reliability verification was performed on multiple heat dissipation wafers, and multiple qualified heat dissipation wafers were obtained.

[0207] In detail, the modules in the high-efficiency heat dissipation system 100 integrating superjunction and SiC described in this embodiment of the invention employ the same methods as described above during use. Figure 1 The method described herein is the same as the efficient heat dissipation method for superjunction and SiC integration, and can produce the same technical effect, so it will not be repeated here.

[0208] like Figure 3 The diagram shown is a structural schematic of an electronic device that implements a highly efficient heat dissipation method for superjunction and SiC integration according to an embodiment of the present invention.

[0209] The electronic device 1 may include a processor 10, a memory 11 and a bus 12, and may also include a computer program stored in the memory 11 and executable on the processor 10, such as a program for a high-efficiency heat dissipation method integrating superjunction and SiC.

[0210] The memory 11 includes at least one type of readable storage medium, such as flash memory, portable hard drive, multimedia card, card-type memory (e.g., SD or DX memory), magnetic memory, magnetic disk, optical disk, etc. In some embodiments, the memory 11 can be an internal storage unit of the electronic device 1, such as a portable hard drive. In other embodiments, the memory 11 can be an external storage device of the electronic device 1, such as a plug-in portable hard drive, smart media card (SMC), secure digital card (SD), flash card, etc., equipped on the electronic device 1. Furthermore, the memory 11 includes both internal storage units and external storage devices of the electronic device 1. The memory 11 can be used not only to store application software and various types of data installed on the electronic device 1, such as the code of a high-efficiency heat dissipation method program integrating superjunction and SiC, but also to temporarily store data that has been output or will be output.

[0211] In some embodiments, the processor 10 may be composed of integrated circuits, such as a single packaged integrated circuit or multiple integrated circuits with the same or different functions, including combinations of one or more central processing units (CPUs), microprocessors, digital processing chips, graphics processors, and various control chips. The processor 10 is the control unit of the electronic device, connecting various components of the entire electronic device through various interfaces and lines. It executes programs or modules stored in the memory 11 (e.g., a high-efficiency heat dissipation method program integrating superjunction and SiC), and calls data stored in the memory 11 to perform various functions of the electronic device 1 and process data.

[0212] The bus 12 can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The bus 12 can be divided into an address bus, a data bus, a control bus, etc. The bus 12 is configured to realize the connection and communication between the memory 11 and at least one processor 10, etc.

[0213] Figure 3 Only electronic devices with components are shown; it will be understood by those skilled in the art that... Figure 3 The structure shown does not constitute a limitation on the electronic device 1, and may include fewer or more components than shown, or combine certain components, or have different component arrangements.

[0214] For example, although not shown, the electronic device 1 may also include a power supply (such as a battery) to power the various components. Preferably, the power supply can be logically connected to the at least one processor 10 through a power management system, thereby enabling functions such as charging management, discharging management, and power consumption management through the power management system. The power supply may also include one or more DC or AC power supplies, recharging systems, power fault detection circuits, power converters or inverters, power status indicators, and other arbitrary components. The electronic device 1 may also include various sensors, Bluetooth modules, Wi-Fi modules, etc., which will not be described in detail here.

[0215] Furthermore, the electronic device 1 may also include a network interface. Optionally, the network interface may include a wired interface and / or a wireless interface (such as a Wi-Fi interface, a Bluetooth interface, etc.), which is typically used to establish communication connections between the electronic device 1 and other electronic devices.

[0216] Optionally, the electronic device 1 may further include a user interface, which may be a display, an input unit (such as a keyboard), and optionally, a standard wired interface or a wireless interface. Optionally, in some embodiments, the display may be an LED display, a liquid crystal display, a touch-sensitive liquid crystal display, or an OLED (Organic Light-Emitting Diode) touchscreen, etc. The display may also be appropriately referred to as a screen or display unit, used to display information processed in the electronic device 1 and to display a visual user interface.

[0217] It should be understood that the embodiments described are for illustrative purposes only and are not limited to this structure in the scope of the patent application.

[0218] The program for a high-efficiency heat dissipation method integrating superjunction and SiC, stored in the memory 11 of the electronic device 1, is a combination of multiple instructions. When run in the processor 10, it can achieve the following:

[0219] Obtain multiple superjunction silicon epitaxial wafers, and perform the following operation on each of the multiple superjunction silicon epitaxial wafers:

[0220] A transition layer was deposited on a superjunction silicon epitaxial wafer to obtain a transition supercrystal circle;

[0221] The transition supercrystallized wafer is used to perform low-temperature bonding under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer;

[0222] The heterogeneous integrated wafer is thinned and activated to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer;

[0223] Obtain three heat dissipation paths, and perform the following operations on each of the three heat dissipation paths:

[0224] Microchannels were constructed using an activated silicon carbide layer and a heat dissipation path to obtain sealed microchannels;

[0225] The cooling performance of the sealed microchannel was tested, and a cooling performance score was obtained.

[0226] The cooling performance scores are summarized to obtain three cooling performance scores, and the optimal heat dissipation path is obtained based on the three cooling performance scores;

[0227] The device is cooled using the optimal heat dissipation path at multiple preset gradient flow rates, and the output power is recorded to obtain the output power set.

[0228] Optimal flow velocity is obtained based on gradient flow velocity and output power set;

[0229] Based on the optimal heat dissipation path, optimal flow rate, and thinning of heterogeneous wafers, heat dissipation wafers are obtained, and these heat dissipation wafers are aggregated to obtain multiple heat dissipation wafers;

[0230] Reliability verification was performed on multiple heat dissipation wafers, and multiple qualified heat dissipation wafers were obtained.

[0231] Specifically, the processor 10's implementation method for the above instructions can be found in [reference needed]. Figures 1 to 3 The descriptions of the relevant steps in the corresponding embodiments are not repeated here.

[0232] Furthermore, if the modules / units integrated in the electronic device 1 are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. The computer-readable storage medium can be volatile or non-volatile. For example, the computer-readable medium may include: any entity or system capable of carrying the computer program code, a recording medium, a USB flash drive, a portable hard drive, a magnetic disk, an optical disk, a computer memory, or a read-only memory (ROM).

[0233] The present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor of an electronic device, can perform the following:

[0234] Obtain multiple superjunction silicon epitaxial wafers, and perform the following operation on each of the multiple superjunction silicon epitaxial wafers:

[0235] A transition layer was deposited on a superjunction silicon epitaxial wafer to obtain a transition supercrystal circle;

[0236] The transition supercrystallized wafer is used to perform low-temperature bonding under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer;

[0237] The heterogeneous integrated wafer is thinned and activated to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer includes an activated silicon carbide layer;

[0238] Obtain three heat dissipation paths, and perform the following operations on each of the three heat dissipation paths:

[0239] Microchannels were constructed using an activated silicon carbide layer and a heat dissipation path to obtain sealed microchannels;

[0240] The cooling performance of the sealed microchannel was tested, and a cooling performance score was obtained.

[0241] The cooling performance scores are summarized to obtain three cooling performance scores, and the optimal heat dissipation path is obtained based on the three cooling performance scores;

[0242] The device is cooled using the optimal heat dissipation path at multiple preset gradient flow rates, and the output power is recorded to obtain the output power set.

[0243] Optimal flow velocity is obtained based on gradient flow velocity and output power set;

[0244] Based on the optimal heat dissipation path, optimal flow rate, and thinning of heterogeneous wafers, heat dissipation wafers are obtained, and these heat dissipation wafers are aggregated to obtain multiple heat dissipation wafers;

[0245] Reliability verification was performed on multiple heat dissipation wafers, and multiple qualified heat dissipation wafers were obtained.

[0246] In the embodiments provided by this invention, it should be understood that the disclosed devices, systems, and methods can be implemented in other ways. For example, the system embodiments described above are merely illustrative, and actual implementations may have other classification methods.

[0247] The modules described as separate components may or may not be physically separate. The components shown as modules may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0248] Furthermore, the functional modules in the various embodiments of the present invention can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or in the form of hardware plus software functional modules.

[0249] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the present invention can be implemented in other specific forms without departing from the spirit or essential characteristics of the present invention.

[0250] Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or systems stated in a system claim may also be implemented by a single unit or system through software or hardware. The term "second class" is used to indicate names and does not indicate any specific order.

[0251] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit it. Although the present invention has been described in detail with reference to preferred embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention.

Claims

1. A high-efficiency heat dissipation method integrating super junction with SiC, characterized in that, The method comprises: obtaining a plurality of super junction silicon epitaxial wafers, and performing the following operations on each of the plurality of super junction silicon epitaxial wafers: transition layer deposition is performed on the super junction silicon epitaxial wafer to obtain a transition super junction wafer; low-temperature bonding is performed on the transition super junction wafer under pre-confirmed activation conditions to obtain a heterogeneous integrated wafer; thinning and activation are performed on the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer comprises an activated silicon carbide layer; three heat dissipation paths are obtained, and the following operations are performed on each of the three heat dissipation paths: micro-channel construction is performed on the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel; the micro-channel construction on the activated silicon carbide layer and the heat dissipation path to obtain the sealed micro-channel comprises: a plurality of sets of combined parameters are obtained; etching standard tests are performed on the pre-confirmed test silicon layer using the plurality of sets of combined parameters to obtain a plurality of etching grooves; a plurality of groove parameter sets are obtained based on the plurality of etching grooves, wherein the groove parameter set comprises groove depth, groove width and bottom surface roughness; the following operations are performed on each of the plurality of groove parameter sets: the groove depth, groove width and bottom surface roughness in the groove parameter set are used to calculate an etching score; the etching scores are summarized to obtain a plurality of etching scores; a maximum etching score is obtained based on the plurality of etching scores, and the combined parameters corresponding to the maximum etching score are used as final processing parameters; laser etching is performed on the activated silicon carbide layer using the heat dissipation path and the final processing parameters to obtain a micro-channel groove; a pre-confirmed silicon cover plate is bonded to the micro-channel groove to obtain a sealed micro-channel; cooling performance detection is performed on the sealed micro-channel to obtain a cooling performance score; the cooling performance scores are summarized to obtain three cooling performance scores, and an optimal heat dissipation path is obtained based on the three cooling performance scores; cooling is performed at a plurality of gradient flow rates according to the optimal heat dissipation path, and a device output power is recorded to obtain an output power set; an optimal flow rate is obtained based on the gradient flow rate and the output power set; a heat dissipation wafer is obtained based on the optimal heat dissipation path, the optimal flow rate and the thinned heterogeneous wafer, and the heat dissipation wafers are summarized to obtain a plurality of heat dissipation wafers; reliability verification is performed on the plurality of heat dissipation wafers to obtain a plurality of qualified heat dissipation wafers.

2. The method of claim 1, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The transition layer deposition on the super junction silicon epitaxial wafer to obtain the transition super junction wafer comprises: temporary bonding is performed on the super junction silicon epitaxial wafer and a pre-confirmed glass carrier to obtain a bonded wafer; mechanical grinding is performed on the bonded wafer to obtain a ground bonded wafer; thickness detection is performed on the ground bonded wafer to obtain a silicon thickness, and the silicon thickness is compared with a pre-set silicon thickness threshold value; if the silicon thickness is greater than or equal to the silicon thickness threshold value, the ground bonded wafer is used as the bonded wafer, and the mechanical grinding on the bonded wafer is returned until the silicon thickness is less than the silicon thickness threshold value, and the ground bonded wafer is used as a qualified bonded wafer; if the silicon thickness is less than the silicon thickness threshold value, the ground bonded wafer is used as a qualified bonded wafer; mechanical polishing is performed on the qualified bonded wafer to obtain a polished bonded wafer; back plating transition is performed on the polished bonded wafer to obtain a wafer with a transition layer; The wafer with the transition layer is subjected to a strip cleaning to obtain a transition super-junction wafer.

3. The method of claim 2, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The transition super-junction wafer is subjected to a low-temperature bonding under pre-confirmed activation conditions to obtain an isomorphic integrated wafer, including: obtaining a silicon carbide substrate; polishing the silicon carbide substrate to obtain a polished silicon carbide substrate; detecting the roughness of the polished silicon carbide substrate to obtain a roughness value; comparing the roughness value with a preset roughness threshold value, if the roughness value is greater than or equal to the roughness threshold value, the polished silicon carbide substrate is used as a silicon carbide substrate, and the polishing step is repeated until the roughness value is less than the roughness threshold value, and the polished silicon carbide substrate is used as a qualified polishing substrate; if the roughness value is less than the roughness threshold value, the polished silicon carbide substrate is used as a qualified polishing substrate; subjecting the qualified polishing substrate to a deoxidation treatment to obtain a deoxidized substrate; activating bonding of the transition super-junction wafer and the deoxidized substrate to obtain an isomorphic integrated wafer.

4. The method of claim 3, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The three heat dissipation paths are obtained, including: applying a preset electrical power to the thinned isomorphic wafer and collecting a heat image to obtain a high-heat map; mapping the high-heat map to a grid thermal flux matrix, and obtaining a plurality of high-heat cell coordinates using the grid thermal flux matrix; planning a heat dissipation path using the plurality of high-heat cell coordinates and pre-confirmed historical heat dissipation paths to obtain a plurality of planned heat dissipation paths; performing fast heat-flow coupling simulation on the plurality of planned heat dissipation paths to obtain a plurality of heat data sets, wherein each heat data set corresponds to a planned heat dissipation path, and each heat data set includes a maximum temperature and an average temperature; confirming the three heat dissipation paths based on the plurality of heat data sets.

5. The method of claim 4, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The three heat dissipation paths are obtained based on the plurality of heat data sets, including: obtaining a maximum temperature maximum value, a maximum temperature minimum value, and a comprehensive average temperature based on a plurality of maximum temperatures and a plurality of average temperatures in the plurality of heat data sets; performing the following operations on each heat data set in the plurality of heat data sets: calculating a heat dissipation score using the maximum temperature, the average temperature, the maximum temperature maximum value, the maximum temperature minimum value, and the comprehensive average temperature in the heat data set, wherein the calculation formula is as follows: wherein, represents a heat dissipation score, represents a preset heat peak weight coefficient, represents a maximum value of the highest temperature, represents a minimum value of the highest temperature, represents the highest temperature, represents a preset uniform temperature weight coefficient, represents a comprehensive average temperature, represents an average temperature; summarizing the heat dissipation scores to obtain a plurality of heat dissipation scores; sorting the plurality of heat dissipation scores in descending order to obtain a heat dissipation score sequence, and summarizing the three heat dissipation paths corresponding to the first three heat dissipation scores in the heat dissipation score sequence to obtain the three heat dissipation paths.

6. The method of claim 5, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The cooling performance of the sealed micro-channel is detected to obtain a cooling performance score, including: performing a steady-state heat dissipation test on the sealed micro-channel to obtain a thermal steady-state micro-channel; obtaining an inlet temperature, an outlet temperature, a port pressure difference, and a cooling liquid flow rate based on the thermal steady-state micro-channel; calculating a cooling performance score using the inlet temperature, the outlet temperature, the port pressure difference, and the cooling liquid flow rate, wherein the calculation formula is as follows: wherein, represents a cooling performance score, represents a preset constant power, represents a coolant flow rate, represents an inlet temperature, represents an outlet temperature, represents a port differential pressure.

7. The method of claim 6, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The optimal flow rate is obtained based on the gradient flow rate and the output power set, including: curve fitting the gradient flow rate and the output power set to obtain a flow rate-power relationship curve; calculating a plurality of unit flow rate power gains based on the flow rate-power relationship curve and a preset flow rate interval; Constructing a power gain curve using a plurality of unit flow rate power gains; Obtaining a peak gain based on the plurality of unit flow rate power gains; Obtaining a gain threshold based on the peak gain; Confirming an optimal flow rate based on the gain threshold and the power gain curve.

8. The method of claim 7, wherein the superjunction and SiC integrated high-efficiency heat dissipation method is characterized by, The reliability verification of the plurality of heat dissipation wafers obtains qualified heat dissipation wafers, and the method comprises the following steps of: Each of the plurality of heat dissipation wafers is subjected to the following operations; Performing a thermal cycle test on the heat dissipation wafer to obtain a tested wafer; Collecting an interface image of the tested wafer to obtain the interface image; Performing delamination detection on the interface image to obtain a delamination area; Summarizing the delamination area to obtain a plurality of delamination areas; The heat dissipation wafer corresponding to the delamination area less than or equal to the delamination area threshold is regarded as a qualified heat dissipation wafer, and the qualified heat dissipation wafers are summarized to obtain a plurality of qualified heat dissipation wafers.

9. A system for high efficiency heat dissipation using the super junction and SiC integrated method of any one of claims 1 to 8, characterized in that, The system comprises: A device bonding activation module is configured to obtain a plurality of super junction silicon epitaxial wafers, and each of the plurality of super junction silicon epitaxial wafers is subjected to the following operations: Performing a transition layer deposition on the super junction silicon epitaxial wafer to obtain a transition super junction wafer; Performing a low-temperature bonding on the transition super junction wafer under a pre-confirmed activation condition to obtain a heterogeneous integrated wafer; Performing a thinning activation on the heterogeneous integrated wafer to obtain a thinned heterogeneous wafer, wherein the thinned heterogeneous wafer comprises an activated silicon carbide layer; A heat dissipation path planning module is configured to obtain three heat dissipation paths, and each of the three heat dissipation paths is subjected to the following operations: Performing a micro-channel construction on the activated silicon carbide layer and the heat dissipation path to obtain a sealed micro-channel; Performing a cooling performance detection on the sealed micro-channel to obtain a cooling performance score; Summarizing the cooling performance scores to obtain three cooling performance scores, and obtaining an optimal heat dissipation path based on the three cooling performance scores; An optimal flow rate confirmation module is configured to cool the device by using the optimal heat dissipation path at a plurality of gradient flow rates, and record the output power of the device to obtain an output power set; Obtaining an optimal flow rate based on the gradient flow rates and the output power set; A sample quality detection module is configured to obtain heat dissipation wafers based on the optimal heat dissipation path, the optimal flow rate, and the thinned heterogeneous wafer, and summarize the heat dissipation wafers to obtain a plurality of heat dissipation wafers; The reliability verification of the plurality of heat dissipation wafers obtains a plurality of qualified heat dissipation wafers.

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