Memory device including voltage switching circuit

Abstract

The present disclosure relates to a memory device including a voltage switching circuit, including: a first semiconductor layer including a memory cell array connected to word lines extending in a first direction and bit lines extending in a second direction substantially perpendicular to the first direction; and a second semiconductor layer disposed below the first semiconductor layer and including a first region overlapping the first semiconductor layer in a third direction substantially perpendicular to the first direction and the second direction and a second region overlapping the first region in the first direction, the second semiconductor layer including: a row decoder disposed in the second region, and includes a pass transistor; and a first voltage switching circuit configured to transfer an operating voltage to the transfer transistor, and including switching elements, in which at least one of the switching elements is disposed in the second region and overlaps the transfer transistor in the first direction.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0059581, filed with the Korean Intellectual Property Office on May 7, 2024, which is incorporated herein by reference. Technical Field

[0003] The embodiments of the disclosed technology generally relate to a memory device, and more specifically, to a memory device including a voltage switching circuit. Background Technology

[0004] A three-dimensional memory device with a three-dimensional arrangement of memory cells has been proposed. The advantage of the three-dimensional memory device is that by increasing the number of stacked memory cells in the vertical direction, the memory cells are highly integrated, thereby achieving a larger capacity in the same area, thus providing high performance and excellent power efficiency. Summary of the Invention

[0005] In an embodiment, a memory device may include: a first semiconductor layer including a memory cell array connected to a plurality of word lines extending along a first direction and a plurality of bit lines extending along a second direction substantially perpendicular to the first direction; and a second semiconductor layer disposed below the first semiconductor layer and including a first region overlapping the first semiconductor layer in a third direction substantially perpendicular to the first and second directions and a second region overlapping the first region in the first direction, the second semiconductor layer including: a line decoder disposed in the second region and including a plurality of transmission transistors; and a first voltage switching circuit configured to transmit an operating voltage to the plurality of transmission transistors and including a plurality of switching elements, wherein at least one of the plurality of switching elements is disposed in the second region and overlaps the plurality of transmission transistors in the first direction.

[0006] In an embodiment, a memory device can include a first semiconductor layer including a memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction substantially perpendicular to the first direction, and a second semiconductor layer disposed below the first semiconductor layer and including a first region overlapping the first semiconductor layer in a third direction substantially perpendicular to the first and second directions and a second region overlapping the first region in the first direction, the second semiconductor layer including a page buffer circuit disposed in the first region and connected to the plurality of bit lines, a row decoder disposed in the second region and including a plurality of pass transistors, and a first voltage switching circuit configured to transmit an operating voltage to the plurality of pass transistors and including a plurality of switching elements, wherein at least one switching element among the plurality of switching elements is disposed in the second region and overlaps the page buffer circuit in the first direction.

[0007] In an embodiment, a memory device can include a first semiconductor layer including a memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction substantially perpendicular to the first direction, and a second semiconductor layer disposed below the first semiconductor layer, the second semiconductor layer including a page buffer circuit connected to the plurality of bit lines, a row decoder connected to the plurality of word lines and including a plurality of pass transistors, and a first voltage switching circuit configured to transmit an operating voltage to the plurality of pass transistors and including a plurality of switching elements, wherein at least one switching element among the plurality of switching elements is disposed between the plurality of pass transistors and overlaps the plurality of pass transistors in the first direction. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a block diagram of a memory device based on an embodiment of the disclosed technology.

[0009] Figure 2 is a perspective view of a memory device based on an embodiment of the disclosed technology.

[0010] Figure 3 is a view showing an example of a planar structure of a second semiconductor layer of Figure 2 .

[0011] Figure 4 is a view showing an example of a configuration of a first voltage switching circuit.

[0012] Figure 5 is a view showing an example of a part of the configuration shown in Figure 3 .

[0013] Figure 6 is a view showing an example of a part of the configuration shown in Figure 2FIG. 2 is a view showing another example of a planar structure of the second semiconductor layer.

[0014] Figure 7 FIG. 3 is a view showing an example of a structure in which the second semiconductor layer is expanded. Figure 6

[0015] Figure 8A FIG. 4 is a view showing an example of a circuit structure in the second semiconductor layer. Figure 8B Figure 6

[0016] Figure 9 Figure 10 FIG. 5 is a view showing another example of a planar structure of the second semiconductor layer. Figure 2

[0017] Figure 11 FIG. 6 is a view showing an example of a second voltage switching circuit. DETAILED DESCRIPTION

[0018] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. Spatially relative terms such as "below", "beneath", "lower", "under", "above", "upper", and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features. Thus, the exemplary term "below" can encompass both of the above and below orientations. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0019] Various embodiments of the disclosed technology aim to provide a memory device with high integration.

[0020] Figure 1 FIG. 1 is a block diagram of a memory device based on an embodiment of the disclosed technology.

[0021] Referring to FIG. 1, a memory device 100 based on an embodiment of the disclosed technology includes a memory cell array 110, a row decoder (X-DEC) 120, a page buffer circuit 130, and a peripheral circuit (PERI circuit) 140. Figure 1

[0022] ​​​​​​The memory cell array 110 can include a plurality of memory blocks BLK1 to BLKn (n is a natural number of 2 or more). Each of the memory blocks BLK1 to BLKn can include a plurality of cell strings. Each cell string can include at least one drain select transistor, a memory cell array, and at least one source select transistor connected in series. Each memory cell can be a volatile memory cell, or can be a non-volatile memory cell. Although the memory device 100 described below is a vertical NAND flash memory device, it should be understood that the technical idea of the disclosed technology is not limited thereto.

[0023] The row decoder 120 is connected to the memory cell array 110 through a word line WL.

[0024] The row decoder 120 selects any one of the memory blocks BLK1 to BLKn included in the memory cell array 110 in response to a row address X_A provided by the peripheral circuit 140. The row decoder 120 transmits an operation voltage X_V provided by the peripheral circuit 140 to the word line WL connected to the selected one of the memory blocks BLK1 to BLKn included in the memory cell array 110.

[0025] The memory cell array 110 is connected to the page buffer circuit 130 through a bit line BL. The page buffer circuit 130 includes a plurality of page buffers PB connected to the bit line BL, respectively. The page buffer circuit 130 receives a page buffer control signal PB_C from the peripheral circuit 140, and transmits / receives data DATA to / from the peripheral circuit 140. The page buffer circuit 130 can control the bit line BL disposed in the memory cell array 110 in response to the page buffer control signal PB_C. For example, the page buffer circuit 130 can detect data stored in the memory cell of the memory cell array 110 by sensing a signal of the bit line BL of the memory cell array 110 in response to the page buffer control signal PB_C, and can transmit the data DATA to the peripheral circuit 140 according to the detected data. The page buffer circuit 130 can apply a signal to the bit line BL based on the data DATA received from the peripheral circuit 140 in response to the page buffer control signal PB_C, so that data can be written to the memory cell of the memory cell array 110. The page buffer circuit 130 can write data to or read data from the memory cell connected to the word line activated by the row decoder 120.

[0026] The peripheral circuit 140 receives a command signal CMD, an address signal ADD, and a control signal CTRL from outside the memory device 100, and sends and receives data DATA to and from a device (e.g., a memory controller) outside the memory device 100. The peripheral circuit 140 outputs a signal, e.g., a row address X_A and a page buffer control signal PB_C, for writing data to or reading data from the memory cell array 110, based on the command signal CMD, the address signal ADD, and the control signal CTRL. The peripheral circuit 140 can generate various voltages required for the memory device 100, including an operation voltage X_V.

[0027] Hereinafter, in the drawings, two directions parallel to the upper surface of the first semiconductor layer or the second semiconductor layer are defined as a first direction FD and a second direction SD, respectively, and a direction vertically protruding from the upper surface of the first semiconductor layer or the second semiconductor layer is defined as a third direction VD. For example, the first direction FD can correspond to the extension direction of a word line, and the second direction SD can correspond to the extension direction of a bit line. The first direction FD and the second direction SD can be substantially perpendicular to each other. The third direction VD is a direction perpendicular to the first direction FD and the second direction SD. In the following description, the term "perpendicular" or "perpendicular direction" will be used as a meaning substantially the same as the third direction VD. In the drawings, the direction indicated by an arrow and the direction opposite thereto represent the same direction.

[0028] Figure 2 is a perspective view of a memory device based on an embodiment of the disclosed technology.

[0029] Referring to Figure 2 The memory device 100 includes a first semiconductor layer S1 and a second semiconductor layer S2. The first semiconductor layer S1 and the second semiconductor layer S2 overlap each other in the vertical direction VD. For example, the second semiconductor layer S2 is located below the first semiconductor layer S1 in the vertical direction VD.

[0030] The first semiconductor layer S1 includes a memory cell array 110. The memory cell array 110 can be divided into a first memory group MG1 and a second memory group MG2. Although not shown, the first memory group MG1 can include a plurality of first sub-blocks, and the second memory group MG2 can include a plurality of second sub-blocks. One first sub-block and one second sub-block corresponding thereto constitute one memory block BLK.

[0031] The first memory group MG1 and the second memory group MG2 are arranged along a first direction FD. A plurality of word lines WL and a plurality of bit lines BL are connected to each of the first memory group MG1 and the second memory group MG2. The plurality of word lines WL extend along the first direction FD and are arranged along a second direction SD, and the plurality of bit lines BL extend along the second direction SD and are arranged along the first direction FD.

[0032] The second semiconductor layer S2 includes a pair of first regions A1 and a second region A2 between the first regions A1. The second region A2 overlaps the first regions A1 in the first direction FD.

[0033] The first semiconductor layer S1 and the second semiconductor layer S2 can be fabricated on different wafers and then can be bonded to each other to be integrated by a wafer bonding process. In this case, the memory device 100 can be defined as having a Peripheral Over Cell (POC) structure.

[0034] The first semiconductor layer S1 and the second semiconductor layer S2 can be constructed on a single wafer. Although not shown, the second semiconductor layer S2 can include a substrate, various semiconductor elements formed on the substrate, and a wiring connected to the semiconductor elements. The second semiconductor layer S2 can include a plurality of pass transistors, a block selection circuit, a page buffer circuit, a plurality of voltage switching circuits, and a circuit corresponding to a peripheral circuit. After various circuits are formed in the second semiconductor layer S2, a memory cell array can be formed on the second semiconductor layer S2, and a wiring for electrically connecting the memory cell array and the circuits formed in the second semiconductor layer S2 can be formed. In this case, the memory device 100 can be defined as having a Peripheral Under Cell (PUC) structure.

[0035] Figure 3 is a view showing an example of a planar structure of the second semiconductor layer of Figure 2 .

[0036] Referring to Figure 3 , each of the first regions A1 includes a first under cell region UA1 and a second under cell region UA2. The first under cell region UA1 and the second under cell region UA2 overlap each of the first memory group MG1 and the second memory group MG2 in a vertical direction VD. The first under cell region UA1 and the second under cell region UA2 overlap each other in the second direction SD. A combined region of the first under cell region UA1 and the second under cell region UA2 can correspond to a region in which the first memory group MG1 is disposed or a region in which the second memory group MG2 is disposed. Two regions corresponding to each other means that the areas of the two regions are substantially the same or similar.

[0037] The page buffer circuit 130 is provided in the first lower sub-area UA1 of the first area A1. The page buffer circuit 130 overlaps the first memory group MG1 and the second memory group MG2 in the vertical direction VD.

[0038] The peripheral circuit other than the page buffer circuit 130 and the row decoder 120 can be provided in the second lower sub-area UA2 of the first area A1.

[0039] As Figure 3 illustrated in the example, the second area A2 is located between the two first areas A1. The second area A2 has a width of d2 in the first direction FD. The row decoder 120 can be provided in the second area A2 in a region overlapping the first lower sub-area UA1 and the second lower sub-area UA2 in the first direction FD.

[0040] The first voltage switching circuit 301 is provided in the second area A2 in a region not overlapping the first lower sub-area UA1 and the second lower sub-area UA2 in the first direction FD. The first voltage switching circuit 301 is a circuit that transmits various voltages received from the peripheral circuit to the plurality of transfer transistors PT. The first voltage switching circuit 301 can include a plurality of switching units. Each of the plurality of switching units is connected to one global word line. Each of the plurality of switching units transmits various voltages received from the peripheral circuit to the transfer transistor PT through the global word line. Since the plurality of switching units is connected one-to-one to the global word line, the number of the plurality of switching units can be the same as the number of the global word line. The plurality of first transistors 301TR and the plurality of second transistors 301TR’ are transistors included in the plurality of switching units. Each of the plurality of switching units includes one transistor among the plurality of first transistors 301TR and one transistor among the plurality of second transistors 301TR’. The region in which the plurality of first transistors 301TR is provided has a length of d1 in the second direction SD. In the embodiment, the region in which the plurality of second transistors 301TR’ is provided can also have a length of d1 in the second direction SD.

[0041] Figure 4 is a diagram illustrating an example of a switching unit included in the first voltage switching circuit. Figure 5 is a view illustrating an example of a part of the configuration illustrated in Figure 3 .

[0042] Referring to Figure 4 and Figure 5 , the first switching unit 401 can include a first transistor TRa1, a second transistor TRb1, and a third transistor TRc1.

[0043] Hereinafter, the first transistor TRal is referred to as a first switch element 401al, and the second transistor TRbl is referred to as a second switch element 401bl.

[0044] The plurality of first transistors 301TR include first switch elements 401al to 401an included in the switch units, respectively. The plurality of second transistors 301TR' include second switch elements 401bl to 401bn.

[0045] The plurality of first switch elements 401al to 401an receive an unselected global word line voltage VPUGWL from a peripheral circuit and are controlled in accordance with a control signal. The unselected global word line voltage VPUGWL can be a voltage transmitted to an unselected global word line UGWL.

[0046] The plurality of second switch elements 401bl to 401bn receive a selected global word line voltage VPSGWL from a peripheral circuit and are controlled in accordance with a control signal different from the control signal that controls the plurality of first switch elements 401al to 401an. The selected global word line voltage VPSGWL can be a voltage transmitted to a selected global word line SGWL. The selected global word line voltage VPSGWL can be transmitted from a peripheral circuit.

[0047] The third transistor TRcl receives an internal power supply voltage VSSI and is controlled in accordance with a control signal different from the control signal that controls the first switch element 401al and the second switch element 401bl.

[0048] According to the first switch unit 401, the selected global word line voltage VPSGWL, the unselected global word line voltage VPUGWL, and the internal power supply voltage VSSI can be selectively transmitted to one global word line.

[0049] Reference Figure 3 and Figure 4In the region of the second region A2 that does not overlap the first lower cell region UA1 and the second lower cell region UA2 in the first direction FD, a plurality of first switching elements 401a1 to 401an and a plurality of second switching elements 401b1 to 401bn are provided. The plurality of first switching elements 401a1 to 401an are provided in the region of the second region A2 that is adjacent to the first lower cell region UA1 in the second direction SD and does not overlap the second lower cell region UA2. The plurality of second switching elements 401b1 to 401bn are provided in the region of the second region A2 that is adjacent to the second lower cell region UA2 in the second direction SD and does not overlap the first lower cell region UA1. In an embodiment, the plurality of first switching elements 401a1 to 401an are provided in the region of the second region A2 that is adjacent to the first lower cell region UA1 in the second direction SD and does not overlap the second lower cell region UA2 in the first direction FD or does not overlap the first lower cell region UA1 in the first direction FD. In an embodiment, the plurality of second switching elements 401b1 to 401bn are provided in the region of the second region A2 that is adjacent to the second lower cell region UA2 in the second direction SD and does not overlap the first lower cell region UA1 in the first direction FD or does not overlap the second lower cell region UA2 in the first direction FD. In an embodiment, the plurality of first switching elements 401a1 to 401an are provided in the region of the second region A2 that is adjacent to the first lower cell region UA1 in the second direction SD and does not overlap the second lower cell region UA2 in the second direction SD or does not overlap the first lower cell region UA1 in the second direction SD. In an embodiment, the plurality of second switching elements 401b1 to 401bn are provided in the region of the second region A2 that is adjacent to the second lower cell region UA2 in the second direction SD and does not overlap the first lower cell region UA1 in the second direction SD or does not overlap the second lower cell region UA2 in the second direction SD.

[0050] Figure 6 is a view illustrating an example of a planar structure of the second semiconductor layer of Figure 2 .

[0051] Referring to Figure 6 , at least some of the plurality of switching units of the first voltage switching circuit 301 can be provided in the region of the second region A2 that overlaps the first lower cell region UA1 in the first direction FD. As used herein, the phrase “at least some” includes one or more.

[0052] More specifically, at least some (e.g., 401a1 to 401am, m is a natural number smaller than n) of the plurality of first switching elements 401a1 to 401an included in the switching unit of the first voltage switching circuit 301 overlap the first lower cell region UA1 in the first direction FD. However, embodiments of the disclosed technology are not limited thereto, and some of the first switching elements 401a1 to 401an can also overlap the second lower cell region UA2 in the first direction FD. As used herein, the tilde symbol "~" indicates a range of components. For example, "401a1~401an" indicates Figure 6 the first switching elements 401a1, 401a2,..., and 401an shown in FIG. 13.

[0053] Since the page buffer circuit 130 is disposed in the first lower cell region UA1, at least some of the switching units (or at least some of the switching elements) overlap the page buffer circuit 130 in the first direction FD.

[0054] At least some of the plurality of switching units of the first voltage switching circuit 301 overlap the row decoder 120 disposed in the second region A2 in the first direction FD. More specifically, at least some of the plurality of first switching elements 401a1 to 401am (m is a natural number smaller than n) included in the switching unit of the first voltage switching circuit 301 can be located between the plurality of pass transistors PT included in the row decoder 120 and overlap the plurality of pass transistors PT in the first direction FD.

[0055] Specifically, at least some of the plurality of first switching elements 401a1 to 401an can be located on the same line as at least one of the plurality of pass transistors PT in the first direction FD.

[0056] Since at least some of the switching units (or at least some of the switching elements) are disposed between the plurality of pass transistors PT in the second region A2, the length of the second region A2 in the first direction FD increases compared to a case where no switching units (or no switching elements) are disposed between the plurality of pass transistors PT. That is, d2' is greater than d2. In an embodiment, the width of the second region A2 in the first direction FD is d2', as Figure 6 indicated. That is, the width of the second region A2 in the first direction FD increases from d2 as Figure 3 indicated to d2' as Figure 6 indicated.

[0057] On the other hand, since at least some of the plurality of first switching elements 401a1 to 401an are provided in the second region A2 and overlap the first lower cell region UA1 in the first direction FD, the number of the plurality of first switching elements 401a1 to 401an (e.g., 401a(m+1) to 401an, m is a natural number smaller than n) provided in a region of the second region A2 that does not overlap the first lower cell region UA1 in the first direction FD can be reduced. Thus, compared to a case where none of the plurality of first switching elements 401a1 to 401an overlap the first lower cell region UA1 in the first direction FD, the length in the second direction SD of the region in which the switching elements of the plurality of first switching elements 401a1 to 401an that do not overlap the first lower cell region UA1 in the first direction FD are provided is reduced. That is, d1’ is smaller than d1. In an embodiment, the length in the second direction SD of the region in which the plurality of first voltage switching circuits 401a1 to 401an that do not overlap the first lower cell region UA1 in the first direction FD are provided is d1’, as shown in FIG. 1B. In an embodiment, the length in the second direction SD of the region in which the plurality of second voltage switching circuits 401b1 to 401bn are provided can be d1. Figure 6

[0058] In an embodiment, the length d3 in the second direction of the region in which at least some of the plurality of first switching elements 401a1 to 401an (e.g., 401a1 to 401am, m is a natural number smaller than n) overlap the plurality of transfer transistors PT in the first direction is smaller than the sum of the length d4 in the second direction of the first lower cell region UA1 and the length d5 in the second direction of the second lower cell region UA2. In an embodiment, the sum of the length d4 in the second direction of the first lower cell region UA1 and the length d5 in the second direction of the second lower cell region UA2 can be substantially the same as the length in the second direction of the region in which the row decoder 120 is provided. Figure 7 is a view that shows a structure in which the second semiconductor layer of Figure 6 is expanded.

[0059] Referring to Figure 7 , the second semiconductor layer S2 includes the first regions A1, the second regions A2, the third regions A3, and the fourth regions A4.

[0060] The second regions A2 are located between the first regions A1 and overlap the first regions A1 in the first direction FD. The fourth regions A4 are located between the third regions A3 and overlap the third regions A3 in the first direction FD. The second regions A2 and the fourth regions A4 overlap each other in the second direction SD.

[0061] ​Each of the first regions Al includes a first lower cell region UA1 and a second lower cell region UA2. Each of the third regions A3 includes a third lower cell region UA3 and a fourth lower cell region UA4. The first lower cell region UA1 and the second lower cell region UA2 overlap in the second direction SD. The third lower cell region UA3 and the fourth lower cell region UA4 overlap in the second direction SD.

[0062] The page buffer circuit 130 is provided in the first lower cell region UA1 and the third lower cell region UA3. The page buffer circuit 130 provided in the first lower cell region UA1 is connected to the memory group overlapping the first region Al in the vertical direction VD through a bit line. The page buffer circuit 130 provided in the third lower cell region UA3 is connected to the memory group overlapping the third region A3 in the vertical direction VD through a bit line.

[0063] The row decoder 120 is provided in the second region A2 and the fourth region A4. As described above, the row decoder 120 includes a plurality of pass transistors PT. The plurality of pass transistors PT provided in the second region A2 is connected to the memory group overlapping the first region Al in the vertical direction VD through a word line. The plurality of pass transistors PT provided in the fourth region A4 is connected to the memory group overlapping the third region A3 in the vertical direction VD through a word line.

[0064] The first voltage switching circuit 301 is provided in the second region A2. The third voltage switching circuit 701 is provided in the fourth region A4. The first voltage switching circuit 301 is a circuit that transmits various voltages received from a peripheral circuit to the plurality of pass transistors PT provided in the second region A2. The third voltage switching circuit 701 is a circuit that transmits various voltages received from a peripheral circuit to the plurality of pass transistors PT provided in the fourth region A4.

[0065] The first voltage switching circuit 301 and the third voltage switching circuit 701 can each include a plurality of switching units. The switching unit of the first voltage switching circuit 301 includes a plurality of first switching elements 401al to 401an and a plurality of second switching elements 401bl to 401bn. The switching unit of the third voltage switching circuit 701 includes a plurality of third switching elements 701al to 701an and a plurality of fourth switching elements 701bl to 701bn. Each of the switching units of the first voltage switching circuit 301 includes one of the plurality of first switching elements 401al to 401an and one of the plurality of second switching elements 401bl to 401bn. Each of the switching units of the third voltage switching circuit 701 includes one of the plurality of third switching elements 701al to 701an and one of the plurality of fourth switching elements 701bl to 701bn.

[0066] Each of the plurality of switch units is connected to one of the global word lines. Each of the plurality of switch units is a circuit that transmits various voltages received from the peripheral circuit to the transfer transistor PT through the global word line. Since the plurality of switch units are connected one-to-one to the global word lines, the number of the plurality of switch units can be the same as the number of the global word lines.

[0067] At least some of the plurality of switch units of the first voltage switching circuit 301 are provided in a region of the second region A2 that overlaps the first lower cell region UA1 in the first direction FD. At least some of the plurality of switch units of the third voltage switching circuit 701 are provided in a region of the fourth region A4 that overlaps the third lower cell region UA3 in the first direction FD.

[0068] More specifically, at least some (e.g., 401a1 to 401am, m being a natural number smaller than n) of the plurality of first switch elements 401a1 to 401an are provided in a region of the second region A2 that overlaps the first lower cell region UA1 in the first direction FD. At least some (e.g., 701a1 to 701am, m being a natural number smaller than n) of the plurality of third switch elements 701a1 to 701an are provided in a region of the fourth region A4 that overlaps the third lower cell region UA3 in the first direction FD.

[0069] Since the page buffer circuit 130 is provided in the first lower cell region UA1 and the third lower cell region UA3, at least some of the switch units (or at least some of the switch elements) overlap the page buffer circuit 130 in the first direction FD.

[0070] At least some of the plurality of switch units of the first voltage switching circuit 301 overlap the row decoder 120 provided in the second region A2 in the first direction FD. More specifically, at least some of the plurality of first switch elements 401a1 to 401an included in the switch units of the first voltage switching circuit 301 can be positioned between the plurality of transfer transistors PT included in the row decoder 120 and overlap the plurality of transfer transistors PT in the first direction FD.

[0071] At least some of the plurality of switch units of the third voltage switching circuit 701 overlap the row decoder 120 provided in the fourth region A4 in the first direction FD. More specifically, at least some of the plurality of third switch elements 701a1 to 701an included in the switch units of the third voltage switching circuit 701 can be positioned between the plurality of transfer transistors PT included in the row decoder 120 and overlap the plurality of transfer transistors PT in the first direction FD.

[0072] Since at least some of the plurality of first switching elements 401al to 401an are provided in the second region A2 and overlap the first lower cell region UA1 in the first direction FD, the number of the plurality of first switching elements 401al to 401an provided in the region of the second region A2 that does not overlap the first lower cell region UA1 in the first direction FD can be reduced. Thus, compared to a case where none of the plurality of first switching elements 401al to 401an overlap the first lower cell region UA1 in the first direction FD, the length of the region in the second direction SD in which the switching elements of the plurality of first switching elements 401al to 401an that do not overlap the first lower cell region UA1 in the first direction FD are provided is reduced. That is, dl’ is smaller than dl.

[0073] In addition, since at least some of the plurality of third switching elements 701al to 701an are provided in the fourth region A4 and overlap the third lower cell region UA3 in the first direction FD, the number of the plurality of third switching elements 701al to 701an provided in the region of the fourth region A4 that does not overlap the third lower cell region UA3 in the first direction FD can be reduced. Thus, compared to a case where none of the plurality of third switching elements 701al to 701an overlap the third lower cell region UA3 in the first direction FD, the length of the region in the second direction SD in which the switching elements of the plurality of third switching elements 701al to 701an that do not overlap the third lower cell region UA3 in the first direction FD are provided is reduced. That is, dl’ is smaller than dl.

[0074] Figure 8A and Figure 8B is a view that shows an example of a circuit structure in the second semiconductor layer of Figure 6 .

[0075] Referring to Figure 8A , each of the plurality of first switching elements 401al to 401an is connected to one global word line. As described above, since each switching cell is connected to one global word line, the switching elements included in the switching cell can be connected to the same global word line.

[0076] For example, among the switching cells, the switching cell closest to the second lower cell region UA2 in the second direction SD can be connected to the first global word line GWLl. Among the switching cells, the switching cell farthest from the second lower cell region UA2 in the second direction SD can be connected to the mth global word line GWLm. Here, m is a natural number smaller than n.

[0077] The first global word line GWL1 and the mth global word line GWLm are connected to the transfer transistor PT respectively, and the transfer transistor PT is provided in the region of the second region A2 that is farthest from the first underlying cell region UA1 in the second direction SD.

[0078] The first global word line GWL1 can be connected to the transfer transistor PT near the edge of the region of the second region A2 that is farthest from the first underlying cell region UA1 in the second direction SD, and the mth global word line GWLm can be connected to the transfer transistor PT near the center of the region of the second region A2 that is farthest from the first underlying cell region UA1 in the second direction SD. In other words, the length d6 of the first global word line GWL1 in the first direction FD can be greater than the length d7 of the mth global word line GWLm in the first direction FD.

[0079] Referring to Figure 8B The global word lines can be connected to the plurality of first switching elements 401a1 to 401an respectively. For example, the first global word line GWL1 can be connected to the first switching element 401a1 closest to the second underlying cell region UA2 in the second direction SD. The mth global word line GWLm can be connected to the first switching element 401am farthest from the second underlying cell region UA2 in the second direction SD.

[0080] In the embodiment, the sum of the length in the first direction FD and the length in the second direction SD of the first global word line GWL1 can be substantially the same as the sum of the length in the first direction FD and the length in the second direction SD of the mth global word line GWLm. That is, according to the position of the switching element, by differently setting the length in the first direction FD and the length in the second direction SD of the global word line connected to the switching element to make the total length of each global word line constant, in the embodiment, even in the case where the switching element is provided to overlap the first underlying cell region UA1 in the first direction FD, the resistance variation due to the global word line length variation can be minimized.

[0081] Figure 9 and Figure 10 are views showing other examples of the planar structure of the second semiconductor layer of Figure 2 .

[0082] In describing these examples, the description of components substantially the same as the previous examples will be omitted.

[0083] Referring to Figure 9 At least some of the plurality of switching units of the first voltage switching circuit 301 located in the second region A2 overlap the first underlying cell region UA1 and the second underlying cell region UA2 located in the first region A1 in the first direction FD.

[0084] More specifically, at least some (e.g., 901a1 to 901am, m is a natural number smaller than n) of the plurality of first switching elements 901a1 to 901an included in the switching units, which are located in the second region A2, overlap the first lower cell region UA1 and the second lower cell region UA2 in the first direction FD.

[0085] The length d3’ of the region in which at least some (e.g., 901a1 to 901am, m is a natural number smaller than n) of the plurality of first switching elements 901a1 to 901an overlap the plurality of transfer transistors PT in the first direction can be substantially the same as the sum of the lengths d4, d5 of the first lower cell region UA1 and the second lower cell region UA2 in the second direction SD.

[0086] Since at least some of the switching units are provided not only in the region of the second region A2 that overlaps the first lower cell region UA1 in the first direction FD but also in the region of the second region A2 that overlaps the second lower cell region UA2 in the first direction FD, the length of the second region A2 in the first direction FD increases by a smaller amount compared to a case in which the switching units overlap only the first lower cell region UA1 in the second region A2. That is, d2’’ is smaller than d2’.

[0087] Referring to Figure 10 , the second voltage switching circuit 1000 is provided in the second lower cell region UA2. The second voltage switching circuit 1000 is a circuit that transfers various voltages to the first voltage switching circuit 301. Referring to Figure 9 and Figure 10 , there are a plurality of second switching elements 901b1 to 901bn.

[0088] At least some of the switching units overlap the second voltage switching circuit 1000 in the first direction FD.

[0089] Figure 11 is a diagram illustrating an example of the second voltage switching circuit.

[0090] Referring to Figure 11The second voltage switching circuit 1000 includes a first circuit block 1101, a second circuit block 1102, a third circuit block 1103, and a fourth circuit block 1104. The first circuit block 1101 includes first to fourth switches SW1 to SW4. The first to fourth switches SW1 to SW4 are controlled by first to fourth control signals CNT1 to CNT4, respectively. The second circuit block 1102 includes fifth and sixth switches SW5 and SW6. The fifth and sixth switches SW5 and SW6 are controlled by fifth and sixth control signals CNT5 and CNT6, respectively. The third circuit block 1103 includes seventh to eleventh switches SW7 to SW11. The fourth circuit block 1104 includes twelfth to sixteenth switches SW12 to SW16. The seventh to tenth switches SW7 to SW10 are controlled by seventh to tenth control signals CNT7 to CNT10, respectively. The twelfth to fifteenth switches SW12 to SW15 are controlled by twelfth to fifteenth control signals CNT12 to CNT15, respectively. The eleventh and sixteenth switches, SW11 and SW16, are controlled by the unselected ground control signal VPUGWL_GND.

[0091] pass Figure 11 The second voltage switching circuit 1000 shown transmits voltages VPASS_A to VPASS_C, initialization voltage VPASS_INT, internal low voltage VLV_A, external power supply voltage VCCE, core voltage VCORE, and ground voltage GND to... Figure 10 The first voltage switching circuit 301 is shown. More specifically, through the first circuit block 1101, the second circuit block 1102, and the third circuit block 1103, voltages VPASS_A to VPASS_C, initialization voltage VPASS_INT, internal low voltage VLV_A, external power supply voltage VCCE, core voltage VCORE, and ground voltage GND are transmitted as unselected global word line voltages to... Figure 10 The first voltage switching circuit 301 shown is illustrated.

[0092] On the other hand, through the first circuit block 1101, the second circuit block 1102 and the fourth circuit block 1104, the internal low voltage VLV_A, the external power supply voltage VCCE, the core voltage VCORE and the ground voltage GND are transmitted to the first voltage switching circuit 301 as unselected global word line voltages.

[0093] Refer again Figure 6 The first voltage switching circuit 301 includes at least some of the switching units, more specifically, at least some of the multiple first switching elements 401a1 to 401an included in the switching units and receiving unselected global word line voltages, which may be disposed in the second region A2 in the region that overlaps with the first lower unit region UA1 in the first direction FD.

[0094] According to the embodiment of the disclosed technology, since at least some of the plurality of switching elements included in the switching unit of the first voltage switching circuit 301 are provided in a region overlapping with the first lower cell region UA1 in the first direction FD, a length in the second direction SD of a region of the second region A2 that does not overlap with the first lower cell region UA1 and the second lower cell region UA2 in the first direction FD can be reduced. Thus, in the embodiment, since the gap between the memory banks can be further narrowed, a highly integrated memory device can be realized.

[0095] The above description is to enable any person skilled in the art to make, use, and practice the technical features of the disclosed technology, and has been provided as an example in the context of a specific application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the principles described herein can be applied to other embodiments and applications without departing from the scope of the disclosed technology. Therefore, the embodiments disclosed in the above description and drawings should be considered only as illustrative, and not as limiting the technical scope. The technical scope of the disclosed technology is not limited by the embodiments and drawings. The spirit and scope of the disclosed technology should be interpreted with the appended claims, and encompass all equivalent forms within the scope of the appended claims.

Claims

1. A memory device comprising: a first semiconductor layer including an array of memory cells connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction perpendicular to the first direction; and a second semiconductor layer disposed below the first semiconductor layer and including a first region overlapping the first semiconductor layer in a third direction perpendicular to the first and second directions and a second region overlapping the first region in the first direction, the second semiconductor layer including: a row decoder disposed in the second region and including a plurality of pass transistors; and a first voltage switching circuit transmitting an operating voltage to the plurality of pass transistors and including a plurality of switching elements, wherein at least one switching element among the plurality of switching elements is disposed in the second region and overlaps the plurality of pass transistors in the first direction.

2. The memory device of claim 1, further comprising: a page buffer circuit disposed in the first region and connected to the plurality of bit lines, wherein the at least one switching element overlaps the page buffer circuit in the first direction.

3. The memory device of claim 2, wherein the first region includes a first lower cell region in which the page buffer circuit is disposed and a second lower cell region overlapping the first lower cell region in the second direction, and the at least one switching element overlaps the first lower cell region in the first direction.

4. The memory device of claim 3, wherein the plurality of switching elements include a switching element closest to the second lower cell region in the second direction and a switching element farthest from the second lower cell region in the second direction, and a length of a global word line connected to the switching element closest to the second lower cell region in the second direction in the first direction is greater than a length of a global word line connected to the switching element farthest from the second lower cell region in the second direction in the first direction.

5. The memory device of claim 1, wherein the plurality of switching elements include a first switching element outputting an unselected global word line voltage to a global word line and a second switching element outputting a selected global word line voltage to a global word line, and the first switching element overlaps the plurality of pass transistors in the first direction.

6. The memory device of claim 1, further comprising: a page buffer circuit disposed in the first region and connected to the plurality of bit lines, wherein the first region includes a first lower cell region in which the page buffer circuit is disposed and a second lower cell region overlapping the first lower cell region in the second direction, and the at least one switching element overlaps the first lower cell region and the second lower cell region in the first direction. ​ 7.The memory device of claim 6, wherein a length of a region in the second direction in which the at least one switching element overlaps with the plurality of pass transistors in the first direction is the same as a sum of a length of the first under cell region in the second direction and a length of the second under cell region in the second direction. 8.The memory device of claim 6, further comprising: a second voltage switching circuit disposed in the first region and transmitting an unselected global word line voltage and a selected global word line voltage to the first voltage switching circuit, wherein the second voltage switching circuit overlaps with the at least one switching element in the first direction. 9.The memory device of claim 1, further comprising: a page buffer circuit disposed in the first region and connected with the plurality of bit lines, wherein the first region includes a first under cell region in which the page buffer circuit is disposed, and a second under cell region overlapping with the first under cell region in the second direction, and at least another switching element of the plurality of switching elements is disposed in the second region in a region other than a region overlapping with the first under cell region in the first direction and a region overlapping with the second under cell region in the first direction. 10.A memory device, comprising: a first semiconductor layer including a memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction perpendicular to the first direction; and a second semiconductor layer disposed below the first semiconductor layer and including a first region overlapping with the first semiconductor layer in a third direction perpendicular to the first direction and the second direction, and a second region overlapping with the first region in the first direction, the second semiconductor layer including: a page buffer circuit disposed in the first region and connected with the plurality of bit lines; a row decoder disposed in the second region and including a plurality of pass transistors; and a first voltage switching circuit transmitting an operating voltage to the plurality of pass transistors and including a plurality of switching elements, wherein at least one switching element of the plurality of switching elements is disposed in the second region and overlaps with the page buffer circuit in the first direction. 11.The memory device of claim 10, wherein the first region includes a first under cell region in which the page buffer circuit is disposed, and a second under cell region overlapping with the first under cell region in the second direction, and the at least one switching element overlaps with the first under cell region in the first direction. 12.The memory device of claim 10, wherein ​ The plurality of switching elements includes a first switching element outputting an unselected global word line voltage to a global word line and a second switching element outputting a selected global word line voltage to a global word line, and The first switching element overlaps the plurality of pass transistors in the first direction.

13. The memory device of claim 12, wherein, The first switching element is in line with at least one of the plurality of pass transistors in the first direction.

14. The memory device of claim 10, wherein, The first region includes a first lower cell region in which the page buffer circuit is disposed, and a second lower cell region overlapping the first lower cell region in the second direction, and The at least one switching element overlaps the first lower cell region and the second lower cell region in the first direction.

15. A memory device, comprising: a first semiconductor layer including an array of memory cells connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction perpendicular to the first direction; and a second semiconductor layer disposed below the first semiconductor layer, The second semiconductor layer includes: a page buffer circuit connected to the plurality of bit lines; a row decoder connected to the plurality of word lines and including a plurality of pass transistors; and a first voltage switching circuit transmitting an operating voltage to the plurality of pass transistors and including a plurality of switching elements, wherein at least one of the plurality of switching elements is disposed between the plurality of pass transistors and overlaps the plurality of pass transistors in the first direction.

16. The memory device of claim 15, wherein, The at least one switching element overlaps the page buffer circuit in the first direction.

17. The memory device of claim 15, wherein, A length of an area in which the at least one switching element overlaps the plurality of pass transistors in the first direction is less than a length of an area in which the row decoder is disposed in the second direction.

18. The memory device of claim 15, wherein, A length of an area in which the at least one switching element overlaps the plurality of pass transistors in the first direction is the same as a length of an area in which the row decoder is disposed in the second direction.

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