Data signal optimization method and device, computer equipment and storage medium

Abstract

The invention provides a data signal optimization method and device, computer equipment and a storage medium, and the method comprises the following steps: configuring a group of programmable reference voltages for a plurality of data signals, the number of the programmable reference voltages being determined based on the center level floating range and the programmable step length of the data signals; scanning a central level value of each data signal; setting voltage values of all reference voltages according to the maximum value and the minimum value of the central level values; each of the data signals is matched with a closest reference voltage. According to the invention, the dual technical problems of sampling deviation caused by multi-signal sharing and resource waste caused by independent configuration in the traditional reference voltage design are solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of data processing, and more particularly to a data signal optimization method and device, a computer device and a storage medium. BACKGROUND

[0002] In the field of high-speed data interaction, the signal sampling quality between the master chip and the storage chip directly affects the system reliability. The traditional reference voltage design scheme faces double contradictions: on the one hand, when multiple data signals share a single reference voltage, it is difficult to consider the sampling window requirements of all signals due to the inherent differences in signal levels. With the increase of transmission rate and the decrease of level, this scheme leads to continuous reduction of sampling margin, becoming a bottleneck restricting performance improvement; on the other hand, if a dedicated reference voltage is independently configured for each data signal, the sampling deviation problem can be solved, but the number of reference voltages increases significantly, significantly expanding the chip area and manufacturing cost. The above two schemes lack dynamic adaptation capability, and the fixed sharing mode cannot respond to the characteristic distribution changes of the signal group, and the fully independent configuration scheme sacrifices hardware efficiency. Especially when the signal center level exists floating, the traditional design cannot accurately match the signal group characteristics, nor can it realize resource reuse optimization. SUMMARY

[0003] The purpose of the present application is to overcome the defects of the prior art and provide a data signal optimization method, device, computer device and storage medium, which aims to solve the double technical problems of sampling deviation caused by multiple signal sharing and resource waste caused by independent configuration in the traditional reference voltage design.

[0004] To achieve the above purpose, the technical scheme adopted by the present application is as follows:

[0005] A data signal optimization method, comprising the following steps:

[0006] A set of programmable reference voltages is configured for a plurality of data signals, the number of programmable reference voltages being determined based on the center level floating range and programmable step length of the data signals;

[0007] The center level value of each data signal is scanned;

[0008] The voltage value of all reference voltages is set according to the maximum and minimum values of the center level value;

[0009] The closest reference voltage is matched for each data signal.

[0010] In an embodiment, the step of configuring a set of programmable reference voltages for a plurality of data signals, the number of programmable reference voltages being determined based on the center level floating range and programmable step length of the data signals comprises:

[0011] determining the center level floating range and programmable step size according to engineering data;

[0012] calculating the required number of reference voltages based on the formula number of reference voltages=(floating range×2) / step size+1;

[0013] reserving corresponding number of reference voltage unit circuits.

[0014] In one embodiment, the step of scanning the center level value of each data signal comprises:

[0015] performing digital eye scan on each data signal by continuously adjusting the reference voltage value and detecting the sampling result, and recording the valid level boundary of the data signal;

[0016] based on the obtained valid level boundary, taking the intermediate value between the upper limit and the lower limit of the valid level boundary as the center level value of the data signal.

[0017] In one embodiment, the step of setting the voltage value of all reference voltages according to the maximum value and the minimum value of the center level value comprises:

[0018] identifying the maximum value and the minimum value of all the center level values;

[0019] setting the first reference voltage to the value closest to the minimum value;

[0020] setting the last reference voltage to the value closest to the maximum value;

[0021] setting the remaining reference voltages to equidistant values between the maximum value and the minimum value.

[0022] In one embodiment, the step of matching the closest reference voltage for each data signal comprises:

[0023] calculating the absolute difference value of the center level value of each data signal and all reference voltage values;

[0024] selecting the reference voltage with the minimum difference value for each data signal.

[0025] In one embodiment, when the center level values of multiple data signals are close, the multiple data signals are assigned to the same reference voltage.

[0026] In one embodiment, the number of reference voltages is less than the number of data signals, and the deviation of the center level value of the signal matched by each reference voltage from the set value of the reference voltage is less than the programmable step size.

[0027] A data signal optimization device comprises:

[0028] A programmable reference voltage array module is configured to generate a set of reference voltages, the voltage values of which can be dynamically configured, and the array size is determined based on the center level floating range of target data signals and programmable step length;

[0029] A center level scanning module is connected to the reference voltage array module and configured to perform digital eye diagram scanning on each data signal to obtain the center level value of each data signal;

[0030] A voltage optimization configuration module is connected to the center level scanning module and configured to calculate and set all voltage values in the reference voltage array based on the maximum and minimum values of the center level values;

[0031] A dynamic allocation execution module is connected to the voltage array and scanning module and configured to match the closest reference voltage for each data signal.

[0032] A computer device includes a memory and a processor, the memory stores a computer program, and the processor implements the above method when executing the computer program.

[0033] A computer readable storage medium stores a computer program, the computer program includes program instructions, and the program instructions can implement the above method when executed by a processor.

[0034] Compared with the prior art, the present application has the beneficial effects that: through the dynamic configuration and intelligent matching mechanism of programmable reference voltages, an optimal balance is established between signal sampling quality and hardware resource efficiency. The number of reference voltages is determined based on the floating range and programmable step length of the center level of data signals, so that the hardware resource configuration is accurately adapted to the characteristics of the signal group, and the defects of resource redundancy or insufficient coverage in the traditional scheme are avoided. After the center level values of each signal are scanned and obtained, the maximum and minimum values thereof are used to set the global distribution of the reference voltage group, so that the limited reference voltages form an optimal coverage interval. When the closest reference voltage to the center level of each data signal is locked, the signals with similar level values are automatically collected into the same reference voltage, triggering the resource reuse effect, thereby significantly compressing the total amount of reference voltages while maintaining high sampling quality, and providing expansion capability for high-speed signal evolution through a parameterized framework, forming an adaptive closed-loop optimization system.

[0035] The above description is only a summary of the technical scheme of the present application, in order to more clearly understand the technical means of the present application, the content of the specification can be implemented, and in order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the following preferred embodiments are described in detail as follows. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1A flowchart of a data signal optimization method provided by an embodiment of the present application is shown in the figure;

[0037] Figure 2 A reference voltage unit circuit structure diagram in a data signal optimization method provided by an embodiment of the present application is shown in the figure;

[0038] Figure 3 A schematic block diagram of a data signal optimization device provided by an embodiment of the present application is shown in the figure;

[0039] Figure 4 A schematic block diagram of a computer device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0040] In order to make the objects, technical solutions and advantages of the present application clearer, further detailed description will be given to the present application in combination with the accompanying drawings and specific embodiments.

[0041] The technical solutions in the embodiments of the present application will be described clearly and completely in combination with the accompanying drawings of the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work fall within the scope of protection of the present application.

[0042] It should be understood that, when used in the specification and the appended claims, the terms "comprise" and "include" indicate the presence of the described features, integers, steps, operations, elements, and / or components, but do not exclude one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0043] It should also be understood that the terms used in the present application specification are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the present application specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms, unless the context clearly indicates otherwise.

[0044] It should be further understood that the term "and / or" used in the present application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes these combinations.

[0045] Referring to Figure 1 The embodiment of the present application discloses a data signal optimization method, which includes the following steps:

[0046] S100, configuring a set of programmable reference voltages for a plurality of data signals, a number of the programmable reference voltages being determined based on a center level floating range of the data signals and a programmable step size;

[0047] Specifically, the embodiment establishes a dynamically adaptive hardware resource base, and realizes accurate matching of the reference voltage group size and signal characteristics through a parameterization mechanism. Based on the floating range of the center level of the data signals (such as ±5% voltage fluctuation caused by engineering environment) and the programmable step size (such as 1% voltage adjustment precision), the minimum necessary number of reference voltages is accurately determined, thereby solving the dilemma of the traditional scheme: if the number is insufficient, the signal level distribution interval cannot be covered, resulting in insufficient sampling margin of the edge signal; if the number is too large, chip area is wasted and cost is increased. Through size control, the efficiency of hardware resources is optimized for the first time, providing an expandable physical carrier for subsequent signal matching, while eliminating the risk of systematic deviation caused by signal level fluctuation. The process forms the basis of the entire scheme, ensuring the effective implementation of subsequent optimization steps.

[0048] It can be understood that the programmable reference voltage refers to a reference source whose output voltage value can be dynamically adjusted by a digital register, and its core feature is to change the voltage value through a control signal to adapt to different signal environments. The center level floating range refers to the maximum allowed deviation interval of the center level value of the data signal relative to the nominal value in the actual engineering environment such as temperature change and noise interference.

[0049] S200, scanning the center level value of each data signal;

[0050] Specifically, by measuring and quantifying individual differences of the signals, a high-fidelity data base is provided for global optimization. Boundary scanning is independently performed for each data signal to eliminate the deviation between the theoretical model and the actual working condition. By continuously adjusting the reference voltage value and detecting the sampling result (correct / incorrect), the effective level boundary (non-simulated calculation) is recorded, and then converted into an accurate center level value. In the embodiment, a real distribution map of the data signal group is generated, which directly drives the subsequent distribution optimization of the reference voltage, and is the core basis for solving the sampling deviation, avoiding the sampling window deviation caused by the use of fixed theoretical values due to engineering deviation.

[0051] It can be understood that digital eye diagram scanning refers to a technology for measuring the effective sampling window of a signal by stepwise adjusting the sampling voltage position and detecting the error rate. The effective level boundary refers to the voltage limit value at which the data signal can be correctly sampled, including the upper limit (higher than this value is always judged as "1") and the lower limit (lower than this value is always judged as "0").

[0052] S300, setting the voltage values of all reference voltages according to the maximum and minimum values of the center level values;

[0053] Specifically, the embodiment converts discrete signal features into continuous resource distribution strategies, and constructs an optimal reference voltage grid covering the entire domain. Based on the obtained center level extreme values (maximum and minimum), through boundary alignment (the first voltage is close to the minimum value, and the last voltage is close to the maximum value) and interval equal division (the intermediate voltage is uniformly distributed), it is ensured that any center level value can be matched to the adjacent reference voltage. The boundary alignment eliminates the extreme signal blind area, and the equal interval distribution maximizes the resource utilization efficiency, which is significantly better than the fixed mode or random scheme.

[0054] S400, matching the closest reference voltage for each data signal.

[0055] Specifically, the resource reuse effect is triggered by the minimum deviation principle to achieve the ultimate balance between precision and efficiency. The absolute difference between the center level value of each signal and all reference voltages is calculated and the minimum value is selected, so that signals with similar level values are automatically clustered into the same reference voltage. Under the premise of ensuring that the matching deviation is less than the programmable step length, the total amount of reference voltage demand is compressed to be much smaller than the number of signals (such as 11 services 32 signals), and the problems of resource waste of independent configuration and sampling deviation of common scheme are solved at the same time.

[0056] It can be understood that the absolute difference refers to the absolute value of the difference between two numerical values, which is used to quantify the deviation degree of the signal and the reference voltage.

[0057] In an embodiment, the step of configuring a set of programmable reference voltages for a plurality of data signals, the number of programmable reference voltages being determined based on the center level floating range and the programmable step length of the data signals comprises:

[0058] Determine the center level floating range and the programmable step length according to engineering data;

[0059] Specifically, the embodiment provides accurate input parameters for resource optimization, and ensures signal fluctuations under the worst working condition by analyzing measured data. Based on existing chip test reports, high-temperature aging data and other engineering data, the actual floating range is determined to avoid the disconnection between theoretical models and actual working conditions; at the same time, the programmable step length is set according to the process capability, and a balance is achieved between voltage regulation accuracy and hardware complexity. In the embodiment, engineering experience is converted into quantifiable parameters. If the floating range value is insufficient, it will lead to coverage blind area, the step length is too large, which will reduce the matching accuracy, and the step length is too small, which will increase unnecessary circuit overhead.

[0060] The required number is calculated based on the formula reference voltage number = (floating range x 2) / step length + 1;

[0061] Specifically, a mathematical model is used to achieve precise conversion of parameters to resources, ensuring full coverage without blind spots. A floating range of ×2 covers the entire range of positive and negative signal level fluctuations (e.g., ±4.2% corresponds to an 8.4% span), with the step size determining the voltage regulation accuracy, and +1 eliminating the risk of missing boundary value coverage. This calculation achieves optimal resource deployment with minimal hardware cost, laying the mathematical foundation for subsequent uniform voltage distribution.

[0062] Reserve a corresponding number of reference voltage unit circuits.

[0063] Specifically, in this embodiment, abstract computation is transformed into physical entities, providing a dynamically adjustable hardware platform. Programmable reference voltage unit circuits are instantiated according to the number of computations to support subsequent voltage setting and signal matching operations. Each unit independently adjusts its output voltage through a register control interface. This deployment must be strictly consistent with the number of computations—insufficient numbers result in missing signal coverage, while excessive numbers violate resource optimization goals.

[0064] It is understood that the reference voltage unit circuit refers to a hardware module capable of independently outputting an adjustable reference voltage, including a voltage divider resistor network, a buffer, and a digital control interface. In this embodiment, see [link to documentation]. Figure 2 As shown, the reference voltage unit circuit achieves multi-level adjustable precision through the coordination of the equivalent resistor voltage divider basic architecture and the digital control bus. Two resistors, each with a nominal value of R, are connected in series between the power supply VCC and ground to form a basic voltage divider. The intermediate node directly outputs the reference voltage VREF (theoretical value = VCC / 2), forming the initial voltage anchor point. The parallel-connected VREFSEL[0:3] four-wire control bus points to the core mechanism of the programmable resistor network: by dynamically switching the equivalent resistor array connected to the voltage divider branch through digital signals, the basic voltage division ratio is precisely offset. For example, when the VREFSEL input is binary "0000", it maintains the original VREF value, while the input "0011" may connect a parallel resistor to reduce the impedance of the voltage divider point, raising the output voltage to VCC×R / (R+ΔR), thereby achieving voltage regulation capability with programmable step size (such as ΔV = ±1%VCC), providing a dynamically reconfigurable voltage reference source for high-speed data sampling circuits, perfectly adapting to the matching requirements of multiple signal center levels.

[0065] In one embodiment, the step of scanning the center level value of each of the data signals includes:

[0066] A digital eye diagram scan is performed on each of the data signals. The effective level boundaries of the data signals are recorded by continuously adjusting the reference voltage value and detecting the sampling results.

[0067] Specifically, the embodiment establishes a signal feature database through quantitative measurement, provides a high-fidelity data basement for global optimization, and thus eliminates the deviation between a theoretical model and an actual working condition. Voltage scanning is independently performed on each data signal, the reference voltage value is continuously adjusted (the step precision is consistent with the programmable step length), and the sampling result is detected in real time, so that the effective level boundary of the signal is recorded. This process accurately captures the electrical characteristics of the signal in the real environment, and solves the sampling window offset problem caused by the dependence of the traditional scheme on fixed theoretical values. When the signal fluctuates due to temperature changes or noise interference, the measured boundary data can improve the sampling positioning accuracy, and avoid the risk of code errors from the source.

[0068] Based on the obtained effective level boundary, the intermediate value of the upper limit and the lower limit of the effective level boundary is taken as the center level value of the data signal.

[0069] Specifically, the embodiment converts physical measurement into a mathematical model to provide standard input parameters for subsequent optimization. The arithmetic mean value (formula: (upper limit + lower limit) / 2) is calculated based on the upper limit and the lower limit of the effective level boundary, so as to locate the optimal sampling point of the signal, and solve the center offset problem caused by the fuzzy boundary definition in the traditional scheme. If the geometric mean or weighted average is used, additional deviation will be introduced, and the arithmetic mean has the smallest error under the assumption of normal distribution. The boundary value needs to be calibrated by temperature compensation to ensure that the center level value covers the full working condition requirement; at the same time, the boundary difference range needs to be verified to avoid invalid calculation caused by boundary failure.

[0070] In an embodiment, the step of setting the voltage values of all reference voltages according to the maximum value and the minimum value of the center level values comprises:

[0071] Identifying the maximum value and the minimum value of all the center level values;

[0072] Specifically, the embodiment constructs a spatial coordinate system of signal feature distribution to provide a reference framework for resource allocation. By traversing the center level value data set of all data signals, a dynamic comparison algorithm is used to identify the global maximum value and the minimum value, so as to ensure 100% coverage of all data through full traversal, and solve the incomplete coverage problem of traditional sampling statistics. The algorithm implementation needs to record the current extreme value in the hardware register in real time, and perform 2 comparisons (comparison with the minimum value register→update, comparison with the maximum value register→update) each time a new signal center value is added. The calculation overhead is only O(n) complexity, which meets the demand of high-speed signal processing.

[0073] The first reference voltage is set to the value closest to the minimum value;

[0074] Specifically, the embodiment realizes zero deviation fitting of the left boundary of signal distribution. The first reference voltage (VREF_0) is set as the programmable voltage value closest to the minimum center level value, eliminating the boundary deviation defect of the uniform distribution scheme.

[0075] The last reference voltage is set as the value closest to the maximum value.

[0076] Specifically, the embodiment realizes zero deviation fitting of the right boundary of signal distribution. The last reference voltage (VREF_n) is set as the programmable voltage value closest to the maximum center level value, ensuring that the high-level signal sampling margin is maximized, and avoiding the right shift of the sampling window caused by truncation error in the traditional scheme.

[0077] The remaining reference voltages are set as equidistant values between the maximum value and the minimum value.

[0078] Specifically, the embodiment realizes global optimal coverage through linear interpolation. After the first and last voltages are fixed, the remaining reference voltages are calculated in the [VREF_0, VREF_n] interval according to the formula:

[0079] In an embodiment, the step of matching each data signal to the closest reference voltage includes:

[0080] Calculating the absolute difference between the center level value of each data signal and all reference voltage values.

[0081] Specifically, the embodiment establishes a decision matrix for optimal matching. For each signal center level value Vcent_m and all reference voltages VREF_n, the absolute difference Δmn = |Vcent_m - VREF_n| is calculated.

[0082] Selecting the reference voltage with the smallest difference value for each data signal.

[0083] Specifically, the embodiment realizes precise binding through the minimum value selector.

[0084] In an embodiment, when the center level values of multiple data signals are similar, the multiple data signals are assigned to the same reference voltage.

[0085] Specifically, when the difference between multiple signal center values is less than the programmable step, they are forced to be assigned to the same reference voltage. This design is realized through hardware constraint logic: if |Vcent_a - Vcent_b| < step, then signal b is prohibited from being assigned a new voltage, and directly reuses the reference voltage index of signal a. Taking a step size of 0.8% as an example, the difference between signal A (98.20%) and signal B (98.25%) is 0.05% < 0.8%, triggering the forced reuse mechanism and reducing the occupation of 1 voltage resource.

[0086] In an embodiment, the number of the reference voltages is less than the number of the data signals, and the deviation of the signal center level value matched by each of the reference voltages from the reference voltage setting value is less than the programmable step size.

[0087] Specifically, the embodiment realizes double optimization closed loop through dynamic matching mechanism. When the data signals with similar center level values (such as 98.1% of signal A and 98.3% of signal B) are intelligently clustered and assigned to the same reference voltage (such as VREF_3 of 98.3%), the resource reuse effect is triggered, that is, the total amount of reference voltages is compressed to be much less than the number of data signals (such as 11 reference voltages serving 32 signals in the document embodiment, with a compression rate of 65.6%), significantly reducing chip area and manufacturing cost. At the same time, the absolute deviation of each reference voltage setting value from the signal center level value matched by it is strictly limited within the programmable step size (such as |98.1%-98.3%|=0.2%<step size 0.84%). It can be understood that the fine adjustment capability of the programmable step size supports accurate voltage value setting, the boundary alignment mechanism ensures that the deviation of the extreme signal approaches zero, and the equidistant distribution strategy makes the matching deviation of any signal not more than half of the step size. The whole technical chain forms a self-consistent closed loop: from scanning to obtain signal center level distribution, to extreme value guiding global optimization of reference voltage, and finally to synchronously achieving the dual goals of increasing resource compression rate and reducing sampling window offset through dynamic matching, eliminating the sampling deviation of the traditional common solution while avoiding the resource waste of the independent configuration solution, providing a solution with economic efficiency and reliability for high-speed data interaction scenarios.

[0088] Please refer to Figure 3 , Figure 3 is a schematic block diagram of a data signal optimization device provided by the embodiment of the present application. As Figure 3 shown, corresponding to the above data signal optimization method, the present application also provides a data signal optimization device 500. The data signal optimization device 500 includes units for executing the above data signal optimization method, and the device can be configured in a desktop computer, a tablet computer, a laptop computer, and the like terminal.

[0089] A data signal optimization device 500 includes:

[0090] A programmable reference voltage array module 510 is configured to generate a set of reference voltages, the voltage values of the reference voltages being dynamically configurable, and the array size being determined based on the center level floating range of the target data signal and the programmable step size;

[0091] Specifically, the programmable reference voltage array module 510 is the basic carrier of hardware resource dynamic adaptation, and a set of reference voltage outputs are generated through a register-controlled programmable resistance network, and the array size (i.e., the number of reference voltages) is determined based on the center level floating range of the target data signal and the programmable step size. For example, when the floating range is ±4% and the step size is 0.8%, the array size is automatically configured to 11 independent output channels. The voltage value of each channel is precisely adjusted by a four-wire control bus VREFSEL[0:3] in a step size (e.g., 0.8% step size corresponds to 16 programmable states), forming a set of voltage references covering the signal fluctuation interval, and providing a hardware resource pool for subsequent scanning and matching.

[0092] The center level scanning module 520 is connected to the reference voltage array module, and is configured to perform digital eye diagram scanning on each data signal to obtain the center level value of each data signal.

[0093] Specifically, the center level scanning module 520 is responsible for signal feature quantization collection, and accurately captures the center level value of each data signal through digital eye diagram scanning technology. The working process is as follows: sending a voltage adjustment instruction (e.g., increasing by 0.8% in step size accuracy) to the programmable reference voltage array module, while detecting the sampling result of the corresponding data signal; when the sampling state jumps from "correct" to "error", the voltage value is recorded as the effective level boundary; finally, the arithmetic mean value of the upper and lower boundaries is calculated as the center level value. This process generates an electrical feature map of the signal group, shortens the time consumption of complete scanning of 32 signals, and provides high-fidelity input data for center level value calculation.

[0094] The voltage optimization configuration module 530 is connected to the center level scanning module, and is configured to calculate and set all voltage values in the reference voltage array according to the maximum and minimum values of the center level value.

[0095] Specifically, the voltage optimization configuration module 530 executes a global resource optimization strategy, and intelligently configures the voltage value distribution of the reference voltage array based on the extreme values (maximum value / minimum value) output by the center level scanning module. First, the first reference voltage is set to the programmable value closest to the minimum center level value, and the last voltage is close to the maximum value; then, the remaining reference voltages are executed in equal interval interpolation within the extreme value interval.

[0096] The dynamic allocation execution module 540 is connected to the voltage array and the scanning module, and is configured to match the closest reference voltage for each data signal.

[0097] Specifically, the dynamic allocation execution module 540 implements accurate binding of signals and resources, and triggers a clustering multiplexing effect through a difference minimization algorithm. The hardware architecture thereof includes a parallel subtractor array (calculating the absolute difference between the center level value of each signal and the reference voltage) and a tree-shaped comparator (locating the minimum value index). When the difference between the center level values of signals is less than the step (such as |98.1%-98.3%| = 0.2% < 0.8%), forced allocation to the same reference voltage is implemented, so that a single reference voltage can serve 3-5 signals. Finally, the total amount of reference voltages is compressed while ensuring that the matching deviation is strictly less than the programmable step.

[0098] Referring to Figure 4 As shown in the figure, the computer device 600 includes a processor 620, a memory, and a network interface 650 connected through a system bus 610, wherein the memory can include a non-volatile storage medium 630 and an internal memory 640.

[0099] The non-volatile storage medium 630 can store an operating system 631 and a computer program 632. The computer program 632 includes program instructions which, when executed, can cause the processor 620 to perform a data signal optimization method.

[0100] The processor 620 is configured to provide computing and control capabilities to support the operation of the entire computer device 600.

[0101] The internal memory 640 provides an environment for the execution of the computer program 632 in the non-volatile storage medium 630, which, when executed by the processor 620, can cause the processor 620 to perform a data signal optimization method.

[0102] The network interface 650 is configured to perform network communication with other devices. Those skilled in the art can understand that, Figure 4 The structure shown in the figure is only a block diagram of part of the structure related to the scheme of the present application, and does not constitute a limitation on the computer device 600 to which the scheme of the present application is applied. Specifically, the computer device 600 can include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0103] It should be understood that, in the embodiments of the present application, the processor 620 can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or any conventional processor.

[0104] It can be understood by those skilled in the art that all or part of the processes in the above-mentioned embodiments can be completed by a computer program instructing related hardware. The computer program includes program instructions, and the computer program can be stored in a storage medium, which is a computer-readable storage medium. The program instructions are executed by at least one processor in the computer system to implement the process steps of the above-mentioned embodiments.

[0105] Therefore, the present application also provides a storage medium. The storage medium can be a computer-readable storage medium. The storage medium stores a computer program, wherein the computer program includes program instructions. The program instructions are executed by a processor to perform the following steps:

[0106] S100, configuring a set of programmable reference voltages for a plurality of data signals, the number of programmable reference voltages being determined based on a center level floating range of the data signals and a programmable step size;

[0107] S200, scanning a center level value of each of the data signals;

[0108] S300, setting voltage values of all reference voltages according to a maximum value and a minimum value of the center level values;

[0109] S400, matching each of the data signals with the closest reference voltage.

[0110] The storage medium can be a U disk, a mobile hard disk, a read-only memory (ROM), a magnetic disk or an optical disk, and various computer-readable storage media that can store program codes.

[0111] Those skilled in the art can understand that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be realized in electronic hardware, computer software or a combination of both. In order to clearly illustrate the interchangeability of hardware and software, the components and steps of each example have been described in general terms in the above description. Whether the functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of the present application.

[0112] The non-company software tools or components appearing in the embodiments of the present application are only illustrative and do not represent actual use.

[0113] In several embodiments provided by the present application, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only illustrative. For example, the division of each unit is only a logical functional division, and actual implementation can have another division method. For example, a plurality of units or components can be combined or integrated into another system, or some features can be omitted or not executed.

[0114] The steps in the method embodiments of the present application can be adjusted, combined and deleted in sequence according to actual needs. The units in the device embodiments of the present application can be combined, divided and deleted according to actual needs. In addition, each functional unit in each embodiment of the present application can be integrated in one processing unit, or each unit can exist physically, or two or more units can be integrated in one unit.

[0115] The integrated unit, if realized in the form of a software functional unit and sold or used as an independent product, can be stored in a storage medium. Based on such understanding, the technical solutions of the present application essentially or say the part that contributes to the prior art, or the whole or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions for causing a computer device (which can be a personal computer, a terminal or a network device, etc.) to execute all or part of the steps of the method embodiments of the present application.

[0116] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical scope disclosed by the present application, and these modifications or replacements should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A method of data signal optimization, characterized by, The method comprises the following steps: configuring a set of programmable reference voltages for a plurality of data signals, the number of the programmable reference voltages being determined based on a center level floating range and a programmable step size of the data signals; scanning the center level values of each of the data signals; setting the voltage values of all the reference voltages according to the maximum and minimum of the center level values; matching the closest reference voltage for each of the data signals.

2. The method of claim 1, wherein, The step of configuring a set of programmable reference voltages for a plurality of data signals, the number of the programmable reference voltages being determined based on a center level floating range and a programmable step size of the data signals comprises: determining the center level floating range and the programmable step size according to engineering data; calculating the required number based on the formula reference voltage number=(floating range×2) / step size+1; reserving a corresponding number of reference voltage unit circuits.

3. The method of claim 1, wherein, The step of scanning the center level values of each of the data signals comprises: performing digital eye scan for each of the data signals, recording the effective level boundaries of the data signals by continuously adjusting the reference voltage values and detecting the sampling results; taking the intermediate value between the upper and lower limits of the effective level boundaries as the center level value of the data signal based on the obtained effective level boundaries.

4. The method of claim 1, wherein, The step of setting the voltage values of all the reference voltages according to the maximum and minimum of the center level values comprises: identifying the maximum and minimum of all the center level values; setting the first reference voltage as the value closest to the minimum; setting the last reference voltage as the value closest to the maximum; setting the remaining reference voltages as equidistant values between the maximum and minimum.

5. The method of claim 1, wherein, The step of matching the closest reference voltage for each of the data signals comprises: calculating the absolute difference values of the center level values of each of the data signals and all the reference voltage values; selecting the reference voltage with the minimum difference value for each of the data signals.

6. The method of claim 5, wherein, When the center level values of a plurality of the data signals are close, the plurality of the data signals are assigned to the same reference voltage.

7. The method of claim 1, wherein, The number of the reference voltages is less than the number of the data signals, and the deviation of the center level values of the signals matched by each of the reference voltages from the set values of the reference voltages is less than the programmable step size.

8. A data signal optimization apparatus, characterized by, The method comprises: a programmable reference voltage array module for generating a set of reference voltages, the voltage values of the reference voltages being dynamically configurable, and the array size being determined based on the center level floating range and the programmable step size of target data signals; a center level scanning module connected to the reference voltage array module for performing digital eye scan for each data signal to obtain the center level values of the data signals; a voltage optimization configuration module connected to the center level scanning module for calculating and setting all the voltage values in the reference voltage array according to the maximum and minimum of the center level values; a dynamic assignment execution module connected to the voltage array and the scanning module for matching the closest reference voltage for each data signal.

9. A computer device, comprising: The computer device comprises a memory and a processor, the memory has a computer program stored thereon, and the processor implements the method of any one of claims 1-7 when executing the computer program.

10. A computer-readable storage medium, characterized in that, The storage medium stores a computer program, and the computer program includes program instructions. The program instructions, when executed by a processor, can implement the method in any one of claims 1-7.

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