Access time calculator circuit, corresponding memory device and method

Abstract

The invention relates to an access time calculator circuit, a corresponding memory device and a method. A memory access time is determined via an access time calculator that includes a read data port coupled to a memory that stores alternating data segments at different memory addresses. The read data port receives data read from the memory at a memory access time in a sequence of read events from different memory addresses. Data read in a subsequent read event in the sequence exhibits switching in response to alternating data segments. The edge detector detects a switch of data read from the memory indicating an end of a previous read event in the sequence of read events. Trigger circuitry coupled to the edge detector generates a trigger signal to initiate a new read event in the sequence of read events in response to the detected switching. A duration of alternating data segments in the sequence of read events indicates an access time to the memory.

Description

[0001] CLAIM OF PRIORITY

[0002] This application claims the benefit of priority to Italian Patent Application No. 102024000010195, filed May 7, 2024, the contents of which are hereby incorporated by reference in their entirety to the maximum extent permitted by law. TECHNICAL FIELD

[0003] This specification relates to electronic memory.

[0004] Aspects of this specification can be used in non-volatile memory (NVM) whenever it is desirable to accurately measure access time at the NVM level. BACKGROUND

[0005] Flash memory technology and floating gate transistor technology currently represent the dominant technologies for electronic non-volatile memory (NVM) storage devices that can be electrically erased and reprogrammed.

[0006] This situation can undergo changes (for example, for scaling and cost reasons) and is moving towards other solutions, such as solutions based on magnetoresistive random access memory (MRAM) technology and phase change memory (PCM) technology.

[0007] Read access times are getting faster (i.e., shorter) and the ability to measure read access times in an automatic and accurate manner is a desirable feature. In fact, access times can represent an indicator of memory quality.

[0008] Access times can be measured by comparing the associated timing with the period of a reference clock. However, accurate measurements can involve (very) high frequencies of the external clock.

[0009] Read access times can be measured by using external machine initiated read instructions during electrical wafer sorting (EWS), which refers to the operation of electrically testing the dies on a silicon wafer. This solution is time consuming and input delays and output delays in the external data path can cause the measured access times to be different from the times experienced by the memory, with measurement errors proportional to the variations that the EWS machine can impose on the clock period.

[0010] There is a need in the art to contribute to solving the problems discussed in the foregoing. SUMMARY

[0011] One or more embodiments relate to a circuit.

[0012] One or more embodiments relate to corresponding apparatuses. Non-volatile memories (NVM) embedded in a system on chip (SOC) and using the circuitry described herein can be an example of such apparatuses.

[0013] It is also to be noted that the possible applications of the solution described herein are not limited to NVM memories embedded in a SOC. The solution described herein can be used whenever it is desirable to accurately measure access times at NVM level, unaffected by external paths.

[0014] One or more embodiments relate to corresponding methods.

[0015] The solution described herein is substantially independent of the memory technology involved and can theoretically be applied to any type of memory.

[0016] The solution described herein facilitates accurate measurement of read access times using a "slow" clock as a reference.

[0017] The basic idea behind the solution described herein is to use toggling of the data read from the memory to generate a new clock and use this new clock to initiate a new read.

[0018] The reads are counted until a predefined number is reached and the entire duration is measured using an (low frequency) external clock.

[0019] The solution described herein can use a finite state machine (FSM) to initiate a sequence of N reads at different addresses with alternating data, where each toggle of the data triggers the start of the next read.

[0020] Each read will then be started independently of the external clock, as it is (only) driven by the end of the previous read.

[0021] The data toggling can then be used to create a new clock with a period equal to twice the access time.

[0022] In the solution described herein, the external clock is only used to measure the entire length of the full run and the error in the average measurement will be plus or minus one full clock cycle (FCLK) on the entire run.

[0023] The solution described herein facilitates improved accuracy in measuring access times of non-volatile memories (NVM), unaffected by external data paths, where access time calculations for the entire array are done automatically, with significantly reduced test time.

[0024] The solution described herein provides one or more of the following advantages: improved accuracy of measuring access time to non-volatile memory (NVM) where the result is not affected by external data paths; automatic access time calculation across the memory array, reducing test time; access time calculator embedded in the NVM; and automatic start of read, in response to previous commutation, without being delayed by external clock. BRIEF DESCRIPTION OF DRAWINGS

[0025] One or more embodiments will now be described, by way of example only, with reference to the accompanying drawings:

[0026] Figure 1 is a block diagram example of the circuit architecture described herein;

[0027] Figure 2 is a circuit schematic diagram of possible implementation details of the circuit architecture described herein;

[0028] Figure 3 is a schematic diagram showing possible time behavior of signals that can occur in the circuit architecture described herein; and

[0029] Figure 4 is an example of possible application of the circuit architecture described herein in a system on chip (SOC). DETAILED DESCRIPTION

[0030] The drawings are intended to be illustrative and not limiting of the embodiments. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the embodiments.

[0031] The edges of the features depicted in the drawings are not intended to indicate the extent of the features, but are merely intended to illustrate the features.

[0032] In the following description, one or more specific details are described to provide an example of the embodiments. However, embodiments can be obtained without one or more of the specific details, or with other methods, components, materials, etc. In other instances, well-known structures, materials, or operations are not shown or described in detail to avoid obscuring aspects of the embodiments.

[0033] Reference throughout this specification to "an embodiment" or "one embodiment" means that a particular configuration, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrase "in an embodiment" or "in one embodiment" in various places in this specification are not necessarily referring to the same embodiment. Furthermore, the particular configurations, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0034] The headings / labels used herein are provided for convenience only and do not define the scope or meaning of the protection or the embodiments.

[0035] Throughout the drawings accompanying the present document, identical parts or elements are marked with the same reference numerals / labels and the corresponding description will not be repeated for the sake of brevity.

[0036] Again, for the sake of simplicity and ease of explanation, throughout the present description the same name can be applied to designate: a certain node or line and the signal that appears at that node or line, and / or a certain component (such as a capacitor, resistor or inductor of a coil) and its electrical parameter.

[0037] Figure 1 is a block diagram schematically representing the circuit architecture built around a memory array 100, such as a non-volatile memory (NVM) array.

[0038] Memory circuitry based on flash technology, floating gate transistor technology, magnetoresistive random access memory (MRAM) technology and phase change memory (PCM) technology can be examples of such memory array 100.

[0039] It is further noted that the solutions described herein are substantially independent of the memory technology involved. The solutions can in theory be applied to any type of memory for which it is desirable to accurately measure the access time at memory level (unaffected by external paths).

[0040] As exemplified herein, the access to the memory array represented by reference 100 occurs at an address selected based on an input signal MEMADDRESS.

[0041] The access to the memory array 100 is synchronized with a clock signal, so that the read will be initiated at the rising edge of MEMCLK.

[0042] The result of the access to the array 100 (in the case mainly considered here, the data read therefrom) is provided as an output signal FRDATA, and is assumed to occur after a certain delay with respect to the initiation of the read. This delay is commonly referred to as access time, and is a parameter indicative of the time required for each read in the array by the memory.

[0043] The element 100 discussed so far can be seen as a conventional “old logic” circuitry; for the sake of brevity, the structure and operation of such circuitry will not be further described in detail here, as it is known by those skilled in the art.

[0044] As discussed, the read access time becomes faster, and the ability to measure this time in an automatic and accurate manner is a desirable feature.

[0045] The access time can be measured by comparing the associated timing with the period of a reference clock.

[0046] For example, the read access time can be measured by initiating a read instruction and checking whether the data is correct. This can be done during electrical wafer sort (EWS) (i.e. the operation of electrically testing the dies on a silicon wafer) using an external machine. The EWS test machine for this purpose must then be able to initiate a read, check the result, and - if the data is correct - try to sample the data at a higher frequency, or - if the data is not correct - try to reduce the frequency. In order to obtain the access time for the fastest word and the slowest word in the memory, this is done for all words in the array. The relative error of the measurement is proportional to the variation in clock period that the EWS machine is able to impose.

[0047] In addition: the access time measured via word-by-word reading using an external test machine and varying the clock period requires a non-negligible amount of time, especially for large memory cuts, and the measurement is affected by the input and output delays of the external data path, so the access time measured is not exactly the access time from the memory.

[0048] The solution exemplified herein facilitates accurate measurement of the read access time using the "slow" clock FCLK as a reference.

[0049] For example, assuming an access time to the memory 100 with an associated timing of 30 ns (which is of course merely an exemplary, non-limiting value), the solution described herein facilitates the calculation of the access time TACCESS in (discussed later) by comparing the associated timing with the period of a reference clock FCLK generated in a manner known to the person skilled in the art with a (relatively low) frequency corresponding to a period of 10 ns (again, this is merely an exemplary, non-limiting value). Figure 3

[0050] The basic idea behind the solution exemplified herein is to generate a new clock (Auto_FCLK) using the toggling of the data FRDATA read from the memory 100, and to use this new clock to initiate a new read. The reads are counted until a predefined number is reached, and the entire duration is measured using an (external, low-frequency) clock such as FCLK.

[0051] To this end, the data FRDATA read from the memory 100 is sent to the read data port 200, and then onwards to the edge detector 202 to produce the "automatic" clock signal Auto_FCLK.

[0052] ​Reference 204 indicates a block for counting the number of reads performed. At each rising edge of the signal Auto_FCLK input to block 204, the read count is incremented.

[0053] Reference 205 indicates a watchdog circuit for detecting a possibly too long duration of any read.

[0054] Reference 206 indicates an address calculator circuit which generates an incremented address value at each rising edge of the signal Auto_FCLK, so that a sequence of read events occurs at different addresses.

[0055] Reference 212 represents a first multiplexer which causes the input MEMCLK of the memory array 100 to be applied thereto: either the "external" clock signal FCLK, or the "automatic" clock signal Auto_FCLK from the edge detector 202.

[0056] In that way, the toggling of the data FRDATA read from the memory 100 in response to the signal Auto_FCLK can be used to initiate a new read.

[0057] Reference 214 represents a second multiplexer which causes the input MEMADDRESS of the memory array 100 to be applied thereto: either the "external" address signal FADDR, or the "internal" address calculated in the address calculator 206.

[0058] The operation (switching) of the multiplexers 212 and 214 is controlled by a memory access enable signal AMEnable generated in a manner known per se to the person skilled in the art.

[0059] Reference 210 represents a finite state machine (FSM) which cooperates with the read counter 204, the watchdog circuit 205 and the address calculator 206 to control the flow of read events from the memory array 100, being able to stop the (access time) measurement in response to a last read event having occurred or a watchdog error being detected.

[0060] The FSM 210 is configured to be coupled to a test machine to be driven thereby.

[0061] Advantageously, such a test machine can be implemented on the basis of a conventional test equipment configured to perform the operation of electrically testing dies on silicon wafers (currently known as electrical wafer sorting (EWS)). To this end, Figure 1 The test machine shown in Fig. 1 is labelled EWS.

[0062] It will be appreciated that the test machine EWS is itself a machine for electrically testing dies on silicon wafers, as known per se. Figure 1The different elements of the access time calculator circuit indicated by reference sign 100A in the figure.

[0063] The solution described herein is in fact mainly focused on the structure and operation of the circuit 100A as a standalone entity, intended to be associated with a memory array 100 and intended to cooperate with a test machine during EWS testing in calculating the access time of the memory array 100.

[0064] To this end, the exemplary circuit 100A described herein comprises a read data port 200 configured to be coupled to the memory array 100 in which alternating data runs (e.g. FFF, 000, where a data "run" is understood to mean a consecutive occurrence of the same data bit value, such as all logical "1" bits of data (in the hexadecimal FFF example) or all logical "0" bits of data (in the hexadecimal 000 example), and "alternating" is understood to mean alternating logically opposite bit states) are stored at different memory addresses in a bit sequence. The read data port is configured to receive data such as FRDATA read (at a memory access time TACCESS) from the memory array 100 in a sequence of read events from different memory addresses. Thus, the data FRDATA read from the memory 100 in subsequent read events in the sequence exhibits toggling in response to these alternating data runs.

[0065] The exemplary circuit 100A described herein further comprises an edge detector 202 coupled to the read data port 200 and configured to detect toggling of the data FRDATA read from the memory array 100 in the subsequent read events, and trigger circuitry coupled to the edge detector 202 and configured to generate a trigger signal (such as signal Auto_FCLK) to initiate a new read event in the sequence of subsequent read events (e.g. via a multiplexer 212) in response to toggling of the data FRDATA (indicating the end of a previous read event in the sequence of subsequent read events).

[0066] Thus, the duration of the alternating data runs (e.g. FFF, 000) in the sequence of subsequent read events is indicative of the memory access time.

[0067] In an exemplary method of operation, the EWS test machine can be programmed (in a manner known per se to the person skilled in the art) to store alternating data runs such as FFF and 000 at different memory addresses in the memory array 100.

[0068] When a (new) access time is expected to be measured, the FSM 210 can then start the first read in response to an (external) control signal AMStart asserted by the EWS tester machine.

[0069] The switching of the data FRDATA read from said memory (100) during a subsequent read event can be detected using a trigger signal Auto_FCLK generated in response to the switching of the data FRDATA indicating the end of a previous read event in a sequence of subsequent read events to initiate a new read event in the sequence of subsequent read events.

[0070] The FSM 210 generates a logic output signal AMBusy which is set to a first level (e.g. “high”) when the read stream is started and which returns to a second level (e.g. “low”) when the last read has been performed.

[0071] The duration of the alternating data segments in the sequence of subsequent read events is thus indicative of the memory access time.

[0072] The FSM 210 is further configured to continuously check the watchdog block 205 in order to stop the reads and assert an output warning signal AMError upon detection of any error.

[0073] The external EWS machine will monitor the duration of the output signal AMBusy and count the number of cycles of the clock signal FCLK for the entire duration of a segment or read event (corresponding to AMBusy at high level).

[0074] Figure 2 is a circuit schematic diagram of possible implementation details of the circuit architecture described herein, mainly related to the read data port 200 and the edge detector 202 for generating the “auto” clock signal Auto_FCLK.

[0075] As shown in Figure 2 The data FRDATA read from the memory array 100 is supplied to the inputs of an AND gate 2001 providing as output a first signal Slowest_all_1 indicative of the slowest all “1” sequence in the data FRDATA or an OR gate 2002 providing as output a second signal NSlowest_all_0 indicative of the slowest all “0” sequence in the data FRDATA.

[0076] The signals Slowest_all_1 and NSlowest_all_0 are applied to the inputs of a multiplexer 2003 which outputs either of these signals depending on a “state” signal RISING_FALLING obtained as discussed below.

[0077] The output signal from multiplexer 2003 is applied to the D input of a synchronous flip-flop 2021 clocked by the signal FCLK, where the Q output of flip-flop 2021 is applied to one of the inputs of an EX-OR gate 2022, the other input of EX-OR gate 2022 receiving the output from multiplexer 2003 and producing as output the signal Auto_FCLK.

[0078] Reference numeral 2023 denotes a further flip-flop clocked by the clock signal FCLK, which receives at its D input the Q output of flip-flop 2021 and produces at its Q output the signal RISING_FALLING.

[0079] Figure 3 is a time diagram illustrating the possible limited operation of the circuitry shown in Figure 2

[0080] In particular, Figure 3 The possible time behavior of the following signals is illustrated (from top to bottom) with respect to the common abscissa time scale t:

[0081] The read signal FRDATA, in an exemplary manner, shows the possible alternation of the "all-ones" four-bit segment (hexadecimal FFF) and the "all-zeros" four-bit segment (hexadecimal 000), the cumulative duration of the latter of which is indicative of the access time TACCESS and is denoted by reference numeral 3003;

[0082] The clock signal FCLK;

[0083] The (first) signal Slowest_all_1;

[0084] The (second) signal NSlowest_all_0;

[0085] The "internal" clock signal Auto_FCLK; and

[0086] The "state" signal RISING / FALLING.

[0087] During the passage of FRDATA from FFF to 000: as a direct consequence of the falling edge of NSlowest_all_0, the rising edge of Auto_FCLK is generated - this is indicated in the figure with arrow 3001, and when the synchronous flip-flop 2021 samples NSlowest_all_0, the falling edge of Auto_FCLK is generated (the synchronous flip-flop requires two clock cycles in design) - this is indicated in the figure with arrow 3002.

[0088] ​Thus, the basic idea behind the solution described herein is to use the toggling (indicated by signal RISING / FALLING) of the data FRDATA read from the memory 100 to generate a new clock Auto_FCLK, and to use this new clock to initiate a new read.

[0089] The reads are counted (e.g., in a counter 204) until a predefined number is reached, and the overall duration is measured (e.g., by the EWS machine), wherein a (low frequency) external clock FCLK can be used as the time base for this measurement / computation.

[0090] In summary, the circuit described herein (in Figure 1 and Figure 4 labeled 100A) comprises a read data port 200 (e.g., comprising elements 2001, 2002 in the schematic of Figure 2 ) configured to be coupled to a memory array 100 (as noted, which can itself be a different element than the circuit 100A), the memory array 100 having stored therein - loadable via an EWS test machine - alternating data segments (e.g., FFF, 000) at different memory addresses. The read data port 200 is configured to receive data FRDATA read from the memory array 100 in memory access times TACCESS in a sequence of read events from different memory addresses. Thus, the data FRDATA read from the memory 100 in subsequent read events in the sequence exhibits toggling (e.g., see signal RISING / FALLING) in response to the data segments being alternating data segments (e.g., FFF, 000).

[0091] An edge detector 202 (e.g., comprising elements 2021, 2023 in the schematic of Figure 2 ) coupled to the read data port 200 is provided to detect the toggling of the data FRDATA read from the memory array 100 in the subsequent read event data.

[0092] Trigger circuitry (e.g., comprising elements 2021, 2022 in the schematic of Figure 2 ) coupled to the edge detector 202 is configured to produce a trigger signal Auto_FCLK to initiate (e.g., via a multiplexer 212) a new read event in the sequence of subsequent read events in response to the toggling of the data FRDATA, the toggling of the data FRDATA (via signal Auto_FCLK) indicating a previous read event in the sequence of subsequent read events.

[0093] The duration of the alternating data segments (FFF, 000) in the sequence of the subsequent read events (which can be measured by the EWS machine in a manner known per se to the person skilled in the art) is therefore indicative of the memory access time (TACCESS).

[0094] As can be seen, for example, in Figure 3 As can be seen, for example, in

[0095] The solution described herein uses a finite state machine (FSM 210) to initiate a sequence of n reads at different addresses with alternating data (calculated by the calculator block 206), where each data switch (signal RISING_FALLING) triggers the start of the next read via the signal Auto_CLK.

[0096] Each read will then be started independently of the external clock FCLK, as far as the read action is driven by the end of the previous read via the signal Auto_CLK received through the multiplexer 212.

[0097] The proposed solution uses the FSM 210 to initiate a sequence of n reads at different addresses with alternating data FFF, 000: the alternating data is a very common pattern, for example in the checkerboard test of a memory array.

[0098] Each switch of the data FRDATA will trigger the start of the next read. Each read will then be started independently of the external clock FCLK, as far as it will be driven by the end of the previous read.

[0099] The external clock such as FCLK is used only to measure the entire length of the complete segment. The error in the average measurement will be plus or minus one cycle of the clock cycles of the signal FCLK over the entire segment.

[0100] For example (again by way of non-limiting example only), when the period Tfclk of the signal FCLK is 2.5 ns and the complete segment length is n = 100, the error in the average access time will be plus or minus 0.025 ns.

[0101] It is noted that in the exemplary implementation given here Tfclk < (Tacc / 3), where Tacc is the access time, as far as at least three FCLK clock cycles will be involved in each read.

[0102] As discussed herein by way of example, the access time calculator circuit 100A can comprise an address calculator 206 triggered by the trigger signal Auto_FCLK and configured to generate different memory addresses MEMADDRESS to the memory array 100 to be used in the sequence of read events from different memory addresses.

[0103] Advantageously, the circuit 100A comprises a finite state machine, FSM 210, configured to implement the sequence of read events from different memory addresses as discussed before (e.g. by being coupled to the read counter 204, to the address calculator 206 and to the multiplexers 212, 214).

[0104] As shown, the finite state machine 210 comprises a first input configured to receive a start signal AMStart (e.g. from the EWS tester) to start the sequence of subsequent read events from different memory addresses and a second input configured to receive a (low frequency) clock signal FCLK.

[0105] As Figure 3 As can be seen in the schematic diagram of Fig. 2, the finite state machine 210 is configured to determine, i.e. to calculate, based on the clock signal FCLK, possibly in cooperation with the EWS tester, the (cumulative) duration of the alternating data segments read in the sequence of subsequent read events started by the start signal AMStart.

[0106] Advantageously, a counter 204 triggered by the trigger signal Auto_FCLK is provided to generate a count value of the number of subsequent read events in the sequence of subsequent read events and the FSM 210 is configured to stop the sequence of read events from different memory addresses in response to the count value generated by the counter 204 reaching a count threshold (indicated as n before).

[0107] The solution discussed herein facilitates to use one single bit of the DataBus for FRDATA or to monitor the whole bus by correspondingly configuring the read data port block 200, e.g.:

[0108] If one bit is chosen, every commutation of this bit will trigger a new read and then the result will be the access time measured for this single bit.

[0109] If all bits are monitored, the trigger will be generated when all bits have been toggled so that the result will be the access time of the slowest bit in the DataBus.

[0110] In the solution described herein, the external clock FCLK is used only to measure the entire length of the complete segment (signal AMBusy) and the error in the average measurement will be plus or minus one complete clock cycle of the signal FCLK on the entire segment.

[0111] The solution described herein facilitates achieving an improved accuracy in measuring the access time of a non-volatile memory (NVM), in terms of the measurement being unaffected by the external data path, wherein the access time calculation is performed automatically for the entire array, with a significant reduction in the test time.

[0112] The access time is the time involved in any read in the memory and is a parameter indicative of the level of performance: a high-performance memory exhibits a small access time and an accurate measurement of this parameter is highly desirable.

[0113] Figure 4 is an example of a possible application of the access time calculator circuitry described herein (indicated as a whole by the reference 100A) associated with a memory array 100, independent of the related technology, wherein the resulting arrangement (memory array 100 plus access time calculator circuitry 100A) is embedded in a system on chip (SOC) which, by way of example, comprises a microcontroller M, an address manager ADD, an analog-to-digital converter ADC, an error correction code (ECC) calculator, an oscillator OSC and any possible custom logic CL placed between the ECC and the microcontroller M.

[0114] The access time calculator circuitry 100A described herein can provide a technology-independent, NVM-level accurate measurement of the access time (unaffected by the external path) which can be applied to any memory 100.

[0115] As pointed out above, in addition to this, the possible applications of the circuit 100A described herein are not limited to NVM memories embedded in a SOC. Whenever it is desirable to accurately measure the access time at NVM level (unaffected by the external path), the solution described herein can be used.

[0116] The details and embodiments can vary with respect to what has been described by way of example only, even significantly, without affecting the basic principles, without departing from the scope of protection.

[0117] The claims are an integral part of the technical teaching provided herein with respect to the embodiments.

[0118] The scope of protection is defined by the attached claims.

Claims

1. A circuit comprising: a read data port configured to be coupled to a memory having stored therein alternating data segments located at different memory addresses; wherein the read data port is configured to receive data read from the memory at a memory access time in a sequence of read events from the different memory addresses; wherein the data read from the memory in a subsequent read event in the sequence of read events exhibits a toggle in response to the alternating data segments; an edge detector coupled to the read data port, wherein the edge detector is configured to detect the toggle in the data read from the memory in the subsequent read event; and a trigger circuitry coupled to the edge detector and configured to generate a trigger signal to initiate a new read event in the sequence of read events in response to the toggle in the data indicating an end of a previous read event in the sequence of read events; wherein a duration of the alternating data segments in the sequence of read events is indicative of the memory access time.

2. The circuit of claim 1, comprising an address calculator triggered by the trigger signal and configured to generate different memory addresses to the memory in the sequence of read events from different memory addresses.

3. The circuit of claim 1, comprising a finite state machine (FSM) configured to implement the sequence of read events from the different memory addresses, wherein the FSM comprises: a first input configured to receive a start signal for controlling initiation of the sequence of read events from different memory addresses; and a second input configured to receive a clock signal; wherein the FSM is configured to determine a cumulative duration of the alternating data segments read in the sequence of read events initiated by the start signal based on the clock signal.

4. The circuit of claim 3, comprising a counter triggered by the trigger signal and configured to generate a count value of a number of read events in the sequence of read events, wherein the FSM is configured to stop the sequence of read events from different memory addresses in response to the count value generated by the counter reaching a count threshold.

5. The circuit of claim 1, wherein the read data port comprises: an AND gate coupled to receive data output from the memory and provide a first signal indicative of a slowest logical one segment in the alternating data segments; an OR gate coupled to receive data output from the memory and provide a second signal indicative of a slowest logical zero segment in the alternating data segments; and a multiplexer configured to apply one or the other of the first and second signals to the trigger circuitry based on a state signal having a first value and a second value, respectively, generated in response to the toggle at an end of a previous read event in the sequence of read events.

6. The circuit of claim 5, comprising first and second flip-flops clocked in synchronization with data bits in the alternating data segments, wherein: ​ ​ the first flip-flop has an input configured to be driven by an output of the multiplexer and to receive the one or the other of the first signal and the second signal from the multiplexer; the second flip-flop has an input configured to be driven by an output of the first flip-flop, wherein an output of the second flip-flop provides a state signal indicative of toggling of data read from the memory in a sequence of read events; and the XOR gate has a first input coupled to receive the one or the other of the first signal and the second signal from the multiplexer and a second input coupled to the output of the first flip-flop, wherein an output of the XOR gate provides the trigger signal.

7. A memory device comprising: a memory comprising different memory addresses configured to store alternating data segments therein; and the circuit of claim 1 ; wherein the circuit is arranged with the read data port coupled to the memory; wherein the read data port is configured to receive data read from the memory in a memory access time in a sequence of read events from the different memory addresses; and wherein the circuit is configured to detect a duration of the alternating data segments in the sequence of read events, the duration being indicative of the memory access time.

8. The memory device of claim 7, wherein the memory comprises one of a flash memory, a floating gate transistor memory, a magnetoresistive random access memory, or a phase change memory.

9. A method comprising: storing alternating data segments at different memory addresses in a memory; reading the alternating data segments from the memory in a memory access time; wherein reading comprises performing a sequence of read events from the different memory addresses, wherein data read from the memory in subsequent read events in the sequence of read events exhibits toggling in response to the alternating data segments; detecting toggling of data read from the memory in the subsequent read events; and generating a trigger signal to initiate a new read event in the sequence of read events in response to the detected toggling of data indicative of an end of a previous read event in the sequence of read events, and wherein a duration of the alternating data segments in the sequence of read events is indicative of the memory access time.

10. The method of claim 9, wherein detecting toggling comprises: performing a logical AND on data output from the memory to generate a first signal indicative of a slowest logical one segment in the alternating data segments; and performing a logical OR on data output from the memory to generate a second signal indicative of a slowest logical zero segment in the alternating data segments.

11. The method of claim 10, wherein generating a trigger signal comprises selecting one or the other of the first signal and the second signal based on a state signal having a first value and a second value, respectively, wherein the state signal is generated in response to the toggling at an end of a previous read event in the sequence of read events. ​ ​

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