A 4T2FC ferroelectric memory cell and its fabrication method

Abstract

This application provides a 4T2FC ferroelectric memory cell and its fabrication method. The 4T2FC ferroelectric memory cell includes: a first memory transistor whose drain is connected to the source of a first control transistor; a second memory transistor whose drain is connected to the source of a second control transistor; a first ferroelectric capacitor connected to a first plate line and the gate of the first memory transistor; a second ferroelectric capacitor connected to a second plate line and the gate of the second memory transistor; a memory gate line connected to the gate of the first memory transistor and the gate of the second memory transistor; a control line connected to the gate of the first control transistor and the gate of the second control transistor; a bit line connected to the drain of the first control transistor and / or the second control transistor; and a source line connected to the source of the first memory transistor and / or the second memory transistor.

Description

Technical Field

[0001] This application relates to the field of ferroelectric memory technology, and in particular to a 4T2FC ferroelectric memory cell and its fabrication method. Background Technology

[0002] The development of artificial intelligence (AI) and neuromorphic computing has driven the demand for high-speed, high-density memory systems that support non-volatile in-memory computing (IMC). Compute-in-Memory (CiM) is an architecture that integrates computing functions directly into the storage array, reducing energy consumption for data movement.

[0003] Ferroelectric RAM (FRAM) is a new type of non-volatile memory (NVM) that can immediately capture and save critical data when power is interrupted. It is ideal for mission-critical data logging applications. Ferroelectric RAM adopts a low-power, miniaturized design and can provide instant non-volatility and almost unlimited endurance without affecting speed or energy efficiency.

[0004] Existing ferroelectric memories primarily employ the ferroelectric field-effect transistor (FeFET) architecture. FeFETs can possess stable multi-level states, allowing for the design of appropriate sensing circuits to detect current or threshold voltage, thus distinguishing between various states in AI applications (in-memory computing). However, due to polarization shielding effects and limitations imposed by ferroelectric domain dynamics, FeFETs are prone to durability degradation, decreased data retention capabilities, and increased sensitivity to read / write interference during high-frequency operation. Summary of the Invention

[0005] To address the shortcomings of existing technologies, the purpose of this application is to provide a 4T2FC ferroelectric memory cell and its fabrication method. By setting memory gate lines, charge leakage from the ferroelectric capacitor is prevented after writing, thereby improving data retention and writing stability.

[0006] To achieve the above objectives, this application provides a 4T2FC ferroelectric memory cell, comprising:

[0007] The first storage transistor has its drain connected to the source of the first control transistor;

[0008] The drain of the second storage transistor is connected to the source of the second control transistor;

[0009] The first ferroelectric capacitor is connected to the first plate line and the gate of the first storage transistor, respectively.

[0010] The second ferroelectric capacitor is connected to the second plate line and the gate of the second storage transistor, respectively.

[0011] The storage gate line is connected to the gate of the first storage transistor and the gate of the first storage transistor, respectively.

[0012] A control line is connected to the gates of the first control transistor and the second control transistor;

[0013] Bit lines are connected to the drain of the first control transistor and / or the second control transistor;

[0014] The source line is connected to the source of the first storage transistor and / or the second storage transistor.

[0015] Furthermore, the memory gate line is configured as follows:

[0016] During the writing phase, a reference voltage is provided to the first ferroelectric capacitor and the second ferroelectric capacitor; and

[0017] The first plate line and the second plate line work together to apply a differential voltage, so that the first ferroelectric capacitor and the second ferroelectric capacitor bear net voltages of opposite polarity.

[0018] Furthermore, the gate of the first storage transistor is formed with a first storage gate contact hole, and the gate of the second storage transistor is formed with a second storage gate contact hole;

[0019] A first storage gate contact landing pad and a second storage gate contact landing pad are formed on the first storage gate contact hole and the second storage gate contact hole, respectively;

[0020] The storage gate line is coupled to the first storage transistor gate and the second storage transistor gate through the first storage gate contact landing pad and the second storage gate contact landing pad.

[0021] Furthermore, the storage gate line is coupled to the bottom electrode of the first ferroelectric capacitor and the bottom electrode of the second ferroelectric capacitor, respectively.

[0022] Furthermore, the 4T2FC ferroelectric memory cell is configured such that during a write operation,

[0023] A programming voltage is applied through the first board line and the second board line;

[0024] The control line receives a strobe signal to control the conduction state of the first control transistor and the second control transistor.

[0025] A differential voltage is applied through the storage gate line, the first plate line, and / or the second plate line to polarize the first ferroelectric capacitor and the second ferroelectric capacitor and modulate the threshold voltage of the storage transistor gate.

[0026] Furthermore, when the 4T2FC ferroelectric memory cell is written with logic "1":

[0027] Of the first ferroelectric capacitor and the second ferroelectric capacitor, one ferroelectric capacitor is polarized in the direction toward the gate of the storage transistor, and the other ferroelectric capacitor is polarized in the direction away from the gate of the storage transistor.

[0028] When writing logical "0":

[0029] One of the ferroelectric capacitors is polarized in the direction away from the gate of the storage transistor, and the other ferroelectric capacitor is polarized in the direction toward the gate of the storage transistor.

[0030] Furthermore, the storage gate line is configured to remain at an enhanced retention or floating voltage level after a write operation to prevent charge leakage from the first ferroelectric capacitor and the second ferroelectric capacitor.

[0031] Furthermore, the 4T2FC ferroelectric memory cell is configured to: during differential read operations, sense the drain current of the first and second memory transistors through the bit line, and then determine the memory logic state based on the sensed drain current.

[0032] Furthermore, the differential readout operation includes:

[0033] The control line receives a strobe signal to control the conduction state of the first control transistor and the second control transistor.

[0034] A read voltage is applied through one of the first board line and the second board line, while the other remains grounded to establish a voltage gradient;

[0035] Float the memory gate line;

[0036] Precharge the bit line to the reference voltage;

[0037] Detect the drain current and determine the logic state based on the detected drain current.

[0038] Furthermore, the 4T2FC ferroelectric memory unit is configured in an in-memory computing memory.

[0039] To achieve the above objectives, this application also provides a method for fabricating a 4T2FC ferroelectric memory cell, comprising the following steps:

[0040] A gate oxide layer, a high dielectric constant layer, and a TiN gate electrode are sequentially deposited on a silicon substrate to form a gate stack of two storage transistors and two control transistors, respectively.

[0041] Source diffusion regions and drain diffusion regions are formed on the silicon substrate by ion implantation and activation, respectively.

[0042] Interlayer media are deposited in the source diffusion region and the drain diffusion region, respectively;

[0043] A storage gate line is formed on the gate stack of the two storage transistors;

[0044] A ferroelectric capacitor is formed on each of the memory gate lines;

[0045] Connect each of the ferroelectric capacitors to the board wires.

[0046] Furthermore, after forming the gate stack of the two storage transistors and the two control transistors, the method further includes the step of forming control lines and storage lines.

[0047] Furthermore, the step of forming a storage gate line on the gate stack of the two storage transistors further includes:

[0048] A storage gate contact coupled to the gate of the storage transistor is formed on the TiN gate electrode;

[0049] A storage gate contact landing pad is formed on the storage gate contact;

[0050] A memory gate line is formed on the memory gate contact landing pad and coupled thereto.

[0051] To achieve the above objectives, this application also provides a memory array comprising a plurality of 4T2FC ferroelectric memory cells as described above, wherein the plurality of 4T2FC ferroelectric memory cells are arranged in a matrix and share memory gate lines, control lines, bit lines, source lines, first board lines and second board lines in rows or columns.

[0052] Furthermore, it also includes peripheral circuitry, which includes a high-voltage driver for programming ferroelectric capacitors, a sensing amplifier, and a multi-line address decoder.

[0053] Furthermore, it also includes a column selection circuit, the column selection circuit being configured as follows:

[0054] Selective access to individual memory cells is achieved by controlling the connection status of each column bit line through independent column strobe signals.

[0055] During a read operation, the control lines for unselected rows are kept at a disabled level to isolate the conductive path between their memory cells and bit lines.

[0056] To achieve the above objectives, this application also provides a system-on-a-chip including at least one memory array as described above.

[0057] The 4T2FC ferroelectric memory cell provided in this application improves data retention and write stability by setting up a memory gate line to prevent charge leakage from the ferroelectric capacitor after writing.

[0058] Other features and advantages of this application will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing this application. Attached Figure Description

[0059] The accompanying drawings are provided to further illustrate the present application and form part of the specification. Together with the embodiments of the present application, they serve to explain the present application but do not constitute a limitation thereof. In the drawings:

[0060] Figure 1 This is a schematic diagram of the 4T2FC ferroelectric memory cell structure according to Embodiment 1 of this application;

[0061] Figure 2 This is a schematic diagram of the differential write logic value according to Embodiment 1 of this application;

[0062] Figure 3 This is a schematic diagram of the differential read logic value according to Embodiment 1 of this application;

[0063] Figure 4 This is a schematic diagram of the 4T2FC ferroelectric memory cell structure according to Embodiment 2 of this application;

[0064] Figure 5 This is a flowchart of the fabrication method of the 4T2FC ferroelectric memory cell according to Embodiment 3 of this application;

[0065] Figure 6 This is a schematic diagram of the active device region according to Embodiment 3 of this application;

[0066] Figure 7 This is a schematic diagram of the gate stack, memory lines, and control lines according to Embodiment 3 of this application;

[0067] Figure 8 This is a schematic diagram of the memory gate pad isolation according to Embodiment 3 of this application;

[0068] Figure 9 This is a schematic diagram of the interlayer dielectric layer and the memory gate contact hole according to Embodiment 3 of this application;

[0069] Figure 10 This is a schematic diagram of the bit line and source line contact formation according to Embodiment 3 of this application;

[0070] Figure 11 This is a schematic diagram of the memory gate contact landing pad according to Embodiment 3 of this application;

[0071] Figure 12This is a schematic diagram of the memory gate line according to Embodiment 3 of this application;

[0072] Figure 13 This is a schematic diagram of a through-hole landing pad according to Embodiment 3 of this application;

[0073] Figure 14 This is a schematic diagram of the bottom electrode metal pad according to Embodiment 3 of this application;

[0074] Figure 15 This is a schematic diagram of the stacked structure of the ferroelectric capacitor according to Embodiment 3 of this application;

[0075] Figure 16 This is a schematic diagram of the generated board lines according to Embodiment 3 of this application;

[0076] Figure 17 This is a schematic diagram of the first stage of writing "0" to a memory array according to Embodiment 4 of this application;

[0077] Figure 18 This is a schematic diagram of the second stage of writing "0" to a memory array according to some embodiments 4 of this application;

[0078] Figure 19 This is a schematic diagram of the first stage of writing "1" into a memory array according to some embodiments 4 of this application;

[0079] Figure 20 This is a schematic diagram of the second stage of writing "1" into a memory array according to some embodiments 4 of this application;

[0080] Figure 21 This is a schematic diagram of the first stage of reading data from a memory array according to some other embodiments 4 of this application;

[0081] Figure 22 This is a schematic diagram of the second stage of reading data from a memory array according to some other embodiments 4 of this application.

[0082] Figure label:

[0083] 201-Silicon substrate; 202-Gate terminal; 203-Memory gate contact hole; 204-Memory gate contact landing pad; 205-Conductive metal; 206-Bottom electrode;

[0084] 301 - Active device region; 302 - Oxide; 303 - Gate oxide layer; 304 - High-k dielectric layer; 305 - TiN gate electrode; 306 - Memory line; 307 - Control line; 308 - Source diffusion region; 309 - Drain-source diffusion region; 310 - Drain diffusion region; 311 - Memory gate pad; 312 - Source line; 313 - Bit line; 314 - Memory gate contact hole; 315 - Memory gate contact landing pad; 316 - Memory gate line; 317 - Through-hole landing pad; 318 - Bottom electrode metal pad; 319 - TiN bottom electrode; 320 - HfZrO2 ferroelectric layer; 321 - TiN top electrode; 322 - First board line; 323 - Second board line. Detailed Implementation

[0085] The preferred embodiments of this application are described below with reference to the accompanying drawings. It should be understood that the preferred embodiments described herein are for illustration and explanation only and are not intended to limit this application.

[0086] Embodiments of this application will now be described in more detail with reference to the accompanying drawings. While some embodiments of this application are shown in the drawings, it should be understood that this application can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this application. It should be understood that the drawings and embodiments of this application are for illustrative purposes only and are not intended to limit the scope of protection of this application.

[0087] The term "comprising" and its variations as used herein are open-ended inclusions, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below.

[0088] It should be noted that the terms "first" and "second" may be used in this application only to distinguish different devices, components or parts, and are not used to define the order of functions performed by these devices, components or parts or their interdependence.

[0089] It should be noted that the terms "one" and "more" used in this application are illustrative rather than restrictive, and those skilled in the art should understand that, unless explicitly stated otherwise in the context, they should be understood as "one or more". "More" should be understood as two or more.

[0090] The following terms may be used in this application:

[0091] 4T2FC (four transistors and two ferroelectric capacitors) ferroelectric memory cell: A ferroelectric memory cell containing 4 transistors and 2 ferroelectric capacitors;

[0092] CFA: First Ferroelectric Capacitor;

[0093] CFB: Second ferroelectric capacitor;

[0094] CT (Control Transistor): A control transistor used to enable or disable access to the memory path;

[0095] ST (Storage Transistor): A storage transistor that serves as the primary switch for storing and sensing storage states;

[0096] PLA: First Plate Line;

[0097] PLB: Second Plate Line;

[0098] SGL (Storage Gate Line): The storage gate line connects to the gate of the storage transistor and is used to maintain the integrity of the ferroelectric gate charge after a write operation.

[0099] BL (Bit Line): The wire connecting the drain of the control transistor, used as a channel for data reading;

[0100] SL (Source Line): The source line is the wire that connects to the source of the storage transistor. It serves as a current loop or voltage reference line and works with the bit line to complete data read and write operations.

[0101] CL (Control Line): The control line is a wire connected to the gate of the control transistor and is used to control the conduction and cutoff of the control transistor.

[0102] Definitions for other terms will be provided in the following description.

[0103] Example 1

[0104] Figure 1 The diagram below shows the structure of a 4T2FC ferroelectric memory cell according to Embodiment 1 of this application. Figure 1 As shown, the 4T2FC ferroelectric memory cell of this application embodiment includes:

[0105] The system consists of two storage transistors ST1 and ST2, two control transistors CT1 and CT2, and two ferroelectric capacitors CFA and CFB. The two storage transistors are each connected to one of the two ferroelectric capacitors, and the two control transistors are connected in series with each of the two storage transistors. The sources of both control transistors are connected to the drains of the storage transistors, which are then connected to bit lines (BLA and BLB), respectively. The gates of both control transistors are connected to the control line (CL). The sources of the two storage transistors are connected to source lines (SLA and SLB), and their gates are coupled to one end of each of the two ferroelectric capacitors. The other ends of the two ferroelectric capacitors are connected to plate lines (PLA and PLB), respectively.

[0106] The storage gate line (SGL) is connected to the gates of the two storage transistors, and is coupled to the bottom electrodes of the first and second ferroelectric capacitors, forming an electrical closed loop. Plate lines PLA and PLB are connected to the top electrodes of CFA and CFB, respectively, forming a voltage application loop.

[0107] In this embodiment of the application, the 4T2FC ferroelectric memory cell stores binary data through differential polarization of ferroelectric capacitors. The storage mechanism includes applying high positive and negative voltage pulses to the plate lines (PLA, PLB). Specifically, the 4T2FC ferroelectric memory cell is configured such that during a write operation,

[0108] Voltage pulses are applied by plate lines PLA and PLB connected to the top plates of the ferroelectric capacitors CFA and CFB;

[0109] Activate control transistors CT1 and CT2 via control line CL to enable storage transistors ST1 and ST2;

[0110] A programmable voltage is applied in conjunction with the storage gate line SGL and the plate lines PLA and PLB to induce the polarization of ferroelectric capacitors CFA and CFB, thereby causing a programmable offset of the polarization of ferroelectric capacitors CFA and CFB at the threshold voltages of storage transistors ST1 and ST2.

[0111] The programmable voltage refers to the specific voltage pulse required when writing data to a 4T2FC ferroelectric memory cell, used to change the physical state of the storage medium (such as the polarization direction of the ferroelectric material). The voltage intensity must exceed the coercivity voltage Vc of the ferroelectric material (e.g., ±3V for HfZrO2). Positive and negative voltages correspond to logic "1" and "0", respectively.

[0112] In the embodiments of this application, the storage gate line SGL is configured to: provide a reference voltage to the first and second ferroelectric capacitors during the write phase; and, in conjunction with plate lines PLA and PLB, apply a differential voltage, causing the ferroelectric capacitors CFA and CFB to experience net voltages of opposite polarities, thereby achieving differential polarization and modulating the threshold voltages of the gates of storage transistors ST1 and ST2, thus storing binary data through the differential polarization of the two ferroelectric capacitors. The polarization state of the ferroelectric capacitors is non-volatile, enabling them to retain stored data even without an external power supply.

[0113] The differential voltage refers to a pair of voltage signals that are equal in magnitude but opposite in polarity.

[0114] In embodiments of this application, the storage gate line SGL is configured to prevent charge leakage from the ferroelectric capacitor after a write operation, so as to maintain the integrity of the ferroelectric gate charge.

[0115] Specifically, when a logic "1" is written to a 4T2FC ferroelectric memory cell, one ferroelectric capacitor is polarized in the direction towards the gate of the memory transistor, while the other ferroelectric capacitor is polarized in the direction away from the gate of the memory transistor. For example, -Vpp is applied to PLB to induce CFB to polarize upward, while +Vpp is applied to PLA to induce CFA to polarize downward.

[0116] When writing logic "0", the polarization direction of the two ferroelectric capacitors is opposite to that when writing logic "1".

[0117] Figure 2 This is a schematic diagram of the differential write logic value according to Embodiment 1 of this application, as follows: Figure 2 As shown, when writing logic "0" to the 4T2FC ferroelectric memory cell: +Vpp is applied to PLB, and -Vpp is applied to PLA at the same time, and logic "0" is written to CFB.

[0118] When writing logic "1": apply -Vpp to PLB, apply +Vpp to PLA, and write logic "0" to CFA.

[0119] In the embodiments of this application, after the 4T2FC ferroelectric memory cell is written with a pulse, the memory gate line SGL is pulled to a floating or reserved enhanced voltage level to maintain strong polarization and minimize depolarization or charge leakage, preventing charge leakage from causing data degradation.

[0120] In the embodiments of this application, to prevent charge leakage on the CFA and CFB after writing, which could lead to data degradation, a post-write zeroing operation is employed, including the following steps: driving all active terminals (SGL, BL, SL, PLA, PLB, and CL) to 0V. This state is maintained before the read operation to ensure that all stored ferroelectric capacitor charges are intact. This step eliminates the capacitive memory effect that could affect the accuracy of subsequent reads or cause long-term retention loss.

[0121] In the embodiments of this application, the 4T2FC ferroelectric memory cell adopts this dual capacitor arrangement structure, which achieves high sensing margin by storing the threshold voltage offset difference caused by polarization in the transistor.

[0122] Furthermore, the write operation can be optimized using multi-level voltage technology, which reduces write interference to unselected and semi-selected cells in large arrays by applying fractional voltages in stages (such as ±2 / 3Vpp, ±1 / 3Vpp).

[0123] In the embodiments of this application, during differential read operations, the 4T2FC ferroelectric memory cell senses the drain currents of two memory transistors ST1 and ST2 through the bit line BL, and then determines the memory logic state based on the sensed drain currents.

[0124] Furthermore, the specific steps of the differential readout operation include:

[0125] The control line receives a strobe signal to control the conduction state of the first control transistor and the second control transistor.

[0126] A read voltage is applied through one of the first board line and the second board line, while the other remains grounded to establish a voltage gradient;

[0127] Float the memory gate line;

[0128] Precharge the bit line to the reference voltage;

[0129] The drain current of the storage transistor is detected by a sensing amplifier, and the storage logic state is determined based on the detected current.

[0130] Figure 3 This is a schematic diagram of the differential read logic value according to Embodiment 1 of this application, as follows: Figure 3 As shown, when the 4T2FC ferroelectric memory cell reads data:

[0131] Asserting the control line CL activates the control transistor;

[0132] Apply a small read voltage (Vread=0.7V~0.9V) to one board line (such as PLB) and keep the other board line (such as PLA) grounded to establish a voltage gradient;

[0133] The floating memory gate line SGL is affected by the net polarization state of CFA and CFB;

[0134] Apply a voltage Vd (0.2V~0.7V) to the bit line BLB and measure the drain current of the storage transistor.

[0135] The on-state of ST1 and ST2 depends on the residual polarization of CFA and CFB; the polarization state is undisturbed during reads. A high drain current (on-state) indicates one polarization state (such as logic "1"), and a low drain current (off-state) indicates the opposite polarization state (such as logic "0"). This current-based read is more reliable, supports differential sensing, and can be scaled to multi-level cell (MLC) behavior.

[0136] In the embodiments of this application, the control line CL is configured to control the gate of the control transistor to selectively enable or disable access to the storage transistor, such as enabling when CL=Vdd and disabling when CL=0V, thereby separating the control path and the access path and improving read / write reliability.

[0137] In the embodiments of this application, to prevent data degradation caused by residual charge on the gate or floating node after reading, a post-read discharge operation is employed, including the following steps: driving all active terminals (SGL, BL, SL, PLA, PLB, and CL) to 0V. Maintaining this state for a predetermined time ensures that all stored charge is neutralized. This step eliminates the capacitive memory effect that may distort subsequent reads or cause long-term retention losses.

[0138] The 4T2FC ferroelectric memory cell of this application, by integrating two pairs of series-connected storage transistors and control transistors, along with two ferroelectric capacitors (FeCAPs) and a unique gate access architecture, improves data retention, reliability, and energy efficiency, making it suitable for in-memory computing (CIM) applications in advanced AI accelerators. This architecture provides a robust, scalable, and energy-efficient solution to the limitations of existing FeRAM and FeFET memory architectures. Through dual transistor pairs and SGL-enhanced charge retention mechanisms, this structure exhibits superior performance in non-volatile in-memory computing applications, making it highly relevant in AI, neuromorphic, and edge computing technologies. It also offers the following advantages:

[0139] (1) Improved retention capability: By using a dedicated storage gate line SGL, spontaneous charge dissipation after writing is prevented, thus enhancing non-volatility.

[0140] (2) Reduce interference: The separation of storage path and control path minimizes unnecessary flipping during read and write cycles.

[0141] (3) Enhanced durability: Lower write current stress and isolated gate structure can extend device life.

[0142] (4) High energy efficiency: Supports writing with strong retention capability under low voltage, suitable for energy-constrained edge AI devices.

[0143] (5) Applicable to in-memory calculation: Through multi-level state control of dual ferroelectric capacitors, it supports analog weight storage and calculation functions.

[0144] (6) It features low power consumption and high reliability:

[0145] This was achieved by introducing a separate control transistor:

[0146] Read gating ensures that storage units are only activated when explicitly accessed;

[0147] Leakage current suppression is crucial for large arrays;

[0148] Reduce interference between units, especially during partial access;

[0149] This improves durability because the programming voltage is distributed across two ferroelectric capacitors.

[0150] These improvements significantly enhance reliability, making them particularly suitable for low-voltage or battery-constrained environments (such as edge AI chips, IoT memory modules, and IoT storage modules).

[0151] (7) Supports multiple application scenarios:

[0152] AI inference accelerator: Stores synaptic weights (adjustable parameters of the strength of connections between neurons that determine the strength of signal transmission) using non-volatile and analog computing.

[0153] Edge devices: Reduce power consumption by minimizing DRAM access and local retention weights.

[0154] Neuromorphic systems: support enabling programmable, analog-like, and highly durable non-volatile components.

[0155] (8) Process compatibility and scalability: Compatible with advanced CMOS back-end processes (BEOL), enabling compact cell size, high sensing margin with only small area ferroelectric capacitors, suitable for neuromorphic and AI-centric memory architectures; compatible with 3D BEOL integration, can be stacked on top of standard CMOS logic devices, suitable for monolithic 3D system-on-chip (SoC) architectures.

[0156] (9) Supports multi-level logic states and is suitable for analog in-memory computing memory.

[0157] Example 2

[0158] Based on Embodiment 1, this application provides an implementation scheme for the memory gate line.

[0159] Figure 4 The diagram below shows the structure of the 4T2FC ferroelectric memory cell according to Embodiment 2 of this application. Figure 4 As shown, the 4T2FC ferroelectric memory cell of this application embodiment includes memory transistors (ST1 and ST2) and control transistors (CT1 and CT2) formed on silicon substrate 201 in the FEOL (front-end process) region, and ferroelectric capacitors (CFA and CFB) and memory gate lines (SGL) formed on gate terminals 202 of memory transistors (ST1 and ST2) in the BEOL (back-end process) region.

[0160] In the embodiments of this application, SGL is formed above the logic device in the front-end process (FEOL). Further, the 4T2FC ferroelectric memory cell also includes a memory gate contact hole 203. One end of the memory gate contact hole 203 is connected to the gate terminals 202 of the memory transistors ST1 and ST2, and the other end is coupled to the memory gate line SGL through a memory gate contact landing pad 204. The memory gate line SGL is further connected to the bottom electrodes 206 of the ferroelectric capacitors CFA and CFB through a conductive metal 205.

[0161] In the embodiments of this application, one terminal of each ferroelectric capacitor is coupled to the top of the SGL and the gate of the storage transistor, and the other terminal (plate) is connected to the plate lines (PLA and PLB). Each ferroelectric capacitor includes, from bottom to top, a TiN bottom electrode, an HfZrO2 ferroelectric dielectric layer, and a TiN top electrode.

[0162] Example 3

[0163] In the embodiments of this application, a method for fabricating a 4T2FC ferroelectric memory cell is also provided, comprising the following steps: sequentially depositing a gate oxide layer, a high dielectric constant dielectric layer, and a TiN gate electrode on a silicon substrate to form gate stacks of two memory transistors and two control transistors, respectively; forming source diffusion regions and drain diffusion regions on the silicon substrate by ion implantation and activation; depositing interlayer dielectrics in the source diffusion regions and the drain diffusion regions, respectively; forming a ferroelectric capacitor on each of the gate stacks of the two memory transistors; and connecting each of the ferroelectric capacitors to a board line.

[0164] Figure 5The following is a flowchart illustrating the fabrication method of the 4T2FC ferroelectric memory cell according to Embodiment 3 of this application, with reference to... Figure 5 The fabrication method of the 4T2FC ferroelectric memory cell according to the embodiments of this application is described in detail.

[0165] First, in step 501, active areas are defined and isolated on the silicon substrate using shallow trench isolation (STI).

[0166] In the embodiments of this application, this step includes: firstly, defining a shallow trench isolation region on a silicon substrate by photolithography, and then forming an STI (Shallow Trench Isolation) trench of a predetermined depth by dry etching (such as HBr / Cl2 plasma) on the shallow trench isolation region. Multiple active device regions 301 are isolated on the silicon substrate through the trenches, thereby defining an isolation region around the active device regions 301 on the silicon substrate to prevent leakage and parasitic coupling.

[0167] In step 502, the surface of the silicon substrate is pretreated.

[0168] In embodiments of this application, the step includes: depositing oxide 302 (such as SiO2, by high-density plasma chemical vapor deposition (HDP-CVD)) in the formed trench to fill the trench; and removing excess material by chemical mechanical polishing (CMP) to retain a flat surface. Figure 6 As shown, multiple active device regions 301 are isolated on a silicon substrate by depositing oxide 302 in trenches.

[0169] In step 503, a stack of gates for storage transistors and control transistors is generated on the active device region.

[0170] In embodiments of this application, this step includes:

[0171] Growing or depositing gate oxide layer 303: Growing gate oxide, such as silicon oxynitride gate oxide (SiON gate oxide), on active device region 301, which has a high dielectric constant (high-k) (improving high-k dielectric interface states);

[0172] Depositing a high-k dielectric layer and TiN gate metal to form a gate stack: On four gate oxide layers 303, a high-k dielectric layer 304 and a TiN gate electrode 305 are generated by atomic layer deposition (ALD) to form a gate stack. The gate of the storage transistor and the gate of the control transistor are formed by photolithography and dry etching.

[0173] The patterned storage transistor gate forms a storage line (SL) 306, and the patterned control transistor gate forms a control line (CL) 307;

[0174] Ion implantation and annealing are performed to form N+ source diffusion region 308, drain-source diffusion region 309 (serving as the drain of the storage transistor and the source of the control transistor), and drain diffusion region 310. Thermal annealing activates doping and forms a low-resistance junction. Figure 7 As shown, a gate stack consisting of a gate oxide layer 303, a high-k dielectric layer 304, and a TiN gate electrode 305 is sequentially grown on the active device region 301, forming a memory line 306 and a control line 307. An N+ source diffusion region 308, a drain-source diffusion region 309, and a drain diffusion region 310 are formed by ion implantation. Finally, high-temperature annealing is performed to activate the dopant and form a low-resistance junction.

[0175] Storage gate pad isolation: The storage line 306 is cut off, leaving the portion of storage line 306 above the active device region 301 to form an independent storage gate pad (SGP) 311, such as... Figure 7 and 8 As shown.

[0176] In step 504, bit lines and source lines are generated on the drain and source diffusion regions.

[0177] In embodiments of this application, this step includes: depositing an interlayer dielectric (ILD) on the source diffusion region 308 and the drain diffusion region 310 and etching contact holes to connect the source diffusion region 308 and the drain diffusion region 310 respectively; filling the contact holes with a conductive metal (such as tungsten W or copper Cu) to form a source line (SL) 312 and a bit line (BL) 313. Figure 9 and 10 As shown, interlayer dielectric (ILD) layers are deposited in the source diffusion region 308 and the drain diffusion region 310, respectively, and source line 312 and bit line 313 are formed on the interlayer dielectric layers, respectively.

[0178] In the embodiments of this application, step 504 further includes:

[0179] ILD deposition: An oxide (such as SiO2) is deposited above the source diffusion region 308, the source-drain diffusion region 309, and the drain diffusion region 310, and planarized by CMP to generate an interlayer dielectric layer; Contact hole formation: The interlayer dielectric layer is photolithographically etched to the source diffusion region 308 and the drain diffusion region 310 to form contact holes;

[0180] Metal filling: The contact holes are filled with conductive metal to form source line 312 and bit line 313.

[0181] In step 505, a storage gate line (SGL) is formed on the gate stack of the storage transistor.

[0182] In embodiments of this application, this step includes: before forming the source line 312 and the bit line 313, forming a storage gate contact (SGC) 314 on the storage gate pad 311 that is directly coupled to the gate of the storage transistor, such as... Figure 9 As shown;

[0183] A storage gate contact landing pad (SGCLP) 315 is formed on the storage gate contact hole 314, such as Figure 11 As shown;

[0184] A memory gate line (SGL) 316 coupled to the memory gate contact landing pad 315 is formed thereon, such as Figure 12 As shown.

[0185] In step 506, a ferroelectric capacitor is formed that is connected to the storage gate line.

[0186] In embodiments of this application, this step includes:

[0187] An adjacent via landing pad (LP) 317 is etched above the memory gate line 316 and filled with a conductive material, such as... Figure 13 As shown;

[0188] A bottom electrode metal pad (BE) 318 of a ferroelectric capacitor is formed above the through-hole landing pad 317, such as Figure 14 As shown;

[0189] A TiN bottom electrode 319 is sequentially deposited on the bottom electrode metal pad 318, followed by the growth of an HfZrO2 ferroelectric layer 320 and the deposition of a TiN top electrode 321. Figure 15 As shown. The TiN bottom electrode 319 and TiN top electrode 321 are formed by PEALD deposition, while the HfZrO2 ferroelectric layer 320 is formed by ALD deposition. TiN is titanium nitride, commonly used as a conductive material for electrodes. HfZrO2 (HZO) is hafnium zirconium oxide, a high-k (dielectric constant) dielectric material with ferroelectric properties.

[0190] Annealing activates the ferroelectric layer 320 to form ferroelectric domains, completing the stacked structure of two ferroelectric capacitors (CFA and CFB).

[0191] In step 507, metal wiring is performed.

[0192] In embodiments of this application, this step includes: using a metal wiring layer to connect independent board lines PLA and PLB to CFA and CFB; metallizing and patterning, defining control line 307 and connecting it to the gate of the control transistor. Figure 16As shown, a first plate line 322 and a second plate line 323, namely PLA and PLB, are formed on the TiN top electrode 321 through an interconnect metal layer; the memory gate line 316, control line 307, bit line 313, source line 312 and other peripheral circuits are interconnected through vias.

[0193] Furthermore, it also includes: depositing a SiN (silicon nitride) etching stop layer, connecting the TiN top electrode 321 of the ferroelectric capacitor through photolithographic vias; etching trenches and electroplating copper to form board lines.

[0194] In step 508, the backend integration is completed.

[0195] In the embodiments of this application, the final step involves passivation and planarization required for semiconductor back-end process (BEOL) packaging to complete the integration of the 4T2FC ferroelectric memory cells. This step includes: applying passivation and planarization layers to protect the structure; and opening pad windows after depositing the SiN passivation layer.

[0196] The fabrication method of the 4T2FC ferroelectric memory cell in this application embodiment enables the 4T2FC ferroelectric memory cell to be seamlessly integrated onto standard CMOS logic devices, ensuring high-density scalability and making it suitable for high-density and high-performance system-on-chip (SoC) applications.

[0197] Example 4

[0198] In the embodiments of this application, a memory array is also provided, which includes a plurality of 4T2FC ferroelectric memory cells as described in Embodiment 1 or 2. The memory array employing this 4T2FC ferroelectric memory cell has the following advantages: enhanced current control, reduced charge leakage, and improved retention (the ability of data to be retained after power failure) and durability are achieved through two pairs of storage transistors and control transistors; high-density in-memory computation operations are supported through differential polarization encoding; and charge leakage from the ferroelectric capacitors after writing is prevented through additional storage gate lines (SGLs), thereby improving data retention and write stability.

[0199] In the embodiments of this application, multiple 4T2FC ferroelectric memory cells in the memory array are arranged in a matrix and share memory gate lines, control lines, bit lines, source lines, first board lines and second board lines.

[0200] In the embodiments of this application, each 4T2FC ferroelectric memory cell in the memory array is accessed using a multi-level voltage method to reduce interference to unselected and semi-selected cells.

[0201] In a memory array, a semi-selected cell refers to a memory cell that is only column-selected (activated by a word line or a storage gate line) or row-selected (activated by a bit line) during a read / write operation, but is not fully selected. Such a cell is in a potential interference state; a fully selected cell refers to a cell where both the storage gate line and the bit line are activated (an effective voltage is applied), and the cell can be read and written; an unselected cell refers to a cell where neither the storage gate line nor the bit line is activated.

[0202] In an embodiment of the present application, the writing of logic "0" in the memory array includes two stages. The first stage is as Figure 17 shown, and the second stage is as Figure 18 shown; the writing of logic "1" includes two stages. The first stage is as Figure 19 shown, and the second stage is as Figure 20 shown; the reading of data includes two stages. The first stage is as Figure 21 shown, and the second stage is as Figure 22 shown, where Vread < Vc, Vd = 0.2V - 0.7V (< Vdd). In this way, by stepwise applying fractional voltages (such as ±2 / 3Vpp, ±1 / 3Vpp) for the writing and reading of the target storage cell (Uite Cell), the read / write interference to unselected and semi-selected cells in a large memory array is effectively reduced.

[0203] In an embodiment of the present application, the memory array further includes a peripheral circuit, and this peripheral circuit includes: a high-voltage driver for ferroelectric capacitor programming, a sense amplifier, and a multi-line address decoder.

[0204] The high-voltage driver is used to generate differential high-voltage pulses (such as ±3V, pulse width 10ns) required for ferroelectric programming, and it needs to support fast switching to reduce power consumption, be compatible with the conversion from logic level (1.2V) to high voltage, and ensure compatibility with the CMOS process.

[0205] The low-leakage sense amplifier is used to detect the small current difference of the memory cell (such as ST1 / ST2), and adopts a high-gain (such as >60dB) differential input stage, which improves the read reliability.

[0206] The multi-line address decoder is used to support the independent decoding of row / column addresses (Row / Column Decoder) and achieve:

[0207] Row control: strobe the control line (CL) and the storage gate line (SGL); [[ID=3并2]]

[0208] Column selection: activate the target bit line (BL) and isolate the unselected columns.

[0209] The multi-line address decoder adopts a hierarchical decoding structure (such as pre-decoding + local driving), which reduces the delay and power consumption.

[0210] Through the coordinated action of a high-voltage driver, a sensing amplifier, and a multi-line address decoder: high-voltage writing → differential sensing → precise addressing, the high-speed, high-density, and non-volatile characteristics of the 4T2FC ferroelectric memory cell are ensured.

[0211] In embodiments of this application, the memory array further includes a column selection circuit for supporting fine-grained (highly subdivided) cell access and isolation of unselected rows based on column selection, preventing read interference. The column selection circuit is configured as follows:

[0212] Selective access to individual memory cells is achieved by controlling the connection status of each column (or row) bit line through independent column strobe signals; during read operations, the control line of the unselected row is kept at a disabled level (such as 0V) to isolate the conductive path between its memory cell and the bit line.

[0213] Example 5

[0214] In the embodiments of this application, a system-on-a-chip is also provided, including at least one memory array as described in Embodiment 4. The system-on-a-chip is configured for edge AI or neuromorphic applications, supports non-volatile, low-power and in-memory computing functions, and is used to store synaptic weights and perform logical reasoning.

[0215] It will be understood by those skilled in the art that the above descriptions are merely preferred embodiments of this application and are not intended to limit this application. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art can still modify the technical solutions described in the foregoing embodiments or make equivalent substitutions for some of the technical features. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A 4T2FC ferroelectric memory cell, characterized by, comprises: a first storage transistor having a drain connected to a source of a first control transistor; a second storage transistor having a drain connected to a source of a second control transistor; a first ferroelectric capacitor connected to a first plate line and a gate of the first storage transistor, respectively; a second ferroelectric capacitor connected to a second plate line and a gate of the second storage transistor, respectively; a storage gate line connected to the gate of the first storage transistor and the gate of the second storage transistor, respectively; a control line connected to gates of the first control transistor and the second control transistor; a first bit line connected to a drain of the first control transistor; a second bit line connected to a drain of the second control transistor; a first source line connected to a source of the first storage transistor; a second source line connected to a source of the second storage transistor.

2. The 4T2FC ferroelectric memory cell of claim 1, wherein, the storage gate line is configured to: provide a reference voltage to the first ferroelectric capacitor and the second ferroelectric capacitor during a write phase; and the first plate line and the second plate line cooperatively apply a differential voltage such that the first ferroelectric capacitor and the second ferroelectric capacitor experience a net voltage of opposite polarity.

3. The 4T2FC ferroelectric memory cell of claim 1, wherein, the gate of the first storage transistor forms a first storage gate contact hole, and the gate of the second storage transistor forms a second storage gate contact hole; a first storage gate contact landing pad and a second storage gate contact landing pad are formed on the first storage gate contact hole and the second storage gate contact hole, respectively; the storage gate line is coupled to the gate of the first storage transistor and the gate of the second storage transistor through the first storage gate contact landing pad and the second storage gate contact landing pad.

4. The 4T2FC ferroelectric memory cell of claim 3, wherein, the storage gate line is coupled to a bottom electrode of the first ferroelectric capacitor and a bottom electrode of the second ferroelectric capacitor, respectively.

5. The 4T2FC ferroelectric memory cell of claim 1, wherein, the 4T2FC ferroelectric memory cell is configured to, during a write operation, apply a programming voltage through the first plate line and the second plate line; receive a selection signal through the control line to control on / off states of the first control transistor and the second control transistor; apply a differential voltage through the storage gate line, the first plate line, and the second plate line to polarize the first ferroelectric capacitor and the second ferroelectric capacitor and modulate threshold voltages of the storage transistor gates.

6. The 4T2FC ferroelectric memory cell of claim 5, wherein, when writing a logic "1", the 4T2FC ferroelectric memory cell: one of the first ferroelectric capacitor and the second ferroelectric capacitor is polarized in a direction toward the storage transistor gates, and the other ferroelectric capacitor is polarized in a direction away from the storage transistor gates; when writing a logic "0", the 4T2FC ferroelectric memory cell: the one ferroelectric capacitor is polarized in the direction away from the storage transistor gates, and the other ferroelectric capacitor is polarized in the direction toward the storage transistor gates.

7. The 4T2FC ferroelectric memory cell of claim 5, wherein, the storage gate line is configured to, after the write operation, remain at an enhanced retention or floating voltage level to prevent charge leakage from the first ferroelectric capacitor and the second ferroelectric capacitor.

8. The 4T2FC ferroelectric memory cell of claim 1, wherein, The 4T2FC ferroelectric memory cell is configured to sense drain current of the first and second storage transistors through the first and second bit lines respectively during a differential read operation, and determine a storage logic state based on the sensed drain current.

9. The 4T2FC ferroelectric memory cell of claim 8, wherein, The differential read operation comprises: Receiving a selection signal through the control line to control on / off state of the first and second control transistors; Applying a read voltage through one of the first and second plate lines while the other is kept at ground to establish a voltage gradient; Floating or biasing the storage gate line; If the read voltage is applied through the first plate line, pre-charging the first bit line to a reference voltage; if the read voltage is applied through the second plate line, pre-charging the second bit line to a reference voltage; Detecting drain current of the first and second storage transistors, and determining a logic state based on the detected drain current.

10. The 4T2FC ferroelectric memory cell of claim 1, wherein, The 4T2FC ferroelectric memory cell is configured in an in-memory computing memory.

11. A method of fabricating a 4T2FC ferroelectric memory cell, comprising: Comprising the following steps: Depositing a gate oxide layer, a high-k dielectric layer and a TiN gate electrode on a silicon substrate in sequence to form gate stacks of two storage transistors and two control transistors respectively; Forming source and drain diffusion regions on the silicon substrate by ion implantation and activation respectively; Depositing an interlayer dielectric on the source and drain diffusion regions respectively; Forming a storage gate line on the gate stacks of the two storage transistors; Forming a ferroelectric capacitor on the storage gate line; Connecting each of the ferroelectric capacitors to a plate line.

12. The method of claim 11, wherein the 4T2FC ferroelectric memory cell is formed by: After forming the gate stacks of the two storage transistors and two control transistors, further comprising the steps of forming control lines and storage lines.

13. The method of fabricating a 4T2FC ferroelectric memory cell of claim 11, wherein, The step of forming a storage gate line on the gate stacks of the two storage transistors further comprises: Forming a storage gate contact hole coupled to the storage transistor gate on the TiN gate electrode; Forming a storage gate contact landing pad on the storage gate contact hole; Forming a storage gate line coupled to the storage gate contact landing pad on the storage gate contact landing pad.

14. A memory array, comprising: A plurality of 4T2FC ferroelectric memory cells according to any one of claims 1-10 are arranged in a matrix, and share storage gate lines, control lines, bit lines, source lines, first plate lines and second plate lines in rows or columns.

15. The memory array of claim 14, wherein, Further comprising a peripheral circuit, the peripheral circuit comprising: a high voltage driver for ferroelectric capacitor programming, a sense amplifier and a multi-line address decoder.

16. The memory array of claim 14, wherein, Further comprising a column selection circuit, the column selection circuit is configured to: Control connection state of each column bit line through an independent column selection signal to achieve selective access of a single memory cell; During a read operation, maintain the control lines of unselected rows at a disable level to isolate the conductive path between their memory cells and bit lines.

17. A system on a chip, comprising: Comprising at least one memory array according to any one of claims 14-16.

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