Method for preventing semiconductor device from electrochemical corrosion and semiconductor device
By forming a sacrificial metal layer with higher metal activity than the conductive channel on the second surface of the semiconductor layer, and utilizing the built-in potential difference to make it act as an anode to react with the cleaning solution, the problem of electrochemical corrosion of the conductive channel during the cleaning process is solved, ensuring that the conductivity is not affected.
Patent Information
- Application Number
- CN202511144106.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-08-15
- Publication Date
- 2025-11-07
AI Technical Summary
In traditional cleaning processes, the conductive channel surfaces of semiconductor devices are easily subjected to electrochemical corrosion during the cleaning process, leading to performance defects.
A sacrificial metal layer with higher metal activity than the conductive channel is formed on the second surface of the semiconductor layer. The built-in potential difference between the conductive channels allows the sacrificial metal layer to act as an anode and react with the cleaning solution, protecting the conductive channels from corrosion.
It effectively prevents the formation of surface defects in conductive channels, maintains stable conductivity, and avoids the corrosive effects of cleaning fluid on conductive channels.
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Figure CN120914086A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor devices, and in particular to a method for preventing electrochemical corrosion of a semiconductor device and a semiconductor device. BACKGROUND
[0002] In the process of forming a conductive channel of a semiconductor device, a CMP (Chemical Mechanical Polishing) process is usually used to planarize the surface of the semiconductor device. The CMP process uses a polishing liquid containing a chemical agent and a polishing pad to polish the surface of the semiconductor device under a certain pressure and speed. The chemical agent can chemically react with the material on the surface of the semiconductor device, and the mechanical action removes the reacted material through the friction of the polishing pad to achieve the polishing effect.
[0003] After the CMP process, the surface of the semiconductor device has residual polishing liquid and polishing debris, which can affect the electrical performance of the conductive channel and other performance of the semiconductor device, so it is necessary to remove the residual polishing liquid and polishing debris on the surface of the semiconductor device through a cleaning step. However, in the conventional technology, the cleaning liquid for cleaning the polishing liquid and the polishing debris can cause electrochemical corrosion on the surface of the conductive channel, resulting in defects on the surface of the conductive channel, which further affects the electrical performance of the semiconductor device. SUMMARY
[0004] In view of the above problems, the purpose of the present application is to provide a method for preventing electrochemical corrosion of a semiconductor device and a semiconductor device to prevent defects on the surface of a conductive channel of a semiconductor device.
[0005] According to an aspect of the present application, a method for preventing electrochemical corrosion of a semiconductor device is provided, the semiconductor device comprising a semiconductor layer and a first conductive channel and a second conductive channel on a first surface of the semiconductor layer, a sacrificial metal layer is formed on a second surface of the semiconductor layer, the metal activity of the sacrificial metal layer is higher than that of the first conductive channel and the second conductive channel; the surface of the first conductive channel and the second conductive channel is cleaned; and the sacrificial metal layer is removed; wherein during the cleaning process of the surface of the first conductive channel and the second conductive channel, the sacrificial metal layer formed on the second surface of the semiconductor layer replaces the first conductive channel as an anode to react with the cleaning liquid, so as to protect the first conductive channel.
[0006] Optionally, before forming the sacrificial metal layer, it further comprises: forming a barrier layer on the second surface of the semiconductor layer, and the sacrificial metal layer is formed on the surface of the barrier layer away from the semiconductor layer.
[0007] Optionally, the barrier layer is a SiCN layer.
[0008] Optionally, the sacrificial metal layer is removed by a wet etching process, and during the wet etching process, the barrier layer serves as a protective layer for the semiconductor layer.
[0009] Optionally, the etchant used to remove the sacrificial metal layer is a mixture of hydrofluoric acid, hydrogen peroxide and water, and during the process of removing the sacrificial metal layer, the side of the semiconductor layer that forms the sacrificial metal layer is in contact with the etchant, while the side of the semiconductor layer that forms the first conductive channel and the second conductive channel is not in contact with the etchant.
[0010] Optionally, the thickness of the sacrificial metal layer is less than 50 nanometers.
[0011] Optionally, after the sacrificial metal layer is removed, a step of removing the barrier layer is further included, and the barrier layer is removed by dry etching.
[0012] Optionally, the cleaning solution is an alkaline solution, the material of the first conductive channel and the second conductive channel is tungsten, and the material of the sacrificial metal layer is copper or aluminum, which has higher activity than tungsten.
[0013] Optionally, the semiconductor layer forms a first transistor and a second transistor, the first conductive channel is connected to the first transistor, the second conductive channel is connected to the second transistor, and the built-in potential of the first transistor is higher than the built-in potential of the second transistor.
[0014] According to another aspect of the present application, a semiconductor device formed by the method for preventing electrochemical corrosion of a semiconductor device is provided, and the semiconductor device includes: a semiconductor layer, which includes a first transistor and a second transistor that are complementary to each other; an interlayer dielectric layer, which covers the first transistor and the second transistor; a first conductive channel, which penetrates through the interlayer dielectric layer to reach a gate conductor, a source region and a drain region of the first transistor; and a second conductive channel, which penetrates through the interlayer dielectric layer to reach a gate conductor, a source region and a drain region of the second transistor; wherein the surfaces of the first conductive channel and the second conductive channel are free of defects.
[0015] The present application has the following unexpected technical effects:
[0016] In the embodiment of the present application, the semiconductor layer includes a first transistor and a second transistor which are complementary to each other, and the built-in potential of the first transistor is higher than that of the second transistor. When the semiconductor layer with the interlayer dielectric layer, the conductive channel and the sacrificial metal layer is placed in the cleaning solution, the sacrificial metal layer formed on the second surface of the semiconductor layer forms a conductive connection with the first conductive channel through the cleaning solution. The second conductive channel of the second transistor serves as a cathode, and the sacrificial metal layer with higher metal activity replaces the first conductive channel as an anode to react with the cleaning solution to protect the first conductive channel.
[0017] In the embodiment of the present application, the sacrificial metal layer with higher metal activity than the first conductive channel is formed on the second surface of the semiconductor layer to protect the first conductive channel with lower metal activity, so as to avoid the corrosion of the first conductive channel by the cleaning solution and ensure that the conductive performance of the first conductive channel is not affected.
[0018] Further, the present application utilizes the potential difference between the first transistor and the second transistor to cause the electrochemical corrosion process without additional external power supply. The cleaning solution realizes the conductive connection between the first conductive channel and the sacrificial metal layer, so that the sacrificial metal layer with higher metal activity can replace the first conductive channel with lower metal activity as an anode to react with the cleaning solution to protect the first conductive channel.
[0019] Further, the sacrificial metal layer is formed on the second surface of the semiconductor layer, which does not affect the structure of the conductive channel formed on the first surface of the semiconductor layer.
[0020] In the preferred embodiment, a barrier layer is introduced between the sacrificial metal layer and the semiconductor layer to prevent the metal in the sacrificial metal layer from diffusing into the semiconductor layer.
[0021] In the preferred embodiment, in the process of removing the second metal, only the back surface (i.e. the surface on which the sacrificial metal layer is formed) of the semiconductor device is contacted with the etchant, while the front surface (i.e. the surface on which the conductive channel is formed) of the semiconductor device is not contacted with the etchant, so as to protect the first conductive channel and the second conductive channel on the front surface of the semiconductor device from being corroded by the etchant.
[0022] In the preferred embodiment, the thickness of the sacrificial metal layer is set to be less than 50 nm, so as to prevent the thickness of the sacrificial metal layer from being too thick and causing the sacrificial metal layer to be difficult to be removed. BRIEF DESCRIPTION OF DRAWINGS
[0023] The above and other objects, features and advantages of the present application will become more apparent from the following description of the embodiments of the present application taken with reference to the accompanying drawings, in which:
[0024] Figure 1 A schematic diagram of a semiconductor device cleaning process in the prior art is shown;
[0025] Figures 2a to 2c A schematic view of a semiconductor device after cleaning in one embodiment of the prior art is shown, wherein:
[0026] Figure 2a is a top view of a semiconductor device after cleaning in one embodiment of the prior art;
[0027] Figure 2b is a cross-sectional view along AA direction; Figure 2a
[0028] Figure 2c is a schematic view of elemental analysis; Figure 2b
[0029] Figure 3 A flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application is shown;
[0030] Figure 4 A flow chart of a method for cleaning a surface of a conductive channel according to an embodiment of the present application is shown;
[0031] Figures 5a to 5g Cross-sectional views of various stages in the manufacturing of a semiconductor device according to an embodiment of the present application are shown, wherein:
[0032] Figure 5a A schematic view of forming a first transistor and a second transistor in a semiconductor layer according to an embodiment of the present application is shown;
[0033] Figure 5b A schematic view of forming an interlayer dielectric layer on a first surface of the semiconductor layer and forming a via through the interlayer dielectric layer according to an embodiment of the present application is shown;
[0034] Figure 5c A schematic view of forming a metal layer according to an embodiment of the present application is shown;
[0035] Figure 5d A schematic view of removing the metal layer on the surface of the interlayer dielectric layer using a CMP process according to an embodiment of the present application is shown;
[0036] Figure 5e A schematic view of sequentially forming a barrier layer and a sacrificial metal layer on a second surface of the semiconductor layer according to an embodiment of the present application is shown;
[0037] Figure 5f A schematic view of removing the polishing liquid and polishing debris according to an embodiment of the present application is shown;
[0038] Figure 5g A schematic view of removing the sacrificial metal layer and the barrier layer according to an embodiment of the present application is shown.
[0039] Reference numerals: 101 - substrate; 110 - first transistor; 120 - second transistor; 130 - interlayer dielectric layer; 141 - first conductive channel; 142 - second conductive channel; 180 - defect; 201 - substrate; 210 - first transistor; 211 - first well region; 212 - first source region; 213 - first drain region; 214 - first gate dielectric; 215 - first gate conductor; 220 - second transistor; 221 - second well region; 222 - second source region; 223 - second drain region; 224 - second gate dielectric; 225 - second gate conductor; 230 - interlayer dielectric layer; 231 - via; 240a - metal layer; 241 - first conductive channel; 242 - second conductive channel; 250 - barrier layer; 260 - sacrificial metal layer. DETAILED DESCRIPTION
[0040] The present application will be described in greater detail by referring to the drawings. Like elements in the various drawings are denoted by like reference numerals. Each portion in the drawings is not drawn to scale for the sake of clarity. Also, certain well-known portions can not be shown.
[0041] In describing the structure of a device, when a layer or a region is referred to as being "on" or "over" another layer or region, it can be directly on or over the other layer or region, or can include other layers or regions therebetween. Also, if the device is flipped, the layer or region will be "under" or "below" the other layer or region.
[0042] If for the sake of description, a layer or a region is referred to as being "directly on" or "on and adjacent to" another layer or region, it is directly on the other layer or region.
[0043] Unless otherwise specifically noted, each portion of the semiconductor device can be composed of a material known to those skilled in the art. The semiconductor material includes, for example, a group III-V semiconductor such as gallium arsenide (GaAs), gallium nitride (GaN), etc., a group IV-IV semiconductor such as silicon carbide (SiC), etc., a group II-VI compound semiconductor such as cadmium sulfide (CdS), cadmium telluride (CdTe), etc., and a group IV semiconductor such as silicon (Si), germanium (Ge), etc. The gate conductor can be formed of various materials capable of conducting electricity, such as a metal layer, a doped polysilicon layer, or a stacked gate conductor including a metal layer and a doped polysilicon layer, or other conductive materials such as TaC, TiN, TaSiN, HfSiN, TiSiN, TiCN, TaAlC, TiAlN, TaN, PtSi xSi, Ni3Si, Pt, Ru, W, and combinations of various conductive materials. The gate dielectric layer can be composed of SiO2or a material having a dielectric constant greater than SiO2, such as oxides, nitrides, oxynitrides, silicates, aluminates, titanates, for example. Also, the gate dielectric layer can be formed not only of materials known to those skilled in the art, but also of materials for the gate dielectric layer that will be developed in the future.
[0044] The present application can be presented in various forms, some examples of which will be described below.
[0045] Figure 1 A schematic diagram of a semiconductor device cleaning process in the prior art is shown in Figure 1 As shown, in the prior art, a semiconductor device includes a semiconductor layer, an interlayer dielectric layer 130 on the surface of the semiconductor layer, and a conductive via formed in the interlayer dielectric layer 130. The semiconductor layer includes a substrate 101, a first transistor 110, and a second transistor 120. There is an inherent potential difference between the first transistor 110 and the second transistor 120. A CMP (Chemical Mechanical Polishing) process is used in forming the conductive via, and the CMP process causes impurities such as polishing liquid and polishing debris to remain on the surface of the conductive via. These impurities affect the conductive performance of the conductive via, so it is necessary to remove the impurities such as polishing liquid and polishing debris remaining on the surface of the conductive via.
[0046] In the prior art, the conductive via is usually cleaned to remove the impurities such as polishing liquid and polishing debris remaining on the surface of the conductive via. Specifically, after the first conductive via 141 of the first transistor 110 and the second conductive via 142 of the second transistor 120 are formed, the conductive via is cleaned to remove the polishing liquid and polishing debris remaining on the surface of the conductive via.
[0047] Figures 2a to 2c A schematic diagram of a semiconductor device after cleaning in one embodiment of the prior art is shown in Figure 2a is a top view of a semiconductor device after cleaning in one embodiment of the prior art, Figure 2b is a cross-sectional view along the X-cut direction, Figure 2a is a cross-sectional view along the X-cut direction, Figure 2c is a cross-sectional view along the X-cut direction, Figure 2b is an elemental analysis diagram. Referring to Figure 2a and Figure 2b , the surface of the second conductive via 142 of the second transistor 120 is intact, and the surface of the first conductive via 141 of the first transistor 110 has defects 180. In order to verify the results of Figure 2a and Figure 2b , the first conductive via 141 of the first transistor 110 and the second conductive via 142 of the second transistor 120 are analyzed by energy dispersive spectroscopy (EDS). Figure 2a and Figure 2bThe first conductive channel 141 in the semiconductor device is analyzed by element analysis, and it is found that there is almost no tungsten (W) forming the first conductive channel 141 on the top of the first conductive channel 141.
[0048] The first conductive channel 141 of the first transistor 110 is defective because of the built-in potential difference between the first transistor 110 and the second transistor 120, and the cleaning solution is usually an alkaline solution. During the cleaning process, the first conductive channel 141 of the first transistor 110, the second conductive channel 142 of the second transistor 120, and the cleaning solution form a conductive loop, the first conductive channel 141 of the first transistor 110 acts as an anode, and the second conductive channel 142 of the second transistor 120 acts as a cathode. Under alkaline conditions, the first conductive channel 141 of the first transistor 110 will undergo electrochemical corrosion. The first conductive channel as an anode undergoes an oxidation reaction, and the specific reaction process is as follows:
[0049] pH 6.5-12.5: W + 8OH - = WO4 2- + 4H2O+6e -
[0050] The above oxidation reaction will cause defects 180 on the surface of the first conductive channel 141, thereby affecting the conductive performance of the semiconductor device.
[0051] Based on this, the present application provides a semiconductor device manufacturing method to prevent the conductive channel of the semiconductor device from being corroded by the cleaning solution. Figure 3 A flowchart of a semiconductor device manufacturing method according to an embodiment of the present application is shown in FIG. 1. As shown in FIG. 1, the present application provides a semiconductor device manufacturing method, which comprises the following steps: Figure 3
[0052] S10: Forming an interlayer dielectric layer on a first surface of a semiconductor layer, forming a via penetrating through the interlayer dielectric layer, and forming a metal layer, wherein the metal layer covers the surface of the interlayer dielectric layer and fills the via in the interlayer dielectric layer;
[0053] S20: Removing the metal layer on the surface of the interlayer dielectric layer by a CMP process, and forming a first conductive channel and a second conductive channel by the metal layer filling the via; and
[0054] S30: Cleaning the surfaces of the first conductive channel and the second conductive channel to remove the abrasive and abrasive debris remaining on the surfaces of the first conductive channel and the second conductive channel.
[0055] In order to prevent the first conductive channel and the second conductive channel of the semiconductor device from being corroded by the cleaning solution, the present application provides a method for preventing the semiconductor device from being electrochemically corroded. Figure 4 A flow chart of a method for preventing electrochemical corrosion of a semiconductor device is shown, according to an embodiment of the present application, as shown in Figure 4 The method for preventing electrochemical corrosion of a semiconductor device includes:
[0056] S310: forming a sacrificial metal layer on the second surface of the semiconductor layer, the metal activity of the sacrificial metal layer being higher than the metal activity of the first and second conductive channels;
[0057] S320: cleaning the surfaces of the first and second conductive channels; and
[0058] S330: removing the sacrificial metal layer;
[0059] The semiconductor layer includes a first transistor and a second transistor, and the built-in potential of the first transistor is higher than the built-in potential of the second transistor. When the surfaces of the first and second conductive channels are cleaned, the sacrificial metal layer formed on the second surface of the semiconductor layer replaces the first conductive channel as an anode to react with the cleaning solution, thereby protecting the first conductive channel.
[0060] In the embodiment of the present application, a sacrificial metal layer with a higher metal activity than the first conductive channel is formed on the second surface of the semiconductor layer, thereby protecting the first conductive channel with a lower metal activity, avoiding corrosion of the first conductive channel by the cleaning solution, and ensuring that the conductive performance of the first conductive channel is not affected.
[0061] Further, the present application utilizes the potential difference between the first and second transistors, and the electrochemical corrosion process can occur without additional external power supply. The cleaning solution realizes the conductive connection between the first conductive channel and the sacrificial metal layer, so that the sacrificial metal layer with a higher metal activity can replace the first conductive channel with a lower metal activity as an anode to react with the cleaning solution, thereby protecting the first conductive channel.
[0062] Further, the sacrificial metal layer is formed on the second surface of the semiconductor layer, and does not affect the structure of the conductive channel formed on the first surface of the semiconductor layer.
[0063] Figures 5a to 5g Cross-sectional views of various stages in the manufacturing process of a semiconductor device according to an embodiment of the present application are shown, and the manufacturing method of the semiconductor device according to the embodiment of the present application will be described below with reference to Figure 3 and Figures 5a to 5g
[0064] In step S10, an interlayer dielectric layer is formed on the first surface of the semiconductor layer, a via is formed through the interlayer dielectric layer, and a metal layer is formed, wherein the metal layer covers the surface of the interlayer dielectric layer and fills the via in the interlayer dielectric layer, as shown in Figures 5a to 5c .
[0065] Specifically, such as Figure 5a As shown, the semiconductor layer includes a substrate 201, a first transistor 210, and a second transistor 220. The substrate 201 can be composed of any of the following: a doped semiconductor substrate, a doped well region, and a doped epitaxial semiconductor layer. A first well region 211 of the first transistor 210 and a second well region 221 of the second transistor 220 are disposed in the substrate 201. These are doped regions in the substrate 201, respectively. The first well region 211 has a first doping type, and the second well region 221 has a second doping type opposite to the first doping type. For example, when the first doping type is P-type, the second doping type is N-type. Similarly, when the first doping type is N-type, the second doping type is P-type. P-type dopants may include boron (B), aluminum (Al), indium (In), or combinations thereof, while N-type dopants may include phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof.
[0066] Furthermore, a first source region 212 and a first drain region 213 of a second doping type are provided in the first well region 211. A first gate stack is provided above the first well region 211. The first gate stack includes a first gate dielectric 214 and a first gate conductor 215 stacked sequentially, wherein the first gate dielectric 214 is sandwiched between the first gate conductor 215 and the first well region 211. For example, the first gate dielectric 214 is composed of silicon oxide, and the first gate conductor 215 is composed of doped polysilicon. For an N-type MOS transistor, the first well region 211 of the first transistor 210 is doped with P-type, and the first source region 212 and the first drain region 213 are respectively doped with N-type. For a P-type MOS transistor, the first well region 211 of the first transistor 210 is doped with N-type, and the first source region 212 and the first drain region 213 are respectively doped with P-type.
[0067] The first transistor 210 and the second transistor 220 are an N-type MOS transistor and a P-type MOS transistor, respectively. The second well region 221 of the second transistor 220 has a second doping type, and a second source region 222 and a second drain region 223 of a first doping type are disposed within the second well region 221. A second gate stack is disposed above the second well region 221, comprising a second gate dielectric 224 and a second gate conductor 225 stacked sequentially, wherein the second gate dielectric 224 is sandwiched between the second gate conductor 225 and the second well region 221. For example, the second gate dielectric 224 is composed of silicon oxide, and the second gate conductor 225 is composed of doped polysilicon.
[0068] In this embodiment, the first transistor 210 is, for example, a P-type MOS transistor, and the second transistor 220 is, for example, an N-type MOS transistor. The internal potential of the first transistor 210 is higher than that of the second transistor 220. Specifically, the internal potential of the first transistor 210 is 0.2 to 0.5V higher than that of the second transistor 220.
[0069] like Figure 5b As shown, an interlayer dielectric layer 230 is formed on the first surface of the semiconductor layer, and a via 231 is formed through the interlayer dielectric layer 230.
[0070] In this step, for example, a deposition process is used to form an interlayer dielectric layer 230 on the first surface of the semiconductor layer, and a photolithography and etching process is used to form a via 231 in the interlayer dielectric layer 230. The vias reach the first gate conductor 215, the first source region 212, and the first drain region 213 of the first transistor 210, and the second gate conductor 225, the second source region 222, and the second drain region 223 of the second transistor 220.
[0071] like Figure 5c As shown, a metal layer 240a is formed.
[0072] In this step, for example, a deposition process is used to form a metal layer 240a. The metal layer 240a covers the surface of the interlayer dielectric layer 230 and fills the vias 231 in the interlayer dielectric layer 230. The metal layer 240a is in contact with the first gate conductor 215, the first source region 212, and the first drain region 213 of the first transistor 210, and the second gate conductor 225, the second source region 222, and the second drain region 223 of the second transistor 220. In one embodiment, the metal layer 240a is, for example, tungsten (W), but is not limited thereto.
[0073] Step S20: The metal layer 240a on the surface of the interlayer dielectric layer 230 is removed using a CMP process. The metal layer 240a filling the via 231 forms a first conductive channel and a second conductive channel, as shown below. Figure 5d As shown.
[0074] In this step, for example, a CMP process is used to remove the metal layer 240a on the surface of the interlayer dielectric layer 230, while retaining the metal layer 240a in the via 231. The metal layer 240a in the via 231 forms the first conductive channel 241 of the first transistor 210 and the second conductive channel 242 of the second transistor 220. The first conductive channel 241 leads the first gate conductor 215, the first source region 212 and the first drain region 213 of the first transistor 210 to the front side of the semiconductor device, respectively. The second conductive channel 242 leads the second gate conductor 225, the second source region 222 and the second drain region 223 of the second transistor 220 to the front side of the semiconductor device, respectively.
[0075] In the CMP process, a semiconductor layer with an interlayer dielectric layer 230 and a metal layer 240a is brought into contact with a polishing pad. Specifically, the metal layer 240a is in contact with the polishing pad, and polishing slurry is supplied between the metal layer 240a and the polishing pad to remove the metal layer 240a from the surface of the interlayer dielectric layer 230. After removing the metal layer 240a, the surfaces of the first conductive channel 241 and the second conductive channel 242 are left with impurities such as polishing slurry and polishing debris. These residual impurities can affect the electrical performance of the first conductive channel 241 and the second conductive channel 242, as well as other performance characteristics of the semiconductor device. Therefore, a cleaning step is required to remove the residual polishing slurry and polishing debris from the surfaces of the first conductive channel 241 and the second conductive channel 242.
[0076] Step S30: Clean the surfaces of the first and second conductive channels to remove residual polishing slurry and polishing debris, such as... Figures 5e to 5g As shown.
[0077] Specifically, such as Figure 5e As shown, a barrier layer 250 and a sacrificial metal layer 260 are sequentially formed on the second surface of the semiconductor layer. The barrier layer 250 is formed on the second surface of the semiconductor layer, and the sacrificial metal layer 260 is formed on the surface of the barrier layer 250 away from the semiconductor layer.
[0078] The barrier layer 250 is used to prevent the sacrificial metal layer 260 from diffusing into the semiconductor layer. In this embodiment, the barrier layer 250 is made of, for example, a SiCN layer. The sacrificial metal layer 260 has higher metal activity than the metal layer 240a. In one embodiment, the metal layer 240a forming the first conductive channel 241 and the second conductive channel 242 is, for example, tungsten (W), and the sacrificial metal layer 260 is, for example, copper (Cu) or aluminum (Al), which have higher metal activity than tungsten (W), but is not limited thereto. Furthermore, the thickness of the sacrificial metal layer 260 is, for example, less than 50 nanometers.
[0079] like Figure 5f As shown, the semiconductor device is placed in a cleaning solution to clean the surface of the conductive channel in order to remove the polishing solution and polishing debris.
[0080] In this step, the semiconductor device is placed in a cleaning solution with a pH value of 6.5 to 22.5. The cleaning solution establishes a conductive connection between the first conductive channel 241 and the sacrificial metal layer 260. Due to the inherent potential difference between the first transistor 210 and the second transistor 220 (specifically, the inherent potential of the first transistor 210 is 0.2V to 0.5V higher than that of the second transistor 220), and because the metal activity of the sacrificial metal layer 260 is higher than that of the metal layer 240a, under alkaline conditions, the sacrificial metal layer 260 replaces the first conductive channel 241 of the first transistor 210 as the anode and reacts with the cleaning solution, thereby protecting the first conductive channel 241 of the first transistor 210 from corrosion by the cleaning solution.
[0081] When the sacrificial metal layer 260 is made of copper, the reaction between the sacrificial metal layer 260 and the cleaning solution is as follows:
[0082] pH 6.5~22.5: Cu + 2OH - = Cu(OH)2 + 2e -
[0083] In this step, the sacrificial metal layer 260 reacts with the cleaning solution and is consumed, while the first conductive channel 241 remains unaffected. Compared to the prior art where the top of the first conductive channel 141 is consumed, resulting in a defect 180, this embodiment avoids defects on the surface of the first conductive channel 241 by introducing the sacrificial metal layer 260 on the second surface of the semiconductor layer.
[0084] like Figure 5g As shown, the sacrificial metal layer 260 and the barrier layer 250 are removed.
[0085] In this step, for example, a wet etching process is used to remove the sacrificial metal layer 260, using an etchant such as a mixed solution of hydrofluoric acid (HF), hydrogen peroxide (H2O2), and water (H2O). It is noteworthy that during the removal of the sacrificial metal layer 260, only the back side of the semiconductor device (i.e., the side where the sacrificial metal layer 260 forms) comes into contact with the etchant, while the front side of the semiconductor device (the side forming the conductive channels) remains uncontacted to protect the first conductive channels 241 and 242 on the front side of the semiconductor device from corrosion by the etchant. Specifically, the semiconductor device is rotated, and the etchant is sprayed onto the back side of the semiconductor device (i.e., the side where the sacrificial metal layer 260 forms). Next, for example, a dry etching process is used to remove the barrier layer 250.
[0086] In this embodiment, the thickness of the sacrificial metal layer 260 is set to less than 50 nm to prevent the sacrificial metal layer 260 from being too thick and thus difficult to remove.
[0087] So far, the semiconductor device formed via the above steps includes a semiconductor layer, an interlayer dielectric layer 230 on the surface of the semiconductor layer, and a conductive via formed in the interlayer dielectric layer 230, as shown in FIG. 2. The semiconductor layer includes a substrate 201, a first transistor 210, and a second transistor 220. The substrate 201 is provided with a first well region 211 of the first transistor 210 and a second well region 221 of the second transistor 220, which are respectively doped regions in the substrate 201. The first well region 211 has a first doping type, and the second well region 221 has a second doping type opposite to the first doping type. Figure 5g
[0088] Further, the first well region 211 is provided with a first source region 212 and a first drain region 213 of the second doping type, and a first gate stack is provided above the first well region 211. The first gate stack includes a first gate dielectric 214 and a first gate conductor 215 stacked in sequence, wherein the first gate dielectric 214 is sandwiched between the first gate conductor 215 and the first well region 211. For example, the first gate dielectric 214 is composed of silicon oxide, and the first gate conductor 215 is composed of doped polysilicon. For an N-type MOS transistor, the first well region 211 of the first transistor 210 is doped as P-type, and the first source region 212 and the first drain region 213 are respectively doped as N-type. For a P-type MOS transistor, the first well region 211 of the first transistor 210 is doped as N-type, and the first source region 212 and the first drain region 213 are respectively doped as P-type.
[0089] The first transistor 210 and the second transistor 220 are an N-type MOS transistor and a P-type MOS transistor complementary to each other. The second well region 221 of the second transistor 220 has the second doping type, and is provided with a second source region 222 and a second drain region 223 of the first doping type in the second well region 221. A second gate stack is provided above the second well region 221. The second gate stack includes a second gate dielectric 224 and a second gate conductor 225 stacked in sequence, wherein the second gate dielectric 224 is sandwiched between the second gate conductor 225 and the second well region 221. For example, the second gate dielectric 224 is composed of silicon oxide, and the second gate conductor 225 is composed of doped polysilicon.
[0090] The interlayer dielectric layer 230 is located on the first surface of the semiconductor layer and covers the first transistor 210 and the second transistor 220. The conductive channel is formed in the interlayer dielectric layer 230 and penetrates through the interlayer dielectric layer 230 to reach the first gate conductor 215, the first source region 212 and the first drain region 213 of the first transistor 210 and the second gate conductor 225, the second source region 222 and the second drain region 223 of the second transistor 220. The first conductive channel 241 of the first transistor 210 leads the first gate conductor 215, the first source region 212 and the first drain region 213 of the first transistor 210 to the front surface of the semiconductor device, and the second conductive channel 242 of the second transistor 220 leads the second gate conductor 225, the second source region 222 and the second drain region 223 of the second transistor 220 to the front surface of the semiconductor device.
[0091] It is worth noting that, although the above cleaning steps, but the conductive channel of the semiconductor device of the embodiment of the application, especially the surface of the first conductive channel 241 is not defective.
[0092] The unexpected technical effect of the application is:
[0093] In the embodiment of the application, the semiconductor layer includes the first transistor and the second transistor which are complementary to each other, and the built-in potential of the first transistor is higher than that of the second transistor. When the semiconductor layer formed with the interlayer dielectric layer, the conductive channel and the sacrificial metal layer is placed in the cleaning solution, the sacrificial metal layer formed on the second surface of the semiconductor layer forms a conductive connection with the first conductive channel through the cleaning solution. The second conductive channel of the second transistor acts as a cathode, and the sacrificial metal layer with higher metal activity replaces the first conductive channel as an anode to react with the cleaning solution to protect the first conductive channel.
[0094] In the embodiment of the application, the sacrificial metal layer with greater metal activity than the first conductive channel is formed on the second surface of the semiconductor layer, thereby protecting the first conductive channel with lower metal activity to avoid corrosion of the first conductive channel by the cleaning solution and ensure that the conductive performance of the first conductive channel is not affected.
[0095] Further, the application utilizes the potential difference built in the first transistor and the second transistor, and the electrochemical corrosion process can occur without additional external power supply. The cleaning solution realizes the conductive connection between the first conductive channel and the sacrificial metal layer, so that the sacrificial metal layer with higher metal activity can replace the first conductive channel with lower metal activity as an anode to react with the cleaning solution to protect the first conductive channel.
[0096] Further, the sacrificial metal layer is formed on the second surface of the semiconductor layer and does not affect the structure of the conductive channel formed on the first surface of the semiconductor layer.
[0097] In a preferred embodiment, a barrier layer is introduced between the sacrificial metal layer and the semiconductor layer to prevent the metal in the sacrificial metal layer from diffusing into the semiconductor layer.
[0098] In a preferred embodiment, only the back side of the semiconductor device (i.e. the side on which the sacrificial metal layer is formed) is contacted with the etchant during the process of removing the second metal, while the front side of the semiconductor device (i.e. the side on which the conductive channels are formed) is not contacted with the etchant, so as to protect the first and second conductive channels on the front side of the semiconductor device from being corroded by the etchant.
[0099] In a preferred embodiment, the thickness of the sacrificial metal layer is set to be less than 50 nm, so as to prevent the sacrificial metal layer from being too thick and difficult to be removed.
[0100] In accordance with the embodiments of the present application as described above, these embodiments are not described in detail with all of the possible modifications and alterations. It is apparent that many modifications and changes can be made by those skilled in the art using the above description and accompanying drawings. The present description is selected and described for the best explaining the principles of the application and the practical application, so that those skilled in the art can well utilize the application and make modifications on the basis of the application. The present application is limited only by the claims and their full scope and equivalents.
Claims
1. A method for preventing electrochemical corrosion of a semiconductor device, the semiconductor device comprising a semiconductor layer and a first conductive channel and a second conductive channel on a first surface of the semiconductor layer, the method comprising: forming a sacrificial metal layer on a second surface of the semiconductor layer, the sacrificial metal layer having a higher metal activity than the first conductive channel and the second conductive channel; cleaning surfaces of the first conductive channel and the second conductive channel; and removing the sacrificial metal layer; wherein during the cleaning of the surfaces of the first conductive channel and the second conductive channel, the sacrificial metal layer formed on the second surface of the semiconductor layer replaces the first conductive channel as an anode to react with a cleaning solution to protect the first conductive channel. Before the forming of the sacrificial metal layer, the method further comprises: forming a barrier layer on the second surface of the semiconductor layer, the sacrificial metal layer being formed on a surface of the barrier layer away from the semiconductor layer. The barrier layer is a SiCN layer. The sacrificial metal layer is removed by a wet etching process, and during the wet etching process, the barrier layer acts as a protective layer of the semiconductor layer. The etchant used to remove the sacrificial metal layer is a mixture of hydrofluoric acid, hydrogen peroxide and water, and during the removal of the sacrificial metal layer, the side of the semiconductor layer on which the sacrificial metal layer is formed is in contact with the etchant, while the side of the semiconductor layer on which the first conductive channel and the second conductive channel are formed is not in contact with the etchant. The thickness of the sacrificial metal layer is less than 50 nanometers.
2. The method of preventing electrochemical corrosion of a semiconductor device of claim 1, wherein, After the removal of the sacrificial metal layer, the method further comprises a step of removing the barrier layer, wherein the barrier layer is removed by a dry etching process.
3. The method of preventing electrochemical corrosion of a semiconductor device of claim 2, wherein, The cleaning solution is an alkaline solution, the material of the first conductive channel and the second conductive channel is tungsten, and the material of the sacrificial metal layer is copper or aluminum having a higher metal activity than tungsten.
4. The method of preventing electrochemical corrosion of a semiconductor device of claim 2, wherein, The semiconductor layer forms a first transistor and a second transistor, the first conductive channel is connected to the first transistor, the second conductive channel is connected to the second transistor, and the built-in potential of the first transistor is higher than the built-in potential of the second transistor.
5. The method of preventing electrochemical corrosion of a semiconductor device of claim 4, wherein, 10.A semiconductor device formed by the method for preventing electrochemical corrosion of a semiconductor device according to any one of claims 1-9, comprising: a semiconductor layer, the semiconductor layer comprising a first transistor and a second transistor complementary to each other; an interlayer dielectric layer, the interlayer dielectric layer covering the first transistor and the second transistor; a first conductive channel, the first conductive channel penetrating through the interlayer dielectric layer to reach a gate conductor, a source region and a drain region of the first transistor; and a second conductive channel, the second conductive channel penetrating through the interlayer dielectric layer to reach a gate conductor, a source region and a drain region of the second transistor; wherein the surfaces of the first conductive channel and the second conductive channel are free of defects.
6. The method of preventing electrochemical corrosion of a semiconductor device of claim 4, wherein, 7. The method of preventing electrochemical corrosion of a semiconductor device of claim 2, wherein, 8. The method of preventing electrochemical corrosion of a semiconductor device of claim 1, wherein, 9. The method of preventing electrochemical corrosion of a semiconductor device of claim 1, wherein,