Direct silicon bonding chip barrier strip structure and dry etching method

Abstract

The invention relates to the technical field of a direct silicon bonding chip process, in particular to a direct silicon bonding chip blocking strip structure and a dry etching method, and the method comprises the steps: firstly setting the target thickness of a top silicon layer of a direct silicon bonding chip to be a preset thickness range; etching the top silicon layer by adopting a three-stage etching process, wherein the three stages comprise a starting stage, a main etching stage and an end point control stage; in the main etching stage and the end point control stage, the intensity change of the characteristic peak of the silicon-fluorine compound is monitored in real time through an optical emission spectrum monitoring system; when the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold value, triggering the end point control stage; and in the end point control stage, a pulse process containing fluorocarbon gas is introduced, and the etching power is gradually reduced, so that the gradient reduction of the etching rate is realized, and the problems of large thickness deviation and insufficient side wall angle in the etching of the direct silicon bonding chip are solved.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of silicon direct bonding chip process, and particularly relates to a silicon direct bonding chip barrier structure and a dry etching method. BACKGROUND

[0002] In the field of semiconductor three-dimensional integration technology, the preparation of the barrier structure of a silicon direct bonding (SDB) chip depends on a high-precision etching process. The stability of the thickness of a top silicon layer directly affects the electrical performance and reliability index of a device. In particular, in high-end devices with strict requirements, thickness deviation can cause drift of key electrical parameters and loss of yield. Therefore, developing an etching method capable of achieving sub-micron precision control has become a core link to meet the needs of advanced semiconductor manufacturing.

[0003] A related technical solution monitors the etching process by means of optical emission spectrum endpoint detection. A typical method includes collecting a specific wavelength spectrum signal as a basis for process adjustment, and using a fluorine-based gas combination to achieve anisotropic etching. This type of solution attempts to make endpoint judgment through fixed-threshold spectrum analysis, and relies on constant process parameters to maintain the directionality of etching.

[0004] However, this type of solution still has significant limitations: systematic deviation in thickness control leads to unstable threshold characteristics of the device and yield reduction; insufficient anisotropy of the etching profile causes enhanced parasitic effects; and the formation of bottom micro-defects significantly degrades the voltage resistance characteristics of the device. The root cause lies in the lack of real-time dynamic regulation mechanism, making it difficult to simultaneously solve the three challenges of precision control, profile optimization and defect suppression, and failing to meet the manufacturing standards of high-reliability semiconductor devices. SUMMARY

[0005] The application provides a silicon direct bonding chip barrier structure and a dry etching method to solve the problems of large thickness deviation and insufficient sidewall angle in the etching of a silicon direct bonding chip.

[0006] The first aspect of the application provides a dry etching method for a silicon direct bonding chip barrier structure, which comprises the following steps: Setting a target thickness of a top silicon layer of a silicon direct bonding chip as a predetermined thickness range; Using a three-stage etching process to etch the top silicon layer, the three stages including a start-up stage, a main etching stage and an endpoint control stage; In the main etching stage and the endpoint control stage, the intensity change of a silicon fluoride compound characteristic peak is monitored in real time by an optical emission spectrum monitoring system; When the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold, the endpoint control stage is triggered; In the endpoint control stage, a pulse process of fluorocarbon-containing gas is introduced, and the etching power is gradually reduced to realize the gradient reduction of the etching rate.

[0007] The dry etching method realizes the gradient reduction of the etching rate by adopting the three-stage etching process and the optical emission spectrum monitoring system to monitor the intensity change of the silicon fluoride compound characteristic peak in real time, triggering the endpoint control stage when the absolute value of the second derivative exceeds the set threshold, introducing the pulse process of fluorocarbon-containing gas in the endpoint control stage and gradually reducing the etching power, thereby reducing the thickness deviation of the top silicon layer and improving the sidewall angle, so as to solve the problems of large thickness deviation and insufficient sidewall angle in the etching of silicon direct bonding chips.

[0008] Optionally, the first mixed gas is used in the starting stage, and the first mixed gas includes carbon tetrafluoride, oxygen and argon; The second mixed gas is used in the main etching stage, and the second mixed gas includes carbon tetrafluoride, oxygen and argon; The third gas is introduced in the endpoint control stage, and the third gas is octafluorocyclobutane.

[0009] The three stages use the mixed gas containing carbon tetrafluoride, oxygen and argon in the starting stage and the main etching stage, and introduce octafluorocyclobutane as the third gas in the endpoint control stage. The combination of this gas combination and process stage helps to maintain the stability of the etching process and adjust the etching characteristics in the key stage, thereby positively affecting the improvement of etching uniformity and sidewall morphology.

[0010] Optionally, the volume ratio of the first mixed gas is that carbon tetrafluoride accounts for 40% to 60%, oxygen accounts for 5% to 15%, and argon accounts for 30% to 50%; The third gas is introduced in a pulse manner, and the pulse period is 2 seconds to 5 seconds, and the duty cycle is 30% to 40%.

[0011] By controlling the volume ratio of the first mixed gas to be in the range of carbon tetrafluoride accounting for 40% to 60%, oxygen accounting for 5% to 15%, and argon accounting for 30% to 50%, and introducing the third gas in a pulse period of 2 seconds to 5 seconds and a duty cycle of 30% to 40%, the optimized gas ratio combined with the pulse parameters helps to improve the process controllability, thereby positively affecting the improvement of etching uniformity and the control of etching profile.

[0012] Optionally, the etching rate of the endpoint control stage has an exponential decay trend over time, and the etching rate of the endpoint control stage is: ; Wherein, is the etching rate; A is the initial etching rate; B is the attenuation amplitude parameter of the etching rate in the time dimension; and τ is the time constant.

[0013] The etching rate of the endpoint control stage follows an exponential decay model, achieving precise and gradual regulation of the etching rate. This controlled rate decay helps reduce the likelihood of over-etching and improves the control accuracy of etching depth and morphology.

[0014] Optionally, the characteristic peak monitored by the optical emission spectrum monitoring system is the emission peak of silicon fluoride at a wavelength of 440 nanometers; and the set threshold value is 0.5.

[0015] By setting the characteristic peak of the optical emission spectrum monitoring system as the emission peak of silicon fluoride at a wavelength of 440 nanometers and setting the judgment threshold value as 0.5, this explicit monitoring condition improves the signal specificity and response sensitivity of endpoint detection, thereby helping to reduce the risk of misjudgment of the etching endpoint and improving the accuracy of controlling the stopping time of the etching process.

[0016] Optionally, in the endpoint control stage, the etching power is reduced every predetermined time interval, and each time the power value is reduced by 50 watts until the etching rate is reduced below the target value.

[0017] By gradually reducing the etching power at predetermined time intervals in the endpoint control stage, and reducing the power value by a fixed 50 watts each time until the etching rate is reduced below the target value, this gradual power regulation method helps to achieve a smooth transition of the etching rate, thereby reducing process fluctuations and improving control of the consistency of the final etching depth.

[0018] Optionally, the method further comprises: pretreating the silicon direct bonding chip before etching, the pretreatment comprising the steps of coating photoresist, exposure, development and hardening to form a mask layer and a resist strip pattern.

[0019] By implementing the pretreatment steps of coating photoresist, exposure, development and hardening before etching to form a mask layer with a resist strip pattern, this step helps to improve the transfer accuracy of the subsequent etched pattern, thereby improving the boundary clarity of the etched pattern and reducing pattern defects.

[0020] The second aspect of the present application provides a silicon direct bonding chip resist strip structure suitable for the dry etching method of the silicon direct bonding chip resist strip structure of the first aspect, the resist strip structure comprising a top silicon layer; The thickness of the top silicon layer is within a predetermined thickness range, and the thickness uniformity is less than a predetermined low deviation value; The sidewall angle of the resist strip structure is within a predetermined steep angle range; and the surface roughness is less than a predetermined nanoscale surface roughness threshold value. The top silicon layer is formed by a dry etching process, and the dry etching process comprises three-stage etching control and optical emission spectroscopy end-point detection; the three stages comprise a start-up stage, a main etching stage and an end-point control stage.

[0021] The silicon direct bonding chip resistor bar structure has a top silicon layer with high thickness uniformity, a steep sidewall angle and low surface roughness, and these structural characteristics are achieved by a dry etching process comprising three-stage etching control and optical emission spectroscopy end-point detection, which helps to improve the geometric precision of the device structure and reduce surface topography defects, so as to solve the problems of large thickness deviation and insufficient sidewall angle in the etching of the silicon direct bonding chip.

[0022] Optionally, the predetermined thickness range is 3150 angstroms to 3250 angstroms. The predetermined low deviation value is a thickness uniformity of less than ±1.3%.

[0023] The top silicon layer of the resistor bar structure has a thickness of 3150 angstroms to 3250 angstroms and a thickness uniformity of less than ±1.3%, and this precise thickness control is achieved by a three-stage etching process, which helps to improve the size consistency of the device structure and reduce thickness fluctuations.

[0024] Optionally, the predetermined steep sidewall angle range is 89 degrees ±1 degree. The predetermined nanoscale surface roughness threshold is less than 2 nanometers. The thickness deviation of the resistor bar structure in the thermal cycle test is less than ±30 angstroms, and the electromigration failure time of the resistor bar structure is greater than 2800 hours.

[0025] The resistor bar structure has a steep sidewall angle of 89 degrees ±1 degree and a surface roughness of less than 2 nanometers, and the thickness deviation in the thermal cycle test is less than ±30 angstroms and the electromigration failure time is greater than 2800 hours, which indicates that it can maintain good size stability under thermal stress environment and has high electromigration resistance, thereby improving the reliability of long-term operation of the device.

[0026] According to the technical scheme, the application provides a silicon direct bonding chip resistor structure and a dry etching method. The method sets a target thickness of a top silicon layer of a silicon direct bonding chip as a predetermined thickness range. A three-stage etching process is used to etch the top silicon layer. The three stages include a start-up stage, a main etching stage and an endpoint control stage. In the main etching stage and the endpoint control stage, the intensity change of a silicon fluoride compound characteristic peak is monitored in real time by an optical emission spectrum monitoring system. When the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold, the endpoint control stage is triggered. In the endpoint control stage, a pulse process of a fluorocarbon-containing gas is introduced, and the etching power is gradually reduced to realize the gradient reduction of the etching rate, so as to solve the problems of large thickness deviation and insufficient sidewall angle in the etching of the silicon direct bonding chip. BRIEF DESCRIPTION OF DRAWINGS

[0027] In order to more clearly illustrate the technical scheme of the application, the drawings needed in the embodiments will be briefly introduced as follows. Obviously, other drawings can also be obtained by those skilled in the art without creative effort on the basis of these drawings.

[0028] Figure 1 A flowchart of a dry etching method of a silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure. Figure 2 An OES signal monitoring curve of the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure. Figure 3 A chip cross-section structure after pretreatment in the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure. Figure 4 A chip cross-section during a photoetch process in the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure. Figure 5 A chip cross-section after etching in the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure. Figure 6 A batch thickness distribution of the resistor structure of Example 1 in the dry etching method of the silicon direct bonding chip resistor structure provided by the embodiment of the application is shown in the figure. DETAILED DESCRIPTION

[0029] The embodiments will be described in detail below, and examples are shown in the drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following embodiments do not represent all embodiments consistent with the application. They are only examples of systems and methods consistent with some aspects of the application.

[0030] To solve the problem of large thickness deviation and insufficient sidewall angle in the etching of a silicon direct bonding chip, see Figure 1 The dry etching method of a silicon direct bonding chip barrier structure provided by some embodiments of the present application comprises the following steps: S100: Set the target thickness of the top silicon layer of the silicon direct bonding chip to a predetermined thickness range.

[0031] It should be understood that, see Figures 3-5 , the silicon direct bonding chip can comprise, from top to bottom, a top silicon layer Si (S2), a middle silicon dioxide layer SiO2 (S3), a middle silicon layer Si (S4), and a bottom silicon dioxide layer SiO2 (S3). The predetermined thickness range is 3150 angstroms to 3250 angstroms, and the target thickness of the top silicon layer of the silicon direct bonding chip is preferably 3200 angstroms.

[0032] S200: Etch the top silicon layer by using a three-stage etching process, which comprises a start-up stage, a main etching stage, and an endpoint control stage.

[0033] S210: In the main etching stage and the endpoint control stage, the intensity change of a characteristic peak of a silicon fluoride compound is monitored in real time by an optical emission spectrum monitoring system.

[0034] S220: When the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold value, the endpoint control stage is triggered.

[0035] In some embodiments, the characteristic peak monitored by the optical emission spectrum monitoring system is the emission peak of the silicon fluoride compound at a wavelength of 440 nanometers; and the set threshold value is 0.5.

[0036] It should be understood that when the absolute value of the second derivative of the intensity change of the characteristic peak is greater than 0.5, the endpoint control stage is triggered.

[0037] By specifically setting the characteristic peak of the optical emission spectrum monitoring system to the emission peak of the silicon fluoride compound at a wavelength of 440 nanometers and setting the determination threshold value to 0.5, the explicit monitoring condition improves the signal specificity and response sensitivity of the endpoint detection, thereby helping to reduce the risk of misjudgment of the etching endpoint and improving the accuracy of controlling the timing of stopping the etching process.

[0038] It should be understood that the intensity change of the characteristic peak can be captured by establishing an OES (optical emission spectrum) signal second derivative model. The OES signal second derivative model is as follows: d²I / dt²=-0.02I0e -t / τ ; Wherein, d2I / dt2 represents the second derivative of light emission intensity I with respect to time t, reflecting the curvature change of the signal; -0.02I0 is a proportional coefficient, I0 represents the initial light intensity reference value; e -t / τ is an exponential decay term, and τ is a time constant.

[0039] The model accurately determines the etching endpoint by capturing the extreme value point of the second derivative of the light intensity of a specific wavelength in real time during the etching process. When d2I / dt2 reaches a negative peak value, it indicates that the fluorocarbon passivation layer is completely penetrated, at which time the system automatically terminates etching, and the chip structure is as shown in S7.

[0040] The thickness control accuracy of 3200±50 angstroms is achieved.

[0041] When |d2I / dt2|>0.5, it is calculated in real time by synchronously passing through the thickness inversion formula, and the thickness inversion formula is: ; Wherein, d(t) represents the remaining thickness of the silicon layer at time t, d0 is the initial thickness; the integral term represents the cumulative etching depth from 0 to time t.

[0042] In the OES real-time monitoring curve, the corresponding relationship between the intensity change inflection point of the 440nm peak S8 of the carbon tetrafluoride gas and the etching endpoint is as shown in Figure 2 .

[0043] In some embodiments, the etching rate of the endpoint control stage has an exponential decay trend over time, and the etching rate of the endpoint control stage is: ; Wherein, is the etching rate; is the etching time; A is the initial etching rate, which can be 900 angstroms / minute; B is the decay amplitude parameter of the etching rate in the time dimension, which can be 900 angstroms / minute; τ is a time constant, and τ can be 180s.

[0044] The etching rate of the endpoint control stage follows an exponential decay model, achieving accurate and gradual regulation of the etching rate. This controlled rate decay helps to reduce the possibility of over-etching and improve the control accuracy of etching depth and topography.

[0045] S230: In the endpoint control stage, a pulse process containing fluorocarbon gas is introduced, and the etching power is gradually reduced to achieve a gradient decrease in the etching rate.

[0046] The dry etching method uses a three-stage etching process and an optical emission spectrum monitoring system to monitor the intensity change of the characteristic peak of the silicon fluoride compound in real time. When the absolute value of the second derivative exceeds a set threshold, the endpoint control stage is triggered. In this stage, a pulse process of fluorocarbon-containing gas is introduced and the etching power is gradually reduced to achieve a gradient decrease of the etching rate, thereby reducing the thickness deviation of the top silicon layer and improving the sidewall angle, to solve the problems of large thickness deviation and insufficient sidewall angle in the etching of silicon direct bonding chips.

[0047] In some embodiments, the start-up stage uses a first mixed gas including carbon tetrafluoride, oxygen, and argon.

[0048] Specifically, the steps of the start-up stage can be as follows: first, place the silicon direct bonding chip in the reaction chamber of the etching equipment. Then, configure the mixed gas according to the ratio of carbon tetrafluoride:oxygen:argon = 5:1:4 (vol%) and input it into the reaction chamber, and set the chamber pressure to 3 mTorr. Then, turn on the source power and set it to 450 W. Under this condition, the mixed gas reacts under the action of the electric field, quickly removing the oxide layer on the surface of the top silicon layer of the chip. During the entire start-up stage, the etching rate is monitored in real time to ensure that it is stable at 1200 angstroms per minute until the surface oxide layer is completely removed, preparing for the subsequent main etching stage.

[0049] The main etching stage uses a second mixed gas including carbon tetrafluoride, oxygen, and argon.

[0050] Specifically, the steps of the main etching stage can be as follows: first, configure the second mixed gas according to the ratio of carbon tetrafluoride:oxygen:argon = 3:2:5 (vol%) and continuously input it into the reaction chamber, and accurately control the chamber pressure at 5 mTorr. Then, adjust the source power to 600 W. Under this condition, the second mixed gas reacts under the action of the electric field to form a stable fluorocarbon passivation layer, which can effectively control the anisotropy of etching and achieve an anisotropy ratio of 1:50. During the etching process, when the etching depth reaches 3500 angstroms, immediately start the OES (optical emission spectrum) monitoring system to monitor the intensity change of the specific wavelength light generated during the etching process in real time, so as to accurately determine the etching endpoint and ensure the accuracy and consistency of the etching process.

[0051] It should be understood that in the main etching stage, gas dynamics is applied for optimization. Specifically, the fluorine atom radicals F * The relationship with the oxygen content is: F * cm -3 ; wherein F *concentration of fluorine atom radicals, in units of particles per cubic centimeter (cm-3); -3 CF4 is a proportional constant; CF4 represents the concentration of carbon tetrafluoride; O2 represents the concentration of oxygen; and the index 0.3 indicates the degree of influence of the oxygen content on the concentration of fluorine atom radicals. This means that when the ratio of carbon tetrafluoride to oxygen changes, the concentration of fluorine atom radicals will change accordingly, thereby affecting the etching rate and selectivity. At the same time, the energy distribution of argon ions under a 90V bias shows that 85% of the energy is concentrated in the range of 50-80eV, which exactly matches the sputtering threshold of the Si(100) surface.

[0052] The end-point control stage introduces a third gas, which is octafluorocyclobutane.

[0053] Specifically, the steps of the end-point control stage can be: first, when the etching depth approaches the preset end-point, accurately introduce the octafluorocyclobutane gas, and at the same time start the octafluorocyclobutane pulse supply system, set the pulse period to 3-5 seconds, and control the duty cycle in the range of 30-40%. Then, according to the real-time OES monitoring feedback, gradually adjust the source power, implement the power gradient reduction strategy, i.e. reduce the source power by 50 watts every 30 seconds, until the etching rate is stably reduced to 300 angstroms per minute. In this process, the optical emission spectrum signal is continuously monitored to ensure the accuracy of the etching end-point judgment and avoid over-etching or under-etching, thereby ensuring the integrity and performance consistency of the chip resistor structure.

[0054] The three-stage process uses a mixed gas containing carbon tetrafluoride, oxygen and argon in the start-up stage and main etching stage, and introduces octafluorocyclobutane as the third gas in the end-point control stage. This combination of gas and process stages helps to maintain the stability of the etching process and adjust the etching characteristics at key stages, thereby positively affecting the improvement of etching uniformity and sidewall morphology.

[0055] In some embodiments, the volume ratio of the first mixed gas is: 40% to 60% of carbon tetrafluoride, 5% to 15% of oxygen, and 30% to 50% of argon; The third gas is introduced in a pulsed manner, with a pulse period of 2 to 5 seconds and a duty cycle of 30% to 40%.

[0056] By controlling the volume ratio of the first mixed gas to be in the range of 40% to 60% of carbon tetrafluoride, 5% to 15% of oxygen, and 30% to 50% of argon, and introducing the third gas with a pulse period of 2 to 5 seconds and a duty cycle of 30% to 40%, this optimized gas ratio combined with pulse parameters helps to improve process controllability, thereby positively affecting the improvement of etching uniformity and control of etching profile. ​

[0057] In some embodiments, in the endpoint control phase, the etching power is reduced by a predetermined time interval, and each time the power value is reduced by 50 watts, until the etching rate is reduced to below the target value.

[0058] By gradually reducing the etching power at a predetermined time interval in the endpoint control phase, and reducing the power value by a fixed 50 watts each time, until the etching rate is reduced to below the target value, this gradual power regulation helps to achieve a smooth transition of the etching rate, thereby reducing process fluctuations and improving control of the final etching depth consistency.

[0059] In some embodiments, the method further comprises: before etching, pretreating the silicon direct bonding wafer, the pretreatment comprising the steps of coating photoresist, exposure, development and hardening, to form a mask layer and a resist strip pattern.

[0060] Specifically, first place the SDB wafer on the spin coater, spin at a set speed of 5000 r / min for 30 S, so that the photoresist AZ4620 uniformly covers the top silicon surface of the wafer, forming a mask layer with a thickness of 1 μm (S1). After spin coating, immediately transfer the wafer to the hardening equipment and harden at a temperature of 150°C for 60 S to enhance the adhesion and stability of the mask layer. At this time, the chip structure is as shown in Figure 3 .

[0061] Next, use the exposure equipment SUSS MABA6 (numerical aperture NA = 0.75) to manually expose the wafer after hardening, with an exposure time of 30 S, to form an 8 μm resist strip device (S6) pattern on the wafer.

[0062] After exposure, the chip is developed. Place the chip in the developing solution and control the developing time to 160 S to accurately remove the photoresist in the exposed part. After development, use the spin dryer to spin the chip at a speed of 7000 r / min to remove the residual developing solution on the surface.

[0063] Finally, place the chip on the hot plate again and harden at a temperature of 150°C for 60 S to make the pattern formed after development more stable. The pattern formed after development is as shown in Figure 4 .

[0064] By implementing the pretreatment steps including coating photoresist, exposure, development and hardening before etching, a mask layer with a resist strip pattern is formed, which helps to improve the accuracy of subsequent etching pattern transfer, thereby improving the boundary clarity of the etching pattern and reducing pattern defects.

[0065] Place the pretreated chip in the etching equipment and edit the parameters as follows: First, in the control interface of the etching equipment, find the gas flow setting option. Set the flow rate of carbon tetrafluoride gas to 50 sccm in the start-up stage, the flow rate of oxygen to 8 sccm, the flow rate of argon to 40 sccm, and the flow rate of octafluorocyclobutane gas to 0 sccm. Then, set the pulse frequency to 0 Hz, the power to 450 W, and the time to 1.25 minutes to complete the parameter setting of the start-up stage.

[0066] Subsequently, enter the main etching stage parameter setting. Adjust the flow rate of carbon tetrafluoride gas to 45 sccm, the flow rate of oxygen to 10 sccm, the flow rate of argon to 35 sccm, and the flow rate of octafluorocyclobutane gas to 0 sccm. Keep the pulse frequency at 0 Hz, the power at 450 W, and the time set to 2.22 minutes.

[0067] Next, set the parameters of the transition stage. Set the flow rate of carbon tetrafluoride gas to 30 sccm, the flow rate of oxygen to 0, the flow rate of argon to 40 sccm, and the flow rate of octafluorocyclobutane gas to 25 sccm. Adjust the pulse frequency to 0.2 Hz, the power to 200 W, and the time to 0.83 minutes.

[0068] Finally, set the parameters of the endpoint stage. Set the flow rate of carbon tetrafluoride gas to 15 sccm, the flow rate of oxygen to 0, the flow rate of argon to 30 sccm, and the flow rate of octafluorocyclobutane gas to 30 sccm. Adjust the pulse frequency to 0.3 Hz, the power to 150 W, and the time to 0.33 minutes.

[0069] After all the above parameter settings are completed, start the etching equipment and perform dry etching according to the set menu.

[0070] It should be noted that at the beginning of the transition stage, first pause the introduction of octafluorocyclobutane gas, while maintaining the operation of the octafluorocyclobutane gas pulse supply system, but adjust the pulse period to 2-4 seconds and the duty cycle to 25%-35% to adapt to the change in etching rate. Then, according to the change rate of the 440 nm peak intensity of carbon tetrafluoride gas monitored by OES, when the change rate of the 440 nm peak intensity stabilizes in the range of 3% / s to 4% / s, gradually adjust the source power to 80% of the initial value, and keep the etching chamber pressure stable within the preset range. In this process, the 440 nm peak intensity of carbon tetrafluoride gas in the optical emission spectrum signal and its change rate are continuously monitored to ensure smooth progress of the transition stage and lay a foundation for accurate control of the etching endpoint in the future.

[0071] In some embodiments, before the pretreatment, an appropriate amount of silicon direct bonding chip can be taken out from the storage container and placed on the slide table of a dedicated HMDS processing device to ensure that the silicon direct bonding chip is placed flat and without overlap. Then, the HMDS processing device is started, and the temperature is accurately set to 150°C according to the device operation manual. This temperature has been verified by preliminary experiments to effectively promote the good chemical adsorption reaction of HMDS and the surface of the silicon direct bonding chip, providing a stable basis for subsequent processes. Then, the processing time is set to 60 minutes. During the processing, the HMDS vapor in the device uniformly covers the surface of the silicon direct bonding chip, forming a dense chemical adsorption layer. This adsorption layer can enhance the adhesion of the photoresist to the surface of the silicon direct bonding chip and reduce problems such as delamination and pattern distortion during subsequent photoresist coating, exposure, development, and other processes. After 60 minutes of processing time, the HMDS processing device is turned off, and the HMDS-processed silicon direct bonding chip is taken out after the temperature in the device drops to a safe range. At this time, the silicon direct bonding chip has better surface properties and can enter the subsequent pretreatment process.

[0072] It should be understood that the HMDS processing refers to the process of using hexamethyldisilazane (HMDS) vapor to pretreat the surface of the silicon direct bonding chip. By accurately controlling the processing temperature and time, the HMDS vapor forms a uniform and dense chemical adsorption layer on the surface of the silicon direct bonding chip. This processing method not only improves the wettability of the surface of the silicon direct bonding chip, but also effectively removes the adsorbed water and organic contaminants on the surface, creating ideal surface conditions for subsequent photolithography processes. Experimental data show that the surface contact angle of the silicon direct bonding chip after HMDS processing can be reduced from more than 70° to less than 30°, significantly improving the uniformity of the photoresist adhesion.

[0073] Some embodiments of the present application also provide a silicon direct bonding chip barrier structure suitable for the dry etching method of the silicon direct bonding chip barrier structure described in the above embodiments. The barrier structure includes a top silicon layer; The thickness of the top silicon layer is in a predetermined thickness range, and the thickness uniformity is less than a predetermined low deviation value; The sidewall angle of the barrier structure is in a predetermined steep angle range, and the surface roughness is less than a predetermined nanoscale surface roughness threshold; The top silicon layer is formed by a dry etching process, and the dry etching process includes three-stage etching control and optical emission spectroscopy end-point detection; the three stages include a start-up stage, a main etching stage, and an end-point control stage.

[0074] It should be understood that the optical emission spectroscopy endpoint detection refers to a detection technology for judging whether the etching reaction reaches the preset endpoint in real time by monitoring the characteristic signal of the plasma emission spectrum generated in the dry etching process. By using the change of the characteristic spectral intensity generated in different etching stages and combining the pre-established endpoint judgment model, the instant when the top silicon layer etching is completed can be accurately identified, so as to timely terminate the etching process, effectively avoid over-etching or under-etching phenomenon, and ensure that the sidewall angle and surface roughness of the barrier stripe structure meet the design requirements.

[0075] The silicon direct bonding chip barrier stripe structure has a top silicon layer with high thickness uniformity, a steep sidewall angle and low surface roughness. These structural characteristics are achieved by a dry etching process including three-stage etching control and optical emission spectroscopy endpoint detection, which helps to improve the geometric accuracy of the device structure and reduce surface topography defects, so as to solve the problems of large thickness deviation and insufficient sidewall angle in the etching of silicon direct bonding chips.

[0076] In some embodiments, the predetermined thickness range is 3150 angstroms to 3250 angstroms; The predetermined low deviation value is a thickness uniformity less than ±1.3%.

[0077] The thickness of the top silicon layer of the barrier stripe structure is controlled in the range of 3150 angstroms to 3250 angstroms, and the thickness uniformity is less than ±1.3%. This precise thickness control is achieved by a three-stage etching process, which helps to improve the size consistency of the device structure and reduce thickness fluctuation.

[0078] In some embodiments, the predetermined steep sidewall angle range is 89 degrees ±1 degree; The predetermined nanoscale surface roughness threshold is less than 2 nanometers; The thickness deviation of the barrier stripe structure in the thermal cycle test is less than ±30 angstroms, and the electromigration failure time of the barrier stripe structure is greater than 2800 hours.

[0079] The barrier stripe structure has a steep sidewall angle of 89 degrees ±1 degree and a surface roughness of less than 2 nanometers, and the thickness deviation in the thermal cycle test is less than ±30 angstroms and the electromigration failure time is greater than 2800 hours. These structural characteristics indicate that it can maintain good size stability under thermal stress environment and has high electromigration resistance, thereby improving the reliability of long-term operation of the device.

[0080] For an SDB wafer with a top layer silicon thickness of 1800 angstroms, the following comparative experiments are carried out: Example 1 adopts a three-stage etching process and cooperates with octafluorocyclobutane pulse gas, realizes 1800±50 angstrom thickness control by precisely regulating the gas ratio of carbon tetrafluoride gas / oxygen / argon=3:1:6 and 350W source power, combining with double-wavelength OES (silicon tetrafluoride 440nm+silicon 700nm) endpoint detection, the sidewall angle reaches 89.2°±0.3°, the etching rate is 920 angstrom / minute, and the thickness distribution statistics (see Figure 6 ) show that the accuracy requirements are met.

[0081] Comparative Example 1 cancels the octafluorocyclobutane pulse under the same gas ratio, resulting in a thickness average of 3120 angstrom and a 3σ deviation of ±180 angstrom, a sidewall angle of 86.3°±1.2°, and an etching rate of 850 angstrom / minute, indicating that the octafluorocyclobutane pulse has a significant optimization effect on thickness uniformity and sidewall perpendicularity.

[0082] Comparative Example 2 changes the OES detection wavelength to 511nm, although the etching rate is increased to 900 angstrom / minute, the thickness average is shifted to 3350 angstrom and the 3σ deviation is ±220 angstrom, and the sidewall angle 87.5°±0.8° is also worse than that of Example 1, indicating that the combination of double wavelengths (440nm+700nm) is more conducive to precise control of the etching endpoint.

[0083] From the above technical solutions, the embodiment of the present application provides a silicon direct bonding chip barrier structure and a dry etching method. The method first sets the target thickness of the top silicon layer of the silicon direct bonding chip to a predetermined thickness range; then a three-stage etching process is used to etch the top silicon layer, the three stages including a start-up stage, a main etching stage and an endpoint control stage; in the main etching stage and the endpoint control stage, the intensity change of the silicon fluoride compound characteristic peak is monitored in real time by an optical emission spectrum monitoring system; when the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold, the endpoint control stage is triggered; in the endpoint control stage, a pulse process of fluorine-containing carbon gas is introduced, and the etching power is gradually reduced to realize the gradient reduction of the etching rate, so as to solve the problems of large thickness deviation and insufficient sidewall angle in the etching of the silicon direct bonding chip.

[0084] The similar parts between the embodiments provided by the present application can be referred to each other, and the specific embodiments provided above are only a few examples under the general concept of the present application, and do not constitute a limitation on the protection scope of the present application. For those skilled in the art, any other embodiments extended according to the present application scheme without creative labor are within the protection scope of the present application.

Claims

1. A dry etching method for a silicon direct bonded chip resistor strip structure, characterized by, The method comprises: Setting a target thickness of a top silicon layer of a silicon direct bonding chip to a predetermined thickness range; Using a three-stage etching process to etch the top silicon layer, the three stages including a start-up stage, a main etching stage and an endpoint control stage; In the main etching stage and the endpoint control stage, the intensity change of a characteristic peak of a silicon fluoride compound is monitored in real time by an optical emission spectrum monitoring system; When the absolute value of the second derivative of the intensity change of the characteristic peak is greater than a set threshold value, the endpoint control stage is triggered; In the endpoint control stage, a pulse process of a fluorocarbon-containing gas is introduced, and the etching power is gradually reduced to realize a gradient decline of the etching rate.

2. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, The start-up stage uses a first mixed gas, and the first mixed gas comprises carbon tetrafluoride, oxygen and argon; The main etching stage uses a second mixed gas, and the second mixed gas comprises carbon tetrafluoride, oxygen and argon; The endpoint control stage introduces a third gas, and the third gas is octafluorocyclobutane.

3. The dry etching method of a silicon direct bonded chip resistor structure according to claim 2, wherein, The volume ratio of the first mixed gas is that the volume ratio of methane tetrafluoride is 40% to 60%, the volume ratio of oxygen is 5% to 15%, and the volume ratio of argon is 30% to 50%; The third gas is introduced in a pulse mode, the pulse period is 2 seconds to 5 seconds, and the duty cycle is 30% to 40%.

4. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, The etching rate of the endpoint control stage presents an exponential decay trend with time, and the etching rate of the endpoint control stage is: v(t )=A-Be -t / τ ; where v(t ) is the etching rate; t is the etching time, A is the initial etching rate; B is the attenuation amplitude parameter of the etching rate in the time dimension; and τ is the time constant.

5. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, The characteristic peak monitored by the optical emission spectrum monitoring system is an emission peak of a silicon fluoride compound at a wavelength of 440 nanometers; and the set threshold value is 0.

5.

6. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, In the endpoint control stage, the etching power is reduced once every predetermined time, and the power value of each reduction is 50 watts, until the etching rate is reduced to below the target value.

7. The dry etching method of a silicon direct bonded chip resistor structure according to claim 1, wherein, The method further comprises: Before etching, the silicon direct bonding chip is pretreated, and the pretreatment comprises the steps of coating photoresist, exposure, development and hardening to form a mask layer and a resist strip pattern.

8. A silicon direct bonded chip resistor structure, characterized by, The dry etching method is suitable for the silicon direct bonding chip resist strip structure of any one of claims 1-7, and the resist strip structure comprises a top silicon layer. The thickness of the top silicon layer is in a predetermined thickness range, and the thickness uniformity is less than a predetermined low deviation value; The sidewall angle of the resist strip structure is in a predetermined steep angle range; and the surface roughness is less than a predetermined nanoscale surface roughness threshold value; The top silicon layer is formed by a dry etching process, and the dry etching process comprises three-stage etching control and optical emission spectrum endpoint detection; and the three stages include a start-up stage, a main etching stage and an endpoint control stage.

9. The silicon direct bonded chip resistor structure of claim 8, wherein, The predetermined thickness range is 3150 angstroms to 3250 angstroms; The predetermined low deviation value is that the thickness uniformity is less than ±1.3%.

10. The silicon direct bonding chip resist strip structure of claim 8, wherein The predetermined steep sidewall angle range is 89 degrees ±1 degree; The predetermined nanoscale surface roughness threshold value is less than 2 nanometers; The thickness deviation of the resist strip structure in a thermal cycle test is less than ±30 angstroms, and the electromigration failure time of the resist strip structure is greater than 2800 hours.

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