Bridge encapsulation method and encapsulation structure

Abstract

The application provides a bridging packaging method and packaging structure. The method comprises the following steps: providing a substrate provided with a first conductive column; one end of the first conductive column is flush with a first surface of the substrate, and the other end is embedded in the substrate. A first mounting groove is formed on one side of the first surface of the substrate, and a first chip is attached in the first mounting groove. The first chip comprises a main body part and a flange layer connected to the main body part, and the edge of the flange layer exceeds the edge of the main body part. The part of the flange layer exceeding the main body part is overlapped on the first surface. A first wiring layer electrically connected with the first conductive column is formed on one side of a second surface, and a third conductive column is formed on the second conductive column; a second wiring layer electrically connected with the first conductive column and the third conductive column is formed on one side of the first surface. The first chip is electrically connected with the first wiring layer and the second wiring layer respectively. Through the first chip with the flange layer, the warping deformation in the packaging process can be effectively improved, and the packaging quality is improved.

Description

Technical Field

[0001] This invention relates to the field of semiconductor packaging technology, and in particular to a bridging packaging method and packaging structure. Background Technology

[0002] With the rapid development of the semiconductor industry, chiplet technology employs a new design approach to package small chips with different functions together, forming a heterogeneous integrated chip packaging structure. Silicon bridge technology achieves electrical connections between chips by embedding small bridge chips with multiple RDLs (redistribution layers) in a substrate, effectively reducing manufacturing costs while maintaining high-density interconnect capabilities. The substrates contain different materials, some organic and some inorganic. Their coefficients of thermal expansion and elastic moduli (Young's modulus) are inconsistent, making them susceptible to thermal stress that can cause delamination of the interface layers, thus affecting product performance. Summary of the Invention

[0003] The purpose of this invention is to provide a bridging packaging method and packaging structure that can effectively improve warpage deformation in the packaging process and improve packaging quality.

[0004] In a first aspect, the present invention provides a bridging packaging method, comprising:

[0005] A substrate is provided; wherein a first conductive pillar is provided within the substrate; the substrate has a first surface and a second surface disposed opposite to each other; one end of the first conductive pillar is flush with the first surface, and the other end is embedded within the substrate;

[0006] A first mounting groove is formed on one side of the first surface of the substrate;

[0007] A first chip is mounted in the first mounting slot; wherein the first chip includes a main body and a flange layer connected to one end of the main body, the edge of the flange layer extending beyond the edge of the main body; the main body is located in the first mounting slot, and the portion of the flange layer extending beyond the main body overlaps the first surface; a second conductive post is provided inside the first chip;

[0008] Grind the second surface until the end face of the first conductive post near the second surface is exposed;

[0009] A first wiring layer electrically connected to the first conductive pillar is formed on one side of the second surface;

[0010] A first window is opened on the side of the first chip away from the second surface to expose the second conductive post;

[0011] A third conductive pillar is formed by filling the first window with metal.

[0012] A second wiring layer is formed on one side of the first surface; the second wiring layer is electrically connected to the first conductive post and the third conductive post, respectively.

[0013] The first chip is electrically connected to both the first wiring layer and the second wiring layer.

[0014] In an optional implementation, the step of forming a second wiring layer on one side of the first surface includes:

[0015] A first dielectric layer is formed on one side of the first surface; the thickness of the first dielectric layer is greater than the thickness of the flange layer.

[0016] A second window is formed on the first dielectric layer; the second window exposes the first conductive pillar and the third conductive pillar respectively;

[0017] A second wiring layer is formed by filling the second window with metal.

[0018] In an optional embodiment, the second wiring layer includes a first sub-wiring and a second sub-wiring; the step of forming the second wiring layer on one side of the first surface includes:

[0019] A second dielectric layer is formed on one side of the first surface; the thickness of the second dielectric layer is equal to the thickness of the flange layer.

[0020] A third window is formed on the second dielectric layer; the third window exposes the first conductive pillar.

[0021] A first sub-wiring layer is formed by filling the third window with metal.

[0022] A third dielectric layer covering the flange layer is formed on the first sub-wire;

[0023] A fourth window is formed on the third dielectric layer; the fourth window exposes the first sub-wiring and the third conductive post respectively;

[0024] The fourth window is filled with metal to form a second sub-wiring.

[0025] In an optional implementation, the step of mounting the first chip in the first mounting slot includes:

[0026] The first mounting groove is filled with a semi-cured first colloid;

[0027] A first chip is mounted in the first mounting groove; wherein the first chip presses against the first adhesive so that the first adhesive partially overflows onto the first surface; the flange layer is fixed to the first surface using the overflowed first adhesive; the space between the main body and the groove wall of the first mounting groove is filled with the first adhesive.

[0028] In an optional implementation, after the step of mounting the first chip in the first mounting slot, the following steps are included:

[0029] The first mounting slot is evacuated to remove the gas in the first mounting slot;

[0030] The first colloid is completely cured.

[0031] In an optional embodiment, the flange layer has a sealant portion on the side facing the first surface;

[0032] In the step of pressing the first chip with the first colloid, the first colloid partially overflows onto the first surface; the colloid blocking part is used to prevent the overflowed first colloid from spreading to areas outside the flange layer or overflowing to the side surface of the flange layer away from the first surface.

[0033] Secondly, the present invention provides a packaging structure, comprising:

[0034] A substrate having a first conductive pillar therein; the substrate having a first surface and a second surface disposed opposite to each other; one end of the first conductive pillar being flush with the first surface and the other end being flush with the second surface;

[0035] A first chip, comprising a main body and a flange layer connected to one end of the main body, wherein the edge of the flange layer extends beyond the edge of the main body;

[0036] The first chip has a third surface and a fourth surface disposed opposite to each other; the main body is provided with a first electrical connection portion and a second conductive post that are electrically connected; the end face of the first electrical connection portion away from the second conductive post is flush with the second surface, and the end face of the second conductive post away from the first electrical connection portion is connected to a third conductive post, the end face of the third conductive post away from the first electrical connection portion is flush with the first surface; the portion of the flange layer that extends beyond the main body portion overlaps the first surface.

[0037] A first wiring layer is disposed on the second surface and is electrically connected to the first conductive post and the first electrical connection portion, respectively.

[0038] A second wiring layer is disposed on the first surface and is electrically connected to the first conductive post and the third conductive post, respectively.

[0039] In an optional embodiment, a metal pillar is provided within the flange layer, and the metal pillar and the third conductive pillar are offset from each other.

[0040] In an optional embodiment, the first electrical connection includes an active wiring layer and a fourth conductive post connected together; the active wiring layer and the second conductive post are electrically connected, and the fourth conductive post and the first wiring layer are electrically connected.

[0041] In an optional embodiment, a second chip is also included; the second chip is disposed on one side of the first wiring layer and / or one side of the second wiring layer; and a molding compound covers the second chip.

[0042] In an optional embodiment, a second pad is provided between the third conductive post and the second wiring layer.

[0043] The bridging packaging method and packaging structure provided in this invention have the following advantages:

[0044] The bridging packaging method and packaging structure provided in this invention, by embedding a first chip in a substrate, achieve a compact structure, which is beneficial for high-density packaging. The first chip has a flange layer that overlaps the first surface of the substrate. In the thermal process, the flange layer can provide support and prevent warping, effectively improving warping deformation during the packaging process, enhancing packaging quality, and thus improving product performance. A third conductive post connected to the second conductive post is provided within the flange layer, which can effectively improve electrical connection performance and further mitigate deformation and warping caused by thermal stress. Attached Figure Description

[0045] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 One of the process diagrams for the bridging packaging method provided in the embodiments of the present invention;

[0047] Figure 2 This is a schematic diagram of a first structure of the first chip in the bridging packaging method provided in an embodiment of the present invention.

[0048] Figure 3 This is a schematic diagram of a second structure of the first chip in the bridging packaging method provided in an embodiment of the present invention.

[0049] Figure 4 for Figure 3 A schematic diagram of the structure in which the first chip is mounted on the substrate;

[0050] Figure 5 This is a second schematic diagram of the manufacturing process of the bridging packaging method provided in an embodiment of the present invention;

[0051] Figure 6 The third schematic diagram of the manufacturing process of the bridging packaging method provided in the embodiment of the present invention;

[0052] Figure 7 This is a schematic diagram of the first process of the second wiring layer in the bridging packaging method provided in the embodiment of the present invention;

[0053] Figure 8 This is one of the second process diagrams of the second wiring layer in the bridging packaging method provided in the embodiments of the present invention;

[0054] Figure 9 This is a second schematic diagram of the second process of the second wiring layer in the bridging packaging method provided in the embodiments of the present invention;

[0055] Figure 10 This is a schematic diagram of the process for separating individual products in the bridging packaging method provided in an embodiment of the present invention.

[0056] Figure 11 This is a schematic diagram of a first type of packaging structure provided in an embodiment of the present invention;

[0057] Figure 12 This is a schematic diagram of a second type of packaging structure provided in an embodiment of the present invention;

[0058] Figure 13 This is a schematic diagram of a third type of packaging structure provided in an embodiment of the present invention.

[0059] Icons: 100 - Package structure; 110 - Substrate; 111 - First surface; 112 - Second surface; 113 - First conductive pillar; 114 - First mounting groove; 115 - First colloid; 120 - First chip; 121 - Main body; 122 - Flange layer; 1221 - Adhesive barrier; 123 - Third surface; 124 - Fourth surface; 125 - First electrical connection; 1251 - Active wiring layer; 1252 - Fourth conductive pillar; 126 - Second conductive pillar; 127 - First window; 128 - Third conductive pillar; 129 - Metal pillar; 130 - First carrier; 131 - Bonding adhesive layer; 141- Fourth dielectric layer; 142- First wiring layer; 143- Fifth dielectric layer; 144- First bump; 145- First solder ball; 161- Second chip; 162- Molding body; 163- Second colloid; 171- First dielectric layer; 1711- Second window; 172- Second wiring layer; 1721- First sub-wiring; 1722- Second sub-wiring; 173- Second dielectric layer; 1731- Third window; 1735- Third dielectric layer; 1736- Sixth dielectric layer; 174- Second solder ball; 175- Metal layer; 190- Second pad. Detailed Implementation

[0060] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0061] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0062] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0063] In the description of this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, or the orientation or positional relationship commonly used when the product of this invention is in use. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of this invention. In addition, the terms "first," "second," "third," etc., are only used to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0064] Furthermore, terms such as "horizontal," "vertical," and "sag" do not imply that components must be absolutely horizontal or suspended, but rather that they can be slightly tilted. For example, "horizontal" simply means that its direction is more horizontal relative to "vertical," and does not mean that the structure must be completely horizontal, but can be slightly tilted.

[0065] In the description of this invention, it should also be noted that, unless otherwise explicitly specified and limited, the terms "set," "install," "connect," and "link" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; and they can refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0066] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0067] Please combine Figure 1 and Figure 11 The present invention proposes a bridging packaging method in which a first chip 120 is embedded in a substrate 110 to achieve high-density packaging. The first chip 120 has a flange layer 122 and a third conductive post 128 formed within the flange layer 122, electrically connected to a second conductive post 126. This provides support and anti-warping during the packaging process, effectively improving warping deformation, preventing structural delamination or cracking, enhancing packaging quality, and ultimately improving product performance.

[0068] The bridging encapsulation method mainly includes the following steps:

[0069] S1. A substrate 110 is provided. The substrate 110 has a first conductive post 113 disposed therein; the substrate 110 has a first surface 111 and a second surface 112 disposed opposite to each other. One end of the first conductive post 113 is flush with the first surface 111, and the other end is embedded in the substrate 110. The substrate 110 is made of silicon-based or germanium-based material, or is made of, but not limited to, silicon oxide, phosphosilicate glass, fluorinated glass, or glass. Alternatively, the substrate 110 may also be made of a molding compound material, such as ABF resin, epoxy resin, spherical silicon micropowder, or polymer. The thickness of the substrate 110 is approximately 600µm-1500µm. The first conductive post 113 may be fabricated using a TSV (Through-Vacuum Transformer) process.

[0070] S2. A first mounting groove 114 is formed on one side of the first surface 111 of the substrate 110. Optionally, the first mounting groove 114 is formed on the first surface 111 of the substrate 110 by means of dry etching or chemical etching, and the first mounting groove 114 is used to mount the first chip 120.

[0071] S3. The first chip 120 is mounted in the first mounting groove 114. The first chip 120 includes a main body 121 and a flange layer 122 connected to one end of the main body 121, the edge of the flange layer 122 extending beyond the edge of the main body 121; the main body 121 is located in the first mounting groove 114, and the portion of the flange layer 122 extending beyond the main body 121 overlaps with the first surface 111; the first chip 120 is provided with a second conductive post 126.

[0072] Optionally, S3 includes steps S31 and S32.

[0073] S31. A semi-cured first colloid 115 is filled into the first mounting groove 114. Optionally, a liquid first colloid 115 is filled into the first mounting groove 114 using a coating process. The first colloid 115 is heated and baked to a semi-cured state. The baking temperature is approximately 50 to 80 degrees Celsius, and the baking time is approximately 5 to 15 minutes, so that the first colloid 115 becomes a film, i.e., a semi-cured state.

[0074] S32. The first chip 120 is mounted in the first mounting groove 114. During the mounting process, the first chip 120 is pressed into the first adhesive 115 in the first mounting groove 114 using a mounting head. During the pressing of the first chip 120, the first adhesive 115 overflows from the opening of the first mounting groove 114 onto the first surface 111 of the substrate 110. The overflowing first adhesive 115 contacts the flange layer 122 of the first chip 120, thereby achieving an adhesive effect and fixing the flange layer 122 to the first surface 111. It can be understood that the gap between the main body 121 of the first chip 120 and the groove wall of the first mounting groove 114 is filled with the first adhesive 115, achieving adhesion to the main body 121.

[0075] Optionally, a vacuum is evacuated from the first mounting groove 114 to remove any gas, ensuring that the first colloid 115 is pressed into the groove without voids. Then, the first colloid 115 is heated and baked. The baking temperature is 120 to 180 degrees Celsius, and the baking time is 15 to 30 minutes, allowing the first colloid 115 to fully cure.

[0076] Please combine Figure 2 Optionally, the first chip 120 includes a third surface 123 and a fourth surface 124 disposed opposite to each other. The third surface 123 has a first electrical connection portion 125, and a flange layer 122 is disposed on the fourth surface 124. The first chip 120 has a second conductive post 126 connected to the first electrical connection portion 125. One end of the second conductive post 126 away from the first electrical connection portion 125 extends toward the fourth surface 124 but does not exceed the fourth surface 124. In this embodiment, the first electrical connection portion 125 includes an active wiring layer 1251 and a fourth conductive post 1252 connected together. The side of the active wiring layer 1251 away from the fourth conductive post 1252 is electrically connected to the second conductive post 126.

[0077] Combination Figure 3 and Figure 4Optionally, the flange layer 122 has an annular adhesive barrier 1221 on the side facing the first surface 111. During the mounting of the first chip 120, the first adhesive 115 is squeezed, causing a portion of the first adhesive 115 to overflow onto the first surface 111 of the substrate 110. The flange layer 122 is fixed to the first surface 111 by the overflowed first adhesive 115. The adhesive barrier 1221 prevents the overflowed first adhesive 115 from spreading beyond the flange layer 122 and prevents the first adhesive 115 from overflowing onto the side of the flange layer 122 away from the first surface 111. Optionally, when the substrate 110 is made of a molding compound material, the first adhesive 115 is made of the same material as the substrate 110 to mitigate deformation and warping caused by differences in thermal expansion coefficients.

[0078] S4. Grind the second surface 112 until the end face of the first conductive post 113 near the second surface 112 is exposed.

[0079] Combination Figure 5 Optionally, a first carrier 130 is taken, and a debondable bonding adhesive layer 131 is coated on the surface of the first carrier 130. The bonding adhesive layer 131 can be separated from the first carrier 130 by irradiation with ultraviolet light or by laser debonding.

[0080] The first surface 111 of the substrate 110 is attached to the first carrier 130. The second surface 112 of the substrate 110 faces upward. The second surface 112 is then polished. In this embodiment, a two-stage polishing process is employed. The first stage is coarse polishing, which uses mechanical polishing to reduce the thickness of the substrate 110. The second stage is fine polishing, which uses chemical polishing. In the chemical polishing process, polishing fluids such as ammonia, hydrofluoric acid, or citric acid are used to polish the second surface 112 of the substrate 110 under the pressure of a polishing pad and centrifugal force, thereby exposing the end face of the first conductive post 113 near the second surface 112. It can be understood that the chemical polishing fluid can remove free metal ions from the surface of the substrate 110, thus cleaning the surface.

[0081] In this embodiment, the plane of the bottom of the first mounting groove 114 and the end face of the first conductive post 113 near the second surface 112 are on the same plane. Thus, after the first chip 120 is mounted, the end face of the fourth conductive post 1252 on the third surface 123 and the first conductive post 113 are on the same plane. Grinding the second surface 112 to expose the first conductive post 113 also exposes the fourth conductive post 1252 of the first chip 120, facilitating the subsequent electrical connection of the first wiring layer 142 to the first conductive post 113 and the fourth conductive post 1252, respectively.

[0082] S5. A first wiring layer 142 electrically connected to the first conductive post 113 is formed on one side of the second surface 112.

[0083] Optionally, a fourth dielectric layer 141 is formed on the second surface 112 using a spin coating or spray coating process. The material of the fourth dielectric layer 141 includes, but is not limited to, polyimide, benzocyclobutene, etc. A photomask with a patterned layer is placed on the fourth dielectric layer 141. A first patterned opening is formed on the fourth dielectric layer 141 using an exposure and development process, and metal is filled into the first patterned opening using electroplating, sputtering, or chemical plating to form a first wiring layer 142.

[0084] A fifth dielectric layer 143 is formed on the fourth dielectric layer 141 using a spin coating or spray coating process. The material of the fifth dielectric layer 143 includes, but is not limited to, polyimide, benzocyclobutene, etc. A photomask with a patterned layer is placed on the fifth dielectric layer 143. A first opening is formed on the fifth dielectric layer 143 using an exposure and development process, exposing the first wiring layer 142. Metal is filled into the first opening using electroplating, sputtering, or chemical plating to form a first solder ball 145. Specifically, metal is first electroplated into the first opening to form a first bump 144, which is electrically connected to the first wiring layer 142. Optionally, the first bump is made of copper pillar. Formic acid is used as a reducing agent to remove oxides from the surface of the first bump 144 through high temperature and chemical reaction, which helps to promote the bonding force between the first bump 144 and the solder. Then, at least one of titanium, titanium-tungsten, nickel, tin-silver, tin-silver-copper, and tin-bismuth is electroplated onto the surface of the first bump 144 to form the first solder ball 145.

[0085] Optional, please refer to Figure 6 A second chip 161 is mounted on one side of the second solder ball 174. The second chip 161 and the second solder ball 174 are electrically connected. In this embodiment, the second chip 161 is electrically connected to the substrate 110 and the first chip 120, respectively. A second adhesive 163 is formed by dispensing adhesive around the second chip 161. The second chip 161 is encapsulated to form a molded body 162. The first carrier 130 is removed, exposing the first surface 111 of the substrate 110 and the fourth surface 124 of the first chip 120. After removing the first carrier 130, the flange layer 122 of the first chip 120 can provide support, preventing the molded body 162 from shrinking under stress after the removal of the first carrier 130, thereby preventing the substrate 110 from warping. If the substrate 110 is made of a molding compound, the molding compound 162 and the molding compound of the substrate 110 can be prevented from shrinking under stress after the removal of the first carrier 130, thereby preventing warping deformation.

[0086] S6. A first window 127 is formed on the side of the first chip 120 away from the second surface 112 to expose the second conductive pillar 126. Optionally, the first window 127 is formed on the flange layer 122. The first window 127 can be formed by laser grooving or etching. A third conductive pillar 128 is formed by filling the first window 127 with metal. The formation of the third conductive pillar 128 includes, but is not limited to, electroplating, electroless plating, or sputtering.

[0087] Please combine Figure 7 S7. A second wiring layer 172 is formed on one side of the first surface 111; the second wiring layer 172 is electrically connected to the first conductive post 113 and the third conductive post 128 respectively.

[0088] Optionally, S7 includes S71 and S72.

[0089] S71. A first dielectric layer 171 is formed on one side of the first surface 111. The thickness of the first dielectric layer 171 is greater than the thickness of the flange layer 122. That is, the first dielectric layer 171 covers the flange layer 122. Optionally, the first dielectric layer 171 is formed on the first surface 111 using a spin coating or spray coating process. The material of the first dielectric layer 171 includes, but is not limited to, polyimide, benzocyclobutene, etc.

[0090] A second window 1711 is formed on the first dielectric layer 171; the second window 1711 exposes the first conductive pillar 113 and the third conductive pillar 128 respectively. Optionally, a photomask with a patterned layer is placed on the first dielectric layer 171, and the second window 1711 is formed on the first dielectric layer 171 by an exposure and development process.

[0091] S72, fill the second window 1711 with metal to form a second wiring layer 172. Optionally, the second wiring layer 172 is formed by filling the second window 1711 with metal using electroplating, sputtering, or chemical plating. The second wiring layer 172 is electrically connected to the first conductive post 113 and the third conductive post 128, respectively.

[0092] Please combine Figures 8 to 10 Alternatively, in some other embodiments, the second wiring layer 172 includes a first sub-wiring 1721 and a second sub-wiring 1722. S7 includes S73 to S76.

[0093] S73. A second dielectric layer 173 is formed on one side of the first surface 111, the thickness of the second dielectric layer 173 being equal to the thickness of the flange layer 122. A third window 1731 is formed on the second dielectric layer 173; the third window 1731 exposes the first conductive post 113. The specific process method is similar to the aforementioned step S71.

[0094] S74. Fill the third window 1731 with metal to form a first sub-wiring 1721. The first sub-wiring 1721 is electrically connected to the first conductive post 113. The specific process is similar to the aforementioned step S72.

[0095] S75, a third dielectric layer 1735 covering the flange layer 122 is formed on the first sub-wiring 1721. A fourth window is opened on the third dielectric layer 1735; the fourth window exposes the first sub-wiring 1721 and the third conductive post 128 respectively.

[0096] S76. Fill the fourth window with metal to form the second sub-wiring layer 1722. This completes the fabrication of the second wiring layer 172. The specific process methods for S75 and S76 can be found in S71 and S72 above, and will not be repeated here.

[0097] In this embodiment, the first chip 120 is electrically connected to the first wiring layer 142 and the second wiring layer 172. The second conductive post 126 and the third conductive post 128 of the first chip 120 are connected, and the third conductive post 128 is electrically connected to the second wiring layer 172. The first electrical connection portion 125 of the first chip 120 is electrically connected to the first wiring layer 142.

[0098] Optionally, a second solder ball 174 is formed by placing a ball on one side of the second wiring layer 172. First, a sixth dielectric layer 1736 is coated on the second wiring layer 172. A fifth window is opened on the sixth dielectric layer 1736 to expose the second wiring layer 172. Metal is filled in the fifth window to form a metal layer 175. Then, the second solder ball 174 is formed on the metal layer 175.

[0099] Optionally, after forming the second solder ball 174, it is cut and separated into individual products.

[0100] A second chip 161 is mounted on one side of the first wiring layer 142 or on one side of the second wiring layer 172, or the second chip 161 is mounted on both sides of the first wiring layer 142 and the second wiring layer 172. In this embodiment, the second chip 161 is mounted on one side of the first wiring layer 142. The second chip 161 is a flip chip, and the second chip 161 is electrically connected to the first solder ball 145 by soldering. A second adhesive 163 is formed around the second chip 161 to protect the solder structure. The second chip 161 is then encapsulated to form a plastic encapsulation body 162 covering the second chip 161.

[0101] It should be understood that if the second wiring layer 172 is fabricated after the molding compound 162 is formed, a carrier is not required. The formed molding compound 162 can act as a carrier, providing support for the substrate 110 and facilitating the fabrication of the second wiring layer 172. Of course, the second chip 161 can also be mounted after the first wiring layer 142 and the second wiring layer 172 are completed, respectively; no specific limitation is made here.

[0102] It should be understood that the flange layer 122 structure of the first chip 120 in this embodiment can be formed by edge cutting, or by other methods such as sputtering, electroplating, chemical plating, vapor deposition or bonding, and no specific limitation is made here.

[0103] Please combine Figure 11 This invention also provides a packaging structure 100, including a substrate 110, a first chip 120, a first wiring layer 142, and a second wiring layer 172. A first conductive post 113 is provided within the substrate 110. The substrate 110 has a first surface 111 and a second surface 112 disposed opposite to each other. One end of the first conductive post 113 is flush with the first surface 111, and the other end is flush with the second surface 112. The first chip 120 includes a main body 121 and a flange layer 122 connected to one end of the main body 121, the edge of the flange layer 122 extending beyond the edge of the main body 121. A third conductive post 128 is provided within the flange layer 122. The flange layer 122 helps to improve the bonding force between the dielectric layer and the substrate 110, avoids structural delamination, and also helps to mitigate warpage deformation during the thermal process.

[0104] The first chip 120 has a third surface 123 and a fourth surface 124 disposed opposite to each other. The main body 121 is provided with a first electrical connection portion 125 and a second conductive post 126 electrically connected; the end face of the first electrical connection portion 125 away from the second conductive post 126 is flush with the second surface 112. The end face of the second conductive post 126 away from the first electrical connection portion 125 is connected to a third conductive post 128, and the end face of the third conductive post 128 away from the first electrical connection portion 125 is flush with the first surface 111; the portion of the flange layer 122 extending beyond the main body 121 overlaps the first surface 111.

[0105] Optionally, the cross-section of the third conductive post 128 is larger than that of the second conductive post 126, which can increase the contact area between the third conductive post 128 and the second wiring layer 172 and improve the electrical connection performance.

[0106] The first wiring layer 142 is disposed on the second surface 112 and is electrically connected to the first conductive post 113 and the first electrical connection portion 125, respectively. The second wiring layer 172 is disposed on the first surface 111 and is electrically connected to the first conductive post 113 and the third conductive post 128, respectively.

[0107] Optionally, the package structure 100 further includes a second dielectric layer 173, a third dielectric layer 1735, a fourth dielectric layer 141, a fifth dielectric layer 143, and a sixth dielectric layer 1736. The second dielectric layer 173 covers the first surface 111 of the substrate 110 and has a thickness equal to the thickness of the flange layer 122. A first sub-wire 1721 of the second wiring layer 172 is disposed within the second dielectric layer 173. The third dielectric layer 1735 covers the second dielectric layer 173 and also covers the flange layer 122. The second sub-wire 1722 of the second wiring layer 172 is disposed within the third dielectric layer 1735. The sixth dielectric layer 1736 covers the third dielectric layer 1735. The sixth dielectric layer 1736 has a metal layer 175 that is respectively connected to the second sub-wire 1722 and the second solder ball 174, with the second solder ball 174 protruding from the sixth dielectric layer 1736.

[0108] A fourth dielectric layer 141 covers the second surface 112 of the substrate 110, and a first wiring layer 142 is disposed within the fourth dielectric layer 141. A fifth dielectric layer 143 covers the fourth dielectric layer 141, and a first bump 144 is provided within the fifth dielectric layer 143. A first solder ball 145 protrudes from the fifth dielectric layer 143. The first bump 144 is electrically connected to both the first wiring layer 142 and the first solder ball 145.

[0109] Please combine Figure 12 Optionally, the flange layer 122 is provided with metal pillars 129, which are staggered with the third conductive pillar 128. The metal pillars 129 help improve the heat dissipation performance of the structure and the support of the flange layer 122, thus mitigating the problem of warping deformation of the substrate 110 due to thermal stress.

[0110] It should be noted that during the fabrication of the first wiring layer 142, the first surface 111 of the substrate 110 needs to be mounted onto the first carrier 130, meaning the flange layer 122 is also mounted onto the first carrier 130. Subsequently, during the separation of the substrate 110 and the first carrier 130, the bonding adhesive layer 131 is irradiated with ultraviolet light at a high temperature of 100°C to 300°C. The metal pillars 129 also improve thermal conductivity, thereby increasing the debonding efficiency of the bonding adhesive layer 131 and preventing bonding adhesive layer 131 residue.

[0111] Optionally, the first electrical connection portion 125 includes an active wiring layer 1251 and a fourth conductive post 1252 connected together; the active wiring layer 1251 is electrically connected to the second conductive post 126, and the fourth conductive post 1252 is electrically connected to the first wiring layer 142. It should be noted that the number of active wiring layers 1251, the number of first wiring layers 142, and the number of second wiring layers 172 can be flexibly set according to actual needs. For example, they can be one, two, three, four, or more layers; no specific limitation is made here. In some embodiments, the active wiring layer 1251 may also be omitted.

[0112] Optionally, the package structure 100 further includes a second chip 161; the second chip 161 is disposed on one side of the first wiring layer 142 and / or one side of the second wiring layer 172. That is, the second chip 161 can be mounted on any side or both sides of the substrate 110, which is not specifically limited here. In this embodiment, the second chip 161 is mounted on one side of the first wiring layer 142, that is, the second chip 161 is disposed on the side close to the active wiring layer 1251 of the first chip 120, to realize the interconnection between the first chip 120 and the second chip 161. A second adhesive 163 is disposed on the bottom of the second chip 161 to protect the soldering structure of the second chip 161 and the first solder ball 145. The molding compound 162 covers the second chip 161. The height of the molding compound 162 can be higher than the surface of the second chip 161 away from the substrate 110, or it can be flush with the surface of the second chip 161 away from the substrate 110, which is not specifically limited here.

[0113] Please combine Figure 13 Optionally, a second pad 190 is provided between the third conductive post 128 and the second wiring layer 172. The second pad 190 can increase the electrical contact area between the third conductive post 128 and the second wiring layer 172, thereby improving electrical connection performance. The second pad 190 can be formed during the fabrication of the first chip 120, or it can be formed after the first chip 120 is mounted and before the second wiring layer 172 is fabricated; no specific limitation is made here.

[0114] In some embodiments, a second pad 190 may also be provided at one or both ends of the first conductive post 113, which can increase the electrical contact area between the first conductive post 113 and the first wiring layer 142 or the second wiring layer 172 and improve the electrical connection performance.

[0115] Optionally, the first chip 120 can be a device such as an inductor, voltage regulator, resistor, capacitor, transistor, or diode. The first chip 120 has an active wiring layer 1251 and a second conductive pillar 126. The flange layer 122 of the first chip 120 is made of chip material. The flange layer 122 of the first chip 120 provides support, thereby preventing warping of the substrate 110 structure after the first carrier 130 is removed.

[0116] The bridging packaging method and packaging structure 100 provided in this embodiment of the invention have the following beneficial effects:

[0117] By embedding the first chip 120 in the substrate 110, a compact structure is achieved, which is beneficial for high-density packaging. The first chip 120 has a flange layer 122, which overlaps the first surface 111 of the substrate 110. In the thermal process, the flange layer 122 provides support and prevents warping, effectively improving warping deformation during the packaging process, enhancing packaging quality, and thus improving product performance. The flange layer 122 contains a third conductive post 128 connected to the second conductive post 126, which effectively improves electrical connectivity and further mitigates warping caused by thermal stress. The flange layer 122 also contains metal posts 129 offset from the second conductive post 126, which improves debonding efficiency and heat dissipation, prevents adhesive residue 131, and further mitigates warping of the substrate 110 due to thermal stress.

[0118] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; any modifications, equivalent substitutions, improvements, etc., should be included within the protection scope of the present invention.

Claims

1. A bridging packaging method, characterized in that, include: A substrate is provided; wherein a first conductive pillar is provided within the substrate; The substrate has a first surface and a second surface disposed opposite to each other; one end of the first conductive post is flush with the first surface, and the other end is embedded in the substrate; A first mounting groove is formed on one side of the first surface of the substrate; A first chip is mounted in the first mounting groove; wherein the first chip includes a main body and a flange layer connected to one end of the main body, the edge of the flange layer extending beyond the edge of the main body; the main body is located in the first mounting groove, and the portion of the flange layer extending beyond the main body overlaps the first surface; a baffle portion is provided on the side of the flange layer facing the first surface; a second conductive post is provided inside the first chip; the step of mounting the first chip in the first mounting groove includes: filling the first mounting groove with a semi-cured first adhesive; mounting the first chip in the first mounting groove; wherein the first chip presses against the first adhesive, causing a portion of the first adhesive to overflow onto the first surface; the flange layer is fixed to the first surface by the overflowed first adhesive; the baffle portion is used to prevent the overflowed first adhesive from spreading to areas other than the flange layer or overflowing to the side of the flange layer away from the first surface; the space between the main body and the groove wall of the first mounting groove is filled with the first adhesive. Grind the second surface until the end face of the first conductive post near the second surface is exposed; A first wiring layer electrically connected to the first conductive pillar is formed on one side of the second surface; A first window is opened on the side of the first chip away from the second surface to expose the second conductive post; A third conductive pillar is formed by filling the first window with metal. A second wiring layer is formed on one side of the first surface; the second wiring layer is electrically connected to the first conductive post and the third conductive post, respectively. The first chip is electrically connected to both the first wiring layer and the second wiring layer.

2. The bridging packaging method according to claim 1, characterized in that, The step of forming a second wiring layer on one side of the first surface includes: A first dielectric layer is formed on one side of the first surface; the thickness of the first dielectric layer is greater than the thickness of the flange layer. A second window is formed on the first dielectric layer; the second window exposes the first conductive pillar and the third conductive pillar respectively; A second wiring layer is formed by filling the second window with metal.

3. The bridging packaging method according to claim 1, characterized in that, The second wiring layer includes a first sub-wiring and a second sub-wiring; the step of forming the second wiring layer on one side of the first surface includes: A second dielectric layer is formed on one side of the first surface; the thickness of the second dielectric layer is equal to the thickness of the flange layer. A third window is formed on the second dielectric layer; the third window exposes the first conductive pillar. The third window is filled with metal to form the first sub-wiring; A third dielectric layer covering the flange layer is formed on the first sub-wire; A fourth window is formed on the third dielectric layer; the fourth window exposes the first sub-wiring and the third conductive post respectively; The fourth window is filled with metal to form a second sub-wiring.

4. The bridging packaging method according to claim 1, characterized in that, After the step of mounting the first chip in the first mounting slot, the following steps are included: The first mounting slot is evacuated to remove the gas in the first mounting slot; The first colloid is completely cured.

5. A packaging structure, characterized in that, It is manufactured using the bridging packaging method as described in any one of claims 1 to 4.

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