A method for manufacturing a semiconductor structure

Abstract

This invention discloses a method for fabricating a semiconductor structure, belonging to the field of semiconductor technology. The method includes: providing a substrate, and sequentially forming a pad oxide layer and a pad nitride layer on the substrate; etching portions of the pad oxide layer, the pad nitride layer, and the substrate to form a shallow trench, forming a recessed region between the pad oxide layer and the pad nitride layer; removing the pad nitride layer; performing a first deposition process to form a first isolation medium on the recessed region; performing a second deposition process to form a second isolation medium on the shallow trench, the first isolation medium, and the pad oxide layer; planarizing the second isolation medium; and removing the pad oxide layer and the second isolation medium on the pad oxide layer. The semiconductor structure fabrication method provided by this invention can avoid the occurrence of recesses at the corner edges of the shallow trench isolation structure, thereby improving the performance of the semiconductor structure.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for fabricating a semiconductor structure. Background Technology

[0002] In semiconductor integrated circuits, shallow trench isolation (STI) structures are crucial, placed between semiconductor devices to prevent current leakage between adjacent devices and reduce the area of ​​the isolation region. The formation of STI typically involves in-situ steam generation (ISSG) to form the liner oxide layer, followed by the deposition of the isolation dielectric layer. However, during the etching process to form the shallow trench, a recessed region forms between the pad oxide layer and the pad nitride layer. This recessed region cannot be effectively filled by the isolation dielectric layer, leading to partial filling of the gate oxide layer during subsequent deposition. When voltage is applied, this charge concentration causes gate oxide integrity (GOI) failure, severely impacting product lifespan. Summary of the Invention

[0003] The purpose of this invention is to provide a method for fabricating a semiconductor structure. By using the method provided by this invention, the corner edges of the shallow trench isolation structure are prevented from being recessed, leakage current in the semiconductor structure is avoided, the semiconductor structure has a good isolation effect, and the performance of the semiconductor structure is improved.

[0004] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor structure, comprising at least the following steps:

[0005] A substrate is provided on which a pad oxide layer and a pad nitride layer are sequentially formed;

[0006] The pad oxide layer, the pad nitride layer, and the substrate are etched to form shallow trenches, and a recessed area is formed between the pad oxide layer and the pad nitride layer;

[0007] Remove the nitrided layer of the pad;

[0008] A first deposition process is performed to form a first isolation medium on the recessed area;

[0009] A second deposition process is performed to form a second isolation medium on the shallow trench, the first isolation medium, and the pad oxide layer;

[0010] Flatten the second isolation medium;

[0011] Remove the pad oxide layer and the second isolation medium on the pad oxide layer.

[0012] In one embodiment of the present invention, the first deposition process includes:

[0013] The substrate with the pad nitride layer removed is placed in a deposition apparatus, and a reaction gas is introduced at a preset pressure and a preset temperature.

[0014] The first bias voltage and first bias power of the deposition equipment are controlled, and the deposition direction is at a preset angle to the substrate normal to form the first isolation medium on the recessed area.

[0015] In one embodiment of the present invention, the preset pressure is 0.001 Torr to 0.009 Torr, and the preset temperature is 100℃ to 150℃.

[0016] In one embodiment of the present invention, the reaction gas includes a silicon source, an oxygen source, and a sputtering gas. The silicon source includes at least one of silane, disilane, dichlorosilane, or tetraethyl orthosilicate. The oxygen source includes at least one of oxygen or ozone. The sputtering gas includes at least one of argon, helium, or hydrogen. The gas flow rates of the silicon source and the oxygen source are 40 sccm to 180 sccm, and the gas flow rate ratio of the silicon source to the oxygen source is 1:1.5 to 1:2.

[0017] In one embodiment of the present invention, the first bias voltage is 800V~1000V, and the first bias power is 1000W~2500W.

[0018] In one embodiment of the present invention, the preset angle is 50°~70°.

[0019] In one embodiment of the present invention, the second deposition process includes: after completing the first deposition process, controlling the second bias voltage and the second bias power of the deposition equipment, with the deposition direction perpendicular to the substrate, to form the second isolation medium on the shallow trench, the first isolation medium and the pad oxide layer.

[0020] In one embodiment of the present invention, the second bias voltage is 200V~300V, and the second bias power is 4000W~5000W.

[0021] In one embodiment of the present invention, after the pad nitride layer is removed, a liner oxide layer is formed on the substrate exposed in the shallow trench and the recessed area.

[0022] In one embodiment of the present invention, the surface of the first isolation medium is higher than the surface of the pad oxide layer; and / or, after a second deposition process, the surface of the second isolation medium in the shallow trench is higher than the surface of the pad oxide layer.

[0023] In summary, this invention provides a method for fabricating a semiconductor structure. By improving this method, the unexpected technical effect is the ability to completely fill the recessed areas formed during shallow trench etching, thereby preventing recesses at the corners of the shallow trench isolation structure and avoiding leakage current. This results in a semiconductor structure with excellent isolation performance, improving its overall performance. Furthermore, the deposition process for forming the isolation medium is completed within the same deposition equipment; only the deposition process needs to be changed, simplifying the fabrication process, improving efficiency, and enhancing the stability and quality of the isolation medium deposition process.

[0024] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0025] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of a pad oxide layer, a pad nitride layer, and a patterned photoresist layer formed on a substrate in one embodiment.

[0027] Figure 2 This is a schematic diagram of the shallow trenches and depressions formed in one embodiment.

[0028] Figure 3 This is a schematic diagram of the pad nitriding layer after removal in one embodiment.

[0029] Figure 4 This is a schematic diagram of the formation of the oxide liner in one embodiment.

[0030] Figure 5 This is a schematic diagram of the first isolation medium formed by the first deposition process in one embodiment.

[0031] Figure 6 This is a schematic diagram of the second isolation medium formed by a second deposition process in one embodiment.

[0032] Figure 7 This is a schematic diagram of planarizing the second isolation medium and forming a photoresist layer in one embodiment.

[0033] Figure 8 This is a schematic diagram of a semiconductor structure in one embodiment.

[0034] Label Explanation:

[0035] 100, Substrate; 110, Pad oxide layer; 120, Pad nitride layer; 130, Patterned photoresist layer; 131, First opening; 140, Shallow trench; 141, Recessed area; 150, Substrate oxide layer; 160, First isolation medium; 170, Second isolation medium; 180, Patterned photoresist layer; 190, Shallow trench isolation structure. Detailed Implementation

[0036] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0037] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of the present invention. Therefore, the drawings only show the components related to the present invention and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] In this invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used only for descriptive and distinguishing purposes and should not be construed as indicating or implying relative importance.

[0039] Please see Figure 1 As shown, in one embodiment of the present invention, the substrate 100 provided by the present invention can be any applicable semiconductor material, such as sapphire, silicon wafer, silicon carbide (SiC), gallium nitride (GaN), aluminum nitride (AlN), indium nitride (InN), or silicon germanium (GeSi) substrates, and also includes stacked structures composed of these semiconductor materials, or silicon-on-insulator, silicon-on-insulator stacked, silicon-on-insulator stacked, silicon-on-insulator, and germanium-on-insulator, etc., which can be selected according to the manufacturing requirements of the semiconductor device. In this embodiment, the substrate 100 is, for example, a silicon wafer semiconductor substrate, and the substrate 100 can be an undoped substrate or a doped substrate, such as an N-type substrate or a P-type substrate, and the thickness of the substrate 100 is not specifically limited, but is selected according to the manufacturing requirements.

[0040] Please see Figure 1 As shown, in one embodiment of the present invention, a pad oxide layer 110 is formed on a substrate 100. The pad oxide layer 110 is, for example, a dense silicon oxide material. The pad oxide layer 110 is prepared by methods such as thermal oxidation or in-situ water vapor growth to obtain dense silicon oxide. In this embodiment, the pad oxide layer 110 is prepared by, for example, in-situ water vapor growth. Specifically, the substrate 100 is placed in a furnace tube at a temperature of, for example, 900°C to 1150°C, and oxygen mixed with a small amount of hydrogen is introduced. The silicon on the surface of the substrate 100 reacts with the oxygen at high temperature to generate a dense pad oxide layer 110, and the generated pad oxide layer 110 has good quality. The thickness of the pad oxide layer 110 is, for example, 10 nm to 30 nm, specifically, 10 nm, 20 nm, or 30 nm.

[0041] Please see Figure 1 As shown, in one embodiment of the present invention, after forming the pad oxide layer 110, a pad nitride layer 120 is formed on the pad oxide layer 110. The pad nitride layer 120 is, for example, silicon nitride or a stack of silicon nitride and silicon oxide. The pad oxide layer 110 serves as a buffer layer to improve the stress between the substrate 100 and the pad nitride layer 120. In this embodiment, the pad nitride layer 120 is, for example, silicon nitride, and can be formed by methods such as physical vapor deposition (PVD), plasma enhanced chemical vapor deposition (PECVD), or low-pressure chemical vapor deposition (LPCVD). In this embodiment, specifically, for example, a substrate 100 with a pad oxide layer 110 is placed in a furnace tube filled with dichlorosilane and ammonia gas, and reacted at a pressure of, for example, 2 Torr to 10 Torr and a temperature of, for example, 700°C to 900°C, to deposit a pad nitride layer 120. The thickness of the pad nitride layer 120 can be adjusted by controlling the heating time. In this embodiment, the thickness of the pad nitride layer 120 is, for example, 50 nm to 120 nm. By setting the pad nitride layer 120, the substrate 100 can be protected from planarization processes such as chemical mechanical polishing (CMP) involved in the fabrication of the shallow trench isolation structure. Furthermore, the pad nitride layer 120 can act as a mask during the shallow trench formation process, protecting other parts of the substrate 100 from damage during etching. Since the pad nitride layer 120 has high stress, the pad oxide layer 110 can be used to buffer the stress in the pad nitride layer 120 and avoid the stress causing defects to the substrate 100. At the same time, the pad oxide layer 110 also serves as a stop layer when etching away the pad nitride layer 120.

[0042] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, after forming the pad nitride layer 120, a photoresist layer is formed on the pad nitride layer 120. After exposure, development, and other processes, a patterned photoresist layer 130 is formed. The patterned photoresist layer 130 includes a plurality of first openings 131, which expose a portion of the pad nitride layer 120 and are used to define the location of the shallow trenches. Using the patterned photoresist layer 130 as a mask, shallow trenches 140 are formed, for example, by dry etching in the direction of the substrate 100. The etching gas includes, for example, one or a mixture of several of chlorine (Cl2), trifluoromethane (CHF3), difluoromethane (CH2F2), nitrogen trifluoride (NF3), sulfur hexafluoride (SF6), or hydrogen bromide (HBr), or a mixture of these and oxygen (O2). In this embodiment, after forming the shallow trenches 140, the patterned photoresist layer 130 is removed by wet cleaning or ashing treatment.

[0043] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, during the etching process to form the shallow trench 140, the etching gas also has an etching effect on the pad oxide layer 110 and the pad nitride layer 120, and the etching rate of the pad oxide layer 110 is greater than that of the pad nitride layer 120, forming a recessed region 141 between the pad oxide layer 110 and the pad nitride layer 120. If the isolation dielectric layer is deposited directly, the isolation dielectric layer cannot be deposited into the recessed region 141. After the pad oxide layer 110 and the pad nitride layer 120 are subsequently removed, after the gate is formed, the gate oxide layer and gate material will partially fill the recessed region. When the voltage is applied, the charge concentrates in the recessed region, causing the device to burn out, affecting the device yield and lifespan. Therefore, it is necessary to fill the recessed region 141 with the isolation dielectric.

[0044] Please see Figures 2 to 3 As shown, in one embodiment of the present invention, after forming the shallow trench 140, the pad nitride layer 120 is removed. The pad nitride layer 120 is removed, for example, by dry etching, wet etching, or a combination of dry and wet etching. In this embodiment, the pad nitride layer 120 is removed, for example, by wet etching, and the wet etching solution is, for example, phosphoric acid, with a mass fraction of 80% to 95%, and the etching temperature is, for example, 155°C to 165°C. The etching rate of the pad nitride layer 120 is controlled by controlling the concentration of phosphoric acid, the etching temperature, and the etching time. After removing the pad nitride layer 120, the distance d between the edge of the recessed region 141 and the edge of the adjacent shallow trench 140 is, for example, 70 nm to 100 nm.

[0045] Please see Figures 3 to 4As shown, in one embodiment of the present invention, after removing the pad nitride layer, a liner oxide layer 150 is formed on the substrate 100 exposed in the shallow trench 140 and the recessed region 141. The liner oxide layer 150 is formed, for example, by a furnace tube method, thermal oxidation treatment, or in-situ water vapor growth method, and the thickness of the liner oxide layer 150 is, for example, 2 nm to 3 nm. By forming the liner oxide layer 150, substrate damage caused during the etching process is replicated, interface characteristics are optimized, and a stable isolation base is provided for subsequent processes. At the same time, the bottom corners of the shallow trench 140 are rounded to reduce tip leakage.

[0046] Please see Figures 4 to 5As shown, in one embodiment of the present invention, after forming the oxide liner 150, a first isolation medium 160 is formed on the recessed region 141 by a first deposition process. In this embodiment, the first deposition process employs a method such as high-density plasma chemical vapor deposition (HDPCVD) to form the first isolation medium 160. During the deposition process, the substrate 100 is placed in the deposition equipment, and the preset pressure of the deposition equipment is controlled, for example, to be 0.001 Torr to 0.009 Torr, and the preset temperature is, for example, 100°C to 150°C. A reaction gas is introduced, which includes, for example, at least a silicon source, an oxygen source, and a sputtering gas. The silicon source includes, for example, at least one of silane (SiH4), disilane (Si2H6), dichlorosilane (SiCl2H2), or tetraethyl orthosilicate (Si(OC2H5)4). The oxygen source includes, for example, at least one of oxygen (O2) or ozone (O3). The sputtering gas includes, for example, at least one of argon (Ar), helium (He), or hydrogen (H2) to simultaneously perform deposition and sputtering reactions, thereby improving the quality of the formed oxide layer. The gas flow rates of the silicon and oxygen sources are, for example, 40 sccm to 180 sccm, and the gas flow rate ratio of the silicon and oxygen sources is, for example, 1:1.5 to 1:2. The sputtering gas is, for example, hydrogen, and the sputtering gas flow rate is, for example, 200 sccm to 300 sccm. The first DC voltage, first bias voltage, first RF power, and first bias power of the deposition equipment are controlled. The DC voltage is, for example, 20V to 30V, the bias voltage is, for example, 800V to 1000V, and the total power of the equipment is, for example, 4000W to 5000W. The RF power is, for example, 1000W to 2500W to form a high-density plasma, and the bias power is, for example, 1000W to 2500W to generate a negative bias voltage on the surface of the substrate 100. The plasma is controlled to move to the substrate 100 at a preset angle, that is, the deposition direction is at a preset angle to the substrate normal. The preset angle is, for example, the angle between the deposition direction and the substrate normal. In this embodiment, the preset angle is, for example, 50°~70°. By controlling the deposition conditions of the first deposition process, the deposition occurs on the recessed region 141, and the first isolation medium 160 formed is located on the recessed region 141. The thickness of the first isolation medium 160 on the recessed region 141 is, for example, 5Å~200Å. For example, the first isolation medium 160 protrudes from the surface of the pad oxide layer 110, and the thickness of the silicon oxide layer formed at other locations is extremely small and can be ignored.

[0047] Please see Figures 5 to 6As shown, in one embodiment of the present invention, after the formation of the first isolation medium 160, a second isolation medium 170 is formed on the shallow trench 140, the first isolation medium 160, and the pad oxide layer 110 through a second deposition process. In this embodiment, the second deposition process is formed by, for example, high-density plasma chemical vapor deposition. During the deposition process, it can be completed in the same deposition equipment as the first deposition process. During the second deposition, the preset pressure of the deposition equipment is controlled to be, for example, 0.001 Torr to 0.009 Torr, and the preset temperature is, for example, 100°C to 150°C. A reaction gas is introduced, which includes, for example, at least a silicon source, an oxygen source, and a sputtering gas. The silicon source includes, for example, at least one of silane, disilane, dichlorosilane, or the like. The oxygen source includes, for example, at least one of oxygen or ozone. The sputtering gas includes, for example, at least one of argon, helium, or hydrogen, to simultaneously carry out the deposition and sputtering reactions, thereby improving the quality of the formed oxide layer. The gas flow rates of the silicon source and oxygen source are, for example, 110 sccm to 180 sccm, the gas flow rate ratio of the silicon source and oxygen source is, for example, 1:1.5 to 1:4, the sputtering gas is, for example, hydrogen, and the sputtering gas flow rate is, for example, 300 sccm to 500 sccm. The second DC voltage, second bias voltage, second RF power, and second bias power of the deposition equipment are controlled. The second DC voltage is, for example, 20V~30V, the second bias voltage is, for example, 200V-300V, and the total power of the equipment is, for example, 15000W~18000W. The second RF power is, for example, 1000W~2500W to form a high-density plasma, and the second bias power is, for example, 4000W~5000W. That is, the bias voltage and bias power of the second deposition process are adjusted to adjust the movement mode of the plasma so that the plasma is deposited in a direction perpendicular to the substrate to form the second isolation medium 170. Deposition stops when the second isolation medium 170 in the shallow trench 140 is higher than the pad oxide layer 110.

[0048] Please see Figures 2 to 6As shown, in one embodiment of the present invention, after forming the shallow trench 140, the pad nitride layer 120 is first removed to expose the recessed region 141. Then, through two deposition processes, the recessed region 141 is filled first, and then the shallow trench 140 is filled, to ensure that the recessed region 141 is completely filled. This avoids the gate oxide integrity failure caused by the incomplete filling of the recessed region 141 due to direct deposition of the isolation medium. In other words, this application can completely fill the recessed region 141, thereby avoiding the occurrence of recesses at the corner edges of the shallow trench isolation structure, preventing leakage current in the semiconductor structure, and providing good isolation effect for the semiconductor structure, thus improving the performance of the semiconductor structure. Moreover, the two deposition processes are completed in the same deposition equipment, requiring only a change in the deposition process, which simplifies the fabrication process, improves fabrication efficiency, and enhances the stability of the isolation medium deposition process, thereby improving the deposition quality.

[0049] Please see Figures 6 to 7 As shown, in one embodiment of the present invention, after depositing the second isolation medium 170, a portion of the second isolation medium 170 is removed, for example, by a planarization process such as chemical mechanical polishing, to make the surface of the second isolation medium 170 flush. A photoresist layer is then formed on the second isolation medium 170, and after exposure, development, and other processes, a patterned photoresist layer 180 is formed. The patterned photoresist layer 180 is used to define the position of the shallow trench isolation structure.

[0050] Please see Figures 7 to 8 As shown, in one embodiment of the present invention, after the patterned photoresist layer 180 is formed, the patterned photoresist layer 180 is used as a mask, and etching is performed in the direction of the substrate 100 using, for example, dry etching, wet etching, or a combination of dry etching and wet etching processes, to remove the pad oxide layer 110, part of the first isolation medium 160, and the second isolation medium 170 on the pad oxide layer 110 and part of the first isolation medium 160, thereby forming a shallow trench isolation structure 190. When dry etching is used, the etching gas includes one or more of trifluoromethane, difluoromethane, or sulfur hexafluoride, or a mixture thereof with oxygen. When wet etching is used, the etching solution is, for example, dilute hydrofluoric acid or buffered oxide etch (BOE). Dilute hydrofluoric acid is, for example, a 49wt% hydrofluoric acid solution mixed with deionized water at a volume ratio of 1:20-50, used to etch the isolation dielectric and the pad oxide layer 110. Simultaneously, the etching rate is controlled to prevent over-etching of the isolation dielectric due to excessively fast etching. In this embodiment, wet etching is used, for example. Since the material of the isolation dielectric and the pad oxide layer 110 are the same, the pad oxide layer 110 and the isolation dielectric are etched simultaneously. Furthermore, because the shallow trench corners are completely filled, no edge depressions are generated, reducing leakage current and meeting the fabrication requirements of different semiconductor devices.

[0051] Please see Figures 7 to 8 As shown, in another embodiment of the present invention, for example, after planarizing the isolation medium, ions are implanted into the substrate 100 using the isolation medium and the pad oxide layer 110 as an ion implantation buffer layer to form a well region or other structure, and then the excess pad oxide layer 110 and part of the isolation medium are removed. That is, in this application, the pad oxide layer 110 and the isolation medium can be selectively removed in different steps according to the fabrication requirements of the semiconductor device. When removing the pad oxide layer and part of the isolation medium, the isolation medium completely fills the corner edges of the shallow trench. During etching, the corner edges of the shallow trench isolation structure 190 can be prevented from being recessed. When forming the gate on the substrate, the polysilicon constituting the gate can be prevented from filling the recess, and leakage current in the semiconductor structure can be avoided. The semiconductor structure has a good isolation effect. Through the fabrication method of this application, the morphology of the shallow trench isolation structure 190 can be ensured, the performance of the semiconductor structure can be improved, thereby improving the performance of the semiconductor device including the semiconductor structure.

[0052] In summary, this invention provides a method for fabricating a semiconductor structure. By improving the fabrication method, this application achieves the unexpected technical effect of completely filling the recessed areas formed during shallow trench etching, thereby preventing recesses at the corner edges of the shallow trench isolation structure and avoiding leakage current. The semiconductor structure exhibits excellent isolation performance, thus improving its overall performance. Furthermore, both deposition processes are completed within the same deposition equipment; only the deposition process needs to be changed, simplifying the fabrication process, improving efficiency, and enhancing the stability and quality of the isolation medium deposition process.

[0053] Throughout this specification, the terms "one embodiment," "an embodiment," or "a specific embodiment" refer to a particular feature, structure, or characteristic described in connection with an embodiment that is included in at least one embodiment of the invention, but not necessarily in all embodiments. Therefore, the various representations of the phrases "in one embodiment," "in an embodiment," or "in a specific embodiment" in different places throughout the specification do not necessarily refer to the same embodiment. Furthermore, a particular feature, structure, or characteristic of any specific embodiment of the invention may be combined with one or more other embodiments in any suitable manner. It should be understood that other variations and modifications of the embodiments of the invention described and illustrated herein may be based on the teachings herein and will be considered part of the spirit and scope of the invention.

[0054] It should also be understood that the above-disclosed embodiments of the present invention are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. These embodiments have been selected and specifically described in this specification to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, At least the following steps are included: A substrate is provided on which a pad oxide layer and a pad nitride layer are sequentially formed; The pad oxide layer, the pad nitride layer, and the substrate are etched to form shallow trenches. When the shallow trenches are formed, the etching rate of the pad oxide layer is greater than the etching rate of the pad nitride layer, and a recessed area is formed between the pad oxide layer and the pad nitride layer. Remove the nitrided pad layer to expose the recessed area; A first deposition process is performed to form a first isolation medium on the recessed area; A second deposition process is performed to form a second isolation medium on the shallow trench, the first isolation medium, and the pad oxide layer; Flatten the second isolation medium; Remove the pad oxide layer and the second isolation medium on the pad oxide layer; The first deposition process includes: The substrate with the pad nitride layer removed is placed in a deposition apparatus, and a reaction gas is introduced at a preset pressure and a preset temperature. The first bias voltage and first bias power of the deposition equipment are controlled, the deposition direction is at a preset angle to the substrate normal, and the first isolation medium is formed on the recessed area, the surface of the first isolation medium is higher than the surface of the pad oxide layer; the first bias voltage is 800V~1000V, the first bias power is 1000W~2500W; the preset angle is 50°~70°. The second deposition process includes: After completing the first deposition process, the second bias voltage and the second bias power of the deposition equipment are controlled, and the deposition direction is perpendicular to the substrate to form the second isolation medium on the shallow trench, the first isolation medium and the pad oxide layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The preset pressure is 0.001 Torr to 0.009 Torr, and the preset temperature is 100℃ to 150℃.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The reaction gas includes a silicon source, an oxygen source, and a sputtering gas. The silicon source includes at least one of silane, disilane, dichlorosilane, or tetraethyl orthosilicate. The oxygen source includes at least one of oxygen or ozone. The sputtering gas includes at least one of argon, helium, or hydrogen. The gas flow rates of the silicon source and the oxygen source are 40 sccm to 180 sccm, and the gas flow rate ratio of the silicon source to the oxygen source is 1:1.5 to 1:

2.

4. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The second bias voltage is 200V~300V, and the second bias power is 4000W~5000W.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After removing the pad nitride layer, a liner oxide layer is formed on the substrate exposed in the shallow trenches and the recessed areas.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, After the second deposition process, the surface of the second isolation medium in the shallow trench is higher than the surface of the pad oxide layer.

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