Formation method of semiconductor structure
By using a single photomask to simultaneously form interconnect via structures and the first interconnect layer during the semiconductor structure formation process, the problem of increased process steps and costs in existing technologies is solved, achieving cost reduction.
Patent Information
- Application Number
- CN202410551891.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-05-06
- Publication Date
- 2025-11-07
AI Technical Summary
Existing technologies require two photomasks to be etched separately to form the interconnect via structure and the first interconnect layer when forming 2.5D Interposer devices, which increases the number of process steps and costs.
By using a single photomask to transfer the interconnect via structure and the pattern of the first interconnect layer to the first dielectric layer in the same step, and using the first dielectric layer as an etching mask, the number of process steps is reduced and photomasks are saved.
This reduces the number of process steps for interconnect via structures and the first interconnect layer, thereby lowering process costs.
Smart Images
Figure CN120914162A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] Embodiments of the present application relate to the field of semiconductor manufacturing, and particularly to a method for forming a semiconductor structure. BACKGROUND
[0002] With the advancement of technology, 3D integrated circuits (or 2.5D integrated circuits, etc.) based on Interposer become the most promising solution, which can expand the in-die stacking technology of various complex chips, and let the industry step on a new way to provide large-scale complex chip integration faster than Moore's Law, while reducing power consumption and cost.
[0003] The Interposer is a connection structure made of silicon wafer similar to the circuit board, and similar to the PCB, the Interposer usually has a Through Silicon Via (TSV) interconnection structure, and different chips can be transmitted to the circuit board connected thereto through the TSV interconnection structure, so the Interposer is equivalent to a bridge connecting multiple chips and the same circuit board. Among them, the Interposer with TSV is called TSV Interposer, and the packaging structure using TSV Interposer is called 2.5D Interposer. SUMMARY
[0004] The problem solved by embodiments of the present application is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.
[0005] To solve the above problems, embodiments of the present application provide a method for forming a semiconductor structure, comprising: providing a substrate, the substrate comprising an interconnection region and a capacitor region adjacent thereto; forming a capacitor in the substrate of the capacitor region; forming a first dielectric layer covering the capacitor on the substrate; forming an interconnection via structure in the first dielectric layer and the substrate of the interconnection region, and forming a first interconnection layer in the first dielectric layer of the capacitor region, the first interconnection layer being electrically connected to the capacitor; forming a second dielectric layer covering the first dielectric layer and the interconnection via structure, and the first interconnection layer on the top of the substrate; forming one or more metal lines in the second dielectric layer, the metal lines being electrically connected to the interconnection via structure, and the metal lines being electrically connected to the first interconnection layer.
[0006] Optionally, the step of forming a capacitor in the capacitor region comprises: forming a capacitor trench in the substrate of the capacitor region; forming a plurality of plate layers and a third dielectric layer between adjacent plate layers in a spaced stack on the bottom and sidewalls of the capacitor trench and the top of the substrate on the sides of the capacitor trench, the plurality of plate layers and the third dielectric layer between adjacent plate layers being configured to form a capacitor; and the first interconnect layer being electrically connected to each of the plate layers during the step of forming the first interconnect layer.
[0007] Optionally, after forming the capacitor trench and before forming the capacitor, the method further comprises: forming a second insulating layer on the bottom and sidewalls of the capacitor trench.
[0008] Optionally, the second insulating layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride.
[0009] Optionally, the plate layers comprise one or more of polysilicon, copper, tungsten, cobalt, and titanium nitride; and the third dielectric layer comprises one or more of silicon oxide, silicon nitride, hafnium oxide, zinc oxide, zirconium oxide, and aluminum oxide.
[0010] Optionally, after forming the capacitor and before forming the first dielectric layer, the method further comprises: forming a first insulating layer in the capacitor region covering the capacitor; and forming a passivation layer in the capacitor region and the interconnect region covering the substrate and the first insulating layer.
[0011] Optionally, the passivation layer comprises one or more of silicon nitride, silicon oxide, silicon oxynitride, and polyimide.
[0012] Optionally, the step of forming the first dielectric layer covering the capacitor comprises: forming a first sub-dielectric layer covering the capacitor on the substrate; forming an etching stop layer covering the first sub-dielectric layer; and forming a second sub-dielectric layer covering the etching stop layer, the first sub-dielectric layer, the etching stop layer and the second sub-dielectric layer constituting the first dielectric layer; and the step of forming the interconnection via structure and the first interconnection layer comprises: forming a first recess through the second sub-dielectric layer, the etching stop layer, the first sub-dielectric layer, the passivation layer and a portion of the substrate in the interconnection region; after forming the first recess, forming a second recess through the second sub-dielectric layer, the etching stop layer, the first sub-dielectric layer and the passivation layer above the capacitor in the capacitor region; forming a layer of conductive material in the first recess, the second recess and on top of the second sub-dielectric layer; and planarizing the layer of conductive material above the top of the second sub-dielectric layer as a stop position, the remaining layer of conductive material in the first recess being the interconnection via structure and the remaining layer of conductive material in the second recess being the first interconnection layer.
[0013] Optionally, the process of forming the first recess comprises a dry etching process, and the process of forming the second recess comprises a dry etching process.
[0014] Optionally, the steps of forming the first recess and the second recess comprise: forming a mask layer having mask openings on top of the first dielectric layer, the mask openings in the interconnection region having a greater depth than the mask openings in the capacitor region, and the mask openings in the interconnection region exposing the top surface of the second sub-dielectric layer; patterning the second sub-dielectric layer along the mask openings using the mask layer as a mask, forming a first opening through the second sub-dielectric layer in the interconnection region and a second opening through a portion of the second sub-dielectric layer in the capacitor region; removing the mask layer; after removing the mask layer, performing a first etching process on the etching stop layer, the first sub-dielectric layer, the passivation layer and a portion of the substrate in the interconnection region along the first opening using the second sub-dielectric layer as a mask, forming the first recess; after forming the first recess, removing the remaining second sub-dielectric layer below the second opening along the second opening using the second sub-dielectric layer as a mask; and after removing the remaining second sub-dielectric layer below the second opening, performing a second etching process on the etching stop layer, the first sub-dielectric layer and the passivation layer above the capacitor along the second opening using the second sub-dielectric layer as a mask, forming the second recess.
[0015] Optionally, during the first etching process, the etching selectivity of the first etching process is greater than 10:1, and during the second etching process, the etching selectivity of the second etching process is greater than 5:1.
[0016] Optionally, the step of forming the mask layer with mask openings on top of the first dielectric layer comprises: forming a mask material layer on top of the first dielectric layer, the mask material layer comprising full-exposed regions located at the interconnection regions and half-exposed regions located at the capacitor regions, and the exposed depth of the mask material layer of the full-exposed regions being greater than the exposed depth of the mask material layer of the half-exposed regions; exposing and developing the full-exposed regions and the half-exposed regions of the first dielectric layer to form the mask layer with mask openings on top of the first dielectric layer, the depth of the mask openings of the interconnection regions being greater than the depth of the mask openings of the capacitor regions, and the mask openings of the interconnection regions exposing the top surface of the second sub-dielectric layer.
[0017] Optionally, the full-exposed regions and the half-exposed regions of the first dielectric layer are exposed by a Half Tone mask.
[0018] Optionally, after the first recess is formed, before the second recess is formed, the method further comprises: forming a protection layer on the substrate surface exposed by the first recess; and during the process of forming the conductive material layer, the conductive material layer covers the protection layer.
[0019] Optionally, the material of the protection layer comprises one or more of silicon oxide, silicon oxynitride and silicon carbide.
[0020] Optionally, the process of forming the conductive material layer comprises an electroplating process.
[0021] Optionally, in the step of providing the substrate, the substrate comprises a front surface and a back surface opposite to the front surface; in the step of forming the capacitor, the capacitor exposes the front surface; after the one or more metal lines are formed in the second dielectric layer, the method of forming the semiconductor structure further comprises: thinning the back surface of the substrate until the interconnection via structure is exposed.
[0022] Compared with the prior art, the technical scheme of the embodiment of the application has the following advantages:
[0023] The embodiment of the present application provides a semiconductor structure forming method, a capacitor is formed in a substrate of a capacitor region, a first dielectric layer covering the capacitor is formed on the substrate, an interconnection via structure is formed in the first dielectric layer and the substrate of an interconnection region, a first interconnection layer is formed in the first dielectric layer of the capacitor region, and the first interconnection layer is electrically connected with the capacitor, compared with the prior art which uses two masks to respectively etch to form the interconnection via structure and the first interconnection layer, the embodiment of the present application forms the interconnection via structure and the first interconnection layer in the same step, the pattern of the interconnection via structure and the first interconnection layer is transferred to the first dielectric layer by using only one mask, so that the first dielectric layer is used as an etching mask, the interconnection via structure is formed in the first dielectric layer and the substrate of the interconnection region, and the first interconnection layer is formed in the first dielectric layer of the capacitor region, thereby reducing the process steps of forming the interconnection via structure and the first interconnection layer, and at least one mask is saved, and the process cost is reduced. BRIEF DESCRIPTION OF DRAWINGS
[0024] Figures 1 to 16 FIG. 1 is a structure diagram corresponding to each step in an embodiment of the semiconductor structure forming method of the present application. DETAILED DESCRIPTION
[0025] As known from the background, at present, at least one mask is needed to transfer the pattern of the interconnection via structure to a mask layer in the forming process of the 2.5D Interposer device, and another mask is needed to transfer the pattern of the interconnection layer electrically connected with the capacitor plate layer to another mask layer, and then the interconnection via structure and the interconnection layer are respectively formed through different etching steps and filling processes, thereby increasing the process steps of forming the interconnection via structure and the interconnection layer, and also increasing the process cost of forming the interconnection via structure and the interconnection layer.
[0026] In order to solve the technical problem, the embodiment of the present application provides a semiconductor structure forming method, which comprises the following steps: providing a substrate, the substrate comprising an interconnection region and a capacitor region adjacent to the interconnection region; forming a capacitor in the substrate of the capacitor region; forming a first dielectric layer covering the capacitor on the substrate; forming an interconnection via structure in the first dielectric layer and the substrate of the interconnection region, and forming a first interconnection layer in the first dielectric layer of the capacitor region, the first interconnection layer being electrically connected with the capacitor; forming a second dielectric layer covering the first dielectric layer and the interconnection via structure, and the first interconnection layer on the top of the substrate; forming one or more metal lines in the second dielectric layer, the metal lines being electrically connected with the interconnection via structure, and the metal lines being electrically connected with the first interconnection layer.
[0027] In the scheme disclosed in the embodiment of the present application, the capacitor is formed in the substrate of the capacitor region, the first dielectric layer covering the capacitor is formed on the substrate, the interconnection via structure is formed in the first dielectric layer and the substrate of the interconnection region, and the first interconnection layer is formed in the first dielectric layer of the capacitor region and is electrically connected with the capacitor. Compared with the prior scheme of etching the interconnection via structure and the first interconnection layer by using two masks respectively, the interconnection via structure and the first interconnection layer are formed in the same step in the embodiment of the present application, the pattern of the interconnection via structure and the first interconnection layer is transferred to the first dielectric layer by using only one mask, the first dielectric layer is used as an etching mask, the interconnection via structure is formed in the first dielectric layer and the substrate of the interconnection region, and the first interconnection layer is formed in the first dielectric layer of the capacitor region, thereby reducing the process steps of forming the interconnection via structure and the first interconnection layer and saving at least one mask, and the process cost is reduced.
[0028] In order to make the above-mentioned purposes, features and advantages of the embodiments of the present application more obvious and easy to understand, the specific embodiments of the present application will be described in detail below with reference to the drawings.
[0029] Figures 1 to 16 is a structure schematic diagram corresponding to each step in an embodiment of the forming method of the semiconductor structure of the present application.
[0030] Reference Figure 1 A substrate 100 is provided, and the substrate 100 includes an interconnection region 100A and a capacitor region 100B adjacent to the interconnection region 100A.
[0031] The substrate 100 is used to provide a process platform for the subsequent forming process of the semiconductor structure.
[0032] As an example, the material of the substrate 100 is silicon. In other embodiments, the material of the substrate 100 can also be germanium, silicon carbide, gallium arsenide or indium gallium. The substrate 100 can also be a silicon substrate 100 on an insulator or a germanium substrate 100 on an insulator.
[0033] In the embodiment, the substrate 100 includes a front surface 190 and a back surface 191 opposite to the front surface 190.
[0034] It should be noted that the interconnection region 100A is used as a region for forming the interconnection via structure subsequently, so that the chip located in the interconnection region 100A can be electrically connected with the external circuit structure through the interconnection via structure.
[0035] It should also be noted that the capacitor region 100B is used as a region for forming the capacitor subsequently, and the capacitor is formed to reduce the probability of the power supply voltage noise affecting the semiconductor structure, thereby improving the response speed of the transient current of the semiconductor structure.
[0036] Referring to Figures 2 to 3 A capacitor 102 is formed in the substrate 100 of the capacitor region 100B.
[0037] Specifically, by forming the capacitor 102 in the substrate 100, the capacitor 102 can be mainly used as a decoupling capacitor in the semiconductor structure, which can reduce the probability of the power supply voltage noise affecting the semiconductor structure, thereby improving the response speed of the transient current of the semiconductor structure.
[0038] As an example, the step of forming the capacitor 102 in the capacitor region 100B includes: forming a capacitor trench 199 in the substrate 100 of the capacitor region 100B; forming a plurality of plate layers 1021 and a third dielectric layer 1022 located between adjacent plate layers 1021 on the bottom and sidewall of the capacitor trench 199 and the top of the substrate 100 located on the side of the capacitor trench 199, and the plurality of plate layers 1021 and the third dielectric layer 1022 located between adjacent plate layers 1021 are used to constitute the capacitor 102.
[0039] Specifically, the capacitor trench 199 provides a spatial position for forming the capacitor 102.
[0040] In this embodiment, the process of forming the capacitor trench 199 includes a dry etching process.
[0041] It should be noted that the plate layer 1021 is used as the electrode input end and the electrode output end of the capacitor 102.
[0042] As shown in Figure 3 It is shown that the capacitor 102 has two plate layers 1021.
[0043] As an example, the plate layer 1021 closest to the bottom of the capacitor trench 199 is used as the electrode input end, and the other plate layer 1021 is used as the electrode output end.
[0044] In this embodiment, the material of the plate layer 1021 includes one or more of polysilicon, copper, tungsten, cobalt, and titanium nitride.
[0045] Specifically, polysilicon, copper, tungsten, cobalt, and titanium nitride are all conductive materials, which can make the plate layer 1021 play a conductive role. At the same time, polysilicon, copper, tungsten, cobalt, and titanium nitride are commonly used materials for forming the plate layer 1021, which has low process cost. In addition, the resistivity of polysilicon, copper, tungsten, cobalt, and titanium nitride is low, which is beneficial to further improve the ability of the capacitor 102 to filter high-frequency noise, make the power supply voltage stable and clean, and ensure the normal work of the semiconductor structure.
[0046] It is to be noted that the third dielectric layer 1022 serves to electrically isolate the adjacent plate layers 1021, reducing the risk of leakage current between the adjacent plate layers 1021.
[0047] As an example, the material of the third dielectric layer 1022 includes one or more of silicon oxide, silicon nitride, hafnium oxide, zinc oxide, zirconium oxide, and aluminum oxide.
[0048] Specifically, silicon oxide, silicon nitride, hafnium oxide, zinc oxide, zirconium oxide, and aluminum oxide are all dielectric materials, which can serve to electrically isolate the adjacent plate layers 1021.
[0049] It is to be noted that in the step of forming the capacitor 102, the capacitor 102 exposes the front surface 190.
[0050] It is also to be noted that continuing to refer to Figure 3 After forming the capacitor trench 199, before forming the capacitor 102, a second insulating layer 103 is formed on the bottom and sidewall of the capacitor trench 199 and the top of the substrate 100 on the side of the capacitor trench 199.
[0051] Specifically, the second insulating layer 103 serves to electrically isolate the capacitor 102 from the substrate 100, reducing the probability of leakage current between the capacitor 102 and the substrate 100.
[0052] As an example, the material of the second insulating layer 103 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.
[0053] It is to be noted that silicon oxide, silicon nitride, and silicon oxynitride are all dielectric materials, which can serve to electrically isolate the capacitor 102 from the substrate 100.
[0054] Continuing to refer to Figure 3 After forming the capacitor 102, before subsequently forming the first dielectric layer, a first insulating layer 104 is formed in the capacitor region 100B to cover the capacitor 102, and a passivation layer 101 is formed in the capacitor region 100B and the interconnection region 100A to cover the substrate 100 and the first insulating layer 104.
[0055] Specifically, the first insulating layer 104 serves to electrically isolate the topmost plate layer 1021 of the capacitor 102, reducing the probability of corrosion of the plate layer 1021, and in the process of forming the first insulating layer 104, the material forming the first insulating layer 104 also fills the remaining space in the capacitor trench 199, providing a higher flat surface for subsequent processes.
[0056] As an example, the material of the first insulating layer 104 includes one or more of silicon oxide, silicon nitride, and silicon oxynitride.
[0057] It should be noted that silicon oxide, silicon nitride, and silicon oxynitride are all dielectric materials, which can play a role in electrically isolating the capacitor 102 from the substrate 100.
[0058] Specifically, the passivation layer 101 plays a protective role for the capacitor 102 and the first insulating layer 104, reduces damage to the capacitor 102 and the first insulating layer 104 in subsequent processes of forming the first interconnection layer, and reduces the probability of the first insulating layer 104 being gradually consumed by subsequent processes (such as etching processes).
[0059] As an example, the material of the passivation layer 101 includes one or more of silicon nitride, silicon oxide, silicon oxynitride, and polyimide.
[0060] Reference Figure 4 A first dielectric layer 105 covering the capacitor 102 is formed on the substrate 100.
[0061] It should be noted that the first dielectric layer 105 provides a process basis for subsequent formation of interconnection via structures and the first interconnection layer, and at the same time, the first dielectric layer 105 also plays a role in electrically isolating the interconnection via structures and the first interconnection layer, and in the subsequent process of forming the first interconnection layer and the interconnection via structure, part of the thickness of the first dielectric layer 105 (i.e., the second sub-dielectric layer 1053 formed subsequently) is also used as an etching mask.
[0062] As an example, the step of forming the first dielectric layer 105 covering the capacitor 102 includes: forming a first sub-dielectric layer 1051 covering the capacitor 102 on the substrate 100; forming an etching stop layer 1052 covering the first sub-dielectric layer 1051; and forming a second sub-dielectric layer 1053 covering the etching stop layer 1052, the first sub-dielectric layer 1051, the etching stop layer 1052, and the second sub-dielectric layer 1053 constituting the first dielectric layer 105.
[0063] It should be noted that by forming the first sub-dielectric layer 1051, the first sub-dielectric layer 1051 can provide high support for the first interconnection layer and the interconnection via structure formed subsequently, so that the height of the first interconnection layer and the interconnection via structure can meet the preset requirements.
[0064] It is also to be noted that, by forming the etching stop layer 1052 on top of the first sub-dielectric layer 1051, the etching stop layer 1052 can be used as the etching stop position for forming the first opening and the second opening in the subsequent process of forming the first opening and the second opening, which reduces the probability of over-etching in the process of forming the first opening and the second opening, and in turn reduces the probability of the first sub-dielectric layer 1051 on the bottom of the etching stop layer 1052 being consumed early.
[0065] Specifically, by forming the second sub-dielectric layer 1053 on top of the etching stop layer 1052, in the subsequent process of forming the first interconnection layer and the interconnection via structure, the pattern for forming the interconnection via structure and the first interconnection layer is transferred to the second sub-dielectric layer 1053 by using one mask, so that the second sub-dielectric layer 1053 is used as the etching mask for forming the interconnection via structure and the first interconnection layer.
[0066] As an example, the first sub-dielectric layer 1051, the etching stop layer 1052 and the second sub-dielectric layer 1053 are sequentially formed by performing a plurality of deposition processes.
[0067] In this embodiment, the material of the first dielectric layer 105 includes one or more of silicon nitride, silicon oxynitride, silicon carbide, silicon carbon nitride and silicon oxide.
[0068] Reference Figures 5 to 14 In the first dielectric layer 105 of the interconnection region 100A and the substrate 100, the interconnection via structure 172 is formed, and in the first dielectric layer 105 of the capacitor region 100B, the first interconnection layer 174 is formed, which is electrically connected to the capacitor 102.
[0069] It is to be noted that, compared with the scheme of forming the interconnection via structure 172 and the first interconnection layer 174 by etching respectively using two masks, in this embodiment, the interconnection via structure 172 and the first interconnection layer 174 are formed in the same step, and the pattern for forming the interconnection via structure 172 and the first interconnection layer 174 is transferred to the first dielectric layer 105 (i.e. the second sub-dielectric layer 1053) by using only one mask, so that the second sub-dielectric layer 1053 is used as the etching mask, in the first dielectric layer 105 of the interconnection region 100A and the substrate 100, the interconnection via structure 172 is formed, and in the first dielectric layer 105 of the capacitor region 100B, the first interconnection layer 174 is formed, thereby reducing the process steps of forming the interconnection via structure 172 and the first interconnection layer 174, and at least saving one mask, and in turn reducing the process cost.
[0070] In combination Figures 5 to 14 The steps of forming the interconnection via structure 172 and the first interconnection layer 174 are described in detail.
[0071] Referring to Figures 5 to 12 After the first recess 120 is formed, a second recess 126 is formed through the second sub-dielectric layer 1053, the etching stop layer 1052, the first sub-dielectric layer 1051 and the passivation layer 101 above the capacitor 102 of the capacitor region 100B.
[0072] It should be noted that the first recess 120 provides a spatial position for the subsequent formation of the interconnection via structure 172, and the second recess 126 provides a spatial position for the subsequent formation of the first interconnection layer 174.
[0073] It should be further noted that the first recess 120 is formed through the second sub-dielectric layer 1053, the etching stop layer 1052, the first sub-dielectric layer 1051, the passivation layer 101 and part of the thickness of the substrate 100, and the second recess 126 is formed through the second sub-dielectric layer 1053, the etching stop layer 1052, the first sub-dielectric layer 1051 and the passivation layer 101, that is, the depth of the first recess 120 is greater than the depth of the second recess 126. In order to reduce the probability of over-etching of the respective film layers below the first recess 120 and the second recess 126 during the formation of the first recess 120 and the second recess 126, the first recess 120 is formed first, and then the second recess 126 is formed, which can reduce the probability of damage to the capacitor 102 of the capacitor region 100B caused by the process of forming the first recess 120.
[0074] In combination Figures 5 to 12 The steps of forming the first recess 120 and the second recess 126 are further described in detail.
[0075] Referring to Figures 5 to 7 A mask layer 115 having a mask opening 114 is formed on the top of the first dielectric layer 105, the depth of the mask opening 114 of the interconnection region 100A is greater than the depth of the mask opening 114 of the capacitor region 100B, and the mask opening 114 of the interconnection region 100A exposes the top surface of the second sub-dielectric layer 1053.
[0076] Specifically, the mask layer 115 is used to transfer the pattern of the first interconnection layer 174 and the interconnection via structure 172 to the second sub-dielectric layer 1053.
[0077] It is to be noted that the depth of the mask opening 114 in the interconnection region 100A is greater than the depth of the mask opening 114 in the capacitor region 100B, and the mask opening 114 in the interconnection region 100A exposes the top surface of the second sub-dielectric layer 1053, that is, the mask opening 114 in the capacitor region 100B does not expose the top surface of the second sub-dielectric layer 1053. In the subsequent process of patterning the second sub-dielectric layer 1053 using the mask layer 115 as a mask, since the mask opening 114 in the interconnection region 100A exposes the top surface of the second sub-dielectric layer 1053, the second sub-dielectric layer 1053 exposed by the mask opening 114 in the interconnection region 100A will be completely removed, while the mask opening 114 in the capacitor region 100B does not expose the top surface of the second sub-dielectric layer 1053, and the etching process will first remove the mask layer 115 at the bottom of the mask opening 114 in the capacitor region 100B, and then remove part of the thickness of the second sub-dielectric layer 1053, thereby forming a first opening and a second opening in the second sub-dielectric layer 1053, and the first opening penetrates through the second sub-dielectric layer 1053, while the second opening only penetrates through part of the thickness of the second sub-dielectric layer 1053.
[0078] As an example, the step of forming the mask layer 115 with the mask opening 114 on the top of the first dielectric layer 105 includes: forming a mask material layer 106 on the top of the first dielectric layer 105, the mask material layer 106 including a full exposure region 107A in the interconnection region 100A and a half exposure region 107B in the capacitor region 100B, and the exposed depth of the mask material layer 106 in the full exposure region 107A is greater than the exposed depth of the mask material layer 106 in the half exposure region 107B; exposing and developing the full exposure region 107A and the half exposure region 107B of the first dielectric layer 105 to form the mask layer 115 with the mask opening 114 on the top of the first dielectric layer 105, the depth of the mask opening 114 in the interconnection region 100A is greater than the depth of the mask opening 114 in the capacitor region 100B, and the mask opening 114 in the interconnection region 100A exposes the top surface of the second sub-dielectric layer 1053.
[0079] It is to be noted that the full exposure region 107A refers to the mask material layer 106 in this region being fully exposed, and the half exposure region 107B refers to the mask material layer 106 in this region being partially exposed.
[0080] Specifically, since the mask material layer 106 of the full exposure area 107A is fully exposed, and the mask material layer 106 of the half exposure area 107B is partially exposed, after development, the mask material layer 106 of the full exposure area 107A is fully removed, and the mask material layer 106 of the half exposure area 107B is only partially removed, thereby forming a mask layer 115 with a mask opening 114 on the top of the first dielectric layer 105, the depth of the mask opening 114 of the interconnection area 100A is greater than the depth of the mask opening 114 of the capacitor area 100B.
[0081] As an example, the full exposure area 107A and the half exposure area 107B of the first dielectric layer 105 are exposed by the Half Tone mask 113.
[0082] Specifically, the Half Tone mask 113 itself has a transmission area 110 and a half-transmission area 112, the transmission area 110 corresponds to the position of the full exposure area 107A, and the half-transmission area 112 corresponds to the position of the half exposure area 107B, the light transmittance of the transmission area 110 is higher than that of the half-transmission area 112, and accordingly, in the process of exposing the full exposure area 107A and the half exposure area 107B of the first dielectric layer 105 by the Half Tone mask 113, the mask material layer 106 of the full exposure area 107A is fully exposed by the transmitted light, and the mask material layer 106 of the half exposure area 107B is only partially exposed by the transmitted light.
[0083] Reference Figure 8 With the mask layer 115 as a mask, the second sub-dielectric layer 1053 is patterned along the mask opening 114, a first opening 116 is formed through the second sub-dielectric layer 1053 in the interconnection area 100A, and a second opening 117 is formed through part of the thickness of the second sub-dielectric layer 1053 in the capacitor area 100B.
[0084] Specifically, the first opening 116 is used as a mask opening 114 for subsequent formation of a first groove 120, and the second opening 117 is used as a mask opening 114 for subsequent formation of a second groove 126.
[0085] It should be noted that in the process of subsequently performing first etching along the first opening 116 to form the first groove 120 with the second sub-dielectric layer 1053 as a mask, the second sub-dielectric layer 1053 at the bottom of the second opening 117 can protect the etching stop layer 1052, the first sub-dielectric layer 1051 and the capacitor 102 thereunder, thereby reducing the probability of damage to other film layers caused by the etching process of forming the first groove 120.
[0086] It should be noted that, since the mask opening 114 of the interconnection region 100A exposes the top surface of the second sub-dielectric layer 1053, the second sub-dielectric layer 1053 exposed by the mask opening 114 of the interconnection region 100A will be removed completely, and since the mask opening 114 of the capacitor region 100B does not expose the top surface of the second sub-dielectric layer 1053, the mask layer 115 at the bottom of the mask opening 114 of the capacitor region 100B will be removed first, and then a part of the thickness of the second sub-dielectric layer 1053 will be removed, so as to form the first opening 116 and the second opening 117 in the second sub-dielectric layer 1053, and the first opening 116 penetrates through the second sub-dielectric layer 1053, while the second opening 117 only penetrates through a part of the thickness of the second sub-dielectric layer 1053.
[0087] In this embodiment, the process of patterning the second sub-dielectric layer 1053 along the mask opening 114 includes a dry etching process.
[0088] With reference to Figure 8 , the mask layer 115 is removed.
[0089] It should be noted that, by removing the mask layer 115, it is beneficial for subsequent formation of the first recess 120 and the second recess 126 by taking the second sub-dielectric layer 1053 as an etching mask, and meanwhile, by removing the mask layer 115, the overall height of the etching mask for forming the first recess 120 and the second recess 126 is reduced, and the process difficulty of subsequent etching process is reduced.
[0090] In this embodiment, the mask layer 115 is removed by an ashing process.
[0091] In other embodiments, the mask layer 115 can also be removed by a wet etching process.
[0092] With reference to Figure 9 , after the mask layer 115 is removed, a first etching treatment is performed on the etching stop layer 1052, the first sub-dielectric layer 1051, the passivation layer 101 and a part of the substrate 100 of the interconnection region 100A by taking the second sub-dielectric layer 1053 as a mask along the first opening 116, so as to form the first recess 120.
[0093] It should be noted that, during the first etching treatment, the etching selectivity ratio of the first etching treatment should not be too small. If the etching selectivity ratio of the first etching treatment is too small, the probability of etching and removing the second sub-dielectric layer 1053 is increased during the formation of the first recess 120, and the probability of damage to other film layers is increased. Therefore, in this embodiment, the etching selectivity ratio of the first etching treatment is greater than 10:1 during the first etching treatment.
[0094] As an example, the process of forming the first recess 120 includes a dry etching process.
[0095] Specifically, the dry etching process can form a higher sidewall profile quality, which is beneficial for subsequent filling of the conductive material layer in the first recess 120. Meanwhile, the dry etching process has high pattern transfer accuracy, and can make the subsequently formed interconnection via structure 172 meet the size requirement.
[0096] Reference Figure 10 After forming the first recess 120, before forming the second recess 126, a protection layer 130 is formed on the exposed substrate 100 surface of the first recess 120.
[0097] Specifically, in the process of subsequently removing the remaining second sub-dielectric layer 1053 under the second opening 117 and forming the second recess 126, the protection layer 130 protects the exposed substrate 100 surface of the first recess 120, reducing the probability of damage to the substrate 100 surface caused by the subsequent etching process. After the subsequent formation of the interconnection via structure 172, the protection layer 130 is located between the interconnection via structure 172 and the substrate 100, and the protection layer 130 can electrically isolate the interconnection via structure 172 and the substrate 100, reducing the risk of electrical leakage between the interconnection via structure 172 and the substrate 100.
[0098] As an example, the material of the protection layer 130 includes one or more of silicon oxide, silicon oxynitride, and silicon carbide.
[0099] Specifically, silicon oxide, silicon oxynitride, and silicon carbide are all dielectric materials, which can electrically isolate the interconnection via structure 172 and the substrate 100. Meanwhile, silicon oxide, silicon oxynitride, and silicon carbide have etching selectivity with the material selected for the second sub-dielectric layer 1053, which can protect the exposed substrate 100 surface of the first recess 120.
[0100] As an example, the step of forming the protection layer 130 includes performing a thermal oxidation process on the exposed substrate 100 surface of the first recess 120 to form the protection layer 130.
[0101] Specifically, by performing a thermal oxidation process on the exposed substrate 100 surface of the first recess 120 to form the protection layer 130, the protection layer 130 does not occupy the space position of the first recess 120, and the space position of the first recess 120 is entirely reserved for the subsequently formed interconnection via structure 172, improving the conductive performance of the interconnection via structure 172.
[0102] In other embodiments, the protection layer can also be formed on the exposed substrate surface of the first recess by deposition processing.
[0103] Referring to Figure 11 After the first recess 120 is formed, the second sub-dielectric layer 1053 under the second opening 117 is removed along the second opening 117 by taking the second sub-dielectric layer 1053 as a mask.
[0104] It should be noted that since the capacitor 102 has multiple plate layers 1021, and each plate layer 1021 is electrically connected to the subsequently formed first interconnection layer 174, the depth of each second recess 126 is inconsistent in the process of subsequently forming the second recess 126. By taking the top of the etching stop layer 1052 as the etching stop position, the remaining second sub-dielectric layer 1053 under the second opening 117 is removed first, and in the process of subsequently forming the second recess 126 along the second opening 117, the probability of over-etching can be reduced.
[0105] As an example, the process of removing the remaining second sub-dielectric layer 1053 under the second opening 117 includes a dry etching process.
[0106] Referring to Figure 12 After the remaining second sub-dielectric layer 1053 under the second opening 117 is removed, the etching stop layer 1052, the first sub-dielectric layer 1051, and the passivation layer 101 above the capacitor 102 are subjected to a second etching process along the second opening 117 by taking the second sub-dielectric layer 1053 as a mask, and the second recess 126 is formed.
[0107] It should be noted that in the process of the second etching process, the etching selectivity ratio of the second etching process should not be too small. If the etching selectivity ratio of the second etching process is too small, the probability of the second sub-dielectric layer 1053 being etched and removed is increased in the process of forming the second recess 126, and the probability of other film layers (for example, the film layers covered by the second sub-dielectric layer 1053) being damaged is increased. Therefore, in the present embodiment, the etching selectivity ratio of the second etching process is greater than 5:1 in the process of the second etching process.
[0108] As an example, the process of forming the second recess 126 includes a dry etching process.
[0109] Specifically, the dry etching process can form a higher sidewall topography quality, which is beneficial to subsequent filling of a conductive material layer in the second recess 126. At the same time, the dry etching process has high pattern transfer precision, and the subsequently formed first interconnection layer 174 can meet the size requirements.
[0110] Referring to Figure 13A conductive material layer 170 is formed in the first recess 120, the second recess 126, and on the top of the second sub-dielectric layer 1053.
[0111] Specifically, the conductive material layer 170 is used as a material layer for forming a first interconnection layer 174.
[0112] In this embodiment, the process for forming the conductive material layer 170 includes an electroplating process.
[0113] Specifically, the electroplating process is a commonly used process for forming the conductive material layer 170, which is low in process cost and suitable for mass production. Meanwhile, the quality of the conductive material layer 170 formed by the electroplating process is relatively high, which reduces the risk of forming holes in the conductive material layer 170.
[0114] In this embodiment, during the process of forming the conductive material layer 170, the conductive material layer 170 covers the protective layer 130, so that the subsequently formed interconnection via structure 172 can be electrically isolated from the substrate 100.
[0115] Reference Figure 14 The conductive material layer 170 above the top of the second sub-dielectric layer 1053 is planarized, the remaining conductive material layer 170 in the first recess 120 is used as the interconnection via structure 172, and the remaining conductive material layer 170 in the second recess 126 is used as the first interconnection layer 174.
[0116] Specifically, by planarizing the conductive material layer 170 above the top of the second sub-dielectric layer 1053, the flatness of the top surface of the first dielectric layer 105 is higher, which is beneficial for subsequently forming one or more metal lines on the top surface of the first dielectric layer 105.
[0117] It should be noted that the interconnection via structure 172 is used to electrically connect multiple functional chips in the semiconductor structure to an external circuit structure or an external circuit carrier board, thereby meeting various functional requirements.
[0118] It should also be noted that the first interconnection layer 174 is used to provide a voltage to the capacitor 102, so that the capacitor 102 can be in a working state.
[0119] As an example, during the process of forming the first interconnection layer 174, the first interconnection layer 174 is electrically connected to each of the plate layers 1021, so that each plate layer has a current input, and the capacitor 102 can work normally.
[0120] Reference Figure 15A second dielectric layer 180 is formed on top of the substrate, covering the first dielectric layer 105 and the interconnection via structure 172, and the first interconnection layer 174.
[0121] Specifically, the second dielectric layer 180 provides a process basis for the subsequent formation of metal lines, and also serves to electrically isolate the subsequently formed metal lines.
[0122] In this embodiment, the second dielectric layer 180 is formed by a chemical vapor deposition process.
[0123] As an example, the material of the second dielectric layer 180 includes one or more of silicon nitride, silicon oxynitride, and silicon carbide.
[0124] Continuing to refer to Figure 15 One or more metal lines 182 are formed in the second dielectric layer 180, the metal lines 182 being electrically connected to the interconnection via structure 172 and the first interconnection layer 174.
[0125] It should be noted that the metal lines 182 are used to be electrically connected to a plurality of functional chips subsequently formed on top of the second dielectric layer 180, so that the plurality of functional chips can be electrically connected to an external circuit structure or an external circuit carrier through the interconnection via structure 172, and the metal lines 182 are electrically connected to the first interconnection layer 174, so that the metal lines 182 can provide an operating voltage to the capacitor 102 through the first interconnection layer 174.
[0126] In this embodiment, the metal lines 182 are formed by forming a recess in the second dielectric layer 180 and then depositing a metal material in the recess.
[0127] As an example, the material of the metal lines 182 includes copper.
[0128] Referring to Figure 16 After the one or more metal lines 182 are formed in the second dielectric layer 180, the method of forming the semiconductor structure further includes: performing a thinning process on the back surface 191 of the substrate 100 until the interconnection via structure 172 is exposed.
[0129] Specifically, the thinning process on the back surface 191 of the substrate 100 reduces the overall thickness of the semiconductor structure, which is conducive to further reducing the size, and the interconnection via structure 172 is exposed by the thinning process, which is conducive to the subsequent formation of a conductive bump on the surface of the exposed interconnection via structure 172, so that an external circuit carrier or an external circuit structure can be electrically connected to the semiconductor structure through the conductive bump.
[0130] As an example, the process of thinning the back surface 191 of the substrate 100 includes a chemical mechanical polishing process.
[0131] Although the present application has been disclosed with reference to the above embodiments, the above embodiments are not intended to limit the present application. Various changes and modifications are possible in the present application and therefore the present application should not be limited to the above embodiments but should be defined by the scope of the following claims.
Claims
1. A method of forming a semiconductor structure, characterized by, Comprising: providing a substrate, the substrate comprising an interconnect region and a capacitor region adjacent thereto; forming a capacitor in the substrate of the capacitor region; forming a first dielectric layer on the substrate covering the capacitor; forming an interconnect via structure in the first dielectric layer and substrate of the interconnect region, forming a first interconnect layer in the first dielectric layer of the capacitor region, the first interconnect layer electrically connected to the capacitor; forming a second dielectric layer on top of the substrate covering the first dielectric layer and interconnect via structure, and the first interconnect layer; forming one or more metal lines in the second dielectric layer, the metal lines electrically connected to the interconnect via structure, and the metal lines electrically connected to the first interconnect layer.
2. The method of forming a semiconductor structure of claim 1, wherein, The step of forming a capacitor in the capacitor region comprises: forming a capacitor trench in the substrate of the capacitor region; forming a plurality of plate layers and a third dielectric layer between adjacent plate layers in a spaced stack on the bottom and sidewalls of the capacitor trench and on top of the substrate at the sides of the capacitor trench, the plurality of plate layers and the third dielectric layer between adjacent plate layers for constituting a capacitor; In forming the first interconnect layer, the first interconnect layer is electrically connected to each of the plate layers, respectively.
3. The method of forming a semiconductor structure of claim 2, wherein, After forming the capacitor trench and before forming the capacitor, further comprising: forming a second insulating layer on the bottom and sidewalls of the capacitor trench and on top of the substrate at the sides of the capacitor trench.
4. The method of forming a semiconductor structure of claim 3, wherein, The second insulating layer comprises one or more of silicon oxide, silicon nitride, and silicon oxynitride.
5. The method of forming a semiconductor structure of claim 2, wherein, The plate layers comprise one or more of polysilicon, copper, tungsten, cobalt, and titanium nitride. The third dielectric layer comprises one or more of silicon oxide, silicon nitride, hafnium oxide, zinc oxide, zirconium oxide, and aluminum oxide.
6. The method of forming a semiconductor structure of claim 1, wherein, After forming the capacitor and before forming the first dielectric layer, further comprising: forming a first insulating layer in the capacitor region covering the capacitor; forming a passivation layer in the capacitor region and interconnect region covering the substrate and the first insulating layer.
7. The method of forming a semiconductor structure of claim 6, wherein, The passivation layer comprises one or more of silicon nitride, silicon oxide, silicon oxynitride, and polyimide.
8. The method of forming a semiconductor structure of claim 1, wherein, The step of forming a first dielectric layer covering the capacitor comprises: forming a first sub-dielectric layer on the substrate, the first sub-dielectric layer covering the capacitor; forming an etch stop layer covering the first sub-dielectric layer; forming a second sub-dielectric layer covering the etch stop layer, the first sub-dielectric layer, the etch stop layer, and the second sub-dielectric layer constituting the first dielectric layer; The step of forming the interconnection via structure and the first interconnection layer comprises: forming a first recess in the interconnection region, the first recess penetrating the second sub-dielectric layer, the etching stop layer, the first sub-dielectric layer, the passivation layer and a partial thickness of the substrate; after forming the first recess, forming a second recess above the capacitor in the capacitor region, the second recess penetrating the second sub-dielectric layer, the etching stop layer, the first sub-dielectric layer and the passivation layer; forming a layer of conductive material in the first recess, the second recess and on the top of the second sub-dielectric layer; planarizing the layer of conductive material above the top of the second sub-dielectric layer, taking the top of the second sub-dielectric layer as a stop position, taking the remaining layer of conductive material in the first recess as the interconnection via structure and taking the remaining layer of conductive material in the second recess as the first interconnection layer.
9. The method of forming a semiconductor structure of claim 8, wherein, The process of forming the first recess comprises a dry etching process. The process of forming the second recess comprises a dry etching process.
10. The method of forming a semiconductor structure of claim 8, wherein, The step of forming the first recess and the second recess comprises: forming a mask layer with mask openings on the top of the first dielectric layer, the depth of the mask openings in the interconnection region being greater than the depth of the mask openings in the capacitor region, and the mask openings in the interconnection region exposing the top surface of the second sub-dielectric layer; patterning the second sub-dielectric layer along the mask openings, taking the mask layer as a mask, forming a first opening penetrating the second sub-dielectric layer in the interconnection region and forming a second opening penetrating a partial thickness of the second sub-dielectric layer in the capacitor region; removing the mask layer; after removing the mask layer, performing a first etching process on the etching stop layer, the first sub-dielectric layer, the passivation layer and a partial thickness of the substrate in the interconnection region along the first opening, taking the second sub-dielectric layer as a mask, to form the first recess; after forming the first recess, removing the remaining second sub-dielectric layer below the second opening along the second opening, taking the second sub-dielectric layer as a mask; after removing the remaining second sub-dielectric layer below the second opening, performing a second etching process on the etching stop layer, the first sub-dielectric layer and the passivation layer above the capacitor along the second opening, taking the second sub-dielectric layer as a mask, to form the second recess.
11. The method of forming a semiconductor structure of claim 10, wherein, During the first etching process, the etching selectivity of the first etching process is greater than 10:
1. During the second etching process, the etching selectivity of the second etching process is greater than 5:
1.
12. The method of forming a semiconductor structure of claim 10, wherein, The step of forming the mask layer with mask openings on top of the first dielectric layer includes: forming a mask material layer on top of the first dielectric layer, the mask material layer including full-exposed regions located at the interconnection regions and half-exposed regions located at the capacitor regions, and the exposed depth of the mask material layer of the full-exposed regions being greater than the exposed depth of the mask material layer of the half-exposed regions; and exposing and developing the full-exposed regions and the half-exposed regions of the first dielectric layer to form the mask layer with mask openings on top of the first dielectric layer, the depth of the mask openings of the interconnection regions being greater than the depth of the mask openings of the capacitor regions, and the mask openings of the interconnection regions exposing the top surface of the second sub-dielectric layer.
13. The method of forming a semiconductor structure of claim 10, wherein, The full-exposed regions and the half-exposed regions of the first dielectric layer are exposed by a Half Tone photomask.
14. The method of forming a semiconductor structure of claim 8, wherein, After the first recess is formed, before the second recess is formed, the method further includes: forming a protective layer on the substrate surface exposed by the first recess; During the forming of the conductive material layer, the conductive material layer covers the protective layer.
15. The method of forming a semiconductor structure of claim 14, wherein, The material of the protective layer includes one or more of silicon oxide, silicon oxynitride, and silicon carbide.
16. The method of forming a semiconductor structure of claim 8, wherein, The process of forming the conductive material layer includes an electroplating process.
17. The method of forming a semiconductor structure of claim 1, wherein, In the step of providing the substrate, the substrate includes a front surface and a back surface opposite to the front surface; In the step of forming the capacitor, the capacitor exposes the front surface; After the one or more metal lines are formed in the second dielectric layer, the method of forming the semiconductor structure further includes: thinning the back surface of the substrate until the interconnection via structure is exposed.