Circuitry with non-linearity cancellation

Abstract

The invention relates to circuitry with non-linearity cancellation. An electronic device may include wireless circuitry. The wireless circuitry may include a first input transistor and a second input transistor; a third transistor having a gate terminal coupled to the gate terminal of the first input transistor and having a drain terminal coupled to the second input transistor; a fourth transistor having a gate terminal coupled to a gate terminal of the second input transistor and having a drain terminal coupled to the first input transistor; one or more tail circuits coupled to source terminals of the third transistor and the fourth transistor; and a bias circuit configured to output a bias voltage, the bias voltage being delivered to the gate terminals of the first and second input transistors and the one or more tail circuits. A bias circuit may be coupled to the input transistors via coils and to one or more tail circuits via a feed-forward path.

Description

[0001] This application claims the benefit of provisional patent application No. 18 / 656,594, filed May 7, 2024, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0002] The present disclosure relates generally to electronic devices, and more particularly to electronic devices having wireless communication circuitry. BACKGROUND

[0003] Electronic devices often have wireless communication capabilities. Electronic devices with wireless communication capabilities have wireless communication circuitry with one or more antennas. Wireless transceiver circuitry in the wireless communication circuitry uses the antennas to transmit and receive radio frequency signals.

[0004] Radio frequency signals transmitted by an antenna can be fed through a power amplifier configured to amplify a low power analog signal into a high power signal more suitable for long distance transmission through air. Radio frequency signals received at an antenna can be fed through a low noise amplifier configured to amplify a low power analog signal into a high power signal for processing at a receiver. Designing satisfactory radio frequency amplifiers for electronic devices can be challenging. SUMMARY

[0005] Aspects of the present disclosure provide a circuitry comprising: a first input transistor and a second input transistor; a third transistor having a gate terminal coupled to a gate terminal of the first input transistor and having a drain terminal coupled to a drain terminal of the second input transistor; a fourth transistor having a gate terminal coupled to a gate terminal of the second input transistor and having a drain terminal coupled to a drain terminal of the first input transistor; one or more tail circuits coupled to source terminals of the third transistor and the fourth transistor; and a biasing circuit configured to output a bias voltage delivered to the gate terminals of the first input transistor and the second input transistor and the one or more tail circuits. At least one tail circuit of the one or more tail circuits can comprise: a plurality of tail transistors coupled in series between the source terminals of the third transistor and the fourth transistor and a power supply line; a first switch coupled between the biasing circuit and gate terminals of the plurality of tail transistors; and a second switch coupled between the gate terminals of the plurality of tail transistors and the power supply line. The circuitry can further comprise a coil having a first terminal coupled to a gate terminal of the first input transistor, a second terminal coupled to a gate terminal of the second input transistor, and a center tap terminal configured to receive the bias voltage.

[0006] Aspects of the disclosure provide a circuitry including a first input transistor; a second input transistor; and a nonlinearity cancellation circuit cross-coupled to the first input transistor and the second input transistor and having a plurality of programmable tail circuits. The nonlinearity cancellation circuit can be configured to at least partially cancel intermodulation signals generated from the first input transistor and the second input transistor. The nonlinearity cancellation circuit can include a third transistor having a gate terminal coupled to a gate terminal of the first input transistor and having a drain terminal coupled to a drain terminal of the second input transistor; and a fourth transistor having a gate terminal coupled to a gate terminal of the second input transistor and having a drain terminal coupled to a drain terminal of the first input transistor. The circuitry can further include a bias circuit configured to output a bias voltage that biases the first input transistor and the second input transistor and biases at least one programmable tail circuit of the plurality of programmable tail circuits. At least one programmable tail circuit can include a plurality of tail transistors coupled in series and having gate terminals shorted to each other. The circuitry can further include a coil having a first terminal coupled to a gate terminal of the first input transistor, a second terminal coupled to a gate terminal of the second input transistor, and a center tap terminal configured to receive the bias voltage. The center tap terminal of the coil can be coupled to the gate terminals of the plurality of tail transistors via a feedforward path. A switch can be disposed along the feedforward path.

[0007] Aspects of the disclosure provide a circuitry including input transistors; nonlinearity cancellation transistors cross-coupled to the input transistors; tail transistors coupled to source terminals of the nonlinearity cancellation transistors; and a feedforward path having a first terminal coupled to a common mode voltage for biasing the input transistors and having a second terminal coupled to the tail transistors. The circuitry can further include a coil having opposite terminals coupled to the input transistors and having a center tap terminal coupled to the tail transistors via the feedforward path. The circuitry can further include a bias circuit having an output coupled to the center tap terminal of the coil and coupled to the feedforward path.

[0008] Other features of the disclosure, its nature and various advantages will become more apparent from the drawings and the following detailed description. BRIEF DESCRIPTION OF DRAWINGS

[0009] Figure 1 is a diagram of an illustrative electronic device having wireless communication circuitry in accordance with some embodiments.

[0010] Figure 2 is a diagram of exemplary wireless communication circuitry according to some embodiments.

[0011] Figure 3 is a circuit diagram of exemplary differential circuitry with a three (3rd) order nonlinearity cancellation circuit according to some embodiments.

[0012] Figure 4 is a diagram illustrating third order nonlinearity cancellation according to some embodiments.

[0013] Figure 5 is a diagram illustrating how third order nonlinearity cancellation circuitry according to some embodiments Figure 3 is a diagram illustrating how a third order nonlinearity cancellation circuit of the type shown can be configured to reduce amplitude modulation to phase modulation (AMPM) distortion.

[0014] Figure 6 is a circuit diagram illustrating how a third order nonlinearity cancellation circuit according to some embodiments can include a tail transistor.

[0015] Figure 7 is a circuit diagram illustrating how a third order nonlinearity cancellation circuit according to some embodiments can include a programmable slice of stacked tail transistors.

[0016] Figure 8 is a diagram illustrating how amplitude modulation to amplitude modulation (AMAM) distortion can be reduced by employing a third order nonlinearity cancellation circuit according to some embodiments.

[0017] Figure 9 is a diagram illustrating how amplitude modulation to phase modulation (AMPM) distortion can be reduced by employing a third order nonlinearity cancellation circuit according to some embodiments.

[0018] Figure 10 is a diagram illustrating how a third order intercept point can be improved by employing a third order nonlinearity cancellation circuit according to some embodiments. DETAILED DESCRIPTION

[0019] Electronic devices that can provide wireless circuitry are disclosed. The wireless circuitry can include radio frequency amplifiers, mixers, and other transmit or receive circuitry for processing signals in a transmit path or a receive path. The amplifiers, mixers, or other components in the transmit or receive path can include one or more input transistors that exhibit non-linear behavior in practice. If not carefully managed, such transistor non-linearities can generate third order intermodulation distortion (IMD3), which degrades the signal-to-noise-and-distortion ratio (SNDR) and error vector magnitude (EVM) of the wireless circuitry.

[0020] To compensate for this third-order intermodulation distortion, the input transistor can be cross-coupled with a third-order nonlinearity cancellation circuit configured to provide a reduction in both amplitude modulation to amplitude modulation (AMAM) distortion and amplitude modulation to phase modulation (AMPM) distortion while preserving enhanced reverse isolation. To maintain linear performance across process and temperature corners, a feedforward loop is provided to sense a common-mode signal that biases the input transistor and is used to control a tail current that flows through the third-order nonlinearity cancellation circuit. A radio circuit arranged and operated in this way can be technologically advantageous and beneficial to ensure optimal linearization across different process, voltage, and temperature (PVT) conditions without requiring any dedicated trimming.

[0021] Figure 1 is an illustration of an electronic device, such as electronic device 10, which can be provided with a linear improvement circuit, such as a third (3rd) order nonlinearity cancellation circuit. Electronic device 10 can be a computing device, such as a notebook computer, a desktop computer, a computer monitor containing an embedded computer, a tablet computer, a cellular telephone, a media player, or other hand-held or portable electronic device; a smaller device, such as a wrist-watch device, a pendant device, a headphone or earpiece device, a device embedded in eyeglasses, or other equipment worn on a user’s head or as a piece of jewelry; or other wearable or miniature device, a television, a computer monitor that does not contain an embedded computer, a game device, a navigation device, an embedded system such as a system in which electronic equipment having a display is installed in an information kiosk or a car, a voice-controlled speaker connected to wireless Internet, a home entertainment device, a remote control device, a game controller, a peripheral user input device, a wireless base station or access point, equipment that implements the functionality of two or more of these devices; or other electronic equipment.

[0022] As Figure 1 Device 10 can include components located on or within an electronic device housing, such as housing 12, as shown in the illustration in FIG. 1. Housing 12 (which can sometimes be referred to as a case) can be formed of plastic, glass, ceramic, fiber composite, metal (e.g., stainless steel, aluminum, metal alloys, etc.), other suitable materials, or combinations of these materials. In some cases, some or all of housing 12 can be formed of a dielectric or other low electrical conductivity material (e.g., glass, ceramic, plastic, sapphire, etc.). In other cases, housing 12 or at least some of the structures that make up housing 12 can be formed of metal elements.

[0023] Device 10 can include control circuitry 14. Control circuitry 14 can include storage, such as storage circuitry 16. Storage circuitry 16 can include hard drive storage, non-volatile memory (e.g., flash memory or other electrically programmable read only memory configured to form a solid state drive), volatile memory (e.g., static random access memory or dynamic random access memory), etc. Storage circuitry 16 can include storage that is integrated within device 10 and / or removable storage media.

[0024] Control circuitry 14 can include processing circuitry, such as processing circuitry 18. Processing circuitry 18 can be used to control operation of device 10. Processing circuitry 18 can include one or more microprocessors, microcontrollers, digital signal processors, host processors, baseband processors integrated circuits, application-specific integrated circuits, central processing units (CPUs), etc. Control circuitry 14 can be configured to perform operations in device 10 using hardware (e.g., dedicated hardware or circuitry), firmware, and / or software. Software code for performing operations in device 10 can be stored on storage circuitry 16 (e.g., storage circuitry 16 can include non-transitory (tangible) computer-readable storage media that stores software code). This software code can sometimes be referred to as program instructions, software, data, instructions, or code. Software code stored on storage circuitry 16 can be executed by processing circuitry 18.

[0025] Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, voice-over-internet-protocol (VOIP) telephone call applications, electronic mail applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include: internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols - sometimes referred to as Wi-Fi® protocols), Bluetooth® protocols for other short-range wireless communication links, ZigBee® protocols or other wireless personal area network (WPAN) protocols, IEEE 802.11 ad protocols (e.g., ultra-wideband protocols), cellular telephone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G New Radio (NR) protocols, etc.), MIMO protocols, antenna diversity protocols, satellite navigation system protocols (e.g., global positioning system (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols or other desired distance detection protocols for signals transmitted at millimeter and centimeter wave frequencies), or any other desired communication protocol. Each communication protocol can be associated with a corresponding radio access technology (RAT) that specifies a physical connection method for implementing the protocol. Control circuitry 14 can be used to run software on device 10, such as satellite navigation applications, internet browsing applications, voice-over-internet-protocol (VOIP) telephone call applications, electronic mail applications, media playback applications, operating system functions, etc. To support interaction with external equipment, control circuitry 14 can be used to implement communication protocols. Communication protocols that can be implemented using control circuitry 14 include: internet protocols, wireless local area network (WLAN) protocols (e.g., IEEE 802.11 protocols - sometimes referred to as Wi-Fi® protocols), Bluetooth® protocols for other short-range wireless communication links, ZigBee® protocols or other wireless personal area network (WPAN) protocols, IEEE 802.11 ad protocols (e.g., ultra-wideband protocols), cellular telephone protocols (e.g., 3G protocols, 4G (LTE) protocols, 5G New Radio (NR) protocols, etc.), MIMO protocols, antenna diversity protocols, satellite navigation system protocols (e.g., global positioning system (GPS) protocols, global navigation satellite system (GLONASS) protocols, etc.), antenna-based spatial ranging protocols (e.g., radio detection and ranging (RADAR) protocols or other desired distance detection protocols for signals transmitted at millimeter and centimeter wave frequencies), or any other desired communication protocol. Each communication protocol can be associated with a corresponding radio access technology (RAT) that specifies a physical connection method for implementing the protocol.​

[0026] Device 10 can include input-output circuitry 20. Input-output circuitry 20 can include input-output devices 22. Input-output devices 22 can be used to allow data to be supplied to device 10 and to allow data to be provided from device 10 to external devices. Input-output devices 22 can include user interface devices, data port devices, and other input-output components. For example, input-output devices 22 can include touch sensors, displays, light-emitting components such as displays without touch sensor capabilities, buttons (mechanical, capacitive, optical, etc.), scroll wheels, touch pads, keypads, keyboards, microphones, cameras, buttons, speakers, status indicators, audio jack and other audio port components, digital data port devices, motion sensors (accelerometers, gyroscopes, and / or compasses that detect motion), capacitive sensors, proximity sensors, magnetic sensors, force sensors (e.g., force sensors coupled to a display to detect pressure applied to the display), etc. In some configurations, keyboards, earphones, displays, pointing devices such as touchpads, mice, electronic pens (e.g., styluses), and joysticks, among other input-output devices, can be coupled to device 10 using wired or wireless connections (e.g., some of input-output devices 22 can be peripheral devices that are coupled to a main processing unit or other portion of device 10 via wired or wireless links).

[0027] Input-output circuitry 20 can include wireless communication circuitry for wirelessly communicating radio frequency signals, such as wireless communication circuitry 24 (sometimes referred to herein as wireless circuitry 24). While control circuitry 14 is shown separate from wireless communication circuitry 24 for clarity, wireless communication circuitry 24 can include processing circuitry that forms a portion of processing circuitry 18 and / or storage circuitry that forms a portion of storage circuitry 16 of control circuitry 14 (e.g., portions of control circuitry 14 can be implemented on wireless communication circuitry 24). For example, control circuitry 14 (e.g., processing circuitry 18) can include baseband processor circuitry or other control components that form a portion of wireless communication circuitry 24.

[0028] Wireless communication circuitry 24 can include radio frequency (RF) transceiver circuitry formed from one or more integrated circuits, power amplifier circuitry configured to amplify uplink radio frequency signals (e.g., radio frequency signals transmitted by device 10 to external devices), low noise amplifiers configured to amplify downlink radio frequency signals (e.g., radio frequency signals received by device 10 from external devices), passive radio frequency components, one or more antennas, transmission lines, and other circuitry used in processing radio frequency wireless signals. Wireless signals can also be sent using light (e.g., using infrared communication).

[0029] Wireless circuit 24 may include radio frequency transceiver circuitry for transmitting and / or receiving radio frequency signals in various radio frequency communication bands. For example, the radio frequency transceiver circuitry may handle wireless local area network (WLAN) communication bands such as 2.4 GHz and 5 GHz. (IEEE 802.11) bands, Wireless Personal Area Network (WPAN) communication bands such as 2.4 GHz Communication frequency bands, cellular telephone communication frequency bands such as the cellular low frequency band (LB) (e.g., 600MHz to 960MHz), the cellular low intermediate frequency band (LMB) (e.g., 1400MHz to 1550MHz), the cellular intermediate frequency band (MB) (e.g., 1700MHz to 2200MHz), the cellular high frequency band (HB) (e.g., 2300MHz to 2700MHz), the cellular ultra-high frequency band (UHB) (e.g., 3300MHz to 5000MHz), or other cellular communication frequency bands between approximately 600MHz and approximately 5000MHz (e.g., 3G bands, 4G bands). This includes LTE bands, 5G New Radio Frequency Range 1 (FR1) bands below 10 GHz, 5G New Radio Frequency Range 2 (FR2) bands with millimeter and centimeter wavelengths between 20 GHz and 60 GHz, etc., near field communication (NFC) bands (e.g., 13.56 MHz), satellite navigation bands (e.g., the L1 Global Positioning System (GPS) band at 1575 MHz, the L5 GPS band at 1176 MHz, the Global Navigation Satellite System (GLONASS) band, the BeiDou Navigation Satellite System (BDS) band, etc.), ultra-wideband (UWB) communication bands supported by the IEEE 802.15.4 protocol and / or other UWB communication protocols (e.g., a first UWB communication band at 6.5 GHz and / or a second UWB communication band at 8.0 GHz), and / or any other desired communication bands. Communication bands processed by such RF transceiver circuits are sometimes referred to herein as frequency bands or simply "bands," and may span corresponding frequency ranges. Generally speaking, the radio frequency transceiver circuit in wireless circuit 24 can cover (process) any desired frequency band.

[0030] Figure 2 This is a diagram showing exemplary components within wireless circuit 24. (Example...) Figure 2 As shown, wireless circuitry 24 may include baseband circuitry 26, such as one or more baseband processors, radio frequency (RF) transceiver circuitry, such as an RF transceiver 28, RF front-end circuitry, such as an RF front-end module (FEM) 40, and an antenna 42. Baseband circuitry 26 may be coupled to transceiver 28 via baseband path 34. Transceiver 28 may be coupled to antenna 42 via RF transmission line path 36. RF front-end module 40 may be disposed on RF transmission line path 36 between transceiver 28 and antenna 42. Figure 2Any of the blocks shown can be provided with third order non-linearity cancellation circuitry configured to improve EVM of the overall radio 24.

[0031] In Figure 2 In the example shown for purposes of clarity, the radio 24 is shown as including only a single baseband processor 26, a single transceiver 28, a single front-end module 40, and a single antenna 42. In general, the radio 24 can include any desired number of baseband processors 26, any desired number of transceivers 28, any desired number of front-end modules 40, and any desired number of antennas 42. Each baseband processor 26 can be coupled to one or more transceivers 28 by a respective baseband path 34. Each transceiver 28 can include transmitter circuitry 30 configured to output uplink signals to an antenna 42, can include receiver circuitry 32 configured to receive downlink signals from an antenna 42, and can be coupled to one or more antennas 42 by a respective radio frequency transmission line path 36. Each radio frequency transmission line path 36 can have a respective front-end module 40 disposed thereon. If desired, two or more front-end modules 40 can be disposed on the same radio frequency transmission line path 36. If desired, one or more of the radio frequency transmission line paths in the radio 24 can be implemented without any front-end module disposed thereon.

[0032] The radio frequency transmission line paths 36 can be coupled to antenna feeds on the antennas 42. The antenna feeds may, for example, include a positive antenna feed terminal and a ground antenna feed terminal. The radio frequency transmission line paths 36 can have a positive transmission line signal path that is coupled to the positive antenna feed terminal on the antenna 42. The radio frequency transmission line paths 36 can have a ground transmission line signal path that is coupled to the ground antenna feed terminal on the antenna 42. This example is merely illustrative, and in general the antennas 42 can be fed using any desired antenna feed scheme. If desired, the antennas 42 can have multiple antenna feeds that are coupled to one or more radio frequency transmission line paths 36.

[0033] The radio frequency transmission line paths 36 can include transmission lines for routing radio frequency antenna signals within the device 10 Figure 1 The transmission lines in the device 10 may, for example, include coaxial cables, microstrip transmission lines, stripline transmission lines, edge-coupled microstrip transmission lines, edge-coupled stripline transmission lines, transmission lines formed from combinations of these types of transmission lines, etc. The transmission lines in the device 10, such as the transmission lines in the radio frequency transmission line paths 36, can be integrated into rigid and / or flexible printed circuit boards.

[0034] In performing wireless transmission, the baseband circuitry 26 can provide baseband signals to the transceiver 28 through the baseband path 34. The transceiver 28 can also include circuitry for converting baseband signals received from the baseband circuitry 26 into corresponding radio-frequency signals. For example, the transceiver circuitry 28 can include mixer circuitry for upconverting (or modulating) baseband signals into radio-frequency signals prior to transmission through the antenna 42. The transceiver circuitry 28 can also include digital-to-analog converter (DAC) circuitry and / or analog-to-digital converter (ADC) circuitry for converting signals between digital and analog domains. The transceiver 28 can transmit radio-frequency signals via the radio-frequency transmission line path 36 and the front-end module 40 through the antenna 42 using a transmitter (TX) 30. The antenna 42 can transmit radio-frequency signals to external wireless equipment by radiating the radio-frequency signals into free space.

[0035] In performing wireless reception, the antenna 42 can receive radio-frequency signals from external wireless equipment. The received radio-frequency signals can be passed via the radio-frequency transmission line path 36 and the front-end module 40 to the transceiver 28. The transceiver 28 can include circuitry for receiving signals from the front-end module 40 and for converting received radio-frequency signals into corresponding baseband signals, such as a receiver (RX) 32. For example, the transceiver 28 can include mixer circuitry for downconverting (or demodulating) received radio-frequency signals into baseband frequencies prior to passing the received signals through the baseband path 34 to the baseband circuitry 26.

[0036] The front-end module (FEM) 40 can include radio-frequency front-end circuitry that operates on radio-frequency signals passed (transmitted and / or received) through the radio-frequency transmission line path 36. For example, the FEM 40 can include front-end module (FEM) components such as radio-frequency filter circuitry 44 (e.g., low-pass filters, high-pass filters, notch filters, bandpass filters, multiplexing circuitry, duplexer circuitry, antenna sharing circuitry, triplexer circuitry, etc.), switching circuitry 46 (e.g., one or more radio-frequency switches), radio-frequency amplifier circuitry 48 (e.g., one or more power amplifier circuits 50 and / or one or more low-noise amplifier circuits 52), impedance matching circuitry (e.g., circuitry that helps match the impedance of the antenna 42 to the impedance of the radio-frequency transmission line 36), antenna tuning circuitry (e.g., a network of capacitors, resistors, inductors, and / or switches that adjust the frequency response of the antenna 42), radio-frequency coupler circuitry, charge pump circuitry, power management circuitry, digital control and interface circuitry, and / or any other desired circuitry that operates on radio-frequency signals transmitted and / or received by the antenna 42. Each of the front-end module components can be mounted to a common (shared) substrate, such as a rigid printed circuit board substrate or a flexible printed circuit substrate. If desired, the various front-end module components can also be integrated into a single integrated circuit chip.

[0037] Filter circuitry 44, switching circuitry 46, amplifier circuitry 48, and other circuitry can be disposed along the radio frequency transmission line path 36, can be incorporated into the FEM 40, and / or can be incorporated into the antenna 42 (e.g., to support antenna tuning, to support operation in a desired frequency band, etc.). These components (sometimes referred to herein as antenna tuning components) can be adjusted (e.g., using control circuitry 14) to adjust the frequency response and wireless performance of the antenna 42 over time.

[0038] The transceiver 28 can be separate from the front end module 40. For example, the transceiver 28 can be formed on another substrate, such as a main logic board, a rigid printed circuit board, or a flexible printed circuit of the device 10 that is not part of the front end module 40. Although shown as separate from the radio circuitry 24 for the sake of clarity, the radio circuitry 24 can include processing circuitry that forms part of the processing circuitry 18 and / or storage circuitry that forms part of the storage circuitry 16 of the control circuitry 14 (e.g., portions of the control circuitry 14 can be implemented on the radio circuitry 24). As one example, portions of the baseband circuitry 26 and / or the transceiver 28 (e.g., a host processor on the transceiver 28) can form part of the control circuitry 14. The control circuitry 14 (e.g., portions of the control circuitry 14 formed on the baseband circuitry 26, portions of the control circuitry 14 formed on the transceiver 28, and / or portions of the control circuitry 14 separate from the radio circuitry 24) can provide control signals that control operation of the front end module 40 (e.g., over one or more control paths in the device 10). Figure 1

[0039] The transceiver circuitry 28 can include wireless local area network transceiver circuitry that handles WLAN communication bands (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11) or other WLAN communication bands) such as a 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), a 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), a 6E band (e.g., 5925 MHz to 7125 MHz), and / or other WLAN bands (e.g., 1875 MHz to 5160 MHz). The transceiver circuitry 28 can include wireless local area network transceiver circuitry that handles WLAN communication bands (e.g., Institute of Electrical and Electronics Engineers (IEEE) 802.11) or other WLAN communication bands) such as a 2.4 GHz WLAN band (e.g., 2400 MHz to 2480 MHz), a 5 GHz WLAN band (e.g., 5180 MHz to 5825 MHz), a 6E band (e.g., 5925 MHz to 7125 MHz), and / or other WLAN bands (e.g., 1875 MHz to 5160 MHz). ​​​Wireless personal area network transceiver circuitry for a frequency band or other WPAN communication frequency band; cellular telephone transceiver circuitry for handling cellular telephone frequency bands (e.g., bands from about 600 MHz to about 5 GHz, 3G bands, 4G LTE bands, 5G New Radio Frequency Range 1 (FR1) bands below 10 GHz, 5G New Radio Frequency Range 2 (FR2) bands between 20 GHz and 60 GHz, etc.); near field communication (NFC) transceiver circuitry for handling near field communication frequency bands (e.g., 13.56 MHz); satellite navigation receiver circuitry for handling satellite navigation frequency bands (e.g., GPS bands from 1565 MHz to 1610 MHz, Global Navigation Satellite System (GLONASS) bands, BeiDou Satellite Navigation System (BDS) bands, etc.); ultra-wideband (UWB) transceiver circuitry for handling communications using IEEE 802.15.4 protocols and / or other ultra- wideband communication protocols; and / or any other desired radio frequency transceiver circuitry for covering any other desired frequency band of interest for communication.

[0040] Wireless circuitry 24 can include one or more antennas, such as antenna 42. Antenna 42 can be formed using any desired antenna structure. For example, antenna 42 can be an antenna with resonant elements formed from a loop antenna structure, a patch antenna structure, an inverted-F antenna structure, a slot antenna structure, a planar inverted-F antenna structure, a spiral antenna structure, a monopole, a dipole, a hybrid of these designs, etc. Two or more antennas 42 can be arranged into one or more phased antenna arrays (e.g., for transmitting radio frequency signals at millimeter wave frequencies). Parasitic elements can be included in antenna 42 to adjust antenna performance. Antenna 42 can be provided with a conductive cavity that supports antenna resonant elements of antenna 42 (e.g., antenna 42 can be a back cavity antenna, such as a back cavity slot antenna).

[0041] Figure 3 is an illustration of a differential circuit 60 such as can be part of wireless circuitry 24. Figure 3 Differential circuit 60 of can represent power amplifier 50 in a transmit path, a variable gain amplifier (VGA) in a transmit path, low noise amplifier 52 in a receive path, a mixer or modulator in a transmit path, a mixer or demodulator in a receive path, some other gain block in a transmit or receive path, front end module 40, or some other component in transceiver 28 or other component along transmission line path 36. Scenarios in which differential circuit 60 represents a radio frequency amplifier or mixer are sometimes described herein as examples. Thus, differential circuit 60 can sometimes be referred to as an amplifier or mixer circuit.

[0042] As Figure 3As shown, the differential circuit 60 can include at least transistors Ml and M2. The transistors Ml and M2 can be n-type (n-channel) transistors, such as n-type metal oxide semiconductor (NMOS) devices. The transistor Ml can have a source terminal coupled to a ground supply line 62 (e.g., a ground line that provides a ground supply voltage Vss), a drain terminal, and a gate terminal coupled to a first input terminal INl. The transistor M2 can have a source terminal coupled to the ground supply line 62, a drain terminal, and a gate terminal coupled to a second input terminal IN2. The input terminals INl and IN2 collectively function as a differential input port for the circuit 60. Thus, the transistors Ml and M2 are sometimes referred to as "input transistors." The terms "source" and "drain" terminals for referring to current carrying terminals in a transistor can be used interchangeably, and are sometimes referred to as "source-drain" terminals. Thus, the source terminal of the transistor Ml can sometimes be referred to as a first source-drain terminal, and the drain terminal of the transistor Ml can be referred to as a second source-drain terminal (or vice versa).

[0043] The drain terminal of the input transistor Ml can be coupled to a first output terminal OUTl, and the drain terminal of the input transistor M2 can be coupled to a second output terminal OUT2. The output terminals OUTl and OUT2 can collectively function as a differential output port for the differential circuit 60. A differential output voltage Vout can be provided across the output terminals OUTl and OUT2. In general, radio frequency signals can be provided or generated at the differential input port and / or the differential output port of the circuit 60. Thus, this type of circuit 60 is sometimes referred to as a radio frequency (RF) circuit.

[0044] If desired, the differential circuit 60 can optionally include cascode transistors coupled between the input transistors and the output terminals. For example, a first cascode transistor can be coupled in series between the input transistor Ml and the output terminal OUTl, and a second cascode transistor can be coupled in series between the input transistor M2 and the output terminal OUT2. Such cascode transistors (sometimes referred to as cascode amplifier stages) can be included to increase the output impedance of the circuit 60, and can optionally be used to provide different gain steps (e.g., by selectively adjusting the drive strength of the cascode transistors). In general, one or more transistors, capacitors, resistors, inductors, transformers, and / or other load components can be coupled to the output terminals OUTl and OUT2.

[0045] The performance of a radio frequency circuit is sometimes quantified by a parameter called the error vector magnitude (EVM). Ideally, a signal transmitted by a radio frequency circuit would have signal modulation constellation points located at certain ideal locations on a complex plane. However, due to design imperfections, distortions, parasitic signals, and / or noise, the actual constellation points typically deviate from these ideal locations. The error vector magnitude is a measure of the distance that the actual points deviate from the ideal locations.

[0046] Generally, a differential circuit such as an amplifier has a linear operating range and a non-linear operating range. To avoid signal distortion, an amplifier is typically operated in the linear range. When operated in the non-linear range, the ratio of input power to output power can not be constant. Thus, as the input signal amplitude increases, the output signal amplitude can increase disproportionately. This unwanted additional amplitude modulation due to the non-linear characteristics of the amplifier is sometimes referred to as amplitude modulation to amplitude modulation (AMAM) distortion. Similarly to the output signal amplitude, the output phase of the amplifier can vary disproportionately as the input signal amplitude increases. This unwanted additional amount of phase modulation due to the non-linear characteristics of the amplifier is sometimes referred to as amplitude modulation to phase modulation (AMPM) distortion. Generally, amplitude to amplitude (AMAM) distortion can occur due to undesired gain changes from the non-linear transistors’ transconductance (sometimes referred to as “Gm”) and output resistance (sometimes referred to as “Rout”) of the amplifier.

[0047] According to embodiments, the differential circuit 60 can be provided with a three (3rd) order non-linearity cancellation circuit, such as a third order non-linearity cancellation circuit 66 cross-coupled with the input transistors Ml and M2. In Figure 3 In embodiments of the differential circuit 60, the cancellation circuit 66 can include a third transistor M3, a fourth transistor M4, and a source resistor Rs. The transistor M3 can have a gate terminal coupled to the gate terminal of the input transistor Ml, a source terminal coupled to the tail node 68, and a drain terminal cross-coupled to the output terminal OUT2. The transistor M4 can have a gate terminal coupled to the gate terminal of the input transistor M2, a source terminal coupled to the tail node 68, and a drain terminal coupled to the output terminal OUTl. The source resistor Rs can be coupled between the tail node 68 shorted to the source terminals of the transistors M3 and M4 and the ground line 62. Additionally, the transistors M3 and M4 can exhibit parasitic gate-to-drain capacitances on the output terminals OUTl and OUT2 of the circuit 60. This gate-to-drain capacitance of the transistors M3 and M4 can optionally be configured to function as a capacitive neutralization capacitor for the circuit 60 and can help eliminate the need for a separate dedicated neutralization capacitor. This can help reduce circuit area and cost while preserving enhanced reverse isolation.

[0048] For example, the source resistor Rs can be an adjustable resistance. The adjustable resistance Rs can be tuned by a control voltage output from a source control circuit, such as the source controller 70. The adjustable resistance Rs can be implemented as a programmable resistance bank that can be adjusted to tune the strength of the third order non-linearity cancellation. The source controller 70 can be part of the control circuit 14 Figure 1 ), the transceiver circuit 28 Figure 2 , or the baseband circuit 26. The cancellation circuit 66 configured in this way can be configured to provide third order non-linearity cancellation (see, for example,Figure 4 ). As Figure 4 indicated, amplifier block 80 represents the amplification function of input transistors Ml and M2, while amplifier block 82 represents the amplification function of third order nonlinearity cancellation circuit 66. Consider a scenario in which a two-tone signal (see, e.g., signal 84 at angular frequencies wl and w2) is provided at the input of differential circuit 60.

[0049] Intermodulation distortion occurs when at least two signals of different frequencies are applied to a nonlinear circuit and when amplitude modulation or mixing (multiplication) of the two signals generates intermodulation products when the sum of the two signals rises to a power greater than one. The modulation products are not only at the harmonic frequencies (integer multiples) of the input signals, but also at the sums and differences of the input signal frequencies and also at the sums and differences of multiples of these frequencies. Here, input signal 85 fed through amplification block 80 can generate an inverted signal 86 at frequencies wl and w2, but also third order intermodulation (IM3) products at (2wl-w2) and (2w2-wl), as indicated by signal 88. If not careful, these IM3 signals 88 can degrade the signal of interest 86. In particular, if the difference between wl and w2 is relatively small, the IM3 components generated at (2wl-w2) and (2w2-wl) can appear near wl and w2, as Figure 3 indicated. The amplitude of these IM3 tones (see third order tones 88 appearing on either side of the two signal tones 86) directly leads to third order intermodulation distortion (IMD3).

[0050] In the example of Figure 4 , the nonlinearity cancellation circuit 66 can generate second order intermodulation terms (IM2). According to embodiments, when fed through amplification block 82 of circuit 66, the two signal tones 84 can mix with second order intermodulation (IM2) products 90 generated at frequency (w2-wl) to generate corresponding products 94 at frequencies (2wl-w2) and (2w2-wl). The original two-tone signal 84 at wl and w2 will produce a two-tone signal 92. The cross-coupling of transistors M3 and M4 with input transistors Ml and M2 is represented by cross-coupling block 96 in Figure 4 , and thus inverts the signals (see, e.g., inverted signals 92' and 94'). As Figure 4 indicated, the inverted products 94' can be fed to the output of circuit 60 for destructively canceling the IM3 products 88, and thus are sometimes referred to as third order intermodulation (IM3) cancellation signals. Thus, the third order nonlinearity cancellation circuit 66 is sometimes referred to as a linearization circuit or linearizer. Thus, a nonlinearity cancellation circuit can refer to and is defined herein as a circuit that at least partially cancels intermodulation signals, such as the IM3 terms produced from the input transistors. Thus, transistors M3 and M4 are sometimes referred to as nonlinearity cancellation transistors.

[0051] Referring back Figure 3 , an increase in the input power to the differential circuit 60 will generally increase the DC (direct current) current flowing through the source resistor Rs. Once the current flowing through the resistor Rs exceeds a certain threshold, the transistors M3 and M4 will turn off or be deactivated. Deactivating the transistors M3 and M4 at high input (or output) power levels helps to increase the gain of the circuit 60, as the cross-coupled transistors M3 and M4 generally drain current from the input transistors and thus help to improve the AMAM performance.

[0052] Figure 8 is a graph showing how the AMAM distortion can be reduced by employing the third-order nonlinearity cancellation circuit 66. Specifically, Figure 8 The normalized AMAM is plotted as a function of the difference between the gain at low power levels and the gain at operating power levels as a function of the input power level Pin. The curve 200 can represent the normalized AMAM distribution in the case where the third-order nonlinearity cancellation circuit 66 is completely inactive, while the curve 202 can represent the normalized AMAM distribution in the case where the third-order nonlinearity cancellation circuit 66 is active. As Figure 8 shown, the activation of the cancellation circuit 66 can help to reduce the gain compression at higher power levels, which improves the AMAM performance.

[0053] Referring back Figure 3 , the activation of the third-order nonlinearity cancellation circuit 66 can be accomplished without increasing the gate-to-source voltage Vgs of the main input transistors Ml and M2. At high input (or output) power levels, the gate-to-source capacitance Cgs of the input transistors Ml and M2 increases, while the gate-to-source capacitance Cgs of the cancellation transistors M3 and M4 decreases as they are turned off. Figure 5 An illustration of this phenomenon is shown. As Figure 5 shown, the curve 100 represents the Cgs of the input transistors Ml and M2, while the curve 102 represents the Cgs of the cancellation transistors M3 and M4. At high input power Pin levels, the curve 100 will slope up, while the curve 102 will roll down. This opposite behavior can result in a relatively constant net input capacitance even at high power levels, as shown by the curve 104, and thus helps to improve the AMPM performance.

[0054] Figure 9 is a graph showing how the AMPM distortion can be reduced by employing the third-order nonlinearity cancellation circuit 66. Specifically, Figure 9A normalized AMPM is plotted, which is a function of the difference between the phase at a low power level as a function of the input power level Pin and the phase at an operating power level. Curve 210 can represent the normalized AMPM profile in the case where the third-order nonlinearity cancellation circuit 66 is completely disabled, while curve 212 can represent the normalized AMPM profile in the case where the third-order nonlinearity cancellation circuit 66 is enabled. As shown, activation of the cancellation circuit 66 can help reduce phase compression at higher power levels, which improves the AMPM performance. Figure 9

[0055] where the tail component of the third-order nonlinearity cancellation circuit 66 is implemented as an adjustable source resistor Rs Figure 3 Embodiments of the Figure 6 Another embodiment of the differential circuit 60 is shown, where the cancellation circuit 66 includes a source transistor, such as source transistor 130. The source transistor 130 is sometimes referred to as a tail transistor. The tail transistor 130 can be an n-type transistor (e.g., an NMOS device) having a drain terminal coupled to the tail node 68, a source terminal coupled to the ground line 62, and a gate terminal configured to receive a control voltage Vc from a source controller 70. The tail transistor 130 can have the same structure (e.g., same channel type, channel length, threshold voltage, and / or other transistor characteristics) as the input transistors Ml and M2 to help track the first-order transconductance (Gm) of the main input path. For example, the source controller 70 can be implemented as a proportional to absolute temperature (PTAT) circuit configured to produce an output voltage or current that varies linearly with changes in absolute temperature. Implementing the source controller 70 as a PTAT circuit can help with temperature compensation.

[0056] In Figure 6 ​In the example of FIG. 1, the differential circuit 60 can optionally include capacitors 122 and 124. The capacitor 122 can be a first metal-oxide-semiconductor capacitor (MOSCAP) having a gate terminal coupled to the first input terminal IN1 and having a bulk terminal cross-coupled to a drain terminal of the second input transistor M2. The capacitor 124 can be a second MOSCAP having a gate terminal coupled to the second input terminal IN2 and having a bulk terminal cross-coupled to a drain terminal of the first input transistor M1. Configured in this way, the cross-coupled MOS capacitors 122 and 124 can function as dedicated capacitors for at least partially neutralizing gate-to-drain parasitic capacitances of the input transistors M1 and M2, and are therefore sometimes referred to as parasitic capacitance neutralization components. In other embodiments, the parasitic capacitance neutralization components can be implemented as cross-coupled transistors, metal-insulator-metal (MIM) capacitors, deep-trench capacitors, polysilicon capacitors, or other electronic devices that exhibit capacitance. The use of parasitic capacitance neutralization capacitors 122 and 124 is optional, and can be omitted to save cost.

[0057] The differential input port of the circuit 60 can be coupled to an input transformer, such as the input transformer 110. The input transformer 110 can have a primary coil, such as the primary coil (winding) 112, and a secondary coil, such as the secondary coil (winding) 114. The primary coil 112 can have a first terminal configured to receive an input signal (voltage) Vin and a second terminal coupled to the ground line 62. An input capacitance, such as the input capacitance Cin, can be shunted at the first terminal of the primary coil 112. The secondary coil 114 can have a first terminal coupled to the first input terminal IN1, a second terminal coupled to the second input terminal IN2, and a center tap terminal coupled to the ground line 62 via the resistor 116 and the capacitor 118. The first and second terminals of the coil 114 can be referred to as opposite or distal (coil) terminals. The transformer 110, having a single-ended input and a differential output, is sometimes referred to as a balun.

[0058] According to embodiments, a biasing circuit, such as the biasing circuit 120, can be coupled to the center tap terminal of the coil 114. In Figure 6In the example, bias circuit 120 can be configured to generate a bias voltage Vbias, which is applied to a node located between resistor 116 and capacitor 118. Coupled in this way to the common-mode center tap terminal of coil 114, bias voltage Vbias can be electrically coupled or delivered to the gate terminals of input transistors M1 and M2, and also electrically coupled or delivered to the gate terminals of elimination transistors M3 and M4 (e.g., the input transistors are biased by voltage Vbias). Bias circuit 120 can be implemented as a current mirror circuit or other types of bias voltage generator or voltage reference.

[0059] The tail component of the third-order nonlinear cancellation circuit 66 is implemented as a single tail transistor. Figure 6 The implementation scheme is exemplary. Figure 7 Another embodiment of circuit 60 is shown, wherein the third-order nonlinear cancellation circuit 66 has a tail component that is implemented as one or more programmable tail circuits 150. Figure 7 As shown, each programmable tail circuit 150 may include a plurality of stacked transistors 152 (e.g., two or more transistors 152 connected in series, three to five transistors connected in series, or more than five transistors 152 connected in series). Each tail transistor 152 may have the same structure as the input transistors M1 and M2 (e.g., the same channel type, channel length, threshold voltage, and / or other transistor characteristics) to help track the first-order transconductance (Gm) of the main input path. The transistors 152 may be n-type transistors or alternatively p-type transistors (e.g., if the input transistors M1 and M2 are instead implemented as p-type transistors). Stacking the tail transistors 152 in this manner can be technically advantageous and beneficial in helping to increase the temperature dependence (sensitivity) of each programmable tail circuit 150.

[0060] The plurality of programmable tail circuits 150 can be selectively activated (switched into use) and deactivated (switched out of use) by digital control signals Dc output from a source controller 160. The plurality of programmable tail circuits 150 are sometimes referred to as programmable tail (resistor) slices. The plurality of programmable tail circuits 150 can be coupled together in parallel. For example, the gate terminal of the stacked transistors 152 in each programmable tail circuit 150 can be selectively coupled to a voltage Vbias via a first switch 154, or can be selectively coupled to a ground line 62 via a second switch 156. The controller 160 can switch into use of a particular programmable tail circuit 150 by adjusting the control signals Dc to activate the switch 154 while deactivating the switch 156. The controller 160 can switch out of use of a particular programmable tail circuit 150 by adjusting the control signals Dc to deactivate the switch 154 while activating the switch 156 to turn off all of the tail transistors 152 in the slice. The control signals Dc can include different bits for controlling the switches 154 and 156. The controller 160 can optionally switch any portion (subset) or all of the programmable tail circuits 150 into use. Having multiple programmable tail slices allows for improved programmability of linearization with minimal impact or loading on differential mode operation of the circuit 60. The programmable tail circuits 150 can be set or configured once based on a calibration operation prior to normal operation.

[0061] In Figure 7 In an example, a bias circuit such as bias circuit 120 can be coupled to the center tap terminal of the coil 114. The bias circuit 120 can be configured to generate a bias voltage Vbias that is applied to a node disposed between the resistor 116 and the capacitor 118. Coupled in this way, the bias voltage Vbias can be electrically coupled to the gate terminals of the input transistors Ml and M2, and also to the gate terminals of the cancellation transistors M3 and M4 (e.g., the input transistors are biased by the voltage Vbias). The bias circuit 120 can be implemented as a current mirror circuit, as an example.

[0062] The bias voltage Vbias can also be selectively supplied to the gate terminal of the stacked tail transistor 152 via a feedforward path 290. The series switch 154 coupled at the gate of the tail transistor 152 can be considered to be disposed along the feedforward path 290. This feedforward path 290 forms a feedforward loop with the cancellation transistors M3 and M4 and the input transistors Ml and M2, where the feedforward loop is configured to sense the common mode input transistor bias voltage Vbias and provide the sensed voltage Vbias to the gate terminal of the tail transistor 152 to control the current flowing through the cancellation circuit 66. In other words, the bias voltage Vbias output from the bias circuit 120 can thus simultaneously bias the input transistors Ml and M2 (e.g., via the common mode center tap point of the input balun), the cancellation transistors M3 and M4, and also the stacked tail transistor 152 in one or more active tail circuits 150 (e.g., via the feedforward path 290). Having one common voltage Vbias for biasing the input transistors and tail transistors via the feedforward path 290 (forming a feedforward loop) is technically advantageous and beneficial to help enable the tail transistor 152 to mimic the PVT variability of the input transistors, thus improving linear tracking across PVT conditions without dedicated trimming.

[0063] Figure 10 is a plot showing how the third order intercept point can be improved by the third order cancellation circuit 66. Specifically, Figure 10 The "output" third order intercept point or OIP3 is plotted, which is a parameter used to characterize the linearity of an electronic circuit such as the differential circuit 60. The output 3rd order intercept point can represent an output power level Pout at which the third order intermodulation products generated by the circuit 60 reach the same level as the desired output signal in a two-tone scenario. In general, it is desirable to increase the OIP3. As Figure 10 shown, the curve 220 represents the OIP3 profile of the circuit 60 when the cancellation circuit 66 is deactivated or omitted. In contrast, the curve 222 represents the OIP3 profile of the differential circuit 60 when the cancellation circuit 66 has been activated or switched into use. The curve 222 exhibits improved or higher OIP3 levels compared to the curve 220. Although Figure 10 OIP3 is shown, a similar improvement can be realized when plotting the "input" third order intercept point (IIP3) of the differential circuit 60 (e.g., by selectively activating one or more of the programmable slices 150 in Figure 7 .

[0064] The above in connection with Figures 1 to 10The described methods and operations can be performed by components of device 10 using software, firmware, and / or hardware (e.g., dedicated circuitry or hardware). The software code for performing these operations can be stored on a non-transitory computer-readable storage medium (e.g., a tangible computer-readable storage medium) stored on one or more components of device 10 (e.g., ...). Figure 1 The storage circuitry 16 and / or wireless communication circuitry system 24). This software code may sometimes be referred to as software, data, instructions, program instructions, or code. Non-transitory computer-readable storage media may include drives, non-volatile memory such as non-volatile random access memory (NVRAM), removable flash drives or other removable media, other types of random access memory, etc. The software stored on the non-transitory computer-readable storage medium may be processed by processing circuitry on one or more components of device 10 (e.g., processing circuitry in wireless communication circuitry system 24, ...). Figure 1 The processing circuitry (e.g., 18) executes the operation. This processing circuitry may include a microprocessor, application processor, digital signal processor, central processing unit (CPU), application-specific integrated circuit (ASIC) with processing circuitry, or other processing circuitry.

[0065] According to an embodiment, a circuit system is provided, comprising: a first input transistor and a second input transistor; a third transistor having a gate terminal coupled to a gate terminal of the first input transistor and a drain terminal coupled to the second input transistor; a fourth transistor having a gate terminal coupled to a gate terminal of the second input transistor and a drain terminal coupled to the first input transistor; one or more tail circuits coupled to source terminals of the third transistor and the fourth transistor; and a bias circuit configured to output a bias voltage, the bias voltage being delivered to the gate terminals of the first input transistor and the second input transistor and the one or more tail circuits.

[0066] According to another embodiment, the circuit optionally includes a control circuit configured to output a control signal for selectively activating and deactivating the one or more tail circuits.

[0067] According to another embodiment, at least one of the one or more tail circuits optionally includes a plurality of tail transistors coupled in series between the source terminals of the third transistor and the fourth transistor and the power supply line.

[0068] According to another embodiment, the at least one of the one or more tail circuits optionally includes a first switch coupled between the bias circuit and a gate terminal of the plurality of tail transistors and configured to receive the control signal.

[0069] According to another embodiment, the at least one of the one or more tail circuits optionally includes a second switch coupled between the gate terminal of the plurality of tail transistors and the power supply line and configured to receive the control signal.

[0070] According to another embodiment, the circuit optionally includes a coil having a first terminal coupled to the gate terminal of the first input transistor, a second terminal coupled to the gate terminal of the second input transistor, and a center tap terminal configured to receive the bias voltage.

[0071] According to another embodiment, the circuit optionally includes a resistor having a first terminal coupled to the center tap terminal of the coil and having a second terminal; and a capacitor having a first terminal coupled to the second terminal of the resistor and having a second terminal coupled to a power supply line.

[0072] According to another embodiment, the bias circuit is optionally coupled to a node disposed between the resistor and the capacitor.

[0073] According to another embodiment, the node disposed between the resistor and the capacitor is optionally coupled to the one or more tail circuits via a feedforward path.

[0074] According to another embodiment, the circuit optionally includes a first metal oxide semiconductor capacitor coupled between the gate terminal of the first input transistor and the drain terminal of the third transistor; and a second metal oxide semiconductor capacitor coupled between the gate terminal of the second input transistor and the drain terminal of the fourth transistor.

[0075] According to an embodiment, there is provided a circuitry comprising a first input transistor; a second input transistor; and a non-linear cancellation circuit cross-coupled to the first input transistor and the second input transistor and having a plurality of programmable tail circuits, wherein the non-linear cancellation circuit is configured to at least partially cancel intermodulation signals generated from the first input transistor and the second input transistor.

[0076] According to another embodiment, the non-linear cancellation circuit optionally includes a third transistor having a gate terminal coupled to a gate terminal of the first input transistor, and having a drain terminal coupled to a drain terminal of the second input transistor; and a fourth transistor having a gate terminal coupled to a gate terminal of the second input transistor, and having a drain terminal coupled to a drain terminal of the first input transistor.

[0077] According to another embodiment, the circuit optionally includes a biasing circuit configured to output a bias voltage that biases the first input transistor and the second input transistor, and that biases at least one programmable tail circuit of the plurality of programmable tail circuits.

[0078] According to another embodiment, the at least one programmable tail circuit optionally includes a plurality of tail transistors that are coupled in series, and that have gate terminals shorted to one another.

[0079] According to another embodiment, the circuit optionally includes a coil having a first terminal coupled to a gate terminal of the first input transistor, a second terminal coupled to a gate terminal of the second input transistor, and a center tap terminal configured to receive the bias voltage.

[0080] According to another embodiment, the center tap terminal of the coil is optionally coupled to the gate terminals of the plurality of tail transistors via a feedforward path.

[0081] According to another embodiment, the circuit optionally includes a switch disposed along the feedforward path; and a controller configured to activate or deactivate the switch.

[0082] According to an embodiment, there is provided a circuitry including an input transistor; a non-linear cancellation transistor cross-coupled to the input transistor; a tail transistor coupled to a source terminal of the non-linear cancellation transistor; and a feedforward path having a first terminal coupled to a common mode voltage for biasing the input transistor, and having a second terminal coupled to the tail transistor.

[0083] According to another embodiment, the circuit optionally includes a coil having opposite terminals coupled to the input transistor, and having a center tap terminal coupled to the tail transistor via the feedforward path.

[0084] According to another embodiment, the circuit optionally includes a biasing circuit having the center tap terminal coupled to the coil and coupled to an output of the feed forward path.

[0085] The foregoing is merely illustrative and various modifications can be made to the described embodiments. The foregoing embodiments can be implemented individually or in any combination.

[0086] It is well understood that, in accordance with 47 U.S.C. § 230, no representation or warranty is made that the use of personal identifiable information will not infringe the rights of third parties. It is the responsibility of the user to determine that their use of the personal identifiable information is consistent with applicable law, including Privacy Policies and Practices that are recognized as meeting or exceeding industry or governmental requirements for maintaining the privacy of users.

Claims

1. Circuitry comprising: a first input transistor and a second input transistor; a third transistor having a gate terminal coupled to a gate terminal of the first input transistor and having a drain terminal coupled to a drain terminal of the second input transistor; a fourth transistor having a gate terminal coupled to a gate terminal of the second input transistor and having a drain terminal coupled to a drain terminal of the first input transistor; one or more tail circuits coupled to source terminals of the third transistor and the fourth transistor; and a biasing circuit configured to output a bias voltage delivered to the gate terminals of the first input transistor and the second input transistor and to the one or more tail circuits.

2. The circuitry of claim 1, further comprising: a control circuit configured to output a control signal for selectively activating and deactivating the one or more tail circuits.

3. The circuitry of claim 2, wherein at least one of the one or more tail circuits comprises: a plurality of tail transistors coupled in series between the source terminals of the third transistor and the fourth transistor and a power supply line.

4. The circuitry of claim 3, wherein the at least one of the one or more tail circuits further comprises: a first switch coupled between the biasing circuit and a gate terminal of the plurality of tail transistors and configured to receive the control signal.

5. The circuitry of claim 4, wherein the at least one of the one or more tail circuits further comprises: a second switch coupled between the gate terminal of the plurality of tail transistors and the power supply line and configured to receive the control signal.

6. The circuitry of claim 1, further comprising: a coil having a first terminal coupled to the gate terminal of the first input transistor, a second terminal coupled to the gate terminal of the second input transistor, and a center tap terminal configured to receive the bias voltage.

7. The circuitry of claim 6, further comprising: a resistor having a first terminal coupled to the center tap terminal of the coil and having a second terminal; and a capacitor having a first terminal coupled to the second terminal of the resistor and having a second terminal coupled to a power supply line.

8. The circuitry of claim 7, wherein the biasing circuit is coupled to a node disposed between the resistor and the capacitor.

9. The circuitry of claim 8, wherein the node disposed between the resistor and the capacitor is coupled to the one or more tail circuits via a feed-forward path.

10. The circuitry of claim 1, further comprising: ​ ​ a first metal oxide semiconductor capacitor coupled between the gate terminal of the first input transistor and the drain terminal of the third transistor; and a second metal oxide semiconductor capacitor coupled between the gate terminal of the second input transistor and the drain terminal of the fourth transistor.

11. Circuitry comprising: a first input transistor; a second input transistor; and a non-linear cancellation circuit cross-coupled to the first input transistor and the second input transistor and having a plurality of programmable tail circuits, wherein the non-linear cancellation circuit is configured to at least partially cancel intermodulation signals generated from the first input transistor and the second input transistor.

12. The circuitry of claim 11, wherein the non-linear cancellation circuit comprises: a third transistor having a gate terminal coupled to a gate terminal of the first input transistor and having a drain terminal coupled to a drain terminal of the second input transistor; and a fourth transistor having a gate terminal coupled to a gate terminal of the second input transistor and having a drain terminal coupled to a drain terminal of the first input transistor.

13. The circuitry of claim 11, further comprising: a biasing circuit configured to output a bias voltage that biases the first input transistor and the second input transistor and biases at least one programmable tail circuit of the plurality of programmable tail circuits.

14. The circuitry of claim 13, wherein the at least one programmable tail circuit comprises: a plurality of tail transistors coupled in series and having gate terminals shorted to one another.

15. The circuitry of claim 14, further comprising: a coil having a first terminal coupled to a gate terminal of the first input transistor, a second terminal coupled to a gate terminal of the second input transistor, and a center tap terminal configured to receive the bias voltage.

16. The circuitry of claim 15, wherein the center tap terminal of the coil is coupled to the gate terminals of the plurality of tail transistors via a feedforward path.

17. The circuitry of claim 16, further comprising: a switch disposed along the feedforward path; and a controller configured to activate or deactivate the switch.

18. Circuitry comprising: an input transistor; a non-linear cancellation transistor cross-coupled to the input transistor; a tail transistor coupled to a source terminal of the non-linear cancellation transistor; and a feedforward path having a first terminal coupled to a common mode voltage used to bias the input transistor and having a second terminal coupled to the tail transistor.

19. The circuitry of claim 18, further comprising: a coil having opposite terminals coupled to the input transistor and having a center tap terminal coupled to the tail transistor via the feedforward path.

20. The circuitry of claim 19, further comprising: a biasing circuit having the center tap terminal coupled to the coil and coupled to an output of the feedforward path.

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