Fractional-N phase-locked loop system and control method thereof

Abstract

The invention provides a decimal-N phase-locked loop system and a control method thereof. In the decimal-N phase-locked loop system, a plurality of phase frequency detectors are arranged, a charge pump module directly coupled to the plurality of phase frequency detectors is arranged, the charge pump module comprises a current circuit with M bits, and the proportion of the magnitude of current generated by performing phase frequency detection on different phase frequency detectors corresponding to the charge pump module is controlled. The step length for realizing the fractional frequency division ratio is used for realizing frequency division; wherein Y represents an integer frequency division ratio, Z represents a decimal frequency division ratio, and Z is less than M. Fractional frequency division can be achieved without a complex circuit, phase noise can be reduced without arranging a calibration circuit, and the overall area and consumption of the circuit are reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of circuit technology, in particular to a fractional-N phase-locked loop system and a control method thereof. BACKGROUND

[0002] In any communication application, a clock signal can be needed. Such a signal can be generated from a reference clock using a phase-locked loop (PLL). The relationship between the frequency of the reference clock and the frequency of the output clock of the phase-locked loop can be determined by the division ratio of a divider in the feedback path of the phase-locked loop. In an integer-N phase-locked loop, the frequency of the output clock is an integer multiple of the frequency of the reference clock. In such a phase-locked loop, the resolution of the frequency of the output clock can be limited to N times the resolution of the frequency of the reference clock.

[0003] In some applications, it can be desirable to achieve a finer resolution. A fractional-N phase-locked loop can be employed so that the frequency of the output clock can be a non-integer multiple of the frequency of the reference clock. However, current fractional-N phase-locked loops directly or indirectly introduce phase noise (e.g. in-band phase noise and / or out-of-band phase noise). In order to reduce the phase noise, a corresponding calibration circuit is usually set up, thereby increasing the overall area and power consumption of the circuit. SUMMARY

[0004] It is an object of the present application to provide a fractional-N phase-locked loop system and a control method thereof to reduce the overall phase noise of the fractional-N phase-locked loop with lower hardware consumption.

[0005] To achieve the above object, the present application is implemented by the following technical solutions:

[0006] A fractional-N phase-locked loop system, comprising: a charge pump module, a low-pass filter, a voltage-controlled oscillator, a divider module, and a frequency discriminator; wherein,

[0007] The divider module is configured to receive an integer division ratio signal and a fractional division ratio signal, divide the output clock signal output by the voltage-controlled oscillator, and output X different division clock signals and a charge pump module control signal n i corresponding to the X different division clock signals;

[0008] X frequency discriminators, each configured to receive the X different division clock signals one by one and generate a corresponding charge and discharge control signal according to a reference clock signal;

[0009] The charge pump module comprises an M-bit current circuit configured to generate a corresponding current signal according to the charge pump module control signal n i and the charge and discharge control signal, and the charge pump module control signal n iThe control charge pump module matches the ratio of the current size generated by different frequency and phase detectors;

[0010] The low pass filter is used to charge and discharge according to the current signal to generate a control voltage;

[0011] The voltage controlled oscillator is used to generate the output clock signal according to the control voltage;

[0012] Wherein, 2≤X, and 2≤M, i is an integer and 0≤iX, n i is an integer and 0≤n i <M.

[0013] Optionally, the X different frequency division clock signals are sequentially delayed by one or more oscillation periods.

[0014] Optionally, the X=2, and the difference between the two different frequency division clock signals is one oscillation period.

[0015] Optionally, the frequency divider module includes a multi-mode frequency divider and a fractional frequency control module;

[0016] The multi-mode frequency divider is used to divide the output clock signal of the voltage controlled oscillator by div_int(Y) or div_int(Y+1) to obtain an initial frequency division clock signal, wherein div_int represents an integer frequency division ratio, and Y represents a frequency division ratio value;

[0017] The fractional frequency control module is used to process the initial frequency division clock signal to generate the X frequency division clock signals, and generate the charge pump module control signal and a clock selection signal according to a fractional frequency division ratio signal, wherein the clock selection signal is used to control the multi-mode frequency divider to divide by div_int(Y) or div_int(Y+1).

[0018] Optionally, the fractional frequency control module includes an accumulator, and the accumulator uses the accumulated sum value of the fractional frequency division ratio div_frac(Z) as the charge pump module control signal n i , and the carry signal as the clock selection signal; wherein div_frac represents a fractional frequency division ratio, Z represents a fractional frequency division ratio value, Z takes a value greater than zero and less than the current circuit bit number M of the charge pump module, and Z is an integer.

[0019] Optionally, when the clock selection signal is 1, the multi-mode frequency divider divides by div_int(Y+1); and when the clock selection signal is 0, the multi-mode frequency divider divides by div_int(Y).

[0020] Optionally, when the summation value of the accumulator is less than M, the carry signal remains at 0.

[0021] When the summation value of the accumulator is greater than or equal to M, the carry signal turns to 1, and at this time the summation value overflows. The overflowed summation value is equal to the summation value of the accumulator divided by M and the remainder is taken.

[0022] Optionally, the maximum total current that the charge pump module can output is I. CP ;

[0023] The control signal n corresponding to the same charge pump module i The magnitude I of the current signal corresponding to the j-th of the X frequency and phase detectors Cpj satisfy Furthermore, the charge / discharge control signal determines whether the corresponding current signal is a charging current or a discharging current, where 1≤j≤X.

[0024] Optionally, when X=2, the charge pump module control signal n i Under the control of [the preceding frequency division clock signal], the magnitude I of the current signal corresponding to the frequency discriminator and phase detector controlled by the preceding frequency division clock signal is [the following]. CP1 Satisfy I CP1 =(Mn i )*I CP / M, the magnitude I of the current signal corresponding to the frequency and phase detector controlled by the subsequent frequency division clock signal. CP2 Satisfy I CP2 =n i *I CP / M.

[0025] Optionally, the step size of the fractional frequency division ratio can be adjusted by adjusting the number of bits M in the current circuit of the charge pump module, wherein the step size of the fractional frequency division ratio is...

[0026] A control method for a fractional-N phase-locked loop (PLL) system includes multiple frequency and phase detectors within the system, and a charge pump module with an M-bit current circuit directly coupled to these detectors. The method controls the proportion of current generated by the charge pump module for different frequency and phase detectors, thereby achieving a fractional frequency division ratio step size. To achieve Frequency division; where Y represents the integer frequency division ratio, Z represents the fractional frequency division ratio, and Z < M.

[0027] Optionally, the method can be implemented using a fractional-N phase-locked loop system as described above.

[0028] Compared with the prior art, the present invention has the following advantages:

[0029] The application provides a fractional-N phase-locked loop system and a control method thereof, wherein a plurality of frequency and phase detectors are arranged, and a charge pump module directly coupled to the plurality of frequency and phase detectors includes an M-bit current circuit, and by controlling the charge pump module to generate a current with a proportion corresponding to different frequency and phase detectors, a step of a fractional frequency division ratio is realized as to realize frequency division. The application can realize fractional frequency division without complex circuits, and does not need to arrange a calibration circuit to reduce phase noise, thereby reducing the overall area and consumption of the circuit. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions of the application, the drawings needed to be used in the description will be briefly introduced as follows. Obviously, the drawings in the following description are one embodiment of the application, and other drawings can be obtained by those skilled in the art without creative labor on the basis of the drawings:

[0031] Figure 1 A structure diagram of a fractional-N phase-locked loop system provided by one embodiment of the application;

[0032] Figure 2 A structure diagram of a frequency divider module provided by one embodiment of the application;

[0033] Figure 3 A timing diagram of the frequency divider module;

[0034] Figure 4 A circuit diagram of a charge pump module;

[0035] Figures 5 to 8 Timing diagrams of four embodiments, respectively. DETAILED DESCRIPTION

[0036] The technical solutions of the application will be further described in detail below in combination with the drawings and specific embodiments. According to the following description, the advantages and characteristics of the application will be more apparent. It should be noted that the drawings are greatly simplified and all use non-precise proportions, and are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the application. In order to make the purpose, characteristics and advantages of the application more apparent and easy to understand, please refer to the drawings. It should be noted that the structures, proportions, sizes, etc. shown in the drawings attached to the specification are only used to understand and read by those skilled in the art, and are not used to limit the conditions of the implementation of the application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, without affecting the effect and purpose that can be achieved by the application, should still fall within the scope of the technical content disclosed by the application.

[0037] To achieve non-integer multiple frequency division in existing fractional-N phase-locked loop (PLL) systems, one approach is to continuously switch the division ratio (e.g., 4, 3, 3, 3…) to ensure the average division ratio is a decimal (e.g., 3.25). However, this approach introduces phase noise (the control voltage Vctrl of the voltage-controlled oscillator briefly stabilizes at a certain value), requiring additional circuitry to reduce this noise. Another approach uses multiple frequency dividers, phase and frequency detectors, and charge pumps to simultaneously control the loop. During each phase detection, the average division ratio of each divider is a decimal (e.g., 3.25). While this approach reduces phase noise to some extent, it results in complex circuitry and high hardware consumption.

[0038] Based on this, the present invention provides a control method for a fractional-N phase-locked loop (PLL) system. In the PLL system, multiple frequency and phase detectors are configured, and a charge pump module, including an M-bit current circuit, is directly coupled to these detectors. By controlling the proportion of current generated by the charge pump module corresponding to different frequency and phase detectors, the step size of the fractional frequency division ratio is achieved. To achieve Frequency division; where Y represents the integer frequency division ratio, Z represents the fractional frequency division ratio, and Z < M.

[0039] This invention achieves fractional frequency division without complex circuitry, and eliminates the need for calibration circuitry to reduce phase noise, thereby reducing the overall circuit area and power consumption.

[0040] The fractional-N phase-locked loop system used to implement the above control method will be described in detail below.

[0041] An embodiment of the present invention provides a fractional-N phase-locked loop system, such as... Figure 1 As shown, it includes: a charge pump module 10, a low-pass filter 20, a voltage-controlled oscillator 30, a frequency divider module 40, and a frequency and phase detector 50.

[0042] Frequency divider module 40 receives the integer division ratio signal div_int and the fractional division ratio signal div_frac, divides the output clock signal pll_clk from voltage-controlled oscillator 30, and outputs X different divided clock signals div_clk, along with corresponding charge pump module control signals n that match the X different divided clock signals. i . Figure 1 The example only shows two frequency-divided clock signals, div_clk_lead and div_clk_lag. In other embodiments, more than two frequency-divided clock signals may be generated.

[0043] X frequency detectors 50, each receiving one of the X different divided clock signals div_clk and generating a corresponding charge-discharge control signal based on a reference clock signal ref_clk. The reference clock signal ref_clk can be provided by a crystal oscillator (not shown).

[0044] The charge pump module 10 comprises a M-bit current circuit for generating a corresponding current signal based on the charge pump module control signal n i and the charge-discharge control signal, and the charge pump module control signal n i controls the charge pump module 10 to match the proportion of the current generated by different frequency detectors 50.

[0045] The low pass filter 20 is used to charge and discharge based on the current signal to generate a control voltage Vctrl.

[0046] The voltage controlled oscillator 30 is used to generate the output clock signal pll_clk based on the control voltage Vctrl, and the frequency of the output clock signal pll_clk can be determined by the control voltage.

[0047] wherein 2≤X, and 2≤M, i is an integer and 0≤iX, n i is an integer and 0≤n i <M.

[0048] In this embodiment, the frequency divider module 40 is controlled by an integer division ratio signal div_int and a fractional division ratio signal div_frac to divide the output clock signal pll_clk output by the voltage controlled oscillator 30. The frequency divider module 40 finally outputs at least two divided clock signals div_clk and corresponding charge pump module control signals n i . The at least two divided clock signals div_clk can be sequentially delayed by one or more oscillation periods Tvco, and each of the divided clock signals div_clk is output to one of the frequency detectors 50, and the charge pump module control signals n i are output to the charge pump module 10.

[0049] As Figure 2As shown, the frequency divider module 40 comprises a multi-modulus frequency divider 41 and a fractional frequency control module 42. The multi-modulus frequency divider 41 is used to divide the output clock signal pll_clk of the voltage-controlled oscillator 30 by div_int(Y) or div_int(Y+1) to obtain an initial frequency-divided clock signal mmd_clk, wherein div_int represents an integer frequency division ratio, Y represents a frequency division ratio value; the fractional frequency control module 42 is used to process the initial frequency-divided clock signal mmd_clk to generate the X frequency-divided clock signals div_clk, and generate the charge pump module control signal n i and a clock selection signal clk_sel, which is used to control the multi-modulus frequency divider 41 to divide by div_int(Y) or div_int(Y+1).

[0050] In this embodiment, the initial frequency-divided clock signal mmd_clk is processed by the fractional frequency control module 42 to output two frequency-divided clock signals div_clk_lead and div_clk_lag, which have the same frequency as the signal mmd_clk, and div_clk_lead leads div_clk_lag by one oscillation period Tvco in time.

[0051] In an embodiment, the fractional frequency control module 42 comprises an accumulator, and the sum value after the fractional frequency ratio div_frac(Z) is accumulated by the accumulator is used as the charge pump module control signal n i , and the carry signal is used as the clock selection signal clk_sel; wherein div_frac represents a fractional frequency ratio, Z represents a fractional frequency ratio value, Z takes a value greater than zero and less than the current circuit bit number M of the charge pump module 10, and Z is an integer.

[0052] Figure 3 The timing diagram for implementing the fractional frequency control module 42 with an accumulator is shown. Since the timing diagram is long, it is divided into two parts, as shown in (a) and (b) of FIG. 6. Figure 3 In the initial state, the charge pump module control signal n i [0] = 0, and the carry signal (i.e., the clock selection signal clk_sel in the figure) is 1. The accumulator performs operation for the first time, and the sum value n i [1] after the fractional frequency ratio div_frac(Z) is accumulated is n i[0] + div_frac(Z), the sum is less than M (M is used to determine the step of the fractional division ratio), at this time the carry signal is 0. The accumulator performs the second operation, and the sum n i [2] = n i [1] + div_frac(Z), the sum is also less than M, at this time the carry signal remains 0. In this way, the accumulator continues to perform n i [k] = n i [k-1] + div_frac(Z) accumulations, when the kth operation is performed, the sum n i [k] = n i [k-1] + div_frac(Z) ≥ M, at this time the carry signal turns to 1, and the sum n i [k] overflows, and the sum after overflow is equal to the remainder of the value divided by M, i.e. n i [k] = MOD(n i [k-1] + div_frac(Z), M). Then the process continues to loop.

[0053] In this embodiment, when the clock selection signal clk_sel is 1, the multi-mode frequency divider 41 performs div_int(Y+1) division, i.e. the X frequency-divided clock signals div_clk are div_int(Y+1) frequency-divided clock signals of the output clock signal pll_clk; when the clock selection signal clk_sel is 0, the multi-mode frequency divider 41 performs div_int(Y) division, i.e. the X frequency-divided clock signals div_clk are div_int(Y) frequency-divided clock signals of the output clock signal pll_clk.

[0054] The fractional frequency control module 42 generates a charge pump module control signal n i The process of the clock selection signal clk_sel and the fractional frequency control module control signal n

[0055] The frequency and phase detector 50 monitors the frequency and phase of the frequency-divided clock signal div_clk and the reference clock signal ref_clk, detects the phase difference and frequency difference therebetween, and outputs the up and down signals according to whether the frequency-divided clock signal div_clk lags or leads the reference clock signal ref_clk in frequency or phase, to generate the charge and discharge control signal (up, down).

[0056] The charge pump module 10 is controlled by the charge and discharge control signal (up, down) and the charge pump module control signal n iThis controls the output current of the charge pump module 10. Assume the maximum total current that the charge pump module 10 can output is I. CP The corresponding control signal n of the same charge pump module i Let the magnitude of the current signal corresponding to the j-th frequency discriminator 50 in the X frequency and phase discriminators 50 be I. Cpj The sum of the current signals corresponding to all frequency and phase detectors 50 is equal to the maximum total current that the charge pump module 10 can output, i.e. Where 1≤j≤X. The charge / discharge control signal (up,down) determines whether the corresponding current signal is a charging current or a discharging current.

[0057] Taking X=2, i.e., the frequency divider module 40 outputs two different frequency-divided clock signals div_clk, as an example, in the charge pump module control signal n i Under the control of the frequency divider clock signal, the magnitude I of the current signal corresponding to the frequency discriminator 50 controlled by the previous frequency divider clock signal is determined. CP1 Satisfy I CP1 =(Mn i )*I CP / M, the magnitude I of the current signal corresponding to the frequency discriminator 50 controlled by the subsequent frequency division clock signal. CP2 Satisfy I CP2 =n i *I CP / M. For example... Figure 1 and Figure 4 As shown, the preceding clock signal is div_clk_lead, and the following clock signal is div_clk_lag. div_clk_lead controls the output of the frequency and phase detector, which outputs charge / discharge control signals (up_lead, down_lead), while div_clk_lag controls the output of the frequency and phase detector, which outputs charge / discharge control signals (up_lag, down_lag). When up_lead is high and down_lead is low, I... CP1 =+(Mn i )*I CP / M, at this time, the low-pass filter 20 is charged; when up_lead is low and down_lead is high, I CP1 =-(Mn i )*I CP / M, at this time, the low-pass filter is discharged. When up_lag is high and down_lag is low, I CP2 =+n i *I CP / M, at this time the low-pass filter is charged; when up_lag is low and down_lag is high, I CP2 =-ni I CP / 2, I

[0058] From the above, the value of the current circuit bit number M of the charge pump module 10 determines the step of the fractional division ratio. Therefore, the step of the fractional division ratio can be adjusted by adjusting the size of M, and the step of the fractional division ratio is

[0059] The fractional-N phase-locked loop system of the present application is described below in four embodiments.

[0060] Embodiment 1

[0061] In this embodiment, M=2 is set, the fractional division ratio value Z=1, and the frequency divider module outputs two divided clock signals div_clk_lead and div_clk_lag.

[0062] As shown in the timing diagram of Figure 5 , the n i counter is incremented by 1 (Z=1), and when n i =1, I CP1 is the current size, I CP / 2, and when n CP2 =0, I CP is the current size, I i / 2. CP1 CP CP2

[0063] When n i does not overflow, i.e., n i <M, clk_sel=0, at this time, div_int(Y) is divided, and then div_clk_lead and div_clk_lag are the div_int(Y) division of the output clock signal pll_clk, and when n i overflows, i.e., n i ≥M, clk_sel=1, at this time, div_int(Y+1) is divided, and then div_clk_lead and div_clk_lag are the div_int(Y+1) division of the output clock signal pll_clk.

[0064] According to the above process, 2*Tref=(2*Y+1)*Tvco, where Tref is the period of the reference clock signal ref_clk, and after rearranging, we get The output clock signal pll_clk is the division of the reference clock signal ref_clk. ​​​

[0065] Embodiment 2

[0066] In this embodiment, M=4 is set, fractional frequency ratio Z=1, and the frequency divider module outputs two frequency-divided clock signals div_clk_lead and div_clk_lag.

[0067] As shown in the timing diagram shown in FIG. 3, n Figure 6 div_clk_lag is taken as the synchronous clock, and n i is accumulated by 1 (Z=1), when n i =1, I CP1 current has a size of 3*I CP / 4, I CP2 current has a size of I CP / 4, when n i =2, I CP1 current has a size of 2*I CP / 4, I CP2 current has a size of 2*I CP / 4, when n i =3, I CP1 current has a size of I CP / 4, I CP2 current has a size of 3*I CP / 4, when n i =0, I CP1 current has a size of I CP , I CP2 current has a size of 0.

[0068] When n i has no overflow, i.e., n i <M, clk_sel=0, at this time, div_int(Y) frequency division is performed, and div_clk_lead and div_clk_lag are div_int(Y) frequency-divided output clock signals pll_clk, when n i has overflow, i.e., n i ≥M, clk_sel=1, at this time, div_int(Y+1) frequency division is performed, and div_clk_lead and div_clk_lag are div_int(Y+1) frequency-divided output clock signals pll_clk.

[0069] According to the above process, 4*Tref=(4*Y+1)*Tvco, wherein Tref is the period of the reference clock signal ref_clk, and after rearrangement, 4*Tref=(4*Y+1)*Tvco is obtained. The output clock signal pll_clk is frequency-divided by the reference clock signal ref_clk.

[0070] Embodiment 3 ​

[0071] In this embodiment, M=4 is set, and the fractional frequency division ratio Z=2, and the frequency divider module outputs two frequency division clock signals div_clk_lead and div_clk_lag.

[0072] As shown in the timing diagram shown in Figure 7 , the n i cumulative 2 (Z=2), when n i =2, I CP1 current size is 2*I CP / 4, I CP2 current size is 2*I CP / 4, when n i =0, I CP1 current size is I CP , I CP2 current size is 0.

[0073] When n i no overflow, that is, n i <M, clk_sel=0, at this time, div_int(Y) frequency division is performed, and div_clk_lead and div_clk_lag are div_int(Y) frequency division of the output clock signal pll_clk, when n i overflow, that is, n i ≥M, clk_sel=1, at this time, div_int(Y+1) frequency division is performed, and div_clk_lead and div_clk_lag are div_int(Y+1) frequency division of the output clock signal pll_clk.

[0074] According to the above process, 2*Tref=(2*Y+1)*Tvco, wherein Tref is the period of the reference clock signal ref_clk, and after arrangement, 2*Tref=(2*Y+1)*Tvco is obtained The output clock signal pll_clk is realized frequency division of the reference clock signal ref_clk.

[0075] Embodiment 4

[0076] In this embodiment, M=4 is set, and the fractional frequency division ratio Z=3, and the frequency divider module outputs two frequency division clock signals div_clk_lead and div_clk_lag.

[0077] As shown in the timing diagram shown in Figure 8 , the n i cumulative 3 (Z=3), when n i =1, I CP1 current size is 3*I CP / 4, I CP2 The current size is I CP / 4, when n i = 2, I CP1 The current size is 2*I CP / 4, I CP2 The current size is 2*I CP / 4, when n i = 3, I CP1 The current size is 1*I CP / 4, I CP2 The current size is 3*I CP / 4, when n i = 0, I CP1 The current size is I CP , I CP2 The current size is 0.

[0078] When n i has no overflow, i.e. n i <M, clk_sel = 0, at this time, div_int(Y) frequency division is performed, then div_clk_lead and div_clk_lag are the div_int(Y) frequency division of the output clock signal pll_clk, when n i has overflow, i.e. n i ≥M, clk_sel = 1, at this time, div_int(Y+1) frequency division is performed, then div_clk_lead and div_clk_lag are the div_int(Y+1) frequency division of the output clock signal pll_clk.

[0079] According to the above process, 4*Tref = (4*Y+3)·Tvco, wherein Tref is the period of the reference clock signal ref_clk, and after arrangement, 4*Tref = (4*Y+3)·Tvco is obtained. The output clock signal pll_clk is realized to be the frequency division of the reference clock signal ref_clk.

[0080] It is to be understood that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. It will be apparent to those skilled in the art that various modifications and variations can be made to the present application without departing from the spirit or scope of the application. Thus, it is intended that the present application cover modifications and variations of this application provided they come within the scope of the appended claims and their equivalents.

[0081] While the application has been described in detail and with reference to specific embodiments thereof, it will be apparent to one skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope thereof. It is therefore intended that such changes and modifications be included within the scope of the application as defined by the appended claims.

Claims

1. A fractional-N phase-locked loop system, characterized by, The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The frequency divider module is used for receiving the integer frequency division ratio signal and the fractional frequency division ratio signal, dividing the output clock signal output by the voltage-controlled oscillator, and outputting X different frequency division clock signals and charge pump module control signals n corresponding to the X different frequency division clock signals i ; The application relates to a fractional-N phase-locked loop system. The charge pump module comprises an M-bit current circuit for controlling the charge pump module control signal n i and the charge and discharge control signal generates a corresponding current signal, and the charge pump module control signal n i controls the charge pump module to match the proportion of the frequency discriminator phase detector current generated by different frequency discriminators. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. wherein 2≤X, and 2≤M, i is an integer and 0≤iX, n i is an integer and 0≤n i <M.

2. The fractional-N phase-locked loop system as claimed in claim 1, wherein, The application relates to a fractional-N phase-locked loop system.

3. The fractional-N phase-locked loop system as claimed in claim 2, wherein, The application relates to a fractional-N phase-locked loop system.

4. The fractional-N phase-locked loop system as claimed in claim 1, wherein, The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system.

5. The fractional-N phase-locked loop system as claimed in claim 4, wherein, The fractional division control module comprises an accumulator, and the accumulator takes the accumulated sum of the fractional division ratio div_frac(Z) as the charge pump module control signal n i , and a carry signal as the clock selection signal; wherein div_frac represents a fractional division ratio, Z represents a fractional division ratio value, Z takes a value greater than zero and less than the current circuit bit number M of the charge pump module, and Z is an integer.

6. The fractional-N phase-locked loop system as claimed in claim 5, wherein, The application relates to a fractional-N phase-locked loop system.

7. The fractional-N phase-locked loop system as claimed in claim 5, wherein, The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system.

8. The fractional-N phase-locked loop system according to any one of claims 1 to 7, wherein The maximum total current that the charge pump module is capable of outputting is I CP ; The current signal corresponding to the jth of the X frequency detectors corresponds to the same charge pump module control signal n i The size I of the current signal corresponding to the jth of the X frequency detectors Cpj Satisfies And the charge and discharge control signal determines whether the corresponding current signal is a charging current or a discharging current, where 1≤j≤X.

9. The fractional-N phase-locked loop system as claimed in claim 8, wherein, When X=2, under the control of the charge pump module control signal n i , the size I CP1 of the current signal corresponding to the frequency discriminator phase detector controlled by the preceding frequency division clock signal satisfies I CP1 =(M-n i )*I CP / M, and the size I CP2 of the current signal corresponding to the frequency discriminator phase detector controlled by the subsequent frequency division clock signal satisfies I CP2 =n i *I CP / M.

10. The fractional-N phase-locked loop system according to any one of claims 1 to 9, wherein The step of the fractional division ratio is adjusted by adjusting the size of the current circuit bit number M of the charge pump module, and the step of the fractional division ratio is 11. A control method of a fractional-N phase-locked loop system, characterized by, In the fractional-N phase-locked loop system, a plurality of frequency and phase detectors are provided, and a charge pump module directly coupled to the plurality of frequency and phase detectors includes an M-bit current circuit. By controlling the proportion of the current size generated by the charge pump module corresponding to different frequency and phase detectors, the step size of the fractional division ratio is To achieve frequency division; wherein Y represents an integer division ratio value, Z represents a fractional division ratio value, and Z < M.

12. The method of claim 11, wherein, The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N phase-locked loop system. The application relates to a fractional-N

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