Deterministic random bit generation device and deterministic random bit generation method

Abstract

The invention provides a deterministic random bit generation device and a deterministic random bit generation method, and relates to the technical field of cryptographic hardware implementation. The deterministic random bit generation device comprises a buffer module suitable for accumulating data in a received data stream, and outputting a data block with a preset length under the condition that the accumulated data length is equal to the preset length; the data block polling scheduler is suitable for distributing the data blocks to a target computing core in the parallel processing engine according to a polling scheduling strategy so as to process the received data blocks through the target computing core to obtain random bits; the parallel processing engine comprises a plurality of parallel computing cores, and the plurality of parallel computing cores comprise a target computing core; and the output arbiter is suitable for monitoring the completion state of the plurality of parallel computing cores in real time and outputting the random bits for completing the computation according to the completion state.

Description

TECHNICAL FIELD

[0001] At least one embodiment of the present application relates to the technical field of cryptographic hardware implementation, and more particularly, to a deterministic random bit generation device and a deterministic random bit generation method. BACKGROUND

[0002] Deterministic random bit generators are a key component of modern cryptographic systems, and the cryptographic secure random numbers generated by them are widely used in key generation, digital signature, identity authentication, and secure communication. Various deterministic random bit generator (DRBG) mechanisms are defined in the prior art. With the development of quantum technology, quantum random number generators (QRNG) have become an ideal high-entropy source due to their physical properties based on quantum mechanics and unpredictability. However, the original output of QRNG often has statistical bias or correlation, and needs to be post-processed to obtain high-quality random number sequences that meet the requirements of cryptography. DRBG is a key tool for achieving this post-processing function.

[0003] Although software implementation of DRBG is common, its throughput is limited by the architecture of general-purpose processors, making it difficult to meet the data output rate of several gigabits per second (Gbps) or even higher of high-speed quantum random number generators, thereby forming a performance bottleneck in the post-processing link. Therefore, implementing a DRBG system with high performance, high throughput, flexibility, scalability, and ensuring output determinism on hardware has become an important direction to solve this challenge. SUMMARY

[0004] Therefore, the present application provides a deterministic random bit generation device, comprising:

[0005] A buffering module is adapted to accumulate data in a received data stream, and output a data block with a preset length when the length of the accumulated data is equal to the preset length.

[0006] A data block polling scheduler is adapted to distribute data blocks to a target computing core in a parallel processing engine according to a polling scheduling strategy, so that the target computing core processes the received data blocks to obtain random bits.

[0007] The parallel processing engine includes a plurality of parallel computing cores, and the plurality of parallel computing cores include the target computing core.

[0008] An output arbiter is adapted to monitor the completion status of the plurality of parallel computing cores in real time, and output the random bits of the completed computation according to the completion status.

[0009] According to an embodiment of the present application, the computing core comprises:

[0010] a constant unit adapted to provide I round constants, I being an integer greater than 1;

[0011] a message expansion unit adapted to split the data block into a plurality of initial message words and expand the plurality of initial message words to obtain I expanded message words;

[0012] I computing units, in the case of 1

[0013] an abstract output unit adapted to obtain a random bit according to the values of the plurality of the Ith working registers and the values of the plurality of the first working registers.

[0014] According to an embodiment of the present application, the computing core further comprises:

[0015] a hash register unit comprising a plurality of hash registers, the plurality of hash registers being adapted to determine the values of the plurality of the first working registers.

[0016] According to an embodiment of the present application, the identification of the data block is the nth identification, and the computing core comprises:

[0017] a state register unit comprising a key register and a counter register, the key register being adapted to store the (n-1)th key, and the counter register being adapted to store the (n-1)th counter value;

[0018] a first splicing unit adapted to obtain nth initial splicing data according to the data block and the (n-1)th counter value;

[0019] a first processing unit adapted to obtain an nth intermediate counter value and an nth intermediate key according to the nth initial splicing data and the (n-1)th key;

[0020] a second splicing unit adapted to splice the data block and the nth intermediate counter value to obtain nth target splicing data;

[0021] a second processing unit adapted to obtain an nth key and an nth counter value according to the nth target splicing data and the nth intermediate key, the nth counter value being a random bit.

[0022] According to an embodiment of the present application, the identification of the data block is the nth identification, and the computing core comprises:

[0023] a state register unit, comprising a key register and a counter register, the key register is adapted to store an (n-1)th key, and the counter register is adapted to store an (n-1)th counter value;

[0024] an encryption unit, adapted to encrypt the (n-1)th counter value by using the (n-1)th key to obtain an nth counter value, the nth counter value is a random bit.

[0025] According to an embodiment of the present application, the polling scheduling strategy comprises:

[0026] determining a modulo value between the identity of the data block and the number of computing cores;

[0027] determining the identity of the computing core which is the same as the modulo value from the identities of the plurality of computing cores;

[0028] taking the computing core corresponding to the identity of the computing core which is the same as the modulo value as the target computing core for processing the data block.

[0029] According to an embodiment of the present application, the buffering module is adapted to accumulate the data in the received data stream when detecting that the random number valid signal is at a valid level at a rising edge of the clock signal, output a data block with a preset length when the length of the accumulated data is equal to the preset length, and output a buffered data valid signal with a valid level, the buffered data valid signal with the valid level being used to indicate that the data block polling scheduler works when detecting that the buffered data valid signal is at the valid level at the rising edge of the clock signal.

[0030] According to an embodiment of the present application, the data block polling scheduler is adapted to distribute the data block to the target computing core according to the polling scheduling strategy when detecting that the buffered data valid signal is at the valid level at the rising edge of the clock signal, and output a core valid signal with a valid level, the core valid signal with the valid level being used to indicate that the target computing core works when detecting that the core valid signal is at the valid level at the rising edge of the clock signal.

[0031] According to an embodiment of the present application, the target computing core is adapted to process the received data block to obtain a random bit when detecting that the core valid signal is at the valid level at the rising edge of the clock signal.

[0032] According to an embodiment of the present application, the data block polling scheduler is further adapted to determine the identity of the data block.

[0033] As a second aspect of the present application, a deterministic random bit generation method is also provided, which is implemented by using the above-mentioned deterministic random bit generation device, and the deterministic random bit generation method comprises:

[0034] The buffer module is used for accumulating data in a received data stream, and a data block with a preset length is output when the length of the accumulated data is equal to the preset length.

[0035] The data block polling scheduler is used for distributing the data block to a target computing core in the parallel processing engine according to a polling scheduling strategy, so that the target computing core processes the received data block to obtain random bits; the parallel processing engine includes a plurality of parallel computing cores, and the plurality of parallel computing cores include the target computing core.

[0036] The output arbiter is used for monitoring the completion state of the plurality of parallel computing cores in real time, and outputting the random bits that are calculated and completed according to the completion state.

[0037] According to the embodiment of the present application, the deterministic random bit generation device can be implemented on a hardware such as a Field-Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC). Compared with a software implementation, the hardware buffer module, the data block polling scheduler, the parallel processing engine and the output arbiter can avoid software security vulnerabilities (such as buffer overflow and malicious code injection) by solidifying logic. At the same time, the random bit generation device provided by the embodiment of the present application does not depend on a general-purpose processor, reduces the exposure opportunity of data in the memory, further reduces the information leakage risk in the random bit generation process, and provides a more reliable hardware security foundation for high-security-level scenarios (such as quantum key distribution).

[0038] According to the embodiment of the present application, the buffer module accumulates the non-standard length data stream input from outside to a preset length and then outputs the data block to the data block polling scheduler, avoiding errors in the processing of the data block by the computing core due to the mismatch between the data length of the data block and the computing core. The polling scheduling strategy adopted by the data block polling scheduler ensures that the input data block is evenly distributed to each computing core, avoiding overloading or idling of some computing cores and realizing efficient load balancing. By simultaneously processing different data blocks through a plurality of parallel computing cores, the generation rate of random bits is significantly improved, and the theoretical throughput can reach M times of the single-core implementation (M is the number of computing cores in the parallel processing engine). The output arbiter monitors the completion state of the plurality of parallel computing cores in real time and outputs the random bits that are calculated and completed according to the completion state, avoiding the delay caused by waiting for all computing cores to complete, and further improving the overall efficiency of the system. BRIEF DESCRIPTION OF DRAWINGS

[0039] The above and other objects, features and advantages of the present application will become more apparent from the following description of embodiments of the present application taken in conjunction with the accompanying drawings, in which:

[0040] Figure 1 A deterministic random bit generation apparatus is shown according to an embodiment of the present application.

[0041] Figure 2 A schematic diagram of a computing core is shown according to an embodiment of the present application.

[0042] Figure 3 A schematic diagram of a computing core is shown according to another embodiment of the present application.

[0043] Figure 4 A schematic diagram of a computing core is shown according to still another embodiment of the present application.

[0044] BRIEF DESCRIPTION OF DRAWINGS

[0045] 10: buffer module;

[0046] 20: data block polling scheduler;

[0047] 30: parallel processing engine;

[0048] 31: computing core;

[0049] 311: constant unit;

[0050] 312: message expansion unit;

[0051] 3131: 1st computing unit;

[0052] 313i: i-th computing unit;

[0053] 313I: I-th computing unit;

[0054] 314: digest output unit;

[0055] 316: state register unit;

[0056] 315: hash register unit;

[0057] 317: 1st concatenation unit;

[0058] 318: 1st processing unit;

[0059] 319: 2nd concatenation unit;

[0060] 320: 2nd processing unit;

[0061] 321: output generation unit;

[0062] 322: encryption unit;

[0063] 323: State update unit;

[0064] 40: Output Arbitrator. Detailed Implementation

[0065] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the invention. In the following detailed description, numerous specific details are set forth to provide a thorough understanding of the embodiments of the invention for ease of explanation. However, it will be apparent that one or more embodiments may be practiced without these specific details. Furthermore, descriptions of well-known structures and techniques are omitted in the following description to avoid unnecessarily obscuring the concept of the invention.

[0066] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. The terms “comprising,” “including,” etc., as used herein indicate the presence of the stated features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0067] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein are to be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0068] Figure 1 A deterministic random bit generation apparatus according to an embodiment of the present invention is shown.

[0069] like Figure 1 As shown, the deterministic random bit generation device includes: a buffer module 10, a data block polling scheduler 20, a parallel processing engine 30, and an output arbiter 40. The buffer module 10 is used to accumulate data in the received data stream, and outputs data blocks of a preset length when the accumulated data length equals a preset length. The data block polling scheduler 20 is used to distribute data blocks to target computing cores in the parallel processing engine 30 according to a polling scheduling strategy, so that the target computing cores can process the received data blocks to obtain random bits. The parallel processing engine 30 includes multiple parallel computing cores 31, including the target computing core. The output arbiter 40 is used to monitor the completion status of the multiple parallel computing cores 31 in real time and output the completed random bits according to the completion status.

[0070] According to an embodiment of the present application, the above-mentioned deterministic random bit generation device can be implemented on a hardware such as a Field-Programmable Gate Array (FPGA) or an Application-Specific Integrated Circuit (ASIC). Compared with a software implementation, the hardware buffer module 10, the data block polling scheduler 20, the parallel processing engine 30, and the output arbiter 40 can avoid software-level security vulnerabilities (such as buffer overflow and malicious code injection) by solidifying logic. Meanwhile, the random bit generation device provided by the embodiment of the present application does not rely on a general-purpose processor, reduces the exposure opportunity of data in memory, further reduces the risk of information leakage in the random bit generation process, and provides a more reliable hardware security foundation for high-security-level scenarios (such as quantum key distribution).

[0071] According to an embodiment of the present application, the buffer module 10 accumulates the externally input non-standard length data stream to a preset length and then outputs the data block to the data block polling scheduler 20, avoiding errors in the processing of the data block by the computing core 31 due to the mismatch between the data length of the data block and the computing core 31. The polling scheduling strategy adopted by the data block polling scheduler 20 ensures that the input data block is evenly distributed to each computing core 31, avoiding overloading or idling of some computing cores 31 and realizing efficient load balancing. By simultaneously processing different data blocks through multiple parallel computing cores 31, the generation rate of random bits is significantly improved, and the theoretical throughput can reach M times of that of a single-core implementation (M is the number of computing cores 31 in the parallel processing engine 30). The output arbiter 40 monitors the completion status of the multiple parallel computing cores 31 in real time and outputs the completed random bits according to the completion status, avoiding the delay introduced by waiting for all computing cores 31 to complete, and further improving the overall efficiency of the system.

[0072] According to an embodiment of the present application, the data stream can be a continuous sequence of raw random numbers.

[0073] The buffer module 10 is adapted to accumulate data in the received data stream when the random number valid signal is detected as the valid level at the rising edge of the clock signal, and output a data block with a preset length when the length of the accumulated data is equal to the preset length, and output a buffer data valid signal with the valid level, which is used to indicate that the data block polling scheduler 20 works when the buffer data valid signal is detected as the valid level at the rising edge of the clock signal. According to an embodiment of the present application, for example, the length of each original random number sequence is L, and the length of the data received by the buffer module 10 is L bits when the random number valid signal is detected as the valid level at the rising edge of the clock signal each time. When the length of the data block is, for example, 1024 bits, the buffer module 10 needs to buffer 1024 / L times of accumulation to complete one data block. L < 1024.

[0074] According to an embodiment of the present application, the buffer module 10 can accumulate and assemble the input discontinuous data stream into a data block with a fixed length before outputting, so that the subsequent parallel processing engine 30 can operate at its highest efficiency without being limited by the rate and burstiness of the data stream input. When a complete data block is ready, the buffer module 10 generates a buffer data valid signal, which is used to notify the downstream data block polling scheduler 20 and indicate the validity of the data block, thereby providing a simple and clear trigger condition for the downstream data block polling scheduler 20. The data block polling scheduler 20 does not need to continuously monitor the data bus, but only needs to detect the buffer data valid signal as the valid level (for example, high level) at the rising edge of the clock signal, which can be implemented by a simple state machine, thereby reducing the hardware complexity. The operation of the data block polling scheduler 20 only when the buffer data valid signal is the valid level is a typical clock gating, and the data block polling scheduler 20 can stop working when the random number valid signal is not detected as the valid level at the rising edge of the clock signal, thereby reducing unnecessary dynamic switching activities and effectively reducing the system power consumption.

[0075] According to an embodiment of the present application, the data block polling scheduler 20 is adapted to distribute the data block to the target computing core in the parallel processing engine 30 according to the polling scheduling strategy when the buffer data valid signal is detected as the valid level (for example, high level) at the rising edge of the clock signal, and output a core valid signal with the valid level, which is used to indicate that the target computing core works when the core valid signal is detected as the valid level at the rising edge of the clock signal. According to an embodiment of the present application, the target computing core is adapted to process the received data block to obtain a random bit when the core valid signal is detected as the valid level at the rising edge of the clock signal.

[0076] According to an embodiment of the present application, the data block polling scheduler 20 starts the scheduling only when the buffered data valid signal is at the valid level (the buffered data valid signal is at the high level). The data block polling scheduler 20 activates the target computing core by pulling the core valid signal to the high level. Both the data block polling scheduler 20 and the target computing core are triggered only when the conditions are met, which realizes the precise flow control and avoids the data loss or error processing.

[0077] According to an embodiment of the present application, the computing core 31 of the parallel processing engine 30 internally coordinates the data block processing flow by a state machine. The state machine internally defines three states: an idle state (CTRL_IDLE), a round computing state (CTRL_ROUNDS) and a completion state (CTRL_DONE). When the target computing core is activated by the data block polling scheduler 20 (i.e. receiving the corresponding core valid signal at the high level at the rising edge of the clock signal) and receives the data block, the state machine migrates from the idle state to the round computing state. When the processing of the data block by the target computing core is completed, the state machine is transferred to the completion state.

[0078] According to an embodiment of the present application, the data block polling scheduler 20 is further adapted to determine the identity of the data block. The data block polling scheduler 20 implements the distribution of the data block by the polling scheduling strategy, which includes: determining a modulo value between the identity of the data block and the number of computing cores; determining the identity of the computing core 31 which is the same as the modulo value from the identities of the plurality of computing cores 31; and taking the computing core 31 corresponding to the identity of the computing core 31 which is the same as the modulo value as the target computing core for processing the data block.

[0079] According to an embodiment of the present application, the data block polling scheduler 20 implements the specific distribution of data blocks based on the polling scheduling strategy as follows: the data block polling scheduler 20 is internally provided with a polling counter. When the buffer data valid signal is detected to be valid (i.e. the buffer data valid signal is detected to be high at the rising edge of the clock signal), the data block polling scheduler 20 obtains the identity of the current received data block (i.e. the order of the current received data block) according to the current value of the polling counter (representing the number of data blocks that have been distributed by the data block polling scheduler 20), and then determines the modulo value between the identity of the current received data block and the number of computing cores 31. Then, the identity of the computing core 31 that is identical to the modulo value is determined from the identities of the plurality of computing cores 31, and finally the computing core 31 corresponding to the identity of the computing core 31 that is identical to the modulo value is taken as the target computing core for processing the data block, and a single-hot core valid signal is generated. The core valid signal will precisely enable a target computing core, so that the data block polling scheduler 20 distributes the content of the data block to the target computing core for processing. After the current distribution of the data block, the count value of the polling counter is incremented and moduloed by the number of parallel computing cores 31, in preparation for the next distribution of the data block. This mechanism ensures that the continuously incoming data blocks are smoothly and sequentially distributed to each of the parallel computing cores, achieving load balancing of the computing task.

[0080] According to an embodiment of the present application, the output arbiter 40 is connected to the output ends of the plurality of computing cores 31, and its core function is to monitor the completion status of all computing cores 31 in real time, and immediately output the computing result generated by the computing core 31 that completes the computation when at least one computing core 31 completes the computation. The output arbiter 40 is a pure combinational logic circuit, which can monitor the computation completion flag signals of all parallel computing cores 31 in real time. Once it detects that the computation completion flag signal of any computing core 31 is high (indicating that the computation has been completed, and the computing core 31 is in a completed state), the output arbiter 40 will immediately output the computing result of the computing core 31, and set the random bit valid signal to an effective level (e.g. high). Taking the FPGA hardware implementation as an example, the above functions are implemented by loop statements and interrupt statements in the Verilog hardware description language, and its function is equivalent to a priority encoder that always selects the random bit with the smallest index number and the high level of the random bit valid signal. Through this mechanism, the output arbiter 40 can output the processing result of the computing core 31 that completes the computation in advance, thereby significantly reducing the output delay of the overall system and avoiding the performance bottleneck caused by waiting for the slowest computing core 31 to complete.

[0081] According to an embodiment of the present application, the parallel processing engine 30 is a core of high throughput, and the parallel multiple computing cores 31 in the parallel processing engine 30 can be implemented by a Hash-DRBG (Deterministic Random Bit Generation based on Hash Function) architecture. For example, each computing core 31 is a complete, independent hardware implementation of the SHA-512 algorithm. According to an embodiment of the present application, the length of each data block can be, for example, 1024 bits. The 1024-bit width is completely matched with the standard input block size of algorithms such as SHA-512, without the need for additional padding or truncation logic.

[0082] Figure 2 A schematic diagram of a computing core according to an embodiment of the present application is shown.

[0083] As shown in Figure 1 and Figure 2 , the computing core 31 includes a constant unit 311, a message expansion unit 312, I computing units, and an output unit 314. The I computing units include a first computing unit 3131, an i-th computing unit 313i, and an I-th computing unit 313I. The constant unit 311 is adapted to provide I round constants, where I is an integer greater than 1, and in the SHA-512 algorithm, I can be, for example, 80. For example, the first round constant is , the i-th round constant is , and the I-th round constant is . The computing core 31 further includes I working register groups, and the i-th working register group includes multiple i-th working registers, where the value of each i-th working register is stored in an i-th working register, and i≤I. The number of working registers in each computing core 31 is the same, and for example, the working registers in each computing core 31 can all be 8, and the multiple first working registers in the first working register group are a1~h1. The multiple i-th working registers in the i-th working register group are ai~hi. The multiple I-th working registers in the I-th working register group are ai~hi. i i I I

[0084] The message expansion unit 312 is adapted to split the data block into multiple initial message words, and expand the multiple initial message words to obtain I expanded message words. The message expansion unit 312, for example, pre-computes the input 1024-bit data block, and expands the 1024-bit data block into 80 64-bit message words ​​​​, respectively, to 80 computing units. In the case of 1 < i ≤ I, the ith computing unit is adapted to derive values of a plurality of ith working registers outputted by the ith computing unit from values of a plurality of (i-1)th working registers outputted by the (i-1)th computing unit, the ith expansion message word, and the ith round constant. The digest output unit 314 is adapted to derive the random bit from the values of the plurality of Ith working registers and the values of the plurality of 1st working registers. After the 80 computing units finish the work, the digest output unit 314 is adapted to add the values of the plurality of Ith working registers to the values of the plurality of 1st working registers to derive the random bit. For example, the value of the first Ith working register is added to the value of the first 1st working register, the value of the second Ith working register is added to the value of the second 1st working register, and so on, and the value of the eighth Ith working register is added to the value of the eighth 1st working register to derive the random bit.

[0085] According to an embodiment of the present application, each computing core 31 further comprises a hash register unit 315 comprising a plurality of hash registers (for example, 8), each of which is for example 64 bits, and the plurality of hash registers are adapted to determine the values of the plurality of 1st working registers.

[0086] According to an embodiment of the present application, in a hash algorithm such as SHA-512, initial hash values (for example, H0~H7) are predefined constants, and before the start of the calculation, these initial values are respectively stored in the plurality of hash registers, wherein each hash register stores a 64-bit initial hash value, and after the start of the calculation, these initial hash values are first loaded into the plurality of 1st working registers, and the plurality of hash registers and the plurality of 1st working registers are one-to-one corresponding, that is, each 1st working register loads the initial hash value of the corresponding hash register as the value of the 1st working register.

[0087] According to an embodiment of the present application, the computing core 31 expands the multi-round iterative calculation of the hash algorithm into a fixed pipeline with a depth of I levels on the hardware. The complex I-round algorithm is decomposed into I computing units, avoiding long combinatorial logic chains in software implementation, and improving timing performance and operation speed.

[0088] According to another embodiment of the present application, the parallel plurality of computing cores 31 in the parallel processing engine 30 can also be implemented using a Deterministic Random Bit Generation Architecture Based on Hash Message Authentication Code (HMAC_DRBG).

[0089] Figure 3 A schematic diagram of a computing core according to yet another embodiment of the present application is shown.

[0090] In this implementation, for example, the identifier of the data block output by the data block polling scheduler 20 is the nth identifier. Figure 1 and Figure 3 As shown, the computing core 31 includes: a status register unit 316, a first splicing unit 317, a first processing unit 318, a second splicing unit 319, and a second processing unit 320.

[0091] Status register unit 316 includes a key register and a counter register, both of which are 512-bit registers. The key register is used to store the (n-1)th key, and the counter register is used to store the (n-1)th counter value. First concatenation unit 317 is used to obtain the nth initial concatenation data based on the data block and the (n-1)th counter value. First processing unit 318 is used to obtain the nth intermediate counter value and the nth intermediate key based on the nth initial concatenation data and the (n-1)th key. Second concatenation unit 319 is used to concatenate the data block and the nth intermediate counter value to obtain the nth target concatenation data. Second processing unit 320 is used to obtain the nth key and the nth counter value based on the nth target concatenation data and the nth intermediate key, where the nth counter value is a random bit. The nth key and the nth counter value are stored in the counter register and the key register, respectively.

[0092] According to an embodiment of the present invention, the first splicing unit 317 is adapted to obtain the nth initial spliced ​​data based on the data block and the (n-1)th counter value, including: the first splicing unit 317 is adapted to splice the data block, control bits (e.g., 0x00 or 0x01) and the (n-1)th counter value to obtain the nth initial spliced ​​data.

[0093] After the first splicing unit 317 completes the splicing, it transmits a control signal to the downstream first processing unit 318 to ensure that the nth initial spliced ​​data message is sent to the first processing unit 318 in the correct timing. The first processing unit 318 is implemented based on the multiplexed SHA-512 algorithm core. The first processing unit 318 receives " "As input, a hash operation is performed. Among them, Represents the (n-1)th key. This represents a predefined constant. This represents a bitwise XOR logical operation. The nth initial concatenation data is represented. The second concatenation unit 319 concatenates the data block and the nth intermediate counter value to obtain the nth target concatenation data. Then the second processing unit 320 performs the second round of processing, and the second processing unit 320 is also implemented based on the multiplexed SHA-512 algorithm core. The nth key and the nth counter value obtained by the second processing unit 320 are stored in the key register and the counter register respectively, and provide the internal state basis for the next random bit generation. The control logic of the entire calculation core coordinates the first concatenation unit 317, the first processing unit 318, the second concatenation unit 319 and the second processing unit 320 and the write operation of the state register unit 316 through the handshake signal, to ensure that the data is accurately connected in time sequence. In addition, in this embodiment, the calculation core 31 also includes an output generation unit 321. The output generation unit 321 receives the 512-bit encryption result (i.e. the nth counter value) generated by the second processing unit 320. The output generation unit 321 transmits the encryption result to the output arbiter 40, outputs a calculation completion flag signal, and the state machine of the calculation core 31 switches to the completion state (CTRL_DONE).

[0094] According to still another embodiment of the present aspect, the parallel multiple calculation cores 31 in the parallel processing engine 30 can be implemented based on a deterministic random bit generation architecture (CTR_DRBG) based on a block cipher. The calculation core takes a symmetric block cipher (such as AES-256) as an underlying encryption primitive, controls the entire random bit generation process through a state machine, and correctly iterates the key, counter value and random bit output.

[0095] Figure 4 A schematic diagram of a calculation core according to still another embodiment of the present application is shown.

[0096] In this implementation, for example, the identification of the data block output by the data block polling scheduler 20 is the nth identification, as shown in the following table: Figure 1 and Figure 4As shown, the computing core 31 comprises a state register unit 316 and an encryption unit 322. The state register unit 316 comprises a key register and a counter register, the key register is adapted to store the (n-1)th key, and the counter register is adapted to store the (n-1)th counter value. The encryption unit 322 is adapted to encrypt the (n-1)th counter value with the (n-1)th key to obtain the nth counter value, which is a random bit. The encryption unit 322 is the core for random bit (pseudo-random number) generation. It receives the 128-bit nth counter value from the state register unit 316 as the input plaintext, and encrypts the nth counter value V using a 256-bit key. The encryption unit 322 follows the complete process of the AES-256 algorithm to encrypt the input nth counter value V and outputs a 128-bit encryption result. The embodiment also comprises an output generation unit 321 which receives the 128-bit encryption result generated by the encryption unit 322 and outputs it. After each output, it triggers the state update unit 323 to perform the increment operation (V = V + 1) on the nth counter value V, in preparation for the next random bit generation. When the computing core 31 completes all the computing processes, the output generation unit 321 outputs the computing result of the computing core 31, and transmits the result to the output arbiter 40, while outputting a computing completion flag signal, and the state machine switches to the completion state (CTRL_DONE).

[0097] As a second aspect of the present application, a deterministic random bit generation method is also provided, which is implemented by using the deterministic random bit generation device described above, and comprises operations S1-S4.

[0098] In operation S1, the data in the received data stream is accumulated by using the buffer module 10, and in the case where the accumulated data length is equal to the preset length, a data block with the preset length is outputted.

[0099] In operation S2, the data block is distributed to the target computing core in the parallel processing engine 30 according to the polling scheduling strategy by using the data block polling scheduler 20, so as to process the received data block by the target computing core to obtain a random bit; wherein the parallel processing engine 30 comprises a plurality of parallel computing cores 31, and the plurality of parallel computing cores 31 comprises the target computing core.

[0100] In operation S3, the completion state of the plurality of parallel computing cores is monitored in real time by using the output arbiter 40, and the random bit of the completed computation is outputted according to the completion state.

[0101] According to the deterministic random bit generation device and method provided by the embodiments of the present application, a data block polling scheduler 20 employing a polling scheduling strategy is used to evenly distribute data blocks to a parallel processing engine 30 comprising a plurality of computing cores 31. Meanwhile, an output arbitrator 40 monitors the completion status of each computing core 31 in real time and preferentially outputs the processing result of the computing core 31 that completes the computation first. This parallel architecture combining load-balanced scheduling and preferential arbitration provides a deterministic random bit generation scheme with high throughput, high efficiency and good scalability, which can be widely applied in the fields of quantum secure communication, information security, quantum random number generation and the like.

[0102] The above describes the embodiments of the present application. However, these embodiments are only for illustrative purposes, and are not intended to limit the scope of the present application. Although each embodiment is described above separately, this does not mean that the measures in each embodiment cannot be used advantageously in combination. Those skilled in the art can make various substitutions and modifications without departing from the scope of the present application, and these substitutions and modifications shall fall within the scope of the present application.

Claims

1. A deterministic random bit generation apparatus characterized by comprising: The method comprises the following steps: buffering the data in the received data stream, and outputting a data block with a preset length when the length of the accumulated data is equal to the preset length; distributing the data block to a target computing core in a parallel processing engine according to a round-robin scheduling strategy, processing the received data block by the target computing core, and obtaining a random bit; the parallel processing engine comprises a plurality of parallel computing cores, and the plurality of parallel computing cores comprise the target computing core; monitoring the completion state of the plurality of parallel computing cores in real time, and outputting the random bit after completion of calculation according to the completion state.

2. The deterministic random bit generation device according to claim 1, wherein The computing core comprises: a constant unit for providing I rounds of constants, I being an integer greater than 1; a message expansion unit for splitting the data block into a plurality of initial message words and expanding the plurality of initial message words to obtain I expanded message words; I computing units, in the case of 1 an abstract output unit for obtaining the random bit according to the values of the plurality of first I working registers and the values of the plurality of first 1 working registers.

3. The deterministic random bit generation device of claim 2, wherein The computing core further comprises: a hash register unit comprising a plurality of hash registers, the plurality of hash registers being adapted to determine the values of the plurality of first 1 working registers.

4. The deterministic random bit generation device of claim 1, wherein The identification of the data block is the nth identification, and the computing core comprises: a state register unit comprising a key register and a counter register, the key register being adapted to store an nth-1 key, and the counter register being adapted to store an nth-1 counter value; a first splicing unit adapted to obtain an nth initial splicing data according to the data block and the nth-1 counter value; a first processing unit adapted to obtain an nth intermediate counter value and an nth intermediate key according to the nth initial splicing data and the nth-1 key; a second splicing unit adapted to splice the data block and the nth intermediate counter value to obtain an nth target splicing data; a second processing unit adapted to obtain an nth key and an nth counter value according to the nth target splicing data and the nth intermediate key, the nth counter value being the random bit.

5. The deterministic random bit generation device of claim 1, wherein The identification of the data block is the nth identification, and the computing core comprises: a state register unit comprising a key register and a counter register, the key register being adapted to store an nth-1 key, and the counter register being adapted to store an nth-1 counter value; an encryption unit adapted to encrypt the nth-1 counter value by using the nth-1 key to obtain an nth counter value, the nth counter value being the random bit.

6. The deterministic random bit generation device according to any one of claims 1 to 5, wherein The round-robin scheduling strategy comprises: determining the modulo value between the identification of the data block and the number of computing cores; determine the identity of the computing core that is the same as the modulo value from the identities of the plurality of computing cores; corresponding to the identity of the computing core that is the same as the modulo value as the target computing core for processing the data block.

7. The deterministic random bit generation apparatus according to any one of claims 1-5, wherein the buffer module is configured to accumulate data in the received data stream when the random number valid signal is detected as the active level at the rising edge of the clock signal, output a data block having the preset length when the length of the accumulated data is equal to the preset length, and output a buffer data valid signal having the active level, the buffer data valid signal having the active level being used to indicate that the data block polling scheduler operates when the buffer data valid signal is detected as the active level at the rising edge of the clock signal.

8. The deterministic random bit generation apparatus according to any one of claims 1-5, wherein the data block polling scheduler is configured to distribute the data block to the target computing core according to the polling scheduling strategy when the buffer data valid signal is detected as the active level at the rising edge of the clock signal, and output a core valid signal having the active level, the core valid signal having the active level being used to indicate that the target computing core operates when the core valid signal is detected as the active level at the rising edge of the clock signal.

9. The deterministic random bit generation apparatus according to any one of claims 1-5, wherein the target computing core is configured to process the received data block when the core valid signal is detected as the active level at the rising edge of the clock signal, and obtain the random bit.

10. The deterministic random bit generation device according to any one of claims 1 to 5, wherein the data block polling scheduler is further configured to determine the identity of the data block.

11. A deterministic random bit generation method, implemented by using the deterministic random bit generation apparatus according to any one of claims 1 to 10, characterized by, The deterministic random bit generation method comprises: accumulating data in the received data stream using a buffer module, and outputting a data block having a preset length when the length of the accumulated data is equal to the preset length; distributing the data block to a target computing core in a parallel processing engine according to a polling scheduling strategy using a data block polling scheduler, so that the target computing core processes the received data block and obtains a random bit, wherein the parallel processing engine comprises a plurality of parallel computing cores, and the plurality of parallel computing cores comprises the target computing core; monitoring the completion status of the plurality of parallel computing cores in real time using an output arbiter, and outputting a completed random bit according to the completion status.

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