Semiconductor memory device

Abstract

There is provided a semiconductor memory device including: a substrate including a stack region including a first step region and a second step region, the first step region and the second step region being located at both ends of the stack region in a first horizontal direction; a plurality of word lines each extending in a first horizontal direction in the stack region; a plurality of bit lines extending in a vertical direction in the stack region and spaced apart from each other in a first horizontal direction; a plurality of memory cells between the plurality of word lines and the plurality of bit lines; a first word line contact and a second word line contact connected to each of the plurality of word lines; and a first sub-word line driver and a second sub-word line driver connected to the first word line contact and the second word line contact, respectively.

Description

Cross Reference to Related Applications

[0001] This application is based on and claims priority to Korean Patent Application No. 10-2024-0059884, filed on May 7, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated by reference herein in its entirety. TECHNICAL FIELD

[0002] The present inventive concept relates to a semiconductor memory device, and more particularly, to a three-dimensional semiconductor memory device including a plurality of memory cells arranged in three dimensions. BACKGROUND

[0003] As electronic products require miniaturization and multifunctionality, and have higher performance, semiconductor memory devices of higher capacity are required, and integration is required to be increased to provide semiconductor memory devices of higher capacity. Since the integration of a conventional semiconductor memory device including a plurality of memory cells arranged in two dimensions is mainly determined by the area occupied by a unit memory cell, the integration of a two-dimensional semiconductor memory device is limited although it is increased to some extent. Therefore, a three-dimensional semiconductor memory device including a plurality of memory cells arranged in three dimensions has been proposed, which increases the storage capacity by stacking memory cells in a vertical direction on a substrate. SUMMARY

[0004] The present inventive concept provides a three-dimensional semiconductor memory device having increased integration.

[0005] According to an example embodiment of the present inventive concept, a semiconductor memory device includes a substrate including a stacked region including a first staircase region and a second staircase region, the first staircase region and the second staircase region respectively located at both ends of the stacked region in a first horizontal direction; a plurality of word lines each extending in the first horizontal direction toward each of the first staircase region and the second staircase region in the stacked region, the plurality of word lines spaced apart from each other in a vertical direction; a plurality of bit lines extending in the vertical direction in the stacked region, the plurality of bit lines spaced apart from each other in the first horizontal direction; a plurality of memory cells located between the plurality of word lines and the plurality of bit lines in the stacked region; first word line contacts connected to each of the plurality of word lines in the first staircase region and second word line contacts connected to each of the plurality of word lines in the second staircase region; and first and second sub word line drivers connected to the first and second word line contacts, respectively.

[0006] According to an example embodiment of the inventive concept, a semiconductor memory device includes: a lower structure; and an upper structure stacked on the lower structure, the upper structure including a first sub word line driver and a second sub word line driver, wherein the lower structure includes: a substrate including a stacked region, the stacked region including a first stepped region and a second stepped region, the first stepped region and the second stepped region respectively located at both ends of the stacked region in a first horizontal direction; a plurality of word lines each extending in the first horizontal direction toward each of the first stepped region and the second stepped region in the stacked region, the plurality of word lines spaced apart from each other in a vertical direction; a plurality of bit lines extending in the vertical direction in the stacked region, the plurality of bit lines spaced apart from each other in the first horizontal direction; a plurality of memory cells located between the plurality of word lines and the plurality of bit lines in the stacked region; and a first word line contact and a second word line contact, the first word line contact connected to each of the plurality of word lines in the first stepped region, the second word line contact connected to each of the plurality of word lines in the second stepped region, wherein each of the plurality of word lines is electrically connected to the first sub word line driver through the first word line contact and electrically connected to the second sub word line driver through the second word line contact.

[0007] According to an example embodiment of the inventive concept, a semiconductor memory device includes: a lower structure; and an upper structure stacked on the lower structure, the upper structure including a first sub word line driver and a second sub word line driver, wherein the lower structure includes: a substrate including a stacked region, the stacked region including a first stepped region and a second stepped region, the first stepped region and the second stepped region respectively located at both ends of the stacked region in a first horizontal direction; a plurality of word lines each extending in the first horizontal direction toward each of the first stepped region and the second stepped region in the stacked region, the plurality of word lines spaced apart from each other in a vertical direction; a plurality of bit lines extending in the vertical direction in the stacked region, the plurality of bit lines spaced apart from each other in the first horizontal direction; a plurality of memory cells located between the plurality of word lines and the plurality of bit lines in the stacked region; and a first word line contact and a second word line contact, the first word line contact connected to each of the plurality of word lines in the first stepped region, the second word line contact connected to each of the plurality of word lines in the second stepped region, each of the plurality of word lines is electrically connected to the first sub word line driver through the first word line contact and electrically connected to the second sub word line driver through the second word line contact, each of the plurality of memory cells includes a cell transistor and an information storage element, the cell transistor includes a semiconductor pattern including a source region connected to a corresponding bit line of the plurality of bit lines, a channel region surrounded by a corresponding word line of the plurality of word lines, and a drain region connected to the information storage element, and the source region, the channel region, and the drain region are sequentially arranged from the corresponding bit line of the plurality of bit lines in a second horizontal direction different from the first horizontal direction. Attached Figure Description

[0008] Some exemplary embodiments will become clearer from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0009] Figure 1 This shows an equivalent circuit diagram of a stacked cell array of semiconductor memory devices according to an example embodiment;

[0010] Figure 2 This is a block diagram illustrating a semiconductor memory device according to an example embodiment;

[0011] Figure 3 This is a perspective view showing a semiconductor memory device according to an example embodiment;

[0012] Figure 4A , Figure 4B and Figure 4C This is a perspective view and a cross-sectional view showing a portion of a semiconductor memory device according to an example embodiment;

[0013] Figure 5 This is a planar layout diagram of a semiconductor memory device according to an example embodiment;

[0014] Figure 6 This is a planar layout diagram of a semiconductor memory device according to an example embodiment;

[0015] Figure 7 This shows an equivalent circuit diagram of a stacked cell array of semiconductor memory devices according to an example embodiment;

[0016] Figure 8 This is a planar layout diagram of a semiconductor memory device according to an example embodiment;

[0017] Figure 9 This is a block diagram illustrating a line decoder included in a semiconductor memory device according to an example embodiment; and

[0018] Figure 10 It shows Figure 9 The circuit diagram of the sub-word line driver circuit. Detailed Implementation

[0019] As used herein, expressions such as "at least one of..." modify the entire list of elements when placed after the list of elements, rather than modifying individual elements in the list. Therefore, for example, "at least one of A, B, or C" and "at least one of A, B, and C" both mean A, B, C, or any combination thereof. Similarly, A and / or B means A, B, or A and B.

[0020] Although the terms "same," "equal," or "identical" are used in the description of example embodiments, it should be understood that there can be some inaccuracy. Thus, when an element is referred to as being the same as another element, it should be understood that the element or value is the same as the other element within a desired manufacturing or operational tolerance (e.g., ±10%).

[0021] When the terms "about," "substantially," or "approximately" are used in this specification in connection with a numerical value, it is intended that the associated numerical value include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value. Additionally, when the words "about," "substantially," or "approximately" are used in connection with a geometric shape, it is intended that precision of the geometric shape is not required, but that a tolerance for the shape is within the scope of this disclosure. Furthermore, whether or not a numerical value or shape is modified by "about" or "substantially," it will be understood that these values and shapes are to be interpreted to include manufacturing or operational tolerances (e.g., ±10%) around the stated numerical value or shape.

[0022] Figure 1 is an equivalent circuit diagram illustrating a stacked cell array of a semiconductor memory device according to an example embodiment.

[0023] Referring to Figure 1 , a stacked cell array structure CAR of a semiconductor memory device 1 according to an example embodiment can include a plurality of sub-cell arrays SCA. Each sub-cell array SCA can include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC. Each memory cell of the plurality of memory cells MC includes a cell transistor CT and an information storage element SP. One cell transistor CT can be arranged between one word line WL and one bit line BL. The information storage element SP can be connected to the cell transistor CT. The information storage element SP can be a storage element capable of storing data. The information storage element SP can include a storage element using a capacitor, a storage element using a magnetic tunnel junction pattern, or a storage element using a variable resistor including a phase change material. In some example embodiments, the memory cell MC can be a DRAM cell, and the information storage element SP can be a capacitor, and specific examples thereof will be described later with reference to Figure 4C .

[0024] The word line WL can be a conductive pattern (e.g., a metal line) spaced apart from the substrate and arranged above the substrate. The plurality of word lines WL can extend in a first horizontal direction (X direction). The word lines WL in one sub-cell array SCA can be spaced apart from each other in a vertical direction (Z direction). Each bit line BL can be a conductive pattern (e.g., a metal line) extending from the substrate in the vertical direction (Z direction). The bit lines BL in one sub-cell array SCA can be spaced apart from each other in the first horizontal direction (X direction).

[0025] In the stacked cell array structure CAR, a plurality of word lines WL extend in a first horizontal direction (X direction), and can be spaced apart from each other in a second horizontal direction (Y direction) and a vertical direction (Z direction), respectively. In the stacked cell array structure CAR, a plurality of bit lines BL can extend in the vertical direction (Z direction), and can be spaced apart from each other in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). A plurality of sub cell array SCA can be arranged in the second horizontal direction (Y direction). The second horizontal direction (Y direction) can be orthogonal to the first horizontal direction (X direction).

[0026] A gate of the cell transistor CT can be connected to the word line WL, and a source region of the cell transistor CT can be connected to the bit line BL. The information storage element SP can be connected to a drain region of the cell transistor CT. In some example embodiments, the information storage element SP can be a capacitor including a first electrode, a second electrode, and a capacitor dielectric layer between the first electrode and the second electrode, and the first electrode of the capacitor can be connected to the drain region of the cell transistor CT, and the second electrode of the capacitor can be connected to the ground line PP.

[0027] The stacked cell array structure CAR of the semiconductor storage device 1 includes a plurality of memory cells MC, a plurality of bit lines BL, and a plurality of sub cell arrays SCA, the plurality of memory cells MC are spaced apart from each other in each of a first horizontal direction (X direction) and a vertical direction (Z direction), and are arranged to form rows and columns, the plurality of bit lines BL are connected to cell transistors CT of the memory cells MC arranged in the vertical direction (Z direction), extend in the vertical direction (Z direction), and are spaced apart from each other in the first horizontal direction (X direction), the plurality of sub cell arrays SCA each include a plurality of word lines WL extending in the first horizontal direction (X direction) and spaced apart from each other in the vertical direction (Z direction), and the plurality of sub cell arrays SCA can be arranged in a second horizontal direction (Y direction). The semiconductor storage device 1 can include a plurality of stacked cell array structures CAR, which will be described with reference to Figure 5 to which it is described.

[0028] The first horizontal direction (X direction), the second horizontal direction (Y direction), and the vertical direction (Z direction) can be referred to as a first direction, a second direction, and a third direction, respectively. Alternatively, the first horizontal direction (X direction), the vertical direction (Z direction), and the second horizontal direction (Y direction) can be referred to as a first direction, a second direction, and a third direction, respectively. The first direction, the second direction, and the third direction can be orthogonal to each other.

[0029] In some example embodiments, the source region and the drain region of the cell transistor CT and the information storage element SP can be arranged in a second horizontal direction (Y direction) from a bit line BL connected to the source region of the cell transistor CT. Two groups each including the source region and the drain region of the cell transistor CT and the information storage element SP and connected to respective bit lines of two bit lines BL adjacent to each other in the second horizontal direction (Y direction) can be arranged in opposite directions. For example, the source region and the drain region of the cell transistor CT and the information storage element SP connected to one of the two bit lines BL adjacent to each other in the second horizontal direction (Y direction) can be sequentially arranged in the second horizontal direction (Y direction), and the source region and the drain region of the cell transistor CT and the information storage element SP connected to the other of the two bit lines BL adjacent to each other can be arranged in a direction opposite to the second horizontal direction (Y direction). For example, the plurality of bit lines BL can include a first bit line, a second bit line, a third bit line, and a fourth bit line sequentially arranged adjacent to each other in the second horizontal direction (Y direction). The memory cell MC can not be arranged between the first bit line and the second bit line. Two memory cells MC can be arranged in the second horizontal direction (Y direction) between the second bit line and the third bit line at the same vertical level. The memory cell MC can not be arranged between the third bit line and the fourth bit line.

[0030] Figure 2 is a block diagram illustrating a semiconductor memory device according to an example embodiment.

[0031] Referring to Figure 2 The semiconductor memory device 700 can include a memory cell array 701 including DRAM cells, which are memory cells, and various circuit blocks for driving the DRAM cells. For example, when a chip select signal CSB changes from an inactive level (e.g., logic high) to an active level (e.g., logic low), a timing register 702 can be activated. The timing register 702 can receive command signals (such as a clock signal CLK, a clock enable signal CKE, a chip select signal CSB, a row address strobe signal RASB, a column address strobe signal CASB, a write enable signal WEB, and a data input / output mask signal DQM) from the outside and process the received command signals to generate various internal command signals LRAS, LCBR, LWE, LCAS, LWCBR, and LDQM for controlling the circuit blocks.

[0032] Some internal command signals generated from the timing register 702 are stored in the program register 704. For example, delay information related to data output, burst length information, and the like can be stored in the program register 704. The internal command signals stored in the program register 704 can be provided to the delay / burst length control unit 706, and the delay / burst length control unit 706 can provide a control signal for controlling a delay or a burst length of data output to the column decoder 710 through the column address buffer 708 or to the output buffer 712.

[0033] The address register 720 can receive a clock signal CLK and an address signal ADD from the outside. The row address signal can be provided to the row decoder 724 through the row buffer refresh counter 722. Also, the column address signal can be provided to the column decoder 710 through the column buffer 708. The row buffer refresh counter 722 can also receive a refresh address signal generated from a refresh counter in response to refresh commands LRAS and LCBR, and can provide the row address signal or the refresh address signal to the row decoder 724. In addition, the address register 720 can provide a bank signal for selecting a bank to the bank selection unit 726.

[0034] The row decoder 724 can decode the row address signal or the refresh address signal input from the row buffer refresh counter 722. The row decoder 724 can include a plurality of sub word line drivers 725. The sub word line drivers 725 can activate word lines WL of the memory cell array 701. The sub word line drivers 725 can be arranged adjacent to the memory cell array 701 to form a block at a desired (or alternatively, predetermined) interval within the row decoder 724. For example, the sub word line drivers 725 can be arranged adjacent to one end of the memory cell array 701 perpendicular to the sense amplifier 730.

[0035] The column decoder 710 can decode the column address signal and perform a selection operation on a bit line of the memory cell array 701. For example, a column selection line can be applied to the semiconductor memory device 700 to perform a selection operation through the column selection line.

[0036] The sense amplifier 730 can amplify data of a memory cell selected through the row decoder 724 and the column decoder 710, and provide the amplified data to the output buffer 712. Data for recording a data unit is provided to the memory cell array 701 through the data input register 732, and the input / output controller 734 can control a data transfer operation through the data input register 732.

[0037] Figure 3 FIG. 1 is a perspective view illustrating a semiconductor memory device according to an example embodiment.

[0038] Referring toFigure 3 The semiconductor storage device 100 includes a stacked region STR and a stepped region SIR. A stacked cell array structure CAR can be located in the stacked region STR, and a stepped structure SIS can be located in the stepped region SIR. The stepped region SIR can be arranged on both sides of the stacked region STR in a first horizontal direction (X direction). For example, a pair of stepped regions SIR can be arranged on both sides of the stacked region STR in the first horizontal direction (X direction). The stepped region SIR arranged on one side of the stacked region STR in the first horizontal direction (X direction) can be referred to as a first stepped region SIR (A), and the stepped region SIR arranged on the other side of the stacked region STR in the first horizontal direction (X direction) can be referred to as a second stepped region SIR (B). The stepped structure SIS can be located in each of the first stepped region SIR (A) and the second stepped region SIR (B).

[0039] The stacked cell array structure CAR can include a plurality of sub-cell arrays SCA. The plurality of sub-cell arrays SCA included in one stacked cell array structure CAR can be arranged in a second horizontal direction (Y direction). Each sub-cell array SCA can include a plurality of bit lines BL, a plurality of word lines WL, and a plurality of memory cells MC. Each memory cell of the plurality of memory cells MC includes a cell transistor CT and an information storage element SP.

[0040] The plurality of word lines WL can extend in the first horizontal direction (X direction). In the stacked cell array structure CAR, the plurality of word lines WL extends in the first horizontal direction (X direction) and can be spaced apart from each other in the second horizontal direction (Y direction) and a vertical direction (Z direction), respectively. The word lines WL in one sub-cell array SCA can be spaced apart from each other in the vertical direction (Z direction).

[0041] The bit line BL can extend in the vertical direction (Z direction) from the substrate 102 (101) in the stacked cell array structure CAR. In the stacked cell array structure CAR, the plurality of bit lines BL can extend in the vertical direction (Z direction) and can be spaced apart from each other in each of the first horizontal direction (X direction) and the second horizontal direction (Y direction). The bit lines BL in one sub-cell array SCA can be spaced apart from each other in the first horizontal direction (X direction). Figure 4A

[0042] One cell transistor CT can be arranged between one word line WL and one bit line BL. The information storage element SP can be connected to the cell transistor CT. The information storage element SP can be a storage element capable of storing data. A gate of the cell transistor CT can be connected to the word line WL, and a source region of the cell transistor CT can be connected to the bit line BL. The information storage element SP can be connected to a drain region of the cell transistor CT. ​

[0043] In some example embodiments, the source region and the drain region of the cell transistor CT and the information storage element SP can be arranged in the second horizontal direction (Y direction) from a bit line BL connected to the source region of the cell transistor CT. Two groups each including the source region and the drain region of the cell transistor CT and the information storage element SP and connected to respective bit lines of two bit lines BL adjacent to each other in the second horizontal direction (Y direction) can be arranged in opposite directions. For example, the source region and the drain region of the cell transistor CT and the information storage element SP connected to one of the two bit lines BL adjacent to each other in the second horizontal direction (Y direction) can be sequentially arranged in the second horizontal direction (Y direction), and the source region and the drain region of the cell transistor CT and the information storage element SP connected to the other of the two bit lines BL adjacent to each other can be arranged in a direction opposite to the second horizontal direction (Y direction). For example, the plurality of bit lines BL can include a first bit line, a second bit line, a third bit line, and a fourth bit line sequentially arranged adjacent to each other in the second horizontal direction (Y direction). The memory cell MC can not be arranged between the first bit line and the second bit line. Two memory cells MC can be arranged in the second horizontal direction (Y direction) between the second bit line and the third bit line at the same vertical level. The memory cell MC can not be arranged between the third bit line and the fourth bit line.

[0044] Each of the plurality of word lines WL can extend in the first horizontal direction (X direction) from the stacked region STR to a pair of stepped regions SIR arranged on both sides of the stacked region STR in the first horizontal direction (X direction). For example, each of the plurality of word lines WL can extend from the first stepped region SIR (A) to the second stepped region SIR (B) via the stacked region STR. The plurality of word lines WL can have a stepped structure. The extension length of the plurality of word lines WL in the first horizontal direction (X direction) can decrease in the vertical direction (Z direction) from the lower side to the upper side. For example, the extension length of a lower word line WL among the plurality of word lines WL spaced apart from each other in the vertical direction (Z direction) in the first horizontal direction (X direction) can be greater than the extension length of an upper word line WL in the first horizontal direction (X direction). For example, the extension length of a lowermost word line WL among the word lines WL stacked in the vertical direction (Z direction) in one subcell array SCA can be greater than the extension length of each of the remaining word lines WL. The extension length of an uppermost word line WL among the word lines WL stacked in the vertical direction (Z direction) in one subcell array SCA can be less than the extension length of each of the remaining word lines WL. A word line pad WLP can be located at both ends of each of the plurality of word lines WL. In one subcell array SCA, a portion of another word line WL can not be located above the word line pad WLP in the vertical direction (Z direction).

[0045] A word line WL can include a pair of word line pads WLP at both ends in the first horizontal direction (X direction). A word line contact WLC can be connected to the word line pad WLP. The word line pad WLP can be connected to the sub word line driver SWD through the word line contact WLC. The lower end of the word line contact WLC can be in contact with the word line pad WLP. Although Figure 3 The top end of the word line contact WLC is shown in contact with the sub word line driver SWD in the middle, but example embodiments are not limited thereto. For example, wiring and / or contacts can be arranged between the top end of the word line contact WLC and the sub word line driver SWD to electrically connect the word line contact WLC and the sub word line driver SWD.

[0046] The staircase structure SIS can include a portion of the plurality of word lines WL extending from the stack region STR to the staircase region SIR, and each word line including a word line pad WLP. The staircase structure SIS located in the first staircase region SIR(A) can be referred to as a first staircase structure, and the staircase structure SIS located in the second staircase region SIR(B) can be referred to as a second staircase structure. The word line pad WLP located in the first staircase region SIR(A) can be referred to as a first word line pad, and the word line pad WLP located in the second staircase region SIR(B) can be referred to as a second word line pad.

[0047] The plurality of sub word line drivers SWD can include the word line pad WLP located in the first staircase region SIR(A). That is, the first sub word line driver SWD(A) can be electrically connected to the first word line pad. The word line pad WLP located in the second staircase region SIR(B) (e.g., the second sub word line driver SWD(B)) can be electrically connected to the second word line pad.

[0048] The plurality of memory cells MC included in the stacked cell array structure CAR located in the stacked region STR can include a first sub-memory cell group SMC(A) adjacent to the first stepped region SIR(A), and a second sub-memory cell group SMC(B) adjacent to the second stepped region SIR(B). Each memory cell MC included in the first sub-memory cell group SMC(A) can be electrically connected to the first sub-word line driver SWD(A) through the word line WL. Each memory cell MC included in the second sub-memory cell group SMC(B) can be electrically connected to the second sub-word line driver SWD(B) through the word line WL. That is, the first sub-word line driver SWD(A) can activate the word line WL connected to the memory cell MC included in the first sub-memory cell group SMC(A) to select the memory cell MC included in the first sub-memory cell group SMC(A) together with the bit line BL, and the second sub-word line driver SWD(B) can activate the word line WL connected to the memory cell MC included in the second sub-memory cell group SMC(B) to select the memory cell MC included in the second sub-memory cell group SMC(B) together with the bit line BL.

[0049] The semiconductor memory device 100 according to the present inventive concept includes a pair of word line pads WLP located at both ends of one word line WL in a first horizontal direction (X direction), and includes a pair of sub-word line drivers SWD (e.g., a first sub-word line driver SWD(A) and a second sub-word line driver SWD(B)) electrically connected to the pair of word line pads WLP, so that the number of memory cells MC arranged in the first horizontal direction (X direction) in one stacked region STR can be increased. Accordingly, the integration of the semiconductor memory device 100 can be increased.

[0050] Figure 4A 、 Figure 4B and Figure 4C are a perspective view and a cross-sectional view of a portion of a semiconductor memory device according to an example embodiment. Specifically, Figure 4A is an enlarged perspective view showing a portion IVA of Figure 3 , Figure 4B is a cross-sectional view taken along line B-B' of Figure 3 , and Figure 4C is a cross-sectional view taken along line C-C' of Figure 3 .

[0051] Referring to Figure 4A to Figure 4C together, the semiconductor memory device 100 includes a lower structure LST and an upper structure UST stacked on the lower structure LST. The lower structure LST and the upper structure UST can be referred to as a first structure and a second structure, or a cell structure and a peripheral circuit structure, respectively.

[0052] The lower structure LST has a stacked region STR and a stepped region SIR. The stepped region SIR arranged on one side of the stacked region STR in the first horizontal direction (X direction) can be referred to as a first stepped region SIR (A), and the stepped region SIR arranged on the other side of the stacked region STR in the first horizontal direction (X direction) can be referred to as a second stepped region SIR (B). The lower structure LST includes the substrate 102, and the subcell array SCA arranged in the stacked region STR and the stepped structure SIS arranged in the stepped region SIR on the substrate 102. The stepped structure SIS located in the first stepped region SIR (A) can be referred to as a first stepped structure, and the stepped structure SIS located in the second stepped region SIR (B) can be referred to as a second stepped structure.

[0053] The subcell array SCA can include the substrate 102, a plurality of word lines WL spaced apart from a main surface 102M of the substrate 102 and arranged on the substrate 102, a plurality of bit lines BL extending from the main surface 102M of the substrate 102 in a vertical direction (Z direction), a plurality of cell transistors CT arranged between the plurality of word lines WL and the plurality of bit lines BL, and a plurality of information storage elements SP connected to the plurality of cell transistors CT, respectively. The cell transistors CT and the information storage elements SP can constitute a memory cell MC.

[0054] The substrate 102 can include, for example, silicon (Si) such as crystalline Si, polycrystalline Si, or amorphous Si. In some example embodiments, the substrate 102 can include at least one compound semiconductor selected from among semiconductor elements such as germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In some example embodiments, the substrate 102 can include a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GeOI) substrate. For example, the substrate 102 can include a buried oxide layer (BOX). The substrate 102 can include a conductive region (e.g., an impurity-doped well, or an impurity-doped structure).

[0055] The plurality of word lines WL extend on the substrate 102 in the first horizontal direction (X direction), and can be spaced apart from each other in the vertical direction (Z direction). The plurality of bit lines BL extend from the substrate 102 in the vertical direction (e.g., Z direction), and can be spaced apart from each other in the first horizontal direction (X direction).

[0056] One cell transistor CT can be arranged between one word line WL and one bit line BL. The information storage element SP can be connected to the cell transistor CT. The cell transistor CT and the information storage element SP can be sequentially arranged in the second horizontal direction (Y direction) from the bit line BL connected to the cell transistor CT.

[0057] The word line WL can be adjacent to the semiconductor pattern 110. In some embodiments, the word line WL can surround the semiconductor pattern 110. The gate dielectric layer 132 can be disposed between the word line WL and the semiconductor pattern 110. The word line WL and the gate dielectric layer 132 can constitute a word line structure WLS. The semiconductor pattern 110 and the word line structure WLS can constitute a unit transistor CT.

[0058] The semiconductor pattern 110 can include a source region SD1, a drain region SD2, and a channel region CH disposed between the source region SD1 and the drain region SD2. The source region SD1 can be connected to the bit line BL, and the drain region SD2 can be connected to the information storage element SP. The source region SD1, the channel region CH, and the drain region SD2 can be sequentially disposed in the second horizontal direction (Y direction) from the bit line BL. In some example embodiments, the semiconductor pattern 110 can penetrate the word line WL. For example, the channel region CH can be a portion of the semiconductor pattern 110 that penetrates the word line WL.

[0059] In some example embodiments, the semiconductor pattern 110 can include a material having the same or similar etching characteristics as the etching characteristics of the substrate 102, or can include the same material as the substrate 102. In some example embodiments, the semiconductor pattern 110 can include Si. In some example embodiments, the semiconductor pattern 110 can include a single-crystal semiconductor material. For example, the semiconductor pattern 110 can include a single-crystal Si. In some other example embodiments, the semiconductor pattern 110 can include a two-dimensional (2D) semiconductor material or a semiconductor oxide material. For example, the 2D semiconductor material can include MoS2, WSe2, graphene, carbon nanotube, or a combination thereof. For example, the oxide semiconductor material can include In x Ga y Zn z O, In x Ga y Si z O, In x Sn y Zn z O, In x Zn y O, Zn x O, Zn x Sn y O, Zn x O y N, Zr x Zn y Sn z O, Sn x O, Hf x In y Zn z O, Ga xZn y Sn z O, Al x Zn y Sn z O, Yb x Ga y Zn z O, In x Ga y O or combinations thereof. For example, the semiconductor pattern 110 can include a single layer or multiple layers of an oxide semiconductor material. In some example embodiments, the semiconductor pattern 110 can include a material having a band gap energy greater than that of silicon. For example, the semiconductor pattern 110 can include a material having a band gap energy of about 1.5 eV to about 5.6 eV. For example, each semiconductor pattern 110 can include a material capable of having optimal or desired channel performance when having a band gap energy of about 2.0 eV to about 4.0 eV.

[0060] A first impurity having a first conductivity type can be implanted into the source region SD1 and the drain region SD2 of the semiconductor pattern 110, and a second impurity having a second conductivity type different from the first conductivity type can be implanted into the channel region CH. In some example embodiments, the first conductivity type can be n-type, and the second conductivity type can be p-type.

[0061] In some example embodiments, the word line WL can include a conductive barrier layer covering the gate dielectric layer 182, and a conductive fill layer covering the conductive barrier layer. The conductive barrier layer can include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or combinations thereof. For example, the conductive barrier layer can include TiN. The conductive fill layer can include doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or combinations thereof. In some example embodiments, the conductive fill layer can include W.

[0062] The gate dielectric layer 132 can include at least one selected from silicon oxide, a high-k dielectric material having a dielectric constant higher than that of silicon oxide, and a ferroelectric material. In some example embodiments, the gate dielectric layer 132 can have a stacked structure of a first dielectric layer made of silicon oxide and a second dielectric layer made of at least one selected from the high-k dielectric material and the ferroelectric material. For example, the high-k dielectric material and the ferroelectric material include at least one selected from hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanate (PZT), strontium bismuth tantalum oxide (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0063] The bit line BL can be composed of a conductive barrier layer in contact with one end (e.g., the source region SD1) of the semiconductor pattern 110, and a conductive fill layer covering the conductive barrier layer. The conductive barrier layer can include, for example, a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. For example, the conductive barrier layer can include TiN. The conductive fill layer can include doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TaAlN, TaSiN, or a combination thereof. In some example embodiments, the conductive fill layer can include W.

[0064] In some example embodiments, the information storage element SP can be a capacitor 150 including a first electrode 152, a second electrode 156, and a capacitor dielectric layer 154 disposed between the first electrode 152 and the second electrode 156. The capacitor 150 can include the first electrode 152 connected to the drain region SD2 of the semiconductor pattern 110 and extending in the second horizontal direction (Y direction), the capacitor dielectric layer 154 covering the first electrode 152, and the second electrode 156 covering the capacitor dielectric layer 154. The second electrode 156 can be connected to the ground line PP shown, or can be a part of the ground line PP. The first electrode 152 and the second electrode 156 can be referred to as a lower electrode and an upper electrode, respectively. The capacitor dielectric layer 154 can be disposed between the first electrode 152 and the second electrode 156. Figure 1 The first electrode 152 and the second electrode 156 can be referred to as a lower electrode and an upper electrode, respectively. The capacitor dielectric layer 154 can be disposed between the first electrode 152 and the second electrode 156.

[0065] The first electrode 152 can include a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. In some example embodiments, the first electrode 152 can include a high melting point metal layer such as cobalt, titanium, nickel, tungsten, and molybdenum. For example, the first electrode 152 can include a metal nitride layer such as a titanium nitride layer, a titanium silicon nitride layer, a titanium aluminum nitride layer, a tantalum nitride layer, a tantalum silicon nitride layer, a tantalum aluminum nitride layer, and a tungsten nitride layer.

[0066] The capacitor dielectric layer 154 can include at least one selected from a high-k dielectric material having a dielectric constant higher than that of silicon oxide, and a ferroelectric material. For example, the capacitor dielectric layer 154 can include at least one of a metal oxide or a dielectric material having a perovskite structure. For example, the capacitor dielectric layer 154 includes at least one material selected from hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanate (PZT), strontium bismuth tantalum oxide (STB), bismuth iron oxide (BFO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

[0067] The second electrode 156 can include doped silicon, Ru, RuO, Pt, PtO, Ir, IrO, SRO (SrRuO), BSRO ((Ba,Sr)RuO), CRO (CaRuO), BaRuO, La(Sr,Co)O, Ti, TiN, W, WN, Ta, TaN, TiAlN, TiSiN, TiAlN, TaSiN, or a combination thereof. In some example embodiments, the second electrode 156 can include W. Although Figure 3 to Figure 4C Although a plurality of information storage elements SP are shown as being spaced apart from each other, example embodiments are not limited thereto. In some example embodiments, when the plurality of information storage elements SP are a plurality of capacitors 150, a plurality of second electrodes 156 of the plurality of capacitors 150 included in each of a pair of subcell arrays SCA adjacent in a second horizontal direction (Y direction) can be connected to each other to form an integral body. In some example embodiments, when the plurality of information storage elements SP are a plurality of capacitors 150, and when a plurality of second electrodes 156 of the plurality of capacitors 150 included in each of a pair of subcell arrays SCA adjacent in a second horizontal direction (Y direction) face and are adjacent to each other, the plurality of second electrodes 156 of the plurality of capacitors 150 included in each of the pair of subcell arrays SCA can be connected to each other to form an integral body.

[0068] Each of the plurality of word lines WL can extend in the first horizontal direction (X direction) from the stacked region STR to a pair of stepped regions SIR arranged on both sides of the stacked region STR in the first horizontal direction (X direction). For example, each of the plurality of word lines WL can extend from the first stepped region SIR (A) to the second stepped region SIR (B) via the stacked region STR. The plurality of word lines WL can have a stepped structure. The extension length of the plurality of word lines WL in the first horizontal direction (X direction) can decrease from the lower side to the upper side in the vertical direction (Z direction). The word line pads WLP can be located at both ends of each of the plurality of word lines WL. In one subcell array SCA, a portion of another word line WL can not be located above the word line pad WLP in the vertical direction (Z direction).

[0069] The stepped structure SIS can include the word line pads WLP, respectively, and can include portions of the plurality of word lines WL extending from the stacked region STR to the stepped regions SIR. The word line pads WLP located in the first stepped region SIR (A) can be referred to as first word line pads, and the word line pads WLP located in the second stepped region SIR (B) can be referred to as second word line pads. One word line WL can include a pair of word line pads WLP at both ends in the first horizontal direction (X direction). The word line contacts WLC can be connected to the word line pads WLP.

[0070] When the word line contacts WLC are connected to the corresponding word lines WL included in one subcell array SCA in one stepped region SIR, respectively, the extension length of the word line contacts WLC arranged in the one stepped region SIR in the vertical direction (Z direction) can be different from each other. Among the word line contacts WLC arranged in one stepped region SIR, the extension length of the word line contacts WLC located relatively far from the stacked regions STR adjacent in the first horizontal direction (X direction) in the vertical direction (Z direction) can be greater than the extension length of the word line contacts WLC located relatively close to each other in the vertical direction (Z direction). The extension length of the word line contacts WLC in the vertical direction (Z direction) can increase away from the stacked regions STR in the first horizontal direction (X direction). The word line contacts WLC can include a metal, a conductive metal nitride, a conductive metal silicide, or a combination thereof. The first landing pad portions LP can be connected to the top ends of the word line contacts WLC.

[0071] The first insulating structure 190 can cover the subcell array SCA and the stepped structure SIS on the substrate 102. The first insulating structure 190 can surround the plurality of word lines WL, the plurality of word line contacts WLC, and the plurality of first landing pad portions LP. The top surface of the first landing pad portions LP and the top surface of the first insulating structure 190 can be arranged on the same plane.

[0072] In some example embodiments, the first insulating structure 190 can include an insulating material, which can include silicon oxide, silicon nitride, a low-k dielectric material, or a combination thereof. A low-k dielectric material is a material having a dielectric constant lower than that of silicon oxide, and can include, for example, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorosilicate glass (FSG), organosilicate glass (OSG), spin-on glass (SOG), spin-on polymer, or a combination thereof. In some example embodiments, the first insulating structure 190 can include an ultra-low-k (ULK) layer having an ultra-low dielectric constant k of about 2.2 to about 2.4. The ULK layer can include SiOC or SiCOH. The first landing pad portion LP can include a conductive material, which can include copper (Cu), gold (Au), silver (Ag), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), or a combination thereof.

[0073] The upper structure UST can include a peripheral circuit board 202, a second insulating structure 290 covering a lower portion of the peripheral circuit board 202, a plurality of sub word line drivers SWD disposed between the peripheral circuit board 202 and the second insulating structure 290, a plurality of interconnect structures 210 connected to the plurality of sub word line drivers SWD, and a plurality of second landing pad portions UP connected to lower ends of the plurality of interconnect structures 210. The second insulating structure 290 can surround the plurality of interconnect structures 210 and the plurality of second landing pad portions UP. A bottom surface of the second landing pad portions UP and a bottom surface of the second insulating structure 290 can be disposed on the same plane. The plurality of interconnect structures 210 can respectively electrically connect the plurality of sub word line drivers SWD to the plurality of second landing pad portions UP. The peripheral circuit board 202, the second landing pad portions UP, and the second insulating structure 290 can respectively include the same or similar materials as the substrate 102, the first landing pad portions LP, and the first insulating structure 190. Although Figure 4B It is shown that each of the plurality of interconnect structures 210 includes only a contact portion, but example embodiments are not limited thereto. For example, each of the plurality of interconnect structures 210 can include at least one wiring layer and at least one contact portion.

[0074] The upper structure UST can be bonded to the lower structure LST by bringing the second insulating structure 290 into contact with the first insulating structure 190 and bringing the plurality of second bonding pad portions UP into contact with the plurality of first bonding pad portions LP in correspondence with each other. In some example embodiments, the lower structure LST and the upper structure UST can be bonded to each other by a metal oxide hybrid bonding method, and accordingly, the plurality of word lines WL included in the lower structure LST can be electrically connected to the plurality of sub word line drivers SWD included in the upper structure UST. For example, the plurality of first bonding pad portions LP and the plurality of second bonding pad portions UP in correspondence with each other, after being thermally expanded and brought into contact with each other, can become diffusively bonded to be integrated into a plurality of bonding pads BP by diffusion of contained metal atoms. For example, the first insulating structure 190 and the second insulating structure 290 can be bonded to each other by forming covalent bonds. Among the plurality of bonding pads BP, a lower portion surrounded by the first insulating structure 190 can be a first bonding pad portion LP, and an upper portion surrounded by the second insulating structure 290 can be a second bonding pad portion UP.

[0075] A word line WL can include a pair of word line pads WLP at both ends in the first horizontal direction (X direction). A word line contact WLC can be connected to a word line pad WLP. A word line WL can be connected to a pair of sub word line drivers SWD through a pair of word line contacts WLC, a pair of bonding pads BP, and a pair of interconnector structures 210, respectively. The pair of word line contacts WLC, the pair of bonding pads BP, and the pair of interconnector structures 210 are connected to the pair of word line pads WLP, respectively.

[0076] The plurality of sub word line drivers SWD can include a first sub word line driver SWD(A) electrically connected to a first word line pad in the first stepped region SIR(A), and a second sub word line driver SWD(B) electrically connected to a second word line pad in the second stepped region SIR(B).

[0077] The plurality of memory cells MC located in the stacked region STR can include a first sub memory cell group SMC(A) adjacent to the first stepped region SIR(A), and a second sub memory cell group SMC(B) adjacent to the second stepped region SIR(B). Each memory cell MC included in the first sub memory cell group SMC(A) can be electrically connected to the first sub word line driver SWD(A) through a word line WL. Each memory cell MC included in the second sub memory cell group SMC(B) can be electrically connected to the second sub word line driver SWD(B) through a word line WL.

[0078] The semiconductor memory device 100 according to some example embodiments can include a pair of word line pads WLP located at both ends of one word line WL in a first horizontal direction (X direction), and include a pair of sub word line drivers SWD (i.e., a first sub word line driver SWD(A) and a second sub word line driver SWD(B)) electrically connected to the pair of word line pads WLP, respectively, so that the number of memory cells MC arranged in the first horizontal direction (X direction) can be increased. Accordingly, the integration of the semiconductor memory device 100 can be increased.

[0079] Figure 5 is a plan layout diagram illustrating a semiconductor memory device according to example embodiments.

[0080] Referring to Figure 5 , the semiconductor memory device 100 includes a plurality of stack regions STR, a plurality of staircase regions SIR, and a plurality of isolation insulating regions ISR. A stack cell array structure CAR can be arranged in each stack region STR. The plurality of stack regions STR are arranged to be spaced apart from each other in a first horizontal direction (X direction). A pair of staircase regions SIR can be arranged at both ends of the stack regions STR in the first horizontal direction (X direction). The pair of staircase regions SIR arranged at both ends of the stack regions STR in the first horizontal direction (X direction) can include a first staircase region SIR(A) arranged at one side of the stack regions STR in the first horizontal direction (X direction), and a second staircase region SIR(B) arranged at the other side of the stack regions STR in the first horizontal direction (X direction). The stack cell array structure CAR can include a first sub memory cell group SMC(A) adjacent to the first staircase region SIR(A), and a second sub memory cell group SMC(B) adjacent to the second staircase region SIR(B). A staircase structure SIS can be arranged in each of the staircase regions SIR(A) and SIR(B). An isolation insulating structure ISO can be arranged in each isolation insulating region ISR. The isolation insulating region ISR can be arranged between a pair of staircase regions SIR arranged between a pair of stack regions STR adjacent to each other in the first horizontal direction (X direction) (i.e., between the second staircase region SIR(B) and the first staircase region SIR(A)).

[0081] In the semiconductor memory device 100 according to some example embodiments, because the pair of staircase regions SIR are arranged at both ends of the stack regions STR in the first horizontal direction (X direction), the horizontal width of the stack regions STR in the first horizontal direction (X direction) can be increased, and thus the number of the isolation insulating regions ISR in which the isolation insulating structure ISO is arranged can be relatively reduced. Accordingly, the integration of the semiconductor memory device 100 can be increased.

[0082] Figure 6 is a plan layout diagram illustrating a semiconductor memory device according to an example embodiment.

[0083] Referring to Figure 6 , the semiconductor memory device 100 includes a stacked region STR and a stepped region SIR. A stacked cell array structure CAR can be located in the stacked region STR, and a stepped structure SIS can be located in the stepped region SIR. The stacked cell array structure CAR can include a plurality of sub-cell arrays SCA. The stepped region SIR can be arranged on both sides of the stacked region STR in a first horizontal direction (X direction). The pair of stepped regions SIR arranged on both ends of the stacked region STR in the first horizontal direction (X direction) can include a first stepped region SIR (A) arranged on one side of the stacked region STR in the first horizontal direction (X direction), and a second stepped region SIR (B) arranged on the other side of the stacked region STR in the first horizontal direction (X direction). The stacked cell array structure CAR can include a first sub-memory cell group SMC (A) adjacent to the first stepped region SIR (A), and a second sub-memory cell group SMC (B) adjacent to the second stepped region SIR (B).

[0084] The sub-cell array SCA can include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged between the plurality of word lines WL and the plurality of bit lines BL, each memory cell MC including a cell transistor CT and an information storage element SP.

[0085] The plurality of word lines WL extend in the first horizontal direction (X direction), and can be spaced apart from each other in a vertical direction (Z direction). The plurality of word lines WL can include a first word line WL1, …, an (n-2)th word line WLn-2, an (n-1)th word line WLn-1, and an nth word line WLn arranged to be spaced apart from each other in the vertical direction (Z direction) from a lower side to an upper side. A pair of sub-word line drivers SWD can be connected to each of the first word line WL1, …, the (n-2)th word line WLn-2, the (n-1)th word line WLn-1, and the nth word line WLn.

[0086] The first stepped region SIR (A) and the first sub-memory cell group SMC (A) can be referred to as a first sub-region A, and the second stepped region SIR (B) and the second sub-memory cell group SMC (B) can be referred to as a second sub-region B. The memory cells MC included in the first sub-region A can be selected by the sub-word line drivers SWD connected to the word lines WL through the first stepped region SIR (A), and the memory cells MC included in the second sub-region B can be selected by the sub-word line drivers SWD connected to the word lines WL through the second stepped region SIR (B). That is, the first sub-region A and the second sub-region B can operate like separate stacked cell array structures.

[0087] In the semiconductor storage device 100 according to some example embodiments, because the memory cells MC included in two or more stacked cell array structures can be configured as one stacked cell array structure CAR, the integration of the semiconductor storage device 100 can be increased.

[0088] Figure 7 is a equivalent circuit diagram illustrating a stacked cell array of a semiconductor storage device according to example embodiments.

[0089] Referring to Figure 7 The stacked cell array structure CAR of the semiconductor storage device 2 according to example embodiments can include a plurality of sub-cell arrays SCA. Each sub-cell array SCA can include a plurality of bit lines BLa, a plurality of word lines WL, and a plurality of memory cells MC. Each memory cell of the plurality of memory cells MC includes a cell transistor CT and an information storage element SP. One cell transistor CT can be arranged between one word line WL and one bit line BLa.

[0090] The plurality of word lines WL can extend in a first horizontal direction (X direction). The word lines WL in one sub-cell array SCA can be spaced apart from each other in a vertical direction (Z direction). The bit lines BLa can extend from the substrate 102 in the vertical direction (Z direction). The bit lines BLa in one sub-cell array SCA can be spaced apart from each other in the first horizontal direction (X direction). The gate of the cell transistor CT can be connected to the word line WL, and the source region of the cell transistor CT can be connected to the bit line BLa. The information storage element SP can be connected to the drain region of the cell transistor CT.

[0091] Two sub-cell arrays SCA adjacent to each other in a second horizontal direction (Y direction) can share a bit line BLa. The source region of the cell transistor CT included in each of the two sub-cell arrays SCA can be connected to the bit line BLa shared by the two sub-cell arrays SCA. The source region and the drain region of the cell transistor CT and the information storage element SP of each of the two sub-cell arrays SCA can be arranged in opposite directions from the respective bit line BLa shared by the two sub-cell arrays SCA. For example, the source region and the drain region of the cell transistor CT and the information storage element SP of one sub-cell array SCA connected to one bit line BLa shared by the two sub-cell arrays SCA can be sequentially arranged in the second horizontal direction (Y direction), and the source region and the drain region of the cell transistor CT and the information storage element SP connected to the other sub-cell array SCA can be arranged in a direction opposite to the second horizontal direction (Y direction).

[0092] Figure 8is a plan layout diagram illustrating a semiconductor memory device according to an example embodiment.

[0093] Referring to Figure 8 The semiconductor memory device 200 includes a stacked region STR and a stepped region SIR. A stacked cell array structure CAR can be located in the stacked region STR, and a stepped structure SIS can be located in the stepped region SIR. The stacked cell array structure CAR can include a plurality of sub-cell arrays SCA. The stepped region SIR can be disposed on both sides of the stacked region STR in a first horizontal direction (X direction). The pair of stepped regions SIR disposed on both ends of the stacked region STR in the first horizontal direction (X direction) can include a first stepped region SIR (A) disposed on one side of the stacked region STR in the first horizontal direction (X direction), and a second stepped region SIR (B) disposed on the other side of the stacked region STR in the first horizontal direction (X direction). The stacked cell array structure CAR can include a first sub-memory cell group SMC (A) adjacent to the first stepped region SIR (A), and a second sub-memory cell group SMC (B) adjacent to the second stepped region SIR (B).

[0094] The sub-cell array SCA can include a plurality of word lines WL, a plurality of bit lines BLa, and a plurality of memory cells MC disposed between the plurality of word lines WL and the plurality of bit lines BLa, each memory cell MC including a cell transistor CT and an information storage element SP. Two sub-cell arrays SCA adjacent to each other in a second horizontal direction (Y direction) can share a bit line BLa. Source regions of the cell transistors CT included in each of the two sub-cell arrays SCA can be connected to the bit line BLa shared by the two sub-cell arrays SCA.

[0095] The plurality of word lines WL extend in the first horizontal direction (X direction), and can be spaced apart from each other in a vertical direction (Z direction). The plurality of word lines WL can include a first word line WL1, …, an (n-2)th word line WLn-2, an (n-1)th word line WLn-1, and an nth word line WLn disposed spaced apart from a lower side to an upper side in the vertical direction (Z direction). A pair of sub-word line drivers SWD can be connected to each of the first word line WL1, …, the (n-2)th word line WLn-2, the (n-1)th word line WLn-1, and the nth word line WLn.

[0096] The memory cells MC included in the first sub-region A can be selected by the sub-word line drivers SWD connected to the word lines WL through the first stepped region SIR (A), and the memory cells MC included in the second sub-region B can be selected by the sub-word line drivers SWD connected to the word lines WL through the second stepped region SIR (B).

[0097] Figure 9 is a block diagram illustrating a row decoder included in a semiconductor memory device according to an example embodiment. Specifically, Figure 9 is a block diagram illustrating Figure 2 a row decoder 724 of FIG. 7.

[0098] Referring to Figure 9 , the row decoder 724 can select a word line WL corresponding to a row address RA. As Figure 4B indicated, the row decoder 724 can be disposed on an upper structure UST. In the present example embodiment, the row decoder 724 selects 512 word lines according to a signal configuration of nine row addresses RA<0:8>, but the example embodiment is not limited thereto, and various numbers of word lines can be selected. For example, the row decoder 724 can select 1024 or 2048 word lines WL according to a signal configuration of 10 row addresses RA<0:9> or 11 row addresses RA<0:10>.

[0099] The row decoder 724 can include a main word line driver circuit 610 and a sub word line driver circuit 620. The main word line driver circuit 610 can include a first main word line drive signal generation circuit NWE0 DRV 611 and a second main word line drive signal generation circuit NWE1 DRV 612, and a first sub word line drive signal generation circuit PXID DRV 613 and a second sub word line drive signal generation circuit PXIB DRV 614. The main word line driver circuit 610 can generate a first main word line drive signal NWEIB0<0:7> and a second main word line drive signal NWEIB1<0:7> based on a signal of a most significant bit (MSB) group among the row addresses RA<0:8>. Among the row address RA<0:8> signals, the MSB group signal can be configured as RA<3:8> row addresses. The RA<3:8> row addresses can be divided into a high bit group RA<6:8> row address (hereinafter referred to as "RA678") and a low bit group RA<3:5> row address (hereinafter referred to as "RA345").

[0100] In some example embodiments, the first main word line drive signal generation circuit 611 can generate the first main word line drive signals NWEIB0<0:7> according to decoding the RA678 row address, and the second main word line drive signal generation circuit 612 can generate the second main word line drive signals NWEIB1<0:7> according to decoding the RA345 row address. The main word line driver circuit 610 of the present embodiment divides the MSB signals RA<3:8> of the row address RA<0:8> into two groups (e.g., RA678 and RA345), and generates eight first main word line drive signals NWEIB0<0:7> and eight second main word line drive signals NWEIB1<0:7> based on the two groups, respectively. In other example embodiments, the main word line driver circuit 610 can vary the decoding of generating a plurality of main word line drive signals NWEIBn-1 (where n is a natural number) based on different bit numbers (e.g., 5, 6, and 7) of the MSB group signals of the row address signals according to the configuration of various numbers (e.g., 1024 and 2048) of word lines.

[0101] The second main word line drive signal generation circuit 612 can include eight second main word line drive signal generation circuits that output each of the second main word line drive signals NWEIB1<0:7> in response to the decoded RA345<0:7> row address signal. Since there are eight configurations (e.g., 000, 001, 010, 011, 100, 101, 110, and 111) of the decoded RA345<0:7> row address signal, there can also be eight second main word line drive signals NWEIB1<0:7> to be activated. That is, any one of NWEIB1<0>, NWEIB1<1>, NWEIB1<2>, NWEIB1<3>, NWEIB1<4>, NWEIB1<5>, NWEIB1<6>, and NWEIB1<7> can be activated to a logic low level according to the decoded RA345<0:7> row address signal. The second main word line drive signal NWEIB1<0:7> having a logic low level can have a ground voltage VSS level, and can be provided to the sub word line driver circuit 620 connected with each of the storage blocks BLK1 to BLKi.

[0102] The main word line driver circuit 610 can generate the first sub word line driving signals PXID<0:7> and the second sub word line driving signals PXIB<0:7> based on a signal of a least significant bit (LSB) group among the row address RA<0:8> signals. Among the row address RA<0:8> signals, the LSB group signal can be set as the RA<0:2> row address (hereinafter referred to as "RA012"). The main word line driver circuit 610 can include a first sub word line driving signal generation circuit 613 for generating the first sub word line driving signals PXID<0:7> according to decoding of the RA012 row address, and a second sub word line driving signal generation circuit 614 for generating the second sub word line driving signals PXIB<0:3> according to decoding of the RA012 row address.

[0103] Although the main word line driver circuit 610 of the present example embodiment generates eight first sub word line driving signals PXID<0:3> and eight second sub word line driving signals PXIB<0:3> based on the LSB signals RA<0:2> of the row address signals RA<0:8>, respectively, this is merely an example for understanding and is not intended to limit the inventive concept.

[0104] The first sub word line driving signal generation circuit 613 can include eight first main word line driving signal generation circuits that output each of the first sub word line driving signals PXID<0:7> in response to the decoded RA012<0:2> row address signals. Since there are eight configurations (for example, 000, 001, 010, 011, 100, 101, 110, and 111) of the decoded RA012<0:2> row address signals, there can also be eight first sub word line driving signals PXID<0:7> to be activated. That is, according to the decoded RA012<0:7> row address signals, any one of the PXID<0>, PXID<1>, PXID<2>, PXID<3>, PXID<4>, PXID<5>, PXID<6>, and PXID<7> signals can be activated to a logic high level. The first sub word line driving signals PXID<0:7> having the logic high level can have a high voltage VPP level, and can be provided to the sub word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.

[0105] The second sub word line drive signal generation circuit 614 can include eight second sub word line drive signal generation circuits that output each of the second sub word line drive signals PXIB<0:7> in response to the decoded RA012<0:2> row address signal. Since there are eight configurations (e.g., 000, 001, 010, 011, 100, 101, 110, and 111) of the decoded RA012<0:2> row address signal, there can also be eight second sub word line drive signals PXIB<0:7> to be activated. That is, any one of PXIB<0>, PXIB<1>, PXIB<2>, PXIB<3>, PXIB<4>, PXIB<5>, PXIB<6>, and PXIB<7> can be activated to a logic low level according to the decoded RA012<0:2> row address signal. The second sub word line drive signal PXIB<0:7> having the logic low level can have a ground voltage VSS level and can be provided to the sub word line driver circuit 620 connected to each of the memory blocks BLK1 to BLKi.

[0106] The sub word line driver circuit 620 can include a first sub word line driver SWD(A) and a second sub word line driver SWD(B). Each of the plurality of word lines WL<0:511> can be connected to a first sub memory cell group SMC(A) and a second sub memory cell group SMC(B) located in a stack region STR. The first sub word line driver SWD(A) can be connected to the word line WL through a first stair region SIR(A), and the second sub word line driver SWD(B) can be connected to the word line WL through a second stair region SIR(B). The word line WL selected by the first sub word line driver SWD(A) from among the plurality of word lines WL<0:511> can select the first sub memory cell group SMC(A), and the word line WL selected by the second sub word line driver SWD(B) can select the second sub memory cell group SMC(B). That is, one word line WL is connected to a pair of sub word line drivers 620 including the first sub word line driver SWD(A) and the second sub word line driver SWD(B). The first sub memory cell group SMC(A) connected to one word line WL can be selected by the first sub word line driver SWD(A), and the second sub memory cell group SMC(B) can be selected by the second sub word line driver SWD(B).

[0107] Figure 10 is a circuit diagram illustrating Figure 9 the sub word line driver circuit 620.

[0108] Referring to Figure 10The sub word line driver circuit 620 can include the first to fifth transistors 1001, 1002, 1003, 1004, and 1006. The first transistor 1001 and the second transistor 1002 can be connected in series between the first sub word line driving signal PXID<0:7> and a connection node 1005 of the second transistor 1002 to the fourth transistor 1004. The gate of the first transistor 1001 is connected with the first main word line driving signal NWEIB0<0:7>, and the gate of the second transistor 1002 is connected with the second main word line driving signal NWEIB1<0:7>. The third transistor 1003 and the fourth transistor 1004 are connected in parallel between the connection node 1005 of the second transistor 1002 to the fourth transistor 1004 and the negative voltage VBB line. The gate of the third transistor 1003 is connected with the second main word line driving signal NWEIB1<0:7>, and the gate of the fourth transistor 1004 is connected with the first main word line driving signal NWEIB0<0:7>. The fifth transistor 1006 can be configured as an NMOS transistor, in which the negative voltage VBB line is connected to the source, the connection node 1005 of the second transistor 1002 to the fourth transistor 1004 is connected to the drain, and the second sub word line driving signal PXIB<0:7> is applied to the gate. The connection node 1005 of the second transistor 1002 to the fourth transistor 1004 can be connected to the plurality of word lines WL<0:511> of the storage blocks BLK1 to BLKi. The first to fourth transistors 1001 to 1004 of the sub word line driver circuit 620 can be implemented as a NOR logic circuit.

[0109] The sub word line driver circuit 620 can include 512 sub word line driver circuits connected with the plurality of word lines WL<0:511> in response to the first main word line driving signal NWEIB0<0:7>, the second main word line driving signal NWEIB1<0:7>, the first sub word line driving signal PXID<0:7>, and the second sub word line driving signal PXIB<0:7>, respectively. The sub word line driver circuit 620 can select one of the plurality of word lines WL<0:511> to be activated as a logic high level in response to a logic low level of the first main word line driving signal NWEIB0<0:7> being activated, a logic low level of the second main word line driving signal NWEIB1<0:7> being activated, a logic high level of the first sub word line driving signal PXID<0:7> being activated, and a logic low level of the second sub word line driving signal PXIB<0:7> being activated. The word line selected from the plurality of word lines WL<0:511> can be activated as a high voltage level of the first sub word line driving signal PXID<0:7> having a logic high level.

[0110] Any of the functional blocks shown in the drawings and described above can be implemented in processing circuitry, such as hardware including logic circuitry, hardware / software combinations such as a processor executing software, or combinations thereof. For example, more specifically, processing circuitry can include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable gate array (FPGA), a system on a chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), or the like.

[0111] While the present concept has been particularly shown and described with reference to some example embodiments thereof, it will be understood by those skilled in the art that various changes in form and details can be made therein without departing from the spirit and scope of the claims.

Claims

1. A semiconductor memory device comprising: a substrate including a stacked region, the stacked region including a first stepped region and a second stepped region, the first stepped region and the second stepped region being located at both ends of the stacked region in a first horizontal direction, respectively; a plurality of word lines each extending in the first horizontal direction toward each of the first stepped region and the second stepped region in the stacked region, the plurality of word lines being spaced apart from each other in a vertical direction; a plurality of bit lines extending in the vertical direction in the stacked region, the plurality of bit lines being spaced apart from each other in the first horizontal direction; a plurality of memory cells between the plurality of word lines and the plurality of bit lines in the stacked region; a first word line contact connected to each of the plurality of word lines in the first stepped region; a second word line contact connected to each of the plurality of word lines in the second stepped region; and a first sub-word line driver and a second sub-word line driver connected to the first word line contact and the second word line contact, respectively. Each of the plurality of word lines is electrically connected to the first sub-word line driver through the first word line contact, and is electrically connected to the second sub-word line driver through the second word line contact.

2. The semiconductor memory device according to claim 1, wherein, Each of the plurality of memory cells includes a cell transistor and an information storage element, wherein the cell transistor includes a semiconductor pattern extending from each of the plurality of bit lines in a second horizontal direction different from the first horizontal direction.

3. The semiconductor memory device according to claim 1, wherein, The semiconductor pattern includes:

4. The semiconductor memory device according to claim 3, wherein, a source region connected to each of the plurality of bit lines; a channel region; and a drain region connected to the information storage element, wherein the source region, the channel region, and the drain region are sequentially arranged from each of the plurality of bit lines in the second horizontal direction. The information storage element includes a capacitor including a first electrode connected to the drain region, a capacitor dielectric layer covering the first electrode, and a second electrode covering the capacitor dielectric layer.

5. The semiconductor memory device according to claim 4, wherein, 6. The semiconductor memory device according to claim 4, wherein the semiconductor pattern passes through each of the plurality of word lines, and the channel region is a portion of the semiconductor pattern that passes through each of the plurality of word lines. Among the plurality of memory cells, a memory cell adjacent to the first stepped region is configured to be selected by the first sub-word line driver, and other memory cells adjacent to the second stepped region are configured to be selected by the second sub-word line driver.

7. The semiconductor memory device according to claim 1, wherein, Each of the plurality of word lines extends in the first horizontal direction from the first stepped region to the second stepped region through the stacked region.

8. The semiconductor memory device according to claim 1, wherein, An extension length of the plurality of word lines in the first horizontal direction decreases from a bottom to a top in the vertical direction, such that the plurality of word lines have a stepped structure in each of the first stepped region and the second stepped region.

9. The semiconductor memory device according to claim 8, wherein, 10. The semiconductor memory device according to claim 9, wherein, ​ each of the plurality of word lines includes a first word line pad and a second word line pad at both ends thereof in the first horizontal direction, none of the other word lines among the plurality of word lines is located on an upper side of the first word line pad and the second word line pad in the vertical direction, and the first word line contact and the second word line contact are connected to the first word line pad and the second word line pad, respectively.

11. A semiconductor memory device, comprising: a lower structure; and an upper structure stacked on the lower structure, the upper structure including a first sub-word line driver and a second sub-word line driver, wherein the lower structure includes: a substrate including a stacked region, the stacked region including a first stepped region and a second stepped region, the first stepped region and the second stepped region being located at both ends of the stacked region in a first horizontal direction, respectively, a plurality of word lines, each of the plurality of word lines extending in the first horizontal direction toward each of the first stepped region and the second stepped region in the stacked region, the plurality of word lines being spaced apart from each other in a vertical direction, a plurality of bit lines extending in the vertical direction in the stacked region, the plurality of bit lines being spaced apart from each other in the first horizontal direction, a plurality of memory cells located between the plurality of word lines and the plurality of bit lines in the stacked region, a first word line contact connected to each of the plurality of word lines in the first stepped region, and a second word line contact connected to each of the plurality of word lines in the second stepped region, wherein each of the plurality of word lines is electrically connected to the first sub-word line driver through the first word line contact and to the second sub-word line driver through the second word line contact.

12. The semiconductor memory device according to claim 11, wherein the lower structure includes a first insulating structure covering the plurality of word lines, the plurality of bit lines, the plurality of memory cells, the first word line contact, and the second word line contact on the substrate; and the upper structure includes a peripheral circuit board, an interconnector structure connecting the first sub-word line driver and the second sub-word line driver with the first word line contact and the second word line contact, respectively, and a second insulating structure surrounding and covering the interconnector structure under the peripheral circuit board and in contact with the first insulating structure.

13. The semiconductor memory device according to claim 12, further comprising: a bonding pad connecting each of the first word line contact and the second word line contact with the interconnector structure, wherein a lower portion of the bonding pad is surrounded by the first insulating structure, and an upper portion of the bonding pad is surrounded by the second insulating structure.

14. The semiconductor memory device according to claim 11, wherein each of the plurality of memory cells includes a cell transistor and an information storage element, The unit transistor includes a semiconductor pattern including a source region, a channel region, and a drain region, and The source region, the channel region, and the drain region are sequentially arranged from each of the plurality of bit lines in a second horizontal direction different from the first horizontal direction.

15. The semiconductor memory device according to claim 14, wherein, The source region is connected to each of the plurality of bit lines, the drain region is connected to the information storage element, and the channel region is surrounded by each of the plurality of word lines.

16. The semiconductor memory device according to claim 11, wherein, The first sub-word line driver is configured to select a storage unit adjacent to the first step region from the plurality of storage units, and the second sub-word line driver is configured to select another storage unit adjacent to the second step region from the plurality of storage units.

17. The semiconductor storage device according to claim 11, wherein Each of the plurality of word lines extends in the first horizontal direction from the first step region to the second step region through the stacked region, An extension length of each of the plurality of word lines in the first horizontal direction decreases from a bottom to a top in the vertical direction, The plurality of word lines has a step structure including a first word line pad and a second word line pad, The first word line contact is connected to the first word line pad in the first step region, The second word line contact is connected to the second word line pad in the second step region.

18. A semiconductor storage device, comprising: a lower structure; and an upper structure stacked on the lower structure, the upper structure including a first sub-word line driver and a second sub-word line driver, wherein the lower structure includes: a substrate including a stacked region, the stacked region including a first step region and a second step region, the first step region and the second step region being respectively located at both ends of the stacked region in a first horizontal direction, a plurality of word lines, each of which extends in the first horizontal direction toward each of the first step region and the second step region in the stacked region, the plurality of word lines being spaced apart from each other in a vertical direction, a plurality of bit lines extending in the vertical direction in the stacked region, the plurality of bit lines being spaced apart from each other in the first horizontal direction, a plurality of storage units between the plurality of word lines and the plurality of bit lines in the stacked region, a first word line contact connected to each of the plurality of word lines in the first step region, and a second word line contact connected to each of the plurality of word lines in the second step region, each of the plurality of word lines is electrically connected to the first sub-word line driver through the first word line contact, and is electrically connected to the second sub-word line driver through the second word line contact, ​ Each of the plurality of memory cells includes a cell transistor and an information storage element, the cell transistor including a semiconductor pattern including a source region connected to a corresponding bit line of the plurality of bit lines, a channel region surrounded by a corresponding word line of the plurality of word lines, and a drain region connected to the information storage element, and The source region, the channel region, and the drain region are sequentially arranged from the corresponding bit line of the plurality of bit lines in a second horizontal direction different from the first horizontal direction.

19. The semiconductor memory device of claim 18, further comprising: a bond pad connected to each of the first word line contact and the second word line contact, wherein the lower structure includes a first insulating structure covering the plurality of word lines, the plurality of bit lines, the plurality of memory cells, the first word line contact, and the second word line contact on the substrate, the upper structure includes a peripheral circuit board, an interconnector structure connecting each of the first sub-word line driver and the second sub-word line driver to the bond pad, and a second insulating structure surrounding and covering the interconnector structure under the peripheral circuit board and in contact with the first insulating structure, and a lower portion of the bond pad is surrounded by the first insulating structure, and an upper portion of the bond pad is surrounded by the second insulating structure.

20. The semiconductor memory device of claim 18, wherein the first sub-word line driver is connected to each of the plurality of word lines through the first word line contact and is configured to select memory cells adjacent to the first step region from among the plurality of memory cells, and the second sub-word line driver is connected to each of the plurality of word lines through the second word line contact and is configured to select other memory cells adjacent to the second step region from among the plurality of memory cells.

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