Method for manufacturing three-dimensional dynamic random access memory array structure

Abstract

The invention provides a method for manufacturing a three-dimensional DRAM (Dynamic Random Access Memory) array structure. The method comprises the steps that a plurality of stacked sub-arrays and a plurality of third isolation layers are sequentially formed on a circuit substrate, forming of each stacked sub-array comprises the steps that first isolation layers and stacked layers are alternately stacked on the circuit substrate, and each stacked layer sequentially comprises a first conductive layer, a second isolation layer, a common electrode layer, a second isolation layer and a second conductive layer; bit line holes penetrating through the first isolation layer and the lamination layer and extending to the circuit substrate are formed, and the area of each bit line hole in the lamination layer is larger than that of the bit line hole in the first isolation layer; conformally forming a dielectric layer on the inner surface of each bit line hole, conformally forming a semiconductor material layer on the inner surface of the dielectric layer, and filling the remaining space of the bit line hole with an isolation medium; a hole is formed through the isolation medium, and the hole is filled with a conductive material, a portion of the conductive material corresponding to the stack is separated from the semiconductor material layer by the isolation medium, and a portion of the conductive material corresponding to the first isolation layer is in direct contact with the semiconductor material layer.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of semiconductor technology, and in particular, the present disclosure relates to a method for manufacturing a three-dimensional dynamic random access memory (DRAM) array structure. BACKGROUND

[0002] Since the invention of dynamic random access memory (DRAM) by Intel Corporation in the 1970s, DRAM has been widely used in various computing or control electronic circuit systems.

[0003] A DRAM cell circuit is usually composed of a selection transistor and a storage capacitor for storing charge (1T1C structure). In a DRAM cell structure using a conventional horizontal transistor based on a planar structure, such as a metal oxide semiconductor field effect transistor (MOSFET) to implement the selection transistor, the source, gate and drain of the transistor are arranged in a horizontal direction parallel to the substrate surface. Since the source, gate and drain of the transistor each occupy an independent area in the horizontal direction, the micro-fabrication of the DRAM cell circuit structure is limited by the gate length and contact size, which cannot meet the continuous micro-fabrication needs of the DRAM device, thereby limiting the further increase of the integration and bandwidth of the DRAM device.

[0004] Therefore, in recent years, a vertical DRAM cell structure has been proposed, in which the source, gate and drain of the transistor are arranged in a vertical direction perpendicular to the substrate surface, without occupying additional area, which is conducive to the size micro-fabrication of the DRAM array structure. In addition, by vertically stacking multiple layers of DRAM cells to form a three-dimensional DRAM array, the memory integration density can be further improved.

[0005] DRAM manufacturing is a highly competitive industry. The industry continues to demand smaller individual cell sizes and increased memory cell densities, so that a single memory chip can accommodate more memory.

[0006] The above information disclosed in this BACKGROUND section only for the background of the inventive concept and therefore can contain information that is not prior art. SUMMARY

[0007] In order to solve the above problems existing in the prior art, the present disclosure proposes a novel method for manufacturing a three-dimensional dynamic random access memory (DRAM) array structure.

[0008] According to one aspect of the present disclosure, a method for manufacturing a three-dimensional DRAM array structure is provided, which comprises: sequentially forming a plurality of stacked sub-arrays and a plurality of third isolation layers in a vertical direction on a circuit substrate, the plurality of stacked sub-arrays being separated from each other by the plurality of third isolation layers, wherein forming each of the plurality of stacked sub-arrays comprises: alternately stacking a plurality of first isolation layers and a plurality of stacks in a vertical direction, each of the plurality of stacks sequentially comprising a first conductive layer, a second isolation layer, a common electrode layer, a second isolation layer, and a second conductive layer; forming a plurality of bit line holes extending through the plurality of first isolation layers and the plurality of stacks and extending to the circuit substrate, which are arranged in an array form, wherein an area of each bit line hole in the stack is greater than an area of the bit line hole in the first isolation layer; conformally forming a dielectric layer on an inner surface of each bit line hole, conformally forming a semiconductor material layer on an inner surface of the dielectric layer, and filling a remaining space of the bit line hole with an isolation dielectric; forming a hole extending through the isolation dielectric, and filling the hole with a conductive material, wherein a portion of the conductive material corresponding to the stack is separated from the semiconductor material layer by the isolation dielectric, and a portion of the conductive material corresponding to the first isolation layer is in direct contact with the semiconductor material layer, wherein the conductive material in the respective bit line holes in the plurality of stacked sub-arrays are electrically connected to each other.

[0009] The DRAM cell structure constituting the DRAM array structure according to the present disclosure comprises two gate-all-around transistors and one storage capacitor which are mirror arranged in a vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two gate-all-around transistors are formed by the same semiconductor material layer, thus having the advantages of simple structure, good switching performance, etc. In particular, the cell structure solves the connection problem of the transistor source / drain and the inner electrode of the storage capacitor by using a vertical structure, and is suitable for three-dimensional vertical integration of multi-layer cells. In addition, the DRAM array structure according to the present disclosure can be stacked in a circuit substrate comprising a plurality of circuits, thus realizing three-dimensional vertical integration at the system level, thereby greatly reducing the area overhead of the circuit system.

[0010] The method for manufacturing a three-dimensional DRAM array structure according to the present disclosure can realize three-dimensional vertical integration by stacking multi-layer DRAM cells, thereby improving the integration density. The method for manufacturing a three-dimensional DRAM array structure according to the present disclosure adopts a vertical structure suitable for one-time processing formation of multi-layer cells, without the need for multiple epitaxial processes and processing processes, thus being low in manufacturing cost. In particular, the method for manufacturing a three-dimensional DRAM array structure according to the present disclosure can further improve the integration density and storage capacity by sequentially stacking a plurality of stacked sub-arrays in a vertical direction.

[0011] However, the effects of the present disclosure are not limited to the above-described effects, and various extensions can be made without departing from the spirit and scope of the present disclosure. It should be understood that the foregoing General Description and the following Detailed Description are exemplary and explanatory, and are intended to provide further explanation of the present disclosure as claimed. BRIEF DESCRIPTION OF DRAWINGS

[0012] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated in and constitute a part of this specification, illustrate exemplary embodiments of the present disclosure and together with the description serve to explain the principles of the present disclosure.

[0013] Figure 1 is an equivalent circuit diagram illustrating a dynamic random access memory (DRAM) cell structure according to an embodiment of the present disclosure.

[0014] Figure 2 is a perspective view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0015] Figure 3 is a top view illustrating a DRAM cell structure according to an embodiment of the present disclosure.

[0016] Figure 4 is a cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure taken along a line AA' in Figure 3

[0017] Figure 5 is a cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure taken along a line BB' in Figure 3

[0018] Figure 6 is a cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure taken along a line CC' in Figure 4

[0019] Figure 7 is a cross-sectional view illustrating a DRAM cell structure according to an embodiment of the present disclosure taken along a line DD' in Figure 4

[0020] Figure 8 is a top view illustrating a DRAM cell structure according to another embodiment of the present disclosure.

[0021] Figure 9 is a cross-sectional view illustrating a DRAM cell structure according to another embodiment of the present disclosure taken along a line AA' in Figure 8

[0022] Figure 10 Figure 8 ​​​​​​is a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure, taken along line BB' in

[0023] Figure 11 is a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure, taken along line BB' in Figure 9

[0024] Figure 12 is a cross-sectional view of a DRAM cell structure according to another embodiment of the present disclosure, taken along line BB' in Figure 9

[0025] Figure 13 is an equivalent circuit diagram illustrating a DRAM array structure formed by the DRAM cell structure shown in Figure 1

[0026] Figure 14 is an equivalent circuit diagram illustrating a first row of DRAM cell structures of the DRAM array structure according to an embodiment of the present disclosure shown in Figure 13

[0027] Figure 15 is a schematic perspective view illustrating a first row of DRAM cell structures of a first layer of the DRAM array structure according to an embodiment of the present disclosure shown in Figure 13

[0028] Figure 16 is a top view illustrating a partial DRAM array structure of the DRAM array structure according to an embodiment of the present disclosure shown in Figure 13

[0029] is a cross-sectional view of the DRAM array structure according to an embodiment of the present disclosure, taken along line AA' in Figure 17 Figure 16 is a cross-sectional view of the DRAM array structure according to an embodiment of the present disclosure, taken along line BB' in

[0030] Figure 18 Figure 16 is a cross-sectional view of the DRAM array structure according to an embodiment of the present disclosure, taken along line BB' in

[0031] Figure 19 is a cross-sectional view of the DRAM array structure according to an embodiment of the present disclosure, taken along line CC' in Figure 17

[0032] is a cross-sectional view of the DRAM array structure according to an embodiment of the present disclosure, taken along line DD' in Figure 20 Figure 17

[0033] Figure 21 ​​​​​​​​​A flowchart illustrating a method for fabricating a DRAM array structure according to an embodiment of the present disclosure is shown.

[0034] Figure 22A to Figure 29B are schematic cross-sectional views respectively illustrating various process steps of a method for fabricating a DRAM array structure according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0035] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of example embodiments of the present disclosure. As used herein, an "embodiment" is a non-limiting example of an apparatus or method employing one or more inventive concepts disclosed herein. It will be evident, however, that the example embodiments can be practiced without these specific details, or with one or more equivalent configurations. In other instances, well-known structures and functions have not been described in detail in order to not unnecessarily obscure the example embodiments.

[0036] Unless otherwise indicated, the example embodiments described are to be understood as providing example features that can vary in detail without departing from the inventive concept. Therefore, features, components, modules, regions, and / or aspects of each embodiment (hereinafter individually or collectively referred to as "elements") can be otherwise combined, separated, interchanged, and / or rearranged without departing from the inventive concept, unless otherwise indicated.

[0037] For purposes of the present disclosure, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to include only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0038] Although the terms "first," "second," etc. can be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, a first element discussed below could be termed a second element without departing from the teachings of the present disclosure.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting. As used herein, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, to the extent that the terms "including," "includes," "having," "has," "a" or "an," or the like are used in the detailed description and / or claims, such terms are intended to be inclusive (i.e., to say that at least the stated feature is present), unless otherwise indicated. Still further, it should be noted that, as used in the present specification, the terms "substantially," "approximately," and other similar terms are used to describe and account for small variations in the value of a quantity that can occur in a system or process that is dependent on one or more measurement, calculation, and / or provision of values by one of ordinary skill in the art.

[0040] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and are not to be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0041] Embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. However, the present disclosure can be implemented in many different ways and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that the disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. Like reference numerals refer to like parts throughout the specification. Furthermore, in the drawings, the components are not necessarily to scale, and the proportions of the various components can be exaggerated for clarity.

[0042] A dynamic random access memory (DRAM) cell structure according to embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

[0043] Figure 1 An equivalent circuit diagram of a DRAM cell structure 100 according to embodiments of the present disclosure is shown.

[0044] As Figure 1 shown, the DRAM cell structure 100 according to embodiments of the present disclosure can employ a 2T1C (i.e., two pass-gate transistors and one storage capacitor) cell structure. Specifically, the DRAM cell structure 100 can include two gate-all-around (GAA) transistors, i.e., a first GAA transistor T1 and a second GAA transistor T2, disposed in a vertical direction (z-direction) in sequence and electrically connected in parallel, each of the first and second GAA transistors T1 and T2 can have a tubular structure of a channel and function as a pass-gate transistor of the DRAM cell structure 100.

[0045] According to an embodiment of this disclosure, the first source / drain S / D11 of the first GAA transistor T1 and the first source / drain S / D21 of the second GAA transistor T2 are commonly connected to one plate (internal electrode) of the memory capacitor C, and the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 are commonly connected to the bit line BL. According to an embodiment of this disclosure, the bit line BL can extend in the vertical direction (z-direction). Furthermore, according to an embodiment of this disclosure, the gate G1 of the first GAA transistor T1 can be connected to the first word line WLA, and the gate G2 of the second GAA transistor T2 can be connected to the second word line WLB. According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can extend along a first horizontal direction (y-direction) and overlap in the vertical direction (z-direction). According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can be shorted together. Alternatively, according to embodiments of this disclosure, the first word line WLA and the second word line WLB may not be shorted together to control the first GAA transistor T1 and the second GAA transistor T2 respectively.

[0046] Furthermore, according to embodiments of this disclosure, the other plate (external electrode) of the storage capacitor C can be connected to the source line SL. Those skilled in the art will recognize that in a DRAM array structure composed of the DRAM cell structure 100 according to this disclosure, the source lines SL of all DRAM cell structures can be connected together commonly or in groups; therefore, the source line SL can also be referred to herein as a "common electrode".

[0047] Figure 2 A perspective view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 3 A top view of a DRAM cell structure 100 according to an embodiment of the present disclosure is shown. Figure 4 It shows along Figure 3 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line AA'. Figure 5 It shows along Figure 3 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line BB'. Figure 6 It shows along Figure 4 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line CC'. Figure 7 It shows along Figure 4 The image shows a cross-sectional view of the DRAM cell structure 100 according to an embodiment of the present disclosure, taken by line DD'.

[0048] like Figure 2 to Figure 7As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include bit line holes (such as...) extending in the vertical direction (z-direction). Figure 3 , Figure 6 and Figure 7 The hole shown is located at the center and has, for example, a circular cross-section, and a common electrode trench (e.g., extending in the first horizontal direction (y direction) and penetrating the DRAM cell structure 100 in the vertical direction (z direction) is also present. Figure 2 , Figure 3 , Figure 4 , Figure 6 and Figure 7 The slots located on both sides of the central bit line hole are shown.

[0049] like Figure 2 to Figure 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include conductor lines 109 disposed in bit line holes. The conductor lines 109 extend in the vertical direction (z-direction) and can be used as... Figure 1 The bit line BL of the DRAM cell structure 100 shown. According to embodiments of the present disclosure, the material used to form the conductor line 109 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof. In particular, according to embodiments of the present disclosure, the conductor line 109 may have a cylindrical shape extending in the vertical direction (z-direction). For example, as Figure 3 , Figure 6 and Figure 7 As shown, conductor line 109 can be a cylinder with a first diameter d1.

[0050] like Figure 2 to Figure 7 As shown, according to embodiments of this disclosure, the DRAM cell structure 100 may include a semiconductor material layer 107 with a tubular structure and a first isolation material layer 111 disposed in a bit line hole surrounding a conductor line 109. Specifically, as Figure 4 and Figure 5 As shown more clearly, the upper and lower ends of the semiconductor material layer 107 are in direct contact with the conductor line 109, and the middle portion of the semiconductor material layer 107 is separated from the conductor line 109 by the first insulating material layer 111. In other words, according to embodiments of this disclosure, both the semiconductor material layer 107 and the first insulating material layer 111 have a tubular structure surrounding the conductor line 109. Although in Figure 3 , Figure 6 and Figure 7 In this invention, the tubular structure has a circular cross-section, but this disclosure is not limited to this. Those skilled in the art should recognize that the tubular structure may also have other arbitrary cross-sections, such as elliptical, square or rectangular cross-sections, in which case the cross-sectional shape of the conductor line 109 can be adjusted accordingly.

[0051] According to embodiments of the present disclosure, the material used to form the first isolation material layer 111 can be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, phosphosilicate glass, or a combination thereof. According to embodiments of the present disclosure, the material used to form the first isolation material layer 111 can also be a low-k material. A low-k material can have a lower dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the first isolation material layer 111 can include a low-k material having a dielectric constant of about 3.9 or lower. According to embodiments of the present disclosure, the low-k material can include porous silicon oxide (SiO2), organosilicon, fluorinated silicon glass (FSG), hydrogen silsesquioxane (HSQ), silicon oxycarbide (SiCOH), or polymeric materials such as Parylene, polyimide (PI), etc. According to embodiments of the present disclosure, the material used to form the first isolation material layer 111 can also be a combination of the above-mentioned dielectric materials and the above-mentioned low-k materials.

[0052] According to embodiments of the present disclosure, the material used to form the semiconductor material layer 107 can be a semiconductor thin film material, such as single-crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanide compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene, or a combination thereof. According to embodiments of the present disclosure, the material used to form the semiconductor material layer 107 can be an oxide semiconductor material, such as indium gallium zinc oxide (IGZO) with different ratios, indium oxide (InO), zinc oxide (ZnO), indium tungsten oxide (InWO), or indium aluminum oxide (InAlO). In particular, according to embodiments of the present disclosure, the semiconductor material layer 107 can include a single layer of IGZO or a stack of multiple layers of IGZO with different ratios.

[0053] Further, according to embodiments of the present disclosure, as described in more detail below, the semiconductor material layer 107 can form source / drain regions and channel regions of the first GAA transistor T1 and the second GAA transistor T2 as shown in Figure 1 , where the source / drain regions of the first GAA transistor T1 and the second GAA transistor T2 correspond to the first source / drain S / D 11 and the second source / drain S / D 12 of the first GAA transistor T1 and the first source / drain S / D 21 and the second source / drain S / D 22 of the second GAA transistor T2. It is noted here that the source / drain regions described from a structural perspective are equivalent to the source / drain described from a circuit perspective. Further, according to embodiments of the present disclosure, the semiconductor material layer 107 can also form an internal electrode of the storage capacitor C as shown in Figure 1 . Thus, according to embodiments of the present disclosure, the storage capacitor C can also have a tubular structure.

[0054] As shown in Figure 2 to Figure 7As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include two first dielectric layers 106 disposed in bit line vias, respectively surrounding the upper and lower ends of the semiconductor material layer 107. According to embodiments of the present disclosure, the two first dielectric layers 106 may be respectively formed as shown in the diagram. Figure 1 The gate dielectric of the first GAA transistor T1 and the second GAA transistor T2 are shown. Figure 4 and Figure 5 As shown, according to embodiments of this disclosure, the first dielectric layer 106 may also have a tubular structure with a bent cross-section. In other words, as... Figure 2 to Figure 5 As shown, in a cross-section along the vertical direction (z-direction), the first dielectric layer 106 may have a thinner first portion near the end of the conductor line 109 and a thicker second portion relative to the first portion and away from the end of the conductor line 109. The first and second portions may be connected by a horizontal connecting portion. According to embodiments of this disclosure, the material used to form the first dielectric layer 106 may include, for example, silicon oxide (SiO2), silicon oxynitride (SiON), aluminum oxide (Al2O3), hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), or combinations thereof.

[0055] Therefore, according to the embodiments of this disclosure, both the first GAA transistor T1 and the second GAA transistor T2 are formed to have a tubular structure and both have a tubular channel.

[0056] like Figure 2 to Figure 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include a lower first gate layer 104 and an upper second gate layer 105 configured to surround a thicker second portion of a lower and upper first dielectric layer 106, respectively. Figure 2 and Figure 6 As shown, according to embodiments of the present disclosure, the first gate layer 104 and the second gate layer 105 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the first gate layer 104 may correspond to... Figure 1 The first GAA transistor T1 shown has a gate G1, and the second gate layer 105 can correspond to, as shown in the figure. Figure 1 The gate G2 of the second GAA transistor T2 is shown. Furthermore, as... Figure 2 , Figure 3 and Figure 5 As shown, according to an embodiment of this disclosure, the first gate layer 104 may extend in a first horizontal direction (y-direction) to further correspond to, as Figure 1The first word line WLA is shown, connected to the first gate G1 of the first GAA transistor T1. Accordingly, according to embodiments of this disclosure, the second gate layer 105 may extend in the first horizontal direction (y direction) to further correspond to, as shown in the figure. Figure 1 The second word line WLB is shown connected to the gate G2 of the second GAA transistor T2. According to an embodiment of this disclosure, the first word line WLA and the second word line WLB can be led out from the distal end in a first horizontal direction (y direction).

[0057] Therefore, according to embodiments of the present disclosure, the DRAM cell structure 100 may have a bit line BL extending in the vertical direction (z-direction), and a first word line WLA and a second word line WLB extending in the first horizontal direction (y-direction). According to embodiments of the present disclosure, the bit line BL of the DRAM cell structure 100 may extend vertically within a tubular structure formed by the first GAA transistor T1, the second GAA transistor T2, and the storage capacitor C. Furthermore, according to embodiments of the present disclosure, the first gate layer 104 and the second gate layer 105 corresponding to the first word line WLA and the second word line WLB of the DRAM cell structure 100 may overlap in the vertical direction (z-direction).

[0058] Furthermore, according to embodiments of this disclosure, the materials used to form the first gate layer 104 and the second gate layer 105 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof.

[0059] like Figure 2 to Figure 7 As shown, according to embodiments of the present disclosure, the DRAM cell structure 100 may include two second insulating material layers 103 configured to surround, respectively, a thinner first portion of a first dielectric layer 106 above and below. Figure 2 and Figure 3 As shown, according to embodiments of the present disclosure, the second insulating material layer 103 may have a strip shape with a hole in the middle. According to embodiments of the present disclosure, the material used to form the second insulating material layer 103 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon carbide (SiCOH), or aluminum oxide (Al2O3). According to embodiments of the present disclosure, the first insulating material layer 111 and the second insulating material layer 103 may be formed of the same or different insulating materials.

[0060] like Figure 4 and Figure 5As shown, according to embodiments of the present disclosure, the semiconductor material layer 107 can include, along the vertical direction (z direction), a first portion 1071 of the channel region of the first and second GAA transistors T1 and T2, and a second portion 1072 of the channel region of the first and second GAA transistors T1 and T2 formed between the first portion 1071, as described above. Figure 1 As shown, the first portion 1071 of the channel region of the first and second GAA transistors T1 and T2, and the second portion 1072 of the channel region of the first and second GAA transistors T1 and T2 formed between the first portion 1071, as described above. Figure 1 As shown, the first source / drain region of the first GAA transistor T1 (corresponding to the first source / drain S / D 11 of the first GAA transistor T1), the first source / drain region of the second GAA transistor T2 (corresponding to the first source / drain S / D 21 of the second GAA transistor T2), and the second portion 1072 of the inner electrode of the memory capacitor C. Thus, according to embodiments of the present disclosure, the first source / drain S / D 11 of the first GAA transistor T1 and the first source / drain S / D 21 of the second GAA transistor T2 are connected together with the inner electrode of the memory capacitor C. According to embodiments of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 are separated from the conductor line 109 (bit line BL) by the first isolation material layer 111 surrounding the conductor line 109 (bit line BL).

[0061] According to embodiments of the present disclosure, the doping type, doping concentration, and / or atomic composition ratio of the second portion 1072 of the semiconductor material layer 107 can be changed by material modification processes such as doping, etching, etc., so that it has better conductive performance as the inner electrode of the memory capacitor C. That is, according to embodiments of the present disclosure, the first portion 1071 and the second portion 1072 of the semiconductor material layer 107 can have different doping types, doping concentrations, and / or atomic composition ratios. According to embodiments of the present disclosure, when the semiconductor material layer 107 is an IGZO oxide semiconductor, all or part of the gallium (Ga) atoms in the second portion 1072 can be removed by, for example, an etching process to improve its conductivity, or part of the oxygen (O) atoms in the second portion 1072 can be removed by, for example, an etching process to form metal atom interstitials or oxygen atom vacancies to improve its conductivity.

[0062] In addition, as shown in FIG. 1C, according to embodiments of the present disclosure, the semiconductor material layer 107 can further include, along the vertical direction (z direction), a third portion 1073 of the channel region of the first and second GAA transistors T1 and T2 formed between the first portion 1071 and the second portion 1072, as described above. Figure 4 and Figure 5 As shown, according to embodiments of the present disclosure, the semiconductor material layer 107 can include, along the vertical direction (z direction), a first portion 1071 of the channel region of the first and second GAA transistors T1 and T2, and a second portion 1072 of the channel region of the first and second GAA transistors T1 and T2 formed between the first portion 1071, as described above. Figure 1The diagram shows the third portion 1073 of the second source / drain region of the first GAA transistor T1 (corresponding to the second source / drain S / D12 of the first GAA transistor T1) and the second source / drain region of the second GAA transistor T2 (corresponding to the second source / drain S / D22 of the second GAA transistor T2), and the first horizontal connection portion 1074 connecting the first portion 1071 and the third portion 1073. Therefore, according to an embodiment of this disclosure, the third portion 1073 of the semiconductor material layer 107 contacts the conductor line 109, such that the second source / drain S / D12 of the first GAA transistor T1 and the second source / drain S / D22 of the second GAA transistor T2 corresponding to the third portion 1073 of the semiconductor material layer 107 are connected to the bit line BL corresponding to the conductor line 109.

[0063] like Figure 3 As shown, according to an embodiment of this disclosure, the third portion 1073 of the tubular semiconductor material layer 107 may have a second diameter d2, which is larger than the first diameter d1 of the conductor line 109. Furthermore, as... Figure 3 to Figure 7 As shown, according to an embodiment of the present disclosure, the first portion 1071 and the second portion 1072 of the tubular semiconductor material layer 107 may have a third diameter d3, which is larger than the second diameter d2 of the third portion 1073 of the semiconductor material layer 107.

[0064] like Figure 2 to Figure 7 As shown, according to an embodiment of the present disclosure, the DRAM cell structure 100 may include a second dielectric layer 108 disposed in a common electrode trench as a capacitor dielectric for a storage capacitor C. According to an embodiment of the present disclosure, the second dielectric layer 108 may be formed conformally along the trench wall of the common electrode trench. Figure 2 and Figure 4 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 can contact the two second insulating material layers 103, the first gate layer 104, the second gate layer 105, and the second portion of the semiconductor material layer 107 in the second horizontal direction (x direction). Furthermore, as... Figure 2 and Figure 5 As shown, according to an embodiment of this disclosure, the second dielectric layer 108 can contact a second portion of the semiconductor material layer 107 in a first horizontal direction (y-direction). The first horizontal direction, i.e., the y-direction, can be perpendicular to the second horizontal direction, i.e., the x-direction.

[0065] Further, according to embodiments of the present disclosure, the material used to form the second dielectric layer 108 can be a high-K material. The high-K material can have a higher dielectric constant than silicon oxide. Silicon oxide can have a dielectric constant of about 3.9, and the second dielectric layer 108 can include a high-K material having a dielectric constant of about 4 or greater. According to embodiments of the present disclosure, the high-K material can include hafnium oxide (Hf02), zirconium oxide (Zr02), aluminum oxide (AI2O3), lanthanum oxide (La203), titanium oxide (Ti02), tantalum oxide (Ta205), niobium oxide (Nb205), strontium titanium oxide (SrTi03), or a combination thereof.

[0066] As shown in FIG. 1, according to embodiments of the present disclosure, the DRAM cell structure 100 can include a first gate layer 104 and a second gate layer 105 extending along the surface of the first dielectric layer 102 and filling the first and second gate trenches. According to embodiments of the present disclosure, the first and second gate layers 104 and 105 can correspond to the gate electrodes of the first and second GAA transistors T1 and T2, respectively. Figure 2 to Figure 7 As shown in FIG. 1, according to embodiments of the present disclosure, the DRAM cell structure 100 can include a first gate layer 104 and a second gate layer 105 extending along the surface of the first dielectric layer 102 and filling the first and second gate trenches. According to embodiments of the present disclosure, the first and second gate layers 104 and 105 can correspond to the gate electrodes of the first and second GAA transistors T1 and T2, respectively. Figure 1 As shown in FIG. 1, according to embodiments of the present disclosure, the DRAM cell structure 100 can include a first gate layer 104 and a second gate layer 105 extending along the surface of the first dielectric layer 102 and filling the first and second gate trenches. According to embodiments of the present disclosure, the first and second gate layers 104 and 105 can correspond to the gate electrodes of the first and second GAA transistors T1 and T2, respectively. Figure 2 to Figure 7 As shown in FIG. 1, according to embodiments of the present disclosure, the DRAM cell structure 100 can include a first gate layer 104 and a second gate layer 105 extending along the surface of the first dielectric layer 102 and filling the first and second gate trenches. According to embodiments of the present disclosure, the first and second gate layers 104 and 105 can correspond to the gate electrodes of the first and second GAA transistors T1 and T2, respectively.

[0067] Further, although not shown in the figures, according to embodiments of the present disclosure, a third isolation material layer can also be provided between the first and second gate layers 104 and 105 and the second dielectric layer 108, for reducing the parasitic capacitance and leakage current between the outer electrode of the storage capacitor (the source line SL) and the gates G1 and G2 of the first and second GAA transistors T1 and T2 (i.e., the first and second word lines WLA and WLB).

[0068] Figure 8 FIG. 2B is a cross-sectional view showing the DRAM cell structure 100" according to another embodiment of the present disclosure, taken along the line AA' in FIG. 2A. Figure 9 FIG. 2B is a cross-sectional view showing the DRAM cell structure 100" according to another embodiment of the present disclosure, taken along the line AA' in FIG. 2A. Figure 8 FIG. 2B is a cross-sectional view showing the DRAM cell structure 100" according to another embodiment of the present disclosure, taken along the line AA' in FIG. 2A. Figure 10 FIG. 2B is a cross-sectional view showing the DRAM cell structure 100" according to another embodiment of the present disclosure, taken along the line AA' in FIG. 2A.Figure 8 is a cross-sectional view of a DRAM cell structure 100" according to another embodiment of the disclosure, taken along line BB' in Figure 11 is a plan view showing a top view of the DRAM cell structure 100" according to another embodiment of the disclosure, taken along Figure 9 is a cross-sectional view of the DRAM cell structure 100" according to another embodiment of the disclosure, taken along line CC' in Figure 12 is a plan view showing a top view of the DRAM cell structure 100" according to another embodiment of the disclosure, taken along Figure 9 is a cross-sectional view of the DRAM cell structure 100" according to another embodiment of the disclosure, taken along line DD' in Figure 8 to Figure 12 elements shown in Figure 3 to Figure 7 elements shown in

[0069] Figure 8 to Figure 12 The DRAM cell structure 100" shown in Figure 3 to Figure 7 is different from the DRAM cell structure 100 shown in Figure 9 and Figure 10 According to embodiments of the disclosure, the third dielectric layer 113 can be provided to have a tubular structure conformally surrounding the semiconductor layer 107.

[0070] According to embodiments of the disclosure, the material used to form the third dielectric layer 113 can be a high-K material, such as hafnium oxide (Hf02), zirconium oxide (Zr02), aluminum oxide (AI2O3), lanthanum oxide (La2O3), titanium oxide (Ti02), tantalum oxide (Ta2O5), niobium oxide (Nb2O5), strontium titanium oxide (SrTi03), or a combination thereof.

[0071] Further, as shown in Figure 9 and Figure 10 According to embodiments of the disclosure, since the common electrode trench is omitted, the electrode layer 110 (corresponding to the outer electrode of the storage capacitor C and the source line SL) is electrically connected to the first gate layer 104 (corresponding to the gate G1 of the first GAA transistor T1 and the first word line WLA) and the second gate layer 105 (corresponding to the gate G2 of the second GAA transistor T2 and the second word line WLB) through the third dielectric layer 113. Figure 1 and Figure 1 and Figure 1A fourth isolation material layer 112 is provided between the gate G2 and the second word line WLB of the second GAA transistor T2 shown, for achieving electrical isolation between the electrode layer 110 and the first gate layer 104 and the second gate layer 105. According to embodiments of the present disclosure, the fourth isolation material layer 112 may be formed of the same or different isolation material as the first isolation material layer 111 and / or the second isolation material layer 103.

[0072] Therefore, according to the embodiments of this disclosure, such as Figure 9 , Figure 10 and Figure 12 As shown, in the DRAM cell structure 100", since the source line SL (electrode layer 110) extends in the horizontal direction (x and y directions), the source line SL can be led out from the far end in the horizontal direction (x and / or y directions). Furthermore, since the common electrode trench is omitted, and the first gate layer 104 and the second gate layer 105 also extend in the horizontal direction (x and y directions), it differs from the above reference. Figure 3 to Figure 7 The DRAM cell structure 100 described herein includes a first gate layer 104 and a second gate layer 105 extending from a distal end in a second horizontal direction (x direction), in addition to the first horizontal direction (y direction).

[0073] According to embodiments of this disclosure, such as Figure 8 to Figure 12 As shown, the DRAM cell structure 100" can further simplify the structure and process, and reduce manufacturing costs.

[0074] Figure 13 This illustrates an embodiment according to the present disclosure. Figure 1 The equivalent circuit diagram of the DRAM array structure 200 formed by the DRAM cell structure shown is as follows. Figure 13 As shown, according to an embodiment of this disclosure, by Figure 1 The DRAM array structure 200 formed by the DRAM cell structure shown can be a three-dimensional DRAM array structure stacked in the vertical direction (z direction).

[0075] like Figure 13 As shown, according to embodiments of this disclosure, the DRAM array structure 200 may include, for example: Figure 1 to Figure 12The plurality of DRAM cell structures 100 or 100" is shown. For the sake of clarity, certain reference numerals inside each DRAM cell structure are omitted. According to an embodiment of the present disclosure, the plurality of DRAM cell structures is arranged in L layers, M rows, and N columns, where L, M, and N are each a natural number greater than 1. Herein, each of the plurality of DRAM cell structures included in the DRAM array structure 200 can be denoted as Clmn, i.e., a DRAM cell structure located in the m-th row, the n-th column, and the l-th layer in the DRAM array structure 200, where m, n, and l are natural numbers, and 1≤m≤M, 1≤n≤N, and 1≤l≤L. Further, herein, M denotes the number of rows of DRAM cell structures along a first horizontal direction (y direction) of the DRAM array structure 200, N denotes the number of columns of DRAM cell structures along a second horizontal direction (x direction) of the DRAM array structure 200, and L denotes the number of layers of DRAM cell structures along a vertical direction (z direction) of the DRAM array structure 200.

[0076] According to an embodiment of the present disclosure, a cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M first word lines WLA11 to WLALM and L×M second word lines WLB11 to WLBLM and M×N bit lines BL11 to BLMN.

[0077] Accordingly, as Figure 13 shown, according to an embodiment of the present disclosure, in the DRAM array structure 200, each of the L layers of DRAM cell structures includes M rows of N columns, i.e., M×N DRAM cell structures, each of the M rows of DRAM cell structures includes L layers of N columns, i.e., L×N DRAM cell structures, and each of the N columns of DRAM cell structures includes L layers of M rows, i.e., L×M DRAM cell structures.

[0078] As described above with reference to Figure 1 to Figure 12 each of the plurality of DRAM cell structures included in the DRAM array structure 200 can include: a first GAA transistor and a second GAA transistor each having a tubular structure of a channel, disposed in a vertical direction in sequence and electrically connected in parallel; and a storage capacitor having a tubular structure, disposed between the first GAA transistor and the second GAA transistor in the vertical direction, an inner electrode of which is connected to a first source / drain of the first GAA transistor and the second GAA transistor.

[0079] Further, as Figure 13As shown, according to an embodiment of the present disclosure, the DRAM array structure 200 may further include M×N bit lines BL11 to BLMN, which extend vertically inside a tubular structure formed by L first GAA transistors, L second GAA transistors, and L storage capacitors in the M-row N-column DRAM cell structure, and are respectively connected to the second source / drain of the L first GAA transistors and L second GAA transistors in the M-row N-column DRAM cell structure.

[0080] Furthermore, although not shown, according to embodiments of this disclosure, in each row of an M-row DRAM array structure, L first word lines WLA1m to WLALm can be respectively connected to L second word lines WLB1m to WLBLm. For example, as Figure 13 As shown, in the first row of the DRAM array structure, the first word line WLA11 can be connected to the second word line WLB11, the first word line WLA21 can be connected to the second word line WLB21, and so on, until the first word line WLAL1 can be connected to the second word line WLBL1. According to an embodiment of this disclosure, in each row of the M-row DRAM array structure, the corresponding connections of L first word lines and L second word lines can be implemented from the remote end outside the array. In this document, since the paired first word lines WLAlm and second word lines WLBlm extending along the first horizontal direction (y direction) can be connected together, they can be collectively referred to as word lines WL and assigned the same number as the corresponding first word line WLAlm and second word line WLBlm, i.e., WLlm. At this time, according to an embodiment of this disclosure, the cell selection operation of the plurality of DRAM cell structures included in the DRAM array structure 200 can be performed by L×M word lines WL11 to WLLM and M×N bit lines BL11 to BLMN.

[0081] Furthermore, according to embodiments of this disclosure, the DRAM array structure 200 may further include L source lines SL corresponding to the L-layer DRAM cell structure, which extend along a first horizontal direction (y-direction) and are respectively connected to the external electrodes of the storage capacitors in the L-layer DRAM cell structure. Additionally, as... Figure 13 As shown, according to an embodiment of this disclosure, L source lines SL can be connected together by a common electrode trench disposed between the bit lines that runs vertically (z-direction) through the entire DRAM array structure 200, while the source lines SL also extend vertically (z-direction). Although not shown, according to an alternative embodiment of this disclosure, the L source lines SL can also be connected together simply outside the DRAM array structure 200, either commonly or in groups, thus omitting the common electrode trench.

[0082] Figure 14 It is shown Figure 13An equivalent circuit diagram of the first row of DRAM cell structures C111 to CL1N of the DRAM array structure 200 according to the embodiment of the present disclosure is shown. As Figure 14 As shown, a first row first column first layer DRAM cell structure C111 is provided at an intersection of a first row first column bit line BL11 extending in a vertical direction (z direction) and a first layer word line (a first word line WLA11 and a second word line WLB11) extending in a first horizontal direction (y direction). By analogy, Figure 14 As shown, the first row of the DRAM array structure 200 includes N x L DRAM cell structures C111 to CL1N.

[0083] As described above with reference to Figure 1 According to the embodiment of the present disclosure, each of the plurality of DRAM cell structures constituting the DRAM array structure 200, for example Figure 9 As shown, the DRAM cell structure C111 includes a first GAA transistor T1, a second GAA transistor T2, and a storage capacitor C.

[0084] Figure 15 is a schematic perspective view showing Figure 13 As shown, the first layer first row DRAM cell structure of the DRAM array structure 200 according to the embodiment of the present disclosure. In Figure 15 , the DRAM array structure 200 can be composed of a plurality of DRAM cell structures 100" described above with reference to Figure 8 to Figure 12 As shown, in the first layer first row DRAM cell structure of the DRAM array structure, the first layer first row word line WL11 (the first word line WLA11 and the second word line WLB11) can extend in the first horizontal direction (y direction), and the first row bit line (only BL11 to BL13 are shown) can extend in the vertical direction (z direction). According to the embodiment of the present disclosure, the source line SL of the first layer DRAM cell structure can extend in the first horizontal direction (y direction). Figure 15

[0085] In addition, as Figure 13 to Figure 15 As shown, according to the embodiment of the present disclosure, the mth row nth column bit line BLmn can be commonly connected to the second source / drain of the L first GAA transistors and the L second GAA transistors in the mth row nth column DRAM cell structure of the DRAM array structure 200, for performing a cell selection operation on the mth row nth column DRAM cell structure.

[0086] Figure 16 is a top view showing Figure 13 As shown, the top view of the partial DRAM array structure 201 of the DRAM array structure 200 according to the embodiment of the present disclosure. Figure 17 is a top view showing the first row of the DRAM array structure 200 according to the embodiment of the present disclosure.​Figure 16 is a cross-sectional view of the DRAM array structure 201 according to the embodiment of the present disclosure, taken along the line AA' in FIG. 2A. Figure 18 is a plan view showing the DRAM array structure 201 according to the embodiment of the present disclosure, taken along the line AA' in FIG. 2A. Figure 16 is a cross-sectional view of the DRAM array structure 201 according to the embodiment of the present disclosure, taken along the line BB' in FIG. 2B. Figure 19 is a plan view showing the DRAM array structure 201 according to the embodiment of the present disclosure, taken along the line BB' in FIG. 2B. Figure 17 is a cross-sectional view of the DRAM array structure 201 according to the embodiment of the present disclosure, taken along the line CC' in FIG. 2C. Figure 20 is a plan view showing the DRAM array structure 201 according to the embodiment of the present disclosure, taken along the line CC' in FIG. 2C. Figure 17 is a cross-sectional view of the DRAM array structure 201 according to the embodiment of the present disclosure, taken along the line DD' in FIG. 2D.

[0087] Note that, Figure 16 to Figure 20 is exemplarily shown as a partial DRAM array structure 201 that is a part of the DRAM array structure 200 shown in FIG. 2A, which includes first-layer first-row first-column to second-layer second-row second-column DRAM cell structures C111, C112, C121, C122, C211, C212, C221, and C222, which are arranged in two rows, two columns, and two layers. Each of the DRAM cell structures can have a structure as shown in FIG. 2E. Figure 13 is exemplarily shown as a partial DRAM array structure 201 that is a part of the DRAM array structure 200 shown in FIG. 2A, which includes first-layer first-row first-column to second-layer second-row second-column DRAM cell structures C111, C112, C121, C122, C211, C212, C221, and C222, which are arranged in two rows, two columns, and two layers. Each of the DRAM cell structures can have a structure as shown in FIG. 2E. Figure 8 to Figure 12 is exemplarily shown as a partial DRAM array structure 201 that is a part of the DRAM array structure 200 shown in FIG. 2A, which includes first-layer first-row first-column to second-layer second-row second-column DRAM cell structures C111, C112, C121, C122, C211, C212, C221, and C222, which are arranged in two rows, two columns, and two layers. Each of the DRAM cell structures can have a structure as shown in FIG. 2E.

[0088] According to the embodiment of the present disclosure, the M rows N columns bit lines BL11 to BLMN of the DRAM array structure 200 can extend in the vertical direction (z direction) and be arranged in a 2 x 2 matrix form in the first horizontal direction (y direction) and the second horizontal direction (x direction). Further, according to the embodiment of the present disclosure, the L layers of DRAM cell structures of the DRAM array structure 200 are sequentially stacked in the vertical direction, and each of the layers of DRAM cell structures includes M x N DRAM cell structures.

[0089] Specifically, as shown in FIG. 2A, two rows two columns total four bit lines BL11, BL12, BL21, and BL22 can extend in the vertical direction (z direction) and be arranged in a 2 x 2 matrix form in the first horizontal direction (y direction) and the second horizontal direction (x direction). Further, as shown in FIG. 2B, the first-layer DRAM cell structures C111, C112, C121, and C122 are stacked above the second-layer DRAM cell structures C211, C212, C121, and C222. Figure 16 to Figure 20 Figure 17 Figure 18

[0090] As shown in FIG. 2A and FIG. 2B, the first-layer DRAM cell structures C111, C112, C121, and C122 are stacked above the second-layer DRAM cell structures C211, C212, C121, and C222. Figure 16 Figure 17 ​​​​As shown, first tier first row first word line WLA11 is connected to the gates of the first GAA transistor in first tier first row DRAM cell structures C111 and C112, and first tier second word line WLB11 is connected to the gates of the second GAA transistor in first tier first row DRAM cell structures C111 and C112. Similarly, first tier second row first word line WLA12 is connected to the gates of the first GAA transistor in first tier second row DRAM cell structures C121 and C122, and first tier second row second word line WLB12 is connected to the gates of the second GAA transistor in first tier second row DRAM cell structures C121 and C122. Similarly, second tier first row first word line WLA21 is connected to the gates of the first GAA transistor in second tier first row DRAM cell structures C211 and C212, and second tier first row second word line WLB21 is connected to the gates of the second GAA transistor in second tier first row DRAM cell structures C211 and C212. Similarly, second tier second row first word line WLA22 is connected to the gates of the first GAA transistor in second tier second row DRAM cell structures C221 and C222, and second tier second row second word line WLB22 is connected to the gates of the second GAA transistor in second tier second row DRAM cell structures C221 and C222.

[0091] As Figure 16 to Figure 20As shown, four bit lines BL11, BL12, BL21, and BL22 are formed in four bit line holes extending through the DRAM array structure in the vertical direction (z-direction). Specifically, the first row first column bit line BL11 extends in the vertical direction inside the tubular structure of the first GAA transistor and the second GAA transistor and the storage capacitor in the first row first column DRAM cell structure C111 and C211, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the first row first column DRAM cell structure C111 and C211. Similarly, the first row second column bit line BL12 extends in the vertical direction inside the tubular structure of the first GAA transistor and the second GAA transistor and the storage capacitor in the first row second column DRAM cell structure C112 and C212, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the first row second column DRAM cell structure C112 and C212. Similarly, the second row first column bit line BL21 extends in the vertical direction inside the tubular structure of the first GAA transistor and the second GAA transistor and the storage capacitor in the second row first column DRAM cell structure C121 and C221, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the second row first column DRAM cell structure C121 and C221. Similarly, the second row second column bit line BL22 extends in the vertical direction inside the tubular structure of the first GAA transistor and the second GAA transistor and the storage capacitor in the second row second column DRAM cell structure C122 and C222, and is connected to the second source / drain of the first GAA transistor and the second GAA transistor in the second row second column DRAM cell structure C122 and C222.

[0092] According to embodiments of the present disclosure, in the DRAM cell structure of each of the M rows by N columns, the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor are formed by the same semiconductor material layer. That is, according to embodiments of the present disclosure, in each of the MxN bit line holes extending through the L-layer DRAM cell structure in the vertical direction (z-direction), the first source / drain and the second source / drain of the first GAA transistor and the second GAA transistor, the channel region, and the inner electrode of the storage capacitor in the L-layer DRAM cell structure are formed by the same semiconductor material layer having a tubular structure. That is, the semiconductor material layer of this tubular structure extends through the entire DRAM array structure 200 in the vertical direction (z-direction).

[0093] Specifically, as Figure 16 to Figure 20As shown, the first source / drain and second source / drain of the first and second GAA transistors, the channel region, and the inner electrode of the storage capacitor in the first layer DRAM cell structure C111 and the second layer DRAM cell structure C211 connected to the first column bit line BL11 of the first row are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain of the first and second GAA transistors, the channel region, and the inner electrode of the storage capacitor in the first layer DRAM cell structure C112 and the second layer DRAM cell structure C212 connected to the second column bit line BL12 of the first row are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain of the first and second GAA transistors, the channel region, and the inner electrode of the storage capacitor in the first layer DRAM cell structure C121 and the second layer DRAM cell structure C221 connected to the first column bit line BL21 of the second row are formed from the same semiconductor material layer. Similarly, the first source / drain and second source / drain of the first and second GAA transistors, the channel region, and the inner electrode of the storage capacitor in the first layer DRAM cell structure C122 and the second layer DRAM cell structure C222 connected to the second column bit line BL22 of the second row are formed from the same semiconductor material layer.

[0094] According to embodiments of the present disclosure, in the DRAM cell structure of each of the M rows by N columns, the gate dielectric of the first and second GAA transistors and the capacitor dielectric of the storage capacitor are formed from the same dielectric layer. That is, according to embodiments of the present disclosure, in each of the M by N bit line holes extending through the L layer DRAM cell structure in the vertical direction (z-direction), the gate dielectric of the first and second GAA transistors and the capacitor dielectric of the storage capacitor in the L layer DRAM cell structure are formed from the same dielectric layer. That is, the dielectric layer of this tubular structure extends through the entire DRAM array structure 200 in the vertical direction (z-direction).

[0095] In particular, as Figure 16 to Figure 20As shown, the gate dielectric of the first and second GAA transistors and the capacitor dielectric of the storage capacitor in the first layer DRAM cell structure C111 and the second layer DRAM cell structure C211 connected to the first column bit line BL11 are formed by the same dielectric layer. Similarly, the gate dielectric of the first and second GAA transistors and the capacitor dielectric of the storage capacitor in the first layer DRAM cell structure C112 and the second layer DRAM cell structure C212 connected to the second column bit line BL12 are formed by the same dielectric layer. Similarly, the gate dielectric of the first and second GAA transistors and the capacitor dielectric of the storage capacitor in the first layer DRAM cell structure C121 and the second layer DRAM cell structure C221 connected to the first row bit line BL21 are formed by the same dielectric layer. Similarly, the gate dielectric of the first and second GAA transistors and the capacitor dielectric of the storage capacitor in the first layer DRAM cell structure C122 and the second layer DRAM cell structure C222 connected to the second row bit line BL22 are formed by the same dielectric layer.

[0096] Furthermore, according to embodiments of the present disclosure, in each of the M rows x N columns of DRAM cell structures, the outer electrode of the storage capacitor is connected to a source line SL extending in the horizontal direction (first and second horizontal directions). In other words, the source line SL also serves as the outer electrode of the storage capacitor in each DRAM cell structure.

[0097] The method for fabricating a DRAM array structure according to embodiments of the present disclosure will be described below in connection with Figure 21 and Figure 22A to Figure 28B A method for fabricating a DRAM array structure according to embodiments of the present disclosure will be described below in connection with

[0098] Figure 21 A flowchart of a method 2100 for fabricating a DRAM array structure 200 according to embodiments of the present disclosure is shown. Figure 22A to Figure 28B A schematic cross-sectional view of each process step of a method for fabricating a DRAM array structure 200 according to embodiments of the present disclosure is shown, respectively. It should be noted that Figure 22A to Figure 28A is a cross-sectional view taken along the second horizontal direction (x-direction) in the vertical direction (z-direction) of the DRAM array structure, while Figure 22B to Figure 28B is a cross-sectional view taken along the first horizontal direction (y-direction) in the vertical direction (z-direction) of the DRAM array structure.

[0099] It should be noted that the method for fabricating a DRAM array structure according to embodiments of the present disclosure is described in connection with Figure 21 and Figure 22A to Figure 28BThe described method can be used to manufacture, as referenced above. Figure 8 to Figure 12 The DRAM array structure 200 is described as having a DRAM cell structure 100".

[0100] Although for ease of description, Figure 22A to Figure 28B Only an exemplary method is shown for fabricating a DRAM array structure 200 by stacking two subarrays, namely a first stacked subarray and a second stacked subarray, wherein each stacked subarray comprises a 2-layer × 2-row × 2-column DRAM cell structure. However, those skilled in the art will recognize that, according to the combination of Figure 21 as well as Figure 22A to Figure 28B The method described for manufacturing a DRAM array structure according to an embodiment of the present disclosure can be readily extended to manufacture a DRAM array structure 200 having three or more stacked subarrays, comprising an L-layer × M-row × N-column DRAM cell structure 100".

[0101] In the following description, the materials for each layer are illustrated. The primary purpose of selecting different materials is to provide the desired etching selectivity. The following description, "(relative to A) selective etching of B," means that the etching formulation used can primarily affect B, while having little or no effect on A or other material layers exposed to the etching formulation during the etching of B (where A is not explicitly mentioned or only part of such material layers is mentioned). Those skilled in the art will understand from these descriptions how to select the materials for each layer, rather than being limited to the materials illustrated herein.

[0102] exist Figure 21 In step S2101 shown, as Figure 22A and Figure 22B As shown, multiple material layers can be repeatedly stacked on the circuit substrate 300, as described below. These multiple material layers may include alternating stacked first isolation layers 303 and multiple stacked layers 304. According to embodiments of this disclosure, the circuit substrate 300 may be a semiconductor substrate on which multiple circuits can be fabricated using semiconductor manufacturing processes, such as standard CMOS processes. According to embodiments of this disclosure, as... Figure 13 The L-layer DRAM cell structure of the DRAM array structure 200 shown can be stacked on the circuit board 300 in the vertical direction (z direction) to achieve system-level three-dimensional vertical integration.

[0103] like Figure 22A and Figure 22B As shown, a pad structure 301 can be pre-formed in the circuit board 300 to achieve electrical connections, such as bit lines, with the DRAM array structure 200. Furthermore, as... Figure 22A and Figure 22BAs shown, a capping layer 302 may be provided on the circuit board 300 to cover the circuit board 300 (including the pad structure 301 therein), for protecting the circuit board 300 and achieving electrical isolation between the circuit board 300 and the DRAM array structure 200 fabricated thereon. According to embodiments of this disclosure, the material used to form the capping layer 302 may be a dielectric material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof.

[0104] like Figure 22A and Figure 22B As shown, according to an embodiment of the present disclosure, a plurality of first isolation layers 303 and a plurality of stacked layers 304 can be alternately stacked from bottom to top in the vertical direction (z direction) above the cover layer 302 disposed on the circuit board 300.

[0105] According to embodiments of this disclosure, the first isolation layer 303 can be formed in subsequent process steps as described above. Figure 8 to Figure 12 The second isolation material layer 103 of the described DRAM cell structure 100". Therefore, according to embodiments of the present disclosure, the material used to form the first isolation layer 303 may include silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), silicon oxycarbide (SiCOH), or aluminum oxide (Al2O3).

[0106] like Figure 22A and Figure 22B As shown, according to an embodiment of the present disclosure, each of the plurality of stacked layers 304 may include, from bottom to top, a first conductive layer 3041, a second isolation layer 3044, a common electrode layer 3042, a second isolation layer 3044, and a second conductive layer 3043.

[0107] According to embodiments of this disclosure, the first conductive layer 3041 and the second conductive layer 3043 can be formed respectively in subsequent process steps as described above. Figure 8 to Figure 12 The DRAM cell structure 100" described includes a first gate layer 104 and a second gate layer 105. Therefore, according to embodiments of this disclosure, the materials used to form the first conductive layer 3041 and the second conductive layer 3043 may include titanium nitride (TiN), tantalum nitride (TaN), aluminum titanium carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polycrystalline / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or combinations thereof.

[0108] Furthermore, according to embodiments of this disclosure, the first conductive layer 3041 and the second conductive layer 3043 can be formed respectively in subsequent process steps as described above. Figure 8 to Figure 12The first word line WL1 and the second word line WL2 of the described DRAM cell structure 100" can thus also be connected together at the distal ends of the first conductive layer 3041 and the second conductive layer 3043.

[0109] According to embodiments of the present disclosure, the common electrode layer 3042 can be formed in a subsequent process step from the materials described above with reference to Figure 8 to Figure 12 The electrode layer 110 of the described DRAM cell structure 100" can be used as a source line SL and an outer electrode of a storage capacitor C of the DRAM cell structure 100". Thus, according to embodiments of the present disclosure, the material used to form the common electrode layer 3042 can comprise titanium nitride (TiN), tantalum nitride (TaN), titanium aluminum carbide (TiAlC), aluminum (Al), copper (Au), titanium (Ti), palladium (Pd), molybdenum (Mo), platinum (Pt), tungsten (W), doped polysilicon / amorphous silicon, indium tin oxide (ITO), indium zinc oxide (IZO), or a combination thereof.

[0110] Further, according to embodiments of the present disclosure, since the common electrode layer 3042 is used as a source line SL and an outer electrode of a storage capacitor C of the DRAM cell structure 100", the common electrode layer 3042 comprised in each of the plurality of stacks 304 can be connected together at the distal ends, either collectively or in groups.

[0111] According to embodiments of the present disclosure, as shown in Figure 22A and Figure 22B The two second isolation layers 3044 disposed above and below the common electrode layer 3042 can be used to achieve electrical isolation between the common electrode layer 3042 and the first conductive layer 3041 and the second conductive layer 3043, respectively, according to embodiments of the present disclosure. The second isolation layers 3044 can be formed from the same or different isolation material as the first isolation layers 303, according to embodiments of the present disclosure.

[0112] Subsequently, in a step S2102 shown in Figure 21 as shown in Figure 23A and Figure 23B The plurality of first isolation layers 303 and the plurality of stacks 304 can be etched, e.g. by an etching process, to form a plurality of bit line holes T1 extending to the upper surface of the circuit substrate 300, i.e. the upper surface of the cap layer 302, according to embodiments of the present disclosure.

[0113] According to embodiments of the present disclosure, the bit line holes T1 can correspond to the bit line holes described above with reference to Figure 8 to Figure 12 the bit line holes of the described DRAM cell structure 100", wherein the conductor line 109, the first isolation material layer 111, the semiconductor material layer 107 and the first dielectric layer 106 can be disposed in this order from the inside out. Thus, according to embodiments of the present disclosure, the bit line holes T1 can be arranged in an M rows by N columns array, as described above with reference to Figure 13 ​

[0114] According to embodiments of the present disclosure, the number of bit line holes T1 can be the same as the number of bit lines MxN of the DRAM array structure 200 to be manufactured above the circuit substrate 300. According to embodiments of the present disclosure, the bit line holes T1 can have a circular cross section, but the present disclosure is not limited thereto, and those skilled in the art will recognize that the bit line holes T1 can also have other arbitrary cross sections, such as an elliptical, square, or rectangular cross section.

[0115] According to embodiments of the present disclosure, the diameters of the bit line holes T1 in the respective layers can be set to be different from each other by, for example, a difference in etching selectivity between materials. Specifically, as shown in Figure 23A and Figure 23B According to embodiments of the present disclosure, by a difference in etching selectivity between the material forming the first insulating layer 303 and the material forming the stack 304, the diameter of the bit line hole T1 in the stack 304 can be greater than the diameter of the bit line hole T1 in the first insulating layer 303.

[0116] Further, although shown as the bit line hole T1 having a uniform diameter in the stack 304 in Figure 23A and Figure 23B According to embodiments of the present disclosure, in the stack 304, by a difference in etching selectivity between the materials forming the first and second conductive layers 3041 and 3043 and the material forming the common electrode layer 3042, the diameter of the bit line hole T1 in the common electrode layer 3042 can also be greater than the diameters of the bit line hole T1 in the first and second conductive layers 3041 and 3043. In this case, since the inner electrode of the storage capacitor C (see the portion of the semiconductor material layer 306 corresponding to the common electrode layer 3042 described below in connection with Figure 24A and Figure 24B expands outwardly, so that the facing area between the inner electrode and the outer electrode of the storage capacitor C increases, the capacitance value of the storage capacitor C can be increased. Here, for the sake of brevity, the manufacturing process of this case is not described in more detail.

[0117] Subsequently, in the step S2103 shown in Figure 21 as shown in Figure 24A and Figure 24B The dielectric layer 305 can be conformally formed on the inner surface of the bit line hole T1 by, for example, a deposition process (e.g., an atomic layer deposition (ALD) process), the semiconductor material layer 306 is conformally formed on the inner surface of the dielectric layer 305, and the remaining space of the bit line hole T1 is filled with the insulating medium 307.

[0118] As shown in Figure 24A and Figure 24B Since the inner electrode of the storage capacitor C (see the portion of the semiconductor material layer 306 corresponding to the common electrode layer 3042 described above in connection with Figure 23Aand Figure 23B As noted, the diameter of the bit line hole T1 in the stack 304 can be larger than the diameter of the bit line hole T1 in the first isolation layer 303, and the conductive material 308 has a uniform diameter in the bit line hole T1, so the dielectric layer 305 in the bit line hole T1 can include a portion corresponding to the smaller diameter of the first isolation layer 303 and a portion corresponding to the larger diameter of the stack 304, and similarly, the semiconductor material layer 306 in the bit line hole T1 can include a portion corresponding to the smaller diameter of the first isolation layer 303 and a portion corresponding to the larger diameter of the stack 304.

[0119] According to embodiments of the present disclosure, the dielectric layer 305 can be formed in a subsequent process step from a material described above with reference to the third dielectric layer 113 of the DRAM cell structure 100" described above. Figure 8 to Figure 12 According to embodiments of the present disclosure, the semiconductor material layer 306 can be formed in a subsequent process step from a material described above with reference to the semiconductor material layer 107 of the DRAM cell structure 100" described above. Figure 1 According to embodiments of the present disclosure, the semiconductor material layer 306 can be formed in a subsequent process step from a material described above with reference to the semiconductor material layer 107 of the DRAM cell structure 100" described above.

[0120] According to embodiments of the present disclosure, the dielectric layer 305 can be formed in a subsequent process step from a material described above with reference to the third dielectric layer 113 of the DRAM cell structure 100" described above. Figure 8 to Figure 12 According to embodiments of the present disclosure, the semiconductor material layer 306 can be formed in a subsequent process step from a material described above with reference to the semiconductor material layer 107 of the DRAM cell structure 100" described above. Figure 1 According to embodiments of the present disclosure, the semiconductor material layer 306 can be formed in a subsequent process step from a material described above with reference to the semiconductor material layer 107 of the DRAM cell structure 100" described above.

[0121] According to embodiments of the present disclosure, the semiconductor material layer 306 can be formed in a subsequent process step from a material described above with reference to the semiconductor material layer 107 of the DRAM cell structure 100" described above. Figure 21As shown in step S2103 or subsequent step S2104, the doping type, doping concentration and / or atomic composition ratio of the certain portion of the semiconductor material layer 306 can also be changed by a material modification process such as doping, etching, etc. to change the conductive property of the corresponding portion. For example, the portion of the semiconductor material layer 306 corresponding to the second source / drain S / D 12 of the first GAA transistor T1 and the second source / drain S / D 22 of the second GAA transistor T2 can be changed by a material modification process such as doping, etching, etc. in subsequent step S2104 to improve its contact property with the bit line BL. Figure 4 and Figure 5 As shown in step S2103 or subsequent step S2104, the doping type, doping concentration and / or atomic composition ratio of the certain portion of the semiconductor material layer 306 can also be changed by a material modification process such as doping, etching, etc. to change the conductive property of the corresponding portion. For example, the portion of the semiconductor material layer 306 corresponding to the second source / drain S / D 12 of the first GAA transistor T1 and the second source / drain S / D 22 of the second GAA transistor T2 can be changed by a material modification process such as doping, etching, etc. in subsequent step S2104 to improve its contact property with the bit line BL.

[0122] According to embodiments of the present disclosure, the isolation medium 307 can be formed in a subsequent process step of the first isolation material layer 111 of the DRAM cell structure 100" described above with reference to FIG. 1B. Figure 8 to Figure 12 According to embodiments of the present disclosure, the material used to form the isolation medium 307 can be a medium material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, phosphosilicate glass, or a combination thereof. In addition, according to embodiments of the present disclosure, the material used to form the isolation medium 307 can also be a low-K material. According to embodiments of the present disclosure, the low-K material used to form the isolation medium 307 can include porous silicon oxide (SiO2), organosilicon, fluorinated silicon glass (FSG), hydrogen silsesquioxane (HSQ), silicon oxycarbide (SiCOH), or polymeric materials such as Parylene, polyimide (PI), etc. In addition, according to embodiments of the present disclosure, the material used to form the isolation medium 307 can also be a combination of the above-mentioned medium materials and the above-mentioned low-K materials. In addition, according to embodiments of the present disclosure, a cavity can also be provided in the isolation medium 307.

[0123] Subsequently, in step S2104 as shown in FIG. 2B, the isolation medium 307 and the cap layer 302 of the circuit substrate 300 can be etched, for example, by an etching process (e.g., an anisotropic etching process) to form a hole extending to the upper surface of the pad structure 301 included in the circuit substrate 300, with the uppermost first isolation layer 303 and the semiconductor material layer 306 as a mask, and the hole is filled with the conductive material 308 by, for example, a deposition process, so that the conductive material 308 contacts the pad structure 301. Figure 21 Figure 25A and Figure 25B Subsequently, in step S2104 as shown in FIG. 2B, the isolation medium 307 and the cap layer 302 of the circuit substrate 300 can be etched, for example, by an etching process (e.g., an anisotropic etching process) to form a hole extending to the upper surface of the pad structure 301 included in the circuit substrate 300, with the uppermost first isolation layer 303 and the semiconductor material layer 306 as a mask, and the hole is filled with the conductive material 308 by, for example, a deposition process, so that the conductive material 308 contacts the pad structure 301.

[0124] According to embodiments of the present disclosure, the conductive material 308 can correspond to the conductive material 108 described above with reference to FIG. 1B. Figure 8 to Figure 12 ​The conductor line 109 of the DRAM cell structure 100" described can be used as a bit line BL as shown. Figure 1 According to embodiments of the present disclosure, the conductive material 308 can include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0125] As shown in Figure 25A and Figure 25B According to embodiments of the present disclosure, the conductive material 308 can include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof. Figure 23A and Figure 23B According to embodiments of the present disclosure, the conductive material 308 can include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or a combination thereof.

[0126] So far, by the steps S2101 to S2104 of the method 2100 according to the present disclosure, the first stacked sub-array STA1 can be fabricated on the circuit substrate 300. As mentioned above, although the first stacked sub-array STA1 is shown to include 2 layers x 2 rows x 2 columns of DRAM cell structures, it can also be fabricated to have more layers x more rows x more columns of DRAM cell structures.

[0127] Subsequently, in step S2105 as shown in Figure 21 As shown in Figure 26A and Figure 26B The connection portion medium layer 310 can be formed on the first stacked sub-array STA1 by, for example, a deposition process, and the connection portions 311 can be formed in the connection portion medium layer 310 by, for example, an etching process at positions corresponding to the conductive material 308, i.e., the individual bit lines.

[0128] According to embodiments of the present disclosure, the connection portion medium layer 310 can be formed of a medium material that is the same as or different from the cap layer 302. According to embodiments of the present disclosure, the material used to form the connection portion medium layer 310 can be a medium material commonly used in integrated circuit processes, such as silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, phosphosilicate glass, or a combination thereof.

[0129] According to embodiments of the present disclosure, the connection portions 311 can be used to enable the conductive material 308, i.e., the individual bit lines of the first stacked sub-array STA1, in the first stacked sub-array STA1 to be connected to the second stacked sub-array STA2 (see the subsequently described Figure 28A and Figure 28BThe conductive material 308 in the second stacked subarray represents the electrical connection between corresponding bit lines. Therefore, according to embodiments of this disclosure, the connection portion 311 can be formed of a conductive material. According to embodiments of this disclosure, the material used to form the connection portion 311 can be the same as or different from the material used to form the conductive material 308. According to embodiments of this disclosure, the material used to form the connection portion 311 may include tungsten silicide (WSi), tungsten nitride (WN), tungsten (W), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), or combinations thereof.

[0130] It should be noted that, in combination Figure 26A and Figure 26B Description Figure 21 Step S2105 is optional and can be omitted, therefore in Figure 21 In the diagram, step S2105 is shown with a dashed box. For example... Figure 26A and Figure 26B As shown, according to an embodiment of this disclosure, the area of ​​the horizontal connection portion 311 can be larger than the area of ​​the conductive material 308 (but it is still necessary to ensure that there is no electrical contact between adjacent connection portions 311), so that a larger alignment tolerance can be allowed between the bit lines of the first stacked subarray STA1 and the corresponding bit lines of the subsequently formed second stacked subarray STA2. That is, due to the presence of the larger connection portion 311, even if the first stacked subarray STA1 and the second stacked subarray STA2 are not perfectly aligned in the vertical direction (z direction), an electrical connection can still be achieved between the corresponding bit lines of the first stacked subarray STA1 and the second stacked subarray STA2.

[0131] Subsequently, Figure 21 In step S2106 shown, as Figure 27A and Figure 27B As shown, a third isolation layer 312 can be formed over the connecting dielectric layer 310 and the connecting portion 311 by, for example, a deposition process. According to embodiments of this disclosure, the third isolation layer 312 may be formed of a dielectric material that is the same as or different from the capping layer 302. According to embodiments of this disclosure, the material used to form the third isolation layer 312 may include silicon oxide, silicon nitride, silicon oxynitride, aluminum oxide, glass phosphate, or combinations thereof.

[0132] According to embodiments of the present disclosure, the third isolation layer 312 can be used to achieve isolation between the first stacked subarray STA1 and the second stacked subarray STA2, while the first isolation layer 303 can be used to achieve isolation between the DRAM cell structures of each layer in each stacked subarray, and the second isolation layer 3044 is used to achieve isolation between the common electrode layer 3042 and the first conductive layer 3041 and the second conductive layer 3043, respectively.

[0133] Subsequently, in step S2107 shown in FIG. 21B, as shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312. Figure 21 Figure 28A As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312. Figure 28B Figure 21 As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312. Figure 28A Figure 28B As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312.

[0134] As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312. Figure 28A Figure 28B As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312.

[0135] Subsequently, in step S2108 shown in FIG. 21B, as shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312. Figure 21 Figure 29A As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312. Figure 29B As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312.

[0136] Figure 29A As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312. Figure 29B Figure 21 As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312. Figure 21 As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312.

[0137] Figure 21 As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312.

[0138] As shown in FIG. 21C, the conductive material 308 in the second stacked sub-array STA2 can be directly or through the connecting portion 311 electrically connected with the conductive material 308 in the first stacked sub-array STA1 through the third isolation layer 312. Figure 13 to Figure 20 ​​​​​​​​The described DRAM array structure 200 includes a plurality of DRAM cell structures 100 as described above with reference to Figure 8 to Figure 12 The described DRAM cell structure 100".

[0139] Those skilled in the art will recognize that although Figure 21 The method for manufacturing a DRAM array structure according to the embodiments of the present disclosure is described by way of example of two stacked sub-arrays, but the present disclosure is not limited thereto, and the method can continue to form additional stacked sub-arrays by continuing to repeat steps S2105 to S2107 on the second stacked sub-array STA2, so that the DRAM array structure can include three or more stacked sub-arrays. Figure 21

[0140] The DRAM cell structure constituting the DRAM array structure according to the present disclosure includes two gate-all-around transistors and one storage capacitor arranged in mirror image in the vertical direction, wherein the inner electrode of the storage capacitor and the source / drain and channel regions of the two gate-all-around transistors are formed by the same semiconductor material layer, thus having the advantages of simple structure, good switching performance, etc. In particular, the cell structure solves the connection problem of the transistor source / drain and the inner electrode of the storage capacitor by using a vertical structure, and is suitable for three-dimensional vertical integration of multi-layer cells. In addition, the DRAM array structure according to the present disclosure can be stacked in a circuit substrate including a plurality of circuits, thus realizing three-dimensional vertical integration at the system level, so that the area overhead of the circuit system can be greatly reduced.

[0141] The method for manufacturing a three-dimensional DRAM array structure according to the present disclosure can realize three-dimensional vertical integration by stacking multiple layers of DRAM cells, thus improving the integration density. The method for manufacturing a three-dimensional DRAM array structure according to the present disclosure adopts a vertical structure suitable for one-time processing of multi-layer cells, without the need for multiple epitaxial processes and processing processes, thus being low in manufacturing cost. In particular, the method for manufacturing a three-dimensional DRAM array structure according to the present disclosure can further improve the integration density and storage capacity by stacking multiple stacked sub-arrays in the vertical direction.

[0142] Although numerous details are included, these should not be construed as limiting the present disclosure or the scope of protection that can be claimed, but rather as a description of features that can be specific to certain embodiments. Certain features described herein in the context of separate embodiments can also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment can also be implemented separately or in any suitable subcombination in multiple embodiments. Furthermore, although features can be described above as functioning in certain combinations, and even initially so claimed, in some cases one or more features from a combination can be omitted, and the claimed combination can involve a subcombination or a variation of a subcombination.​

Claims

1. A method for fabricating a three-dimensional dynamic random access memory (DRAM) array structure, comprising: forming a plurality of stacked sub-arrays and a plurality of third isolation layers in a vertical direction on a circuit substrate, the plurality of stacked sub-arrays being separated from each other by the plurality of third isolation layers, wherein forming each of the plurality of stacked sub-arrays comprises: alternately stacking a plurality of first isolation layers and a plurality of stacks in a vertical direction, each of the plurality of stacks comprising, in order, a first conductive layer, a second isolation layer, a common electrode layer, a second isolation layer, and a second conductive layer; forming a plurality of bit line holes extending through the plurality of first isolation layers and the plurality of stacks and to the circuit substrate, which are arranged in an array form, wherein an area of each bit line hole in the stacks is greater than an area of the bit line hole in the first isolation layers; forming a dielectric layer conformally on an inner surface of each bit line hole, forming a semiconductor material layer conformally on an inner surface of the dielectric layer, and filling a remaining space of the bit line hole with an isolation dielectric; and forming a hole through the isolation dielectric, and filling the hole with a conductive material, wherein a portion of the conductive material corresponding to the stacks is separated from the semiconductor material layer by the isolation dielectric, and a portion of the conductive material corresponding to the first isolation layers is in direct contact with the semiconductor material layer, wherein the conductive material in respective bit line holes in the plurality of stacked sub-arrays are electrically connected to each other.

2. The method of claim 1, further comprising: forming a connection at a location corresponding to a bit line hole on each of the plurality of stacked sub-arrays except for an uppermost stacked sub-array, such that the conductive material in respective bit line holes in the plurality of stacked sub-arrays are electrically connected to each other through the connection.

3. The method of claim 1, wherein, the circuit substrate is a semiconductor substrate having a plurality of circuits disposed thereon, and wherein the circuit substrate is provided with a pad structure and a cap layer covering the circuit substrate.

4. The method of claim 3, wherein, the conductive material of a lowermost stacked sub-array in the plurality of stacked sub-arrays contacts the pad structure.

5. The method of claim 3, wherein, the third isolation layers are formed of a same or different material as the cap layer.

6. The method of claim 1, wherein, in forming each of the plurality of stacked sub-arrays, at each bit line hole in each stack, the dielectric layer and the semiconductor material layer form a DRAM cell structure having a tubular structure, which includes a first gate-all-around transistor, a second gate-all-around transistor, and a storage capacitor, the dielectric layer forms a gate dielectric of the first gate-all-around transistor and the second gate-all-around transistor and a capacitor dielectric of the storage capacitor, the semiconductor material layer forms source / drain regions and channel regions of the first gate-all-around transistor and the second gate-all-around transistor and an inner electrode of the storage capacitor, and the first gate-all-around transistor and the second gate-all-around transistor are connected in parallel through a respective bit line.

7. The method of claim 6, wherein, in forming each of the plurality of stacked sub-arrays, in each stack, the first conductive layer forms a gate of the first gate-all-around transistor in each row of DRAM cell structures and a first word line connected thereto, and the second conductive layer forms a gate of the second gate-all-around transistor in each row of DRAM cell structures and a second word line connected thereto. In each stack, the second conductive layer forms gates of second surrounding gate transistors in each row of DRAM cell structures and second word lines connected thereto.

8. The method of claim 6, wherein, In forming each of the plurality of stacked sub-arrays, the common electrode layer forms outer electrodes of the storage capacitors and source lines, and the common electrode layer in each of the plurality of stacks is connected together in groups or collectively.

9. The method of claim 7, wherein, Forming each of the plurality of stacked sub-arrays further comprises: In each of the plurality of stacks, the first word lines and the second word lines are connected together.

10. The method of claim 1, wherein, Forming each of the plurality of stacked sub-arrays further comprises: a material modification process is used to change the doping type, doping concentration and / or atomic composition ratio of specific portions of the semiconductor material layer.

11. The method of claim 1, wherein, The semiconductor material layer comprises a single layer of IGZO or a stack of multiple layers of IGZO with different ratios.

12. The method of claim 1, wherein, The semiconductor material layer comprises single crystal silicon, polycrystalline silicon, amorphous silicon, silicon germanide compound, compound semiconductor, oxide semiconductor, sulfide semiconductor, graphene or a combination thereof.

13. The method of claim 1, wherein, In each stack, each bit line hole has a larger area in the common electrode layer than in the first and second conductive layers.

14. The method of claim 1, wherein, Each bit line hole has a circular cross section.

15. The method of claim 1, wherein, The isolation medium is formed of low-K material.

16. The method of claim 1, wherein, A cavity is provided in the isolation medium.

17. The method of claim 1, wherein, The medium layer is formed of high-K material.

18. The method of claim 1, forming each of the plurality of stacked sub-arrays further comprising: A plurality of isolation trenches extending along a first horizontal direction and through the plurality of first isolation layers and the plurality of stacks are formed at locations where the bit line holes are not provided.

19. The method of claim 1, further comprising: A plurality of isolation trenches extending along a first horizontal direction and through the plurality of stacked sub-arrays are formed at locations where the bit line holes are not provided.

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