MIM capacitor and manufacturing method thereof
By using a silicon oxynitride layer on top of the dielectric of the MIM capacitor, the contact between the dielectric and the top electrode is improved, which solves the problem of MIM capacitor breakdown under high voltage and improves the life of the capacitor.
Patent Information
- Application Number
- CN202511062242.8
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-30
- Publication Date
- 2025-11-07
AI Technical Summary
Existing MIM capacitors have poor dielectric layer breakdown characteristics under high voltage, especially copper-based MIM capacitors, which have a short lifespan.
A silicon oxynitride layer is used as the upper material of the capacitor dielectric to replace the traditional pure silicon nitride layer. By forming a silicon oxynitride layer on the surface of the silicon nitride layer, the adhesion is improved and the contact between the capacitor dielectric and the upper electrode is improved.
The TDDB characteristics of the MIM capacitor were improved, the insulation and passivation effect of the capacitor dielectric were enhanced, and the service life of the capacitor was extended.
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Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor devices and integrated circuits, and in particular to a MIM capacitor and a manufacturing method thereof. BACKGROUND
[0002] Capacitor elements are often used in integrated circuits such as radio frequency, monolithic microwave, etc. as electronic passive devices. Common capacitor elements include metal-oxide-semiconductor (MOS) capacitors, positive negative junction capacitors, poly-insulator-poly (PIP) capacitors, and metal-insulator-metal (MIM) capacitors, etc. Among them, MIM capacitors are widely used in semiconductor integrated circuit manufacturing due to their ease of integration into metal interconnection structures.
[0003] In the back-end of line (BEOL) process of semiconductor integrated circuit manufacturing, three photoetching layers are needed to integrate the MIM capacitor into the metal interconnection structure, which are respectively applied to the process flow of alignment mark (AMARK), the lower plate of the MIM capacitor, and the lower plate of the MIM capacitor. For MIM capacitors, the time-dependent dielectric breakdown (TDDB) characteristics of the dielectric layer can be used to characterize the life and other related parameters of the MIM capacitor. The MIM capacitors provided in the related art have poor TDDB characteristics, especially copper (Cu) MIM capacitors (MIM capacitors with copper material as the upper and lower plates) working at high voltage. Therefore, it is urgent to provide a MIM capacitor and a manufacturing method thereof capable of improving the TDDB characteristics and increasing the life. SUMMARY
[0004] The present application provides a MIM capacitor and a manufacturing method thereof, which can solve the problem of poor TDDB characteristics of the MIM capacitor provided in the related art.
[0005] In one aspect, the present application provides a manufacturing method of a MIM capacitor, comprising:
[0006] forming a silicon nitride layer on a first insulating layer, wherein the first insulating layer has a first metal layer formed therein, and the top of the first metal layer is in contact with the bottom of the silicon nitride layer;
[0007] forming a groove in the first insulating layer and the silicon nitride layer on the side of the first metal layer;
[0008] forming a silicon oxynitride layer on the surface layer of the silicon nitride layer;
[0009] forming a second metal layer, the second metal layer covering the silicon oxynitride layer and the recess;
[0010] taking the recess as an alignment mark, etching other regions except a target region by a photolithography process, etching to a predetermined depth in the silicon nitride layer, the target region being located in a region where the first metal layer is located, the first metal layer constituting a first electrode of the MIM capacitor, the remaining silicon nitride layer and silicon oxynitride layer constituting a capacitor dielectric of the MIM capacitor, and the remaining second metal layer constituting a second electrode of the MIM capacitor.
[0011] In some embodiments, the first metal layer comprises a copper metal layer.
[0012] In some embodiments, the second metal layer comprises a titanium nitride layer.
[0013] In some embodiments, after the etching of other regions except the target region by the photolithography process, the method further comprises:
[0014] forming a second insulating layer, the second insulating layer covering the MIM capacitor and the recess;
[0015] forming a first contact hole and a second contact hole in the second insulating layer, a bottom of the first contact hole being in contact with a top of the first electrode, and a bottom of the second contact hole being in contact with a top of the second electrode.
[0016] In another aspect, the embodiments of the present application provide a MIM capacitor, comprising:
[0017] a first electrode formed in a first insulating layer;
[0018] a capacitor dielectric formed on the first insulating layer, the capacitor dielectric comprising a silicon nitride layer and a silicon oxynitride layer formed on the silicon nitride layer, a bottom of the silicon nitride layer being in contact with a top of the first electrode;
[0019] a second electrode formed on the silicon oxynitride layer, the second electrode being aligned with an edge of the silicon oxynitride layer in a top-down view, and a width of the second electrode being smaller than a width of the first electrode and being located in a region where the first electrode is located.
[0020] In some embodiments, the first electrode comprises a copper metal layer.
[0021] In some embodiments, the second electrode comprises a titanium nitride layer.
[0022] The technical scheme of the present application has at least the following advantages:
[0023] By converting the upper layer of the capacitor dielectric of the MIM capacitor into a more loose and higher-adhesion silicon oxynitride layer (which exhibits less stress), the contact between the capacitor dielectric and the upper electrode is better, the problem of poor insulation and passivation effect of the capacitor dielectric composed of pure silicon nitride due to the large stress is solved, and the TDDB characteristics of the MIM capacitor are improved. BRIEF DESCRIPTION OF DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the specific embodiments or prior art of the present application, the drawings needed to be used in the specific embodiments or prior art description will be briefly introduced. Obviously, the drawings in the following description are some embodiments of the present application, and those skilled in the art can obtain other drawings according to these drawings without creative labor.
[0025] Figure 1 is a flow chart of the manufacturing method of the MIM capacitor provided by an exemplary embodiment of the present application;
[0026] Figures 2 to 10 is a schematic diagram of the manufacturing process of the MIM capacitor provided by an exemplary embodiment of the present application. DETAILED DESCRIPTION
[0027] The technical solutions in the present application will be described clearly and completely in combination with the drawings. Obviously, the described embodiments are some of the embodiments of the present application, not all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative labor are within the scope of protection of the present application.
[0028] In the description of the present application, it should be noted that the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inner", "outer" and the like indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings, and are only for the purpose of facilitating the description of the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore it cannot be understood as a limitation of the present application. In addition, the terms "first", "second", "third" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.
[0029] In the description of the present application, it should be noted that unless specifically defined and limited otherwise, the terms "mounting", "connection", "connecting" should be understood broadly, for example, can be fixed connection, can also be detachable connection, or integrally connected; can be mechanical connection, can also be electrical connection; can be directly connected, can also be indirectly connected through an intermediate medium, and can also be the internal communication of two elements, can be wireless connection, or wired connection. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.
[0030] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as there is no conflict.
[0031] Reference Figure 1 It shows the flow chart of the manufacturing method of the MIM capacitor provided by an exemplary embodiment of the present application, as shown in Figure 1 The method comprises the following steps:
[0032] Step S1, forming a silicon nitride layer on a first insulating layer, the first insulating layer is formed with a first metal layer, the top of the first metal layer is in contact with the bottom of the silicon nitride layer.
[0033] Reference Figure 2 It shows the cross-sectional schematic diagram before forming the silicon nitride layer on the first insulating layer; reference Figure 3 It shows the cross-sectional schematic diagram after forming the silicon nitride layer on the first insulating layer. Exemplarily, as shown in Figure 2 and Figure 3 The first insulating layer 212 is formed on the silicon carbon nitride (SiCN) layer 211, the first metal layer 221 is formed in the first insulating layer 212, the silicon nitride (Si3N4) layer 2221 can be deposited on the first insulating layer 212 by chemical vapor deposition (CVD) process, the bottom of the silicon nitride layer 2221 is in contact with the bottom of the first metal layer 221. The first metal layer 221 can include a copper metal layer.
[0034] Step S2, forming a groove in the first insulating layer and the silicon nitride layer on the side of the first metal layer.
[0035] Reference Figure 4 It shows the cross-sectional schematic diagram after covering photoresist on the silicon nitride layer, and after exposure and development; reference Figure 5 It shows the cross-sectional schematic diagram after forming a groove in the first insulating layer and the silicon nitride layer on the side of the first metal layer. Exemplarily, as shown in Figure 4 and Figure 5As shown, step S2 includes, but is not limited to: covering the silicon nitride layer 2221 with photoresist 301, sequentially performing exposure and development to remove the photoresist 301 in the target area (the target area is located on one side of the first metal layer 221), performing etching to form a groove 401 in the first insulating layer 212 and the silicon nitride layer 2221 on one side of the first metal layer 221.
[0036] Step S3: A silicon oxynitride layer is formed on the surface of the silicon nitride layer.
[0037] refer to Figure 6 This illustrates a schematic cross-sectional view after a silicon oxynitride (SiON) layer has been formed on the surface of a silicon nitride layer. For example, such as... Figure 6 As shown, a silicon oxynitride layer 2222 can be formed on the surface of the silicon nitride layer 2221 by adding oxygen (O2) during the removal of the remaining photoresist 301.
[0038] Step S4: Form a second metal layer, which covers the silicon oxynitride layer and the groove.
[0039] refer to Figure 7 This shows a schematic cross-sectional view after the formation of the second metal layer. For example, as shown... Figure 7 As shown, the second metal layer 223 may include a titanium nitride (TiN) layer, which can be formed by depositing titanium nitride through a physical vapor deposition (PVD) process. The second metal layer 223 covers the silicon oxynitride layer 2222 and the groove 401.
[0040] Step S5: Using the groove as an alignment mark, etch the areas other than the target area using photolithography to a predetermined depth in the silicon nitride layer. From a top view, the target area is located within the area of the first metal layer. The first metal layer constitutes the first electrode of the MIM capacitor, the remaining silicon nitride layer and silicon oxynitride layer constitute the capacitor dielectric of the MIM capacitor, and the remaining second metal layer constitutes the second electrode of the MIM capacitor.
[0041] refer to Figure 8 It shows a cross-sectional schematic diagram after photoresist is applied to the second metal layer, followed by exposure and development; Reference Figure 9 This shows a schematic cross-sectional view after etching to form a MIM capacitor. For example, such as... Figure 8 and Figure 9As shown, step S5 includes but is not limited to: covering photoresist 302 on second metal layer 223, exposing to light with recess 401 as alignment mark, developing to remove photoresist 302 from regions other than target region (from the perspective of top view, the target region is located within the region of first metal layer 221), etching to a predetermined depth in silicon nitride layer 2221, first metal layer 221 constituting the first electrode of MIM capacitor, remaining silicon nitride layer 2221 and silicon oxynitride layer 2222 constituting the capacitor dielectric of MIM capacitor, and remaining second metal layer 223 constituting the second electrode of MIM capacitor.
[0042] Reference is made to Figure 10 which shows a cross-sectional schematic diagram of the MIM capacitor after forming the contact hole. As an example, as shown in Figure 10 after step S5, further including: forming second insulating layer 213, second insulating layer 213 covering the MIM capacitor and recess 401; forming first contact hole 2131 and second contact hole 2132 in second insulating layer 213, the bottom of first contact hole 2131 contacting the top of first electrode 221, and the bottom of second contact hole 2132 contacting the top of second electrode 223. Optionally, first contact hole 2131 and second contact hole 2132 include tungsten (W) metal layer.
[0043] In summary, in the embodiments of the present application, the upper layer of the capacitor dielectric of MIM capacitor is converted into silicon oxynitride layer which is relatively loose and has higher adhesion (it exhibits smaller stress), so that the contact between the capacitor dielectric and the upper electrode is better, the problem of poor insulation and passivation effect caused by the capacitor dielectric composed of pure silicon nitride due to large stress is solved, and the TDDB characteristics of MIM capacitor are improved.
[0044] Reference is made to Figure 10 which shows a cross-sectional schematic diagram of the MIM capacitor provided by an example embodiment of the present application, which can be manufactured by the above-mentioned method embodiments. The MIM capacitor includes:
[0045] First electrode 221 is formed in first insulating layer 212. Optionally, first insulating layer 212 is formed on silicon carbon nitride layer 211.
[0046] Capacitor dielectric is formed on first insulating layer 212, capacitor dielectric includes silicon nitride layer 2221 and silicon oxynitride layer 2222 formed on silicon nitride layer 2221, the bottom of silicon nitride layer 22221 contacting the top of first electrode 221. Optionally, first electrode 221 includes copper metal layer.
[0047] A second electrode 223 is formed on the silicon oxynitride layer 2222. The second electrode 223 is aligned with the edge of the silicon oxynitride layer 2222 from a top view. The width of the second electrode 223 is less than the width of the first electrode 221 and is located in the area where the first electrode 221 is located. Optionally, the second electrode 223 includes a titanium nitride layer.
[0048] The second insulating layer 213 covers the first insulating layer 212, the MIM capacitor, and the first and second electrodes 221 and 223. The second insulating layer 213 includes a first contact hole 2131 and a second contact hole 2132. The bottom of the first contact hole 2131 contacts the top of the first electrode 221. The bottom of the second contact hole 2132 contacts the top of the second electrode 223. Optionally, the first and second contact holes 2131 and 2132 include a tungsten metal layer. The first and second insulating layers 212 and 213 include a silicon dioxide (SiO2) layer.
[0049] Obviously, the above embodiments are only example for clearly illustrating but not limitation to the embodiments. Based on the above description, other different forms of changes or variations can be made by those skilled in the art. Here, all the embodiments are not required to be exhausted. The changes or variations derived from the above are still within the protection scope of the present application.
Claims
1. A method for fabricating a MIM capacitor, comprising: The method comprises: forming a silicon nitride layer on a first insulating layer, the first insulating layer having a first metal layer formed therein, a top of the first metal layer being in contact with a bottom of the silicon nitride layer; forming a groove in the first insulating layer and the silicon nitride layer on a side of the first metal layer; forming a silicon oxynitride layer on a surface layer of the silicon nitride layer; forming a second metal layer, the second metal layer covering the silicon oxynitride layer and the groove; using the groove as an alignment mark, performing etching on other regions except a target region by a photolithography process, the etching being performed to a predetermined depth in the silicon nitride layer, the target region being located in a region where the first metal layer is located, the first metal layer constituting a first electrode of a MIM capacitor, a remaining silicon nitride layer and a silicon oxynitride layer constituting a capacitor dielectric of the MIM capacitor, and a remaining second metal layer constituting a second electrode of the MIM capacitor.
2. The method of claim 1, wherein, The first metal layer comprises a copper metal layer.
3. The method of claim 2, wherein, The second metal layer comprises a titanium nitride layer.
4. The method according to any one of claims 1 to 3, characterized in that, After the etching on the other regions except the target region by the photolithography process, the method further comprises: forming a second insulating layer, the second insulating layer covering the MIM capacitor and the groove; forming a first contact hole and a second contact hole in the second insulating layer, a bottom of the first contact hole being in contact with a top of the first electrode, and a bottom of the second contact hole being in contact with a top of the second electrode.
5. A MIM capacitor, comprising: The method comprises: a first electrode formed in a first insulating layer; a capacitor dielectric formed on the first insulating layer, the capacitor dielectric comprising a silicon nitride layer and a silicon oxynitride layer formed on the silicon nitride layer, a bottom of the silicon nitride layer being in contact with a top of the first electrode; a second electrode formed on the silicon oxynitride layer, the second electrode being aligned with an edge of the silicon oxynitride layer in a top-down view, a width of the second electrode being smaller than a width of the first electrode and being located in a region where the first electrode is located.
6. The capacitor of claim 5, wherein The first electrode comprises a copper metal layer.
7. The capacitor of claim 6, wherein The second electrode comprises a titanium nitride layer.